30th week of 2010 patent applcation highlights part 58 |
Patent application number | Title | Published |
20100191846 | Verifiable service policy inplementation for intermediate networking devices - Various embodiments are disclosed for a services policy communication system and method. In some embodiments, an intermediate networking device acts as a service intermediary or intermediate connection between a network and one or more communications devices; implements a service policy set for assisting control of the intermediate networking device use of a service set on the network, the service policy set including one or more service policies associated with the intermediate networking device or one or more communications devices connected to the intermediate networking device, the service set being one or more network services used by the intermediate networking device or one or more communications devices; and monitors use of the service set based on the first service policy set, in which the implementation of the service policy set is verified. | 2010-07-29 |
20100191847 | Simplified service network architecture - Various embodiments are disclosed for a services policy communication system and method. In some embodiments, a network device collects a plurality of service usage measurements for a communications device use of a service on a network; and compares the plurality of service usage measurements to a device assisted implementation of a service policy to verify the device assisted implementation of the service policy. | 2010-07-29 |
20100191848 | INFORMATION SHARING METHOD BETWEEN NEIGHBORING NODES, NODE AND INFORMATION SHARING PROGRAM - A load caused by an information sharing message in an upper layer is reduced. | 2010-07-29 |
20100191849 | COMMUNICATION METHOD, COMMUNICATION SYSTEM, SERVER AND STORAGE MEDIUM STORING PROGRAM RELATED TO TRANSFER OF SESSION MANAGEMENT - A first server detects a condition that requires a service to be invoked, and the detection of this condition triggers it to establish a connection with a second server. The first server relays data relevant to a first communication between first and second terminals and the second server over the established connection. The first server also relays data relevant to a second communication between the first and second terminals and the second server, or between third and fourth terminals and the second server. Alternatively, the second server both receives and returns the data relevant to the first communication from/to the first server over the established connection. | 2010-07-29 |
20100191850 | SYSTEM AND METHOD FOR DETECTION OF ABERRANT NETWORK BEHAVIOR BY CLIENTS OF A NETWORK ACCESS GATEWAY - A system and method for detecting aberrant network behavior. One embodiment provides a system of detecting aberrant network behavior behind a network access gateway comprising a processor, a first network interface coupled to the processor, a second network interface coupled to the processor, a storage media accessible by the processor and a set of computer instructions executable by the processor. The computer instructions can be executable to observe network communications arriving at the first network interface from multiple clients and determine when the traffic of a particular client is indicative of malware infection or other hostile network activity. If the suspicious network communication is determined to be of a sufficient volume, type, or duration the computer instructions can be executable to log such activity to storage media, or to notify an administrative entity via either the first network interface or second network interface, or to make the computer instructions be executable to perform other configured actions related to the functioning of the network access gateway. | 2010-07-29 |
20100191851 | METHOD AND APPLIANCE FOR USING A DYNAMIC RESPONSE TIME TO DETERMINE RESPONSIVENESS OF NETWORK SERVICES - In a method and appliance for determining responsiveness of a service via a particular protocol, a device intermediary to a plurality of clients and a plurality of services determines response times from each of a plurality of services to respond to requests via a first type of protocol of a plurality of protocols. The device calculates an average response time for the first type of protocol from each of the response times of the plurality of services. The device establishes a predetermined threshold for which a response time of a service for the first type of protocol may deviate from the average response time. The device identifies a service as available responsive to determining that a deviation of the response time of the service from the average response falls within the predetermined threshold. | 2010-07-29 |
20100191852 | SOURCE CONFIGURATION BASED ON CONNECTION PROFILE - Connection profiles are created and stored. The connection profiles are for connections for sources to connect to a network. The connection profiles identify network attributes and server attributes for the connections and each connection profile includes a status of available or subscribed. A connection profile is assigned to a requested connection for a source. The source is authenticated using a credential, and server attributes from the connection profile are sent to the source to configure the source to use the connection. | 2010-07-29 |
20100191853 | Methods And Systems For Managing Network Access - Methods, systems and computer readable mediums storing computer executable programs for managing access to a network at a network access management module are disclosed. A first network request is received from a client at a network access management module. A first determination is made regarding whether the first network request is associated with a restricted network action at the network access management module. A second network request is received from the client at the network access management module. The second network request is intercepted at the network access management module based on the first determination. A network access restriction notification is transmitted from the network access management module to the client based on the first determination. | 2010-07-29 |
20100191854 | PROCESS DEMAND PREDICTION FOR DISTRIBUTED POWER AND RESOURCE MANAGEMENT - Methods and systems for allocating resources in a virtual desktop resource environment are provided. A method includes making a prediction on the future demand for processes running on a distributed environment with several hosts. The prediction is based on the process demand history and includes the removal of historic process demand glitches. Further, the prediction is used to perform a cost and benefit analysis for moving a candidate process from one host to another, and the candidate process is moved to a different host when the cost and benefit analysis recommends such move. In another embodiment, the predictions on future process demand are used for distributed power management by putting hosts in stand-by mode when the overall demand decreases or by adding hosts to the distributed environment when the load increases. | 2010-07-29 |
20100191855 | P2P SYSTEM AND A RESOURCE QUERY METHOD FOR THE SAME - The present invention discloses a P2P system and a resource query method for this system, wherein the P2P system includes: at least one content management servers, for managing the distribution of content resources in its domain and accepting a resource query request from P2P node in its domain; and at least one resource management servers, for managing the content resources of the P2P nodes in its domain, accepting a resource query request from P2P nodes in its domain and in domains of other resource management servers, and reporting to the at least one content management servers the statistic information of the content resources in its domain. | 2010-07-29 |
20100191856 | REDUCING NETWORK CONNECTION LATENCY - Methods, systems, and apparatus, including medium-encoded computer program products, for decreasing latency perceived by a user in retrieving data from a data server. A user-initiated interaction with a user interface can be detected and a user-generated request to retrieve data automatically predicted, based at least in part on the user-initiated interaction. Resolution of a domain name into a network address can be initiated, based on the predicted user-generated request to retrieve data, prior to receiving a user-initiated submission of the user-generated request to retrieve data. In certain instances, a network communication synchronization sequence with a data server associated with the predicted user-generated request to retrieve data can be initiated prior to receiving a user-initiated submission of the user-generated request to retrieve data. | 2010-07-29 |
20100191857 | METHOD AND SYSTEM FOR DISCOVERING THE TOPOLOGY OF THE COMMUNICATIONS BETWEEN APPLICATIONS OF A COMPUTER NETWORK - A method for discovering the topology of communications between applications of a computer network having several items of equipment, the method including the following steps: a) connecting to each of the items of equipment of the network, b) for each item of equipment, acquiring raw data relating to applications hosted within the item of equipment, c) for each item of equipment, acquiring connection data for each live connection established by an application, d) from the raw data and the connection data thus obtained, communication links are determined respectively between pairs of applications of the network, and e) a level-7 topology of the network is generated from the communication links. | 2010-07-29 |
20100191858 | FAILOVER MECHANISM FOR REAL-TIME PACKET STREAMING SESSIONS - Techniques are provided herein for failover streaming mechanisms. At a first device (e.g., a content router device) that is configured to interface with a plurality of streaming servers for real-time protocol packet streams, communications are configured with a client device and a first of the plurality of streaming servers associated with a streaming session from the first streaming server to the client device so that the first device receives client session control and session feedback messages associated with the streaming session and so that a packet stream associated with the streaming session transmitted by the first streaming server to the client device does not pass through the first device. The first device stores session state information comprising an address of the client device, streaming session identification information and data representing a current state of the streaming session at the client device derived from the client session control and session feedback messages. Upon detecting a failure of the first streaming server, the first device selects a second of the plurality of streaming servers for serving the streaming session previously served by the first streaming server, and then initiates a streaming session from the second streaming server to the client device in order to continue from a state of the streaming session previously served by the first streaming server prior to the failure without any indication at the client device of the switching from the first streaming server to the second streaming server. | 2010-07-29 |
20100191859 | MULTIMEDIA MANAGEMENT SYSTEM FOR SEAMLESS MULTIMEDIA CONTENT MOBILITY - In general, techniques are described for providing a multimedia management system to facilitate multimedia content mobility. More specifically, an apparatus may implement the techniques. The apparatus may comprise one or more wireless modems and a control unit. The one or more wireless modems receive multimedia content in a first format from a first application over a wireless communication channel. The control unit includes a Multimedia Management System (MMS) that configures the control unit to provide a multimedia bridge between the first format and a second format, where the second format is supported by a second application. The configured multimedia bridge transforms the multimedia content from the first format to the second format concurrent to the one or more wireless modems receiving a portion of the multimedia content. | 2010-07-29 |
20100191860 | PERSONAL MEDIA BROADCASTING SYSTEM WITH OUTPUT BUFFER - A personal media broadcasting system enables video distribution over a computer network and allows a user to view and control media sources over a computer network from a remote location. A personal broadcaster receives an input from one or more types of media sources, digitizes and compresses the content, and streams the compressed media over a computer network to a media player running on any of a wide range of client devices for viewing the media. The system may allow the user to issue control commands (e.g., “channel up”) from the media player to the broadcaster, causing the source device to execute the commands. The broadcaster and the media player may employ several techniques for buffering, transmitting, and viewing the content to improve the user's experience. | 2010-07-29 |
20100191861 | METHODS AND SYSTEMS USING DATA RATE DRIVEN PROTOCOL ACCELERATOR FOR MOBILE DEVICES - By controlling whether operations are offloaded to a protocol stack hardware accelerator as a function of data rate, power consumption may be reduced, for example, when data rates result in fragmented or segmented data not suitable for processing by the stack hardware accelerator. | 2010-07-29 |
20100191862 | SYSTEM AND METHOD FOR PRIORITY DELIVERY OF LOAD MANAGEMENT MESSAGES ON IP-BASED NETWORKS - Methods for prioritizing load management messages on IP-based networks utilizing an Active Load Directory and IP capable two-way gateway. The messages being received from, or sent to, the ISP through the gateway contain a blend of regulated and unregulated data. The regulated data is high-priority utility load management data such as, equipment status and load control instructions. The unregulated data consists of Internet messages such as email and web site data. These methods process all regulatory data before unregulated data within strict time limits, providing the greatest possible load management control and energy savings. The methods emulate dedicated network processor memory in a manner that permits the rules for prioritizing, scheduling, and routing to remain the same across both hardware and software implementations. | 2010-07-29 |
20100191863 | Protected Device Initiated Pinhole Creation to Allow Access to the Protected Device in Response to a Domain Name System (DNS) Query - Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with a protected device initiating a pinhole through a network address translator and/or firewall to allow access to the protected device in response to a Domain Name System (DNS) query. In response to a received DNS query from a domain name system (DNS) server, an apparatus requests a traffic pinhole be created in a firewall or network address translator for allowing traffic initiated from a device, on another side of the firewall or said network address translator from the apparatus, to reach the apparatus. | 2010-07-29 |
20100191864 | Message conversion method and message conversion system - A message given with an electronic signature is modified, for example, by adding or deleting data to or from the message, while keeping validity of the electronic signature. A conversion information insertion unit | 2010-07-29 |
20100191865 | COMPUTER SYSTEM AND NETWORK INTERFACESUPPORTING CLASS OF SERVICE QUEUES - A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory. A data processing system, a method for management of a network interface and a network interface are also provided by the present invention that include an embedded firewall at the network interface level of the system, which protects against inside and-outside attacks on the security of data processing system. Furthermore, a data processing system, a method for management of a network interface and a network interface are a provided by the present invention that support class of service management for packets incoming from the network, by applying priority rules at the network interface level of the system. | 2010-07-29 |
20100191866 | Information Processing Device, For Controlling The Same Method And Recording Medium - An information processing device that is connected to external devices includes a receiving unit that receives a command from the external devices, a judgment unit that determines whether the command received by the receiving unit is a first type command that reads out, rewrites, or deletes data stored in the information processing device, or a second type command other than the first type command, and a command processing unit in which execution of the command received by the receiving unit is prohibited when the command is the first type command, and execution of the command received by the receiving unit is performed when the command is the second type command, in accordance with determination by the judgment unit. | 2010-07-29 |
20100191867 | Systems and Methods for Performing Field Updates of Firmware - Systems and methods for updating firmware in a target device are disclosed. A system may include a source device, a target device, and a standardized bidirectional communication path coupling the source device to the target device. The source device is operable to verify that the target device is capable of receiving a firmware update from the source device via the standardized bidirectional communication path and communicate the firmware update to the verified target device via the standardized bidirectional communication path. The target device is operable to receive the firmware update from the source device via the standardized bidirectional communication path and perform the firmware update in the target device. The source device is further operable to validate the completion of the firmware update in the target device via the standardized bidirectional communication path. | 2010-07-29 |
20100191868 | System and Method for Migrating Data from a Storage Device - According to one embodiment of the present disclosure, a method for migrating data from a storage device includes accessing data on a storage device. The method also includes providing at least one interface that allows for selecting a first operating system stored on the storage device. The interface further allows for selecting one or more settings stored on the storage device. The method further includes initiating a migration of the one or more settings from the storage device. The method further includes storing the one or more settings. | 2010-07-29 |
20100191869 | REDUNDANT I/O MODULE - A redundant I/O module includes: a control I/O module that communicates with a controller and that comprises a first IOM setting information holding section for storing IOM setting information downloaded from a high-level apparatus, and a standby I/O module that communicates with the controller and that comprises a second IOM setting information holding section for storing IOM setting information downloaded from the high-level apparatus, wherein the controller includes: an IOM status generation section that detects a status of replacement of the standby I/O module; an IOM setting information acquisition section that makes an access to the first IOM setting information holding section of the control I/O module; an IOM setting information generation section that generates IOM setting information about the standby I/O module; and an IOM download section that downloads the generated IOM setting information into the second IOM setting information holding section of the standby I/O module. | 2010-07-29 |
20100191870 | EQUIPMENT AND METHOD TO IMPLEMENT ADAPTIVE FUNCTIONS OF COMMUNICATION PROTOCOLS - An equipment and method to implement the adaptive functions of communication protocols are provided so that the smart card operation system can adaptively select the corresponding communication protocol according to that of the terminal. The equipment includes: a communication protocol setting module; a communication protocol detecting module; a communication protocol selecting module. The method includes: setting communication protocol for the smart card operation system; judging whether the communication protocol type of the smart card operation system is identical with that of the terminal; if not identical, selecting communication protocol for the smart card operation system. Therefore, the communication protocol of the smart card operation system can be adaptively selected according to the protocol of the terminal. | 2010-07-29 |
20100191871 | Controller, Program and Methods for Communicating With Devices Coupled to the Controller - A controller coupled to a redundant array of inexpensive disks (RAID) includes a processor and a non-volatile memory element. The processor has an input/output port that is configurable in one of an open-drain driver configuration, a high-impedance driver configuration and a totem-pole driver configuration. The totem-pole driver configuration is capable of supplying sufficient current to operate a slave device coupled to the input/output port. Firmware stored in the non-volatile memory device dynamically adjusts the driver configuration to prevent negative voltage swings in a signal communicated via the input/output port. | 2010-07-29 |
20100191872 | CONTROLLER - A controller includes an inputting/outputting portion, which receives data from a field device and outputs operated data to the field device, a flash memory including a file system, and a file system driver, which reads data held on a shared memory and writes the read data into the file system to save the data in the file system. The file system driver has a power-failure-safe function. | 2010-07-29 |
20100191873 | ENABLING AND DISABLING DEVICE IMAGES ON A PLATFORM WITHOUT DISRUPTING BIOS OR OS - Device images, for example IDE mass storage device images, may be enabled and disabled without disrupting a host system. In one embodiment, the invention includes a memory device register to indicate the presence of a memory device to a computer system, a switch coupled to the memory device register to set the memory device register to indicate the presence of a memory device, and an external interface coupled to the switch to operate the switch. | 2010-07-29 |
20100191874 | HOST CONTROLLER - The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device. | 2010-07-29 |
20100191875 | Communication network and converter module - A converter module comprising a first connection for connection to a first data line for communication with a superordinate plane, a second connection for connection to a second data line for communication with a subordinate plane having a conversion means for converting a first protocol of the superordinate plane into a second protocol of the subordinate plane, wherein a device for operating safety-oriented communication within the subordinate plane is provided, and wherein the device can be activated by an enabling device. | 2010-07-29 |
20100191876 | Method And System For Optimizing Network Input/Output Performance - A method and system for optimizing network I/O throughput is disclosed. In one embodiment, a method for optimizing an input/output (I/O) throughput for a storage network comprises measuring a service time for a storage device of the storage network in completing an I/O request serviced by a storage driver. The method also comprises determining a status of an I/O performance between the storage driver and the storage device by comparing the service time with an expected service time for the storage device in completing the I/O request, where the expected service time is calculated based on a type of the storage device and a size of the I/O request. The method further comprises adjusting a maximum queue depth associated with the storage device based on the status of the I/O performance. | 2010-07-29 |
20100191877 | METHOD AND SYSTEM FOR POLLING MULTIFUNCTION DEVICES BASED ON PERFORMANCE CRITERIA - A method and system suitable for grouping a plurality of multifunction devices (MFDs), the system including a storage station for storing information gathered from the plurality of MFDs by selectively polling the plurality of MFDs; wherein the information is selectively processed based on static performance data and dynamic performance data relating to the plurality of MFDs. | 2010-07-29 |
20100191878 | METHOD AND APPARATUS FOR ACCOMODATING A RECEIVER BUFFER TO PREVENT DATA OVERFLOW - Methods and apparatuses for preventing overflow at a receiver buffer are provided. Data packets of varying size are received into a receiver buffer and quantified by a byte counter to determine an amount of data in the receiver buffer at a given time. A data capacity status for the receiver buffer is then generated as a function of the amount of data in the receiver buffer. | 2010-07-29 |
20100191879 | HOST-PERIPHERAL ADAPTOR - A host-peripheral adaptor includes a host adaptor and a portable peripheral adaptor. The host adaptor includes a substantially flat peripheral-adaptor-side interface. The peripheral-adaptor-side interface is designed in a way that it is not easy to tamper with. The portable peripheral adaptor includes a host-adaptor-side interface that is designed to operatively connect to the peripheral-adaptor-side interface of the host adaptor. The portable peripheral adaptor also includes one or more peripheral-side interfaces for accommodating one or more peripheral devices such as a storage media. The portable peripheral adaptor and the host adaptor include a set of data lines and the host adaptor also includes circuitry for recognizing the specific type of a peripheral device and, based on its specific type, for setting a suitable communication path to transfer data between a host and the peripheral device. | 2010-07-29 |
20100191880 | MEMORY MODULE CAPABLE OF IMPROVING THE INTEGRITY OF SIGNALS TRANSMITTED THROUGH A DATA BUS AND A COMMAND/ADDRESS BUS, AND A MEMORY SYSTEM INCLUDING THE SAME - A memory module and a related memory system are disclosed. The memory module comprises a semiconductor memory having a data output buffer, a data input buffer, a command/address input buffer and a first termination resistor unit connected to a data bus. The memory module further comprises a second termination resistor unit connected to an internal command/address bus. First and second termination resistor units are preferably of different resistive value and/or type. | 2010-07-29 |
20100191881 | System and Method for Reserving and Provisioning IT Resources - A method for reserving and provisioning IT resources comprises receiving, from a user, a request to reserve a desired configuration of IT resources. The desired configuration comprises one or more desired technical specifications and a desired reservation time having a start time and an end time. The method further comprises accessing an IT resource database to determine one or more of a plurality of resource pools that the user has access to. The one or more resource pools are consulted to determine if one or more IT resources matching the desired configuration are available. If the one or more IT resources matching the desired configuration are available, the one or more IT resources are reserved for the user and provided to the user at the start time. | 2010-07-29 |
20100191882 | COMMUNICATION SYSTEM AND PROTOCOL - A communication system and protocol that permits a first device to communicate a plurality of messages in a predetermined order to a user of the first device, where the plurality of messages, their content, and their predetermined order need not be known to the first device until the messages are provided to the first device by a second device. The user of the first device is permitted to move backward or forward through the messages in the predetermined order while utilizing a minimal amount of resources of the first device, such as processor power and memory. | 2010-07-29 |
20100191883 | INFORMATION DEVICE INCLUDING MAIN PROCESSING CIRCUIT, INTERFACE CIRCUIT, AND MICROCOMPUTER - An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit. | 2010-07-29 |
20100191884 | METHOD FOR REPLICATING LOCKS IN A DATA REPLICATION ENGINE - An automated method is provided of replicating a locking protocol in a database environment for performing I/O operations wherein the database environment includes a plurality of databases. A locking protocol is performed that includes one or more explicit locking operations on objects in a first database of the database environment. The one or more explicit locking operations are replicated in one or more other databases in the database environment. At least some of the explicit locking operations are performed asynchronously with respect to the explicit locking operations performed in the first database. I/O operations are performed at the first database of the database environment that are associated with the one or more explicit locking operations implemented in the first database. | 2010-07-29 |
20100191885 | Guest Interrupt Controllers for Each Processor to Aid Interrupt Virtualization - In one embodiment, a system comprises a processor, a first interrupt controller coupled to the processor, and a second interrupt controller coupled to the processor. The first interrupt controller is configured to signal the processor for an interrupt in response to receiving a first interrupt message communicating a first interrupt that is targeted at a host in the system. The second interrupt controller is configured to signal the processor for an interrupt in response to receiving a second interrupt message communicating a second interrupt that is targeted at a guest that is controlled by the host and that is executable on the processor. | 2010-07-29 |
20100191886 | Resource-limited electronic device comprising means for prioritizing services - An electronic device, including: a storage device operable to store first priority data associated with a first signal, and second priority data associated with a second signal; and a processor operable to compare the first priority data and the second priority data, and when the second priority data is indicative of a higher priority than the first priority data, to use the second signal while suspending use of the first signal. | 2010-07-29 |
20100191887 | Monitoring Interrupt Acceptances in Guests - In one embodiment, an interrupt acceptance control circuit is provided. The interrupt acceptance control circuit may monitor one or more guest interrupt controllers in a system in response to an IPI (or device interrupt) issued in a guest, to determine if each targeted vCPU in the guest has accepted the interrupt. If not, the interrupt acceptance control circuit may communicate the lack of acceptance to the VMM, in one embodiment. The VMM may attempt to schedule the vCPUs that have not accepted the interrupt, for example. | 2010-07-29 |
20100191888 | Guest Interrupt Manager to Aid Interrupt Virtualization - In an embodiment, a system comprises a memory system and a guest interrupt manager. The guest interrupt manager is configured to receive an interrupt message corresponding to an interrupt that is targeted at a guest executable on the system. The guest interrupt manager is configured to record the interrupt in a data structure in the memory system to ensure that the interrupt is delivered to the guest even if the guest is not active in the system at a time that the interrupt message is received. | 2010-07-29 |
20100191889 | MEMORY STRUCTURE TO STORE INTERRUPT STATE FOR INACTIVE GUESTS - In an embodiment, a system comprises a memory system configured to store a data structure. The data structure stores at least an interrupt request state for each destination in each of a plurality of guests executable on the system. The interrupt request state identifies which interrupts have been requested at the corresponding interrupt controller in the corresponding guest of the plurality of guests. A guest interrupt manager is coupled to receive an interrupt message targeted at a first destination in a first guest of the plurality of guests, and the guest interrupt manager is configured to update the interrupt request state in the data structure that corresponds to the first destination and the first guest. | 2010-07-29 |
20100191890 | Globally Unique Transaction Identifiers - In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2 | 2010-07-29 |
20100191891 | Combination Personal Data Assistant and Personal Computing System Dynamic Memory Reclamation - In order to continually receive messages in a dual personal computer system (PC) and personal digital assistant system (PDA) computer architecture, the PC system is deactivated to conserve battery power while the PDA continues to receive messages. As PDA memory is filled with messages, messages that are synchronized and archived with the PC system are deleted and space is freed for incoming messages. When new and non-synchronized messages completely fill the PDA memory array, the PC system is reactivated or the user is informed. | 2010-07-29 |
20100191892 | Peripheral Pointing Devices And Methods For Manufacturing The Same - Embodiments of peripheral pointing devices and methods for manufacturing the same are generally described herein. In at least one embodiment, a peripheral device comprises a housing, one or more buttons at a first side of the housing, a displacement tracker at a second side of the housing, a keypad comprising keys at the second side of the housing; and a keypress restrictor coupled to the housing. Other examples, embodiments, and related methods are further described below. | 2010-07-29 |
20100191893 | Dual Access for Single Port Cache - A method and system for accessing a single port multi-way cache includes an address multiplexer that simultaneously addresses a set of data and a set of program instructions in the multi-way cache. Duplicate output way multiplexers respectively select data and program instructions read from the cache responsive to the address multiplexer. | 2010-07-29 |
20100191894 | Digital Data Architecture Employing Redundant Links in a Daisy Chain of Component Modules - A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips. | 2010-07-29 |
20100191895 | SYSTEM, TEST APPARATUS AND RELAY APPARATUS - There is a system comprising a requesting device including a block generating section which generates an access information block storing access information including a target address of an access target and an access command indicating content to be executed for the access target in each of a plurality of accesses, and a block transmitting section which transmits the generated access information block to a relay apparatus, the relay apparatus including a block receiving section which receives the access information block from the requesting device and an access issuing section which sequentially issues corresponding access to a responding device on the basis of the access information included in the transmitted access information block, and the responding device including an access receiving section which receives each access corresponding to the access information included in the access information block from the relay apparatus and an access processing section which executes an access process for a storage area corresponding to a target address of the received access. | 2010-07-29 |
20100191896 | Solid state drive controller with fast NVRAM buffer and non-volatile tables - Systems and methods for a SSD controller enabling data transfer between a host and flash memories have been achieved. A major component of the SSD controller is a non-volatile buffer memory, which interfaces fast disk drive protocols and slow write and read cycles of NAND flash. Preferably MRAM or Phase Change RAM can be used for the buffer memory. Non-volatile tables can also be implemented for storing dynamic logical to physical address translation, defective sector information and their spare sectors and/or SSD configuration parameters. data are kept in a buffer memory when the buffer memory is not powered | 2010-07-29 |
20100191897 | SYSTEM AND METHOD FOR WEAR LEVELING IN A DATA STORAGE DEVICE - The present disclosure provides a system and method for wear leveling. In one example, the method includes receiving first data to be stored to a first data storage medium and storing the first data to a first storage location in a nonvolatile data store of a second data storage medium comprising a solid-state memory. The method also includes setting a pointer to enable writing second data that is received to a next storage location in the nonvolatile data store. The next storage location comprises an address of the nonvolatile data store that is sequentially after an address of the first storage location. When the address of the first storage location is a last addressed location of the nonvolatile data store the pointer is set to enable writing the second data to a first addressed location of the nonvolatile data store. The method also includes writing the first data stored in the nonvolatile data store to the first data storage medium when a trigger occurs and preserving the pointer during the writing from the nonvolatile data store to the first data storage device such that the pointer enables writing the second data to the next storage location. | 2010-07-29 |
20100191898 | COMPLEX MEMORY DEVICE AND I/O PROCESSING METHOD USING THE SAME - A non-volatile mass storage memory and an input/output processing method using the memory are provided. The memory device includes a storage unit including a non-volatile random access memory and a flash memory and a controller to control the storage to process an input/output request. Accordingly, system memories having different purposes and functionalities, such as a flash memory and a dynamic random access memory (DRAM), may be integrated with each other. | 2010-07-29 |
20100191899 | Information Processing Apparatus and Data Storage Apparatus - According to one embodiment, an information processing apparatus includes an storage apparatus including a first storage and a second storage. The storage apparatus includes a first data management module which stores data which is required to be read in a the predetermined period in the second storage so that the data requested to be read in the predetermined period is distinguishable. The storage apparatus further includes a second data management module which performs replacement of the data in the second storage so that data should be stored in the second storage, in an order reverse to that in which the data is requested to be read, while retaining the data stored in the second storage by the first data management module. | 2010-07-29 |
20100191900 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes memory chips driven in response to respective chip enable signals, and each of the memory chips includes a controller configured to generate and output information about an operation state, and a state information processor configured to calculate an expected consumption current when a target operation is performed based on the information about the operation states for the memory chips, and to output a control signal regarding whether to suspend or perform the target operation. | 2010-07-29 |
20100191901 | NON-VOLATILE STORAGE DEVICE, HOST DEVICE, NON-VOLATILE STORAGE SYSTEM, DATA RECORDING METHOD, AND PROGRAM - A memory controller, a non-volatile storage device, a host device, and a non-volatile storage system capable of performing real-time recording even in the case where normal data and file management information/auxiliary information are written in alternating manner are provided. The host device ( | 2010-07-29 |
20100191902 | STORAGE DEVICE EMPLOYING A FLASH MEMORY - A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased. | 2010-07-29 |
20100191903 | MEMORIES FOR ELECTRONIC SYSTEMS | 2010-07-29 |
20100191904 | SYSTEM AND METHOD OF IMAGING A MEMORY MODULE WHILE IN FUNCTIONAL OPERATION - A memory module (e.g. a hard drive, an optical drive, a flash drive, etc.) associated with a computer system may be imaged without substantial interruption to the operation of the overall system. The imaging may include applying an image to the memory module while execution of one or more operations and/or algorithms that require at least intermittent access to information stored initially in the memory module is ongoing. This may enable a system associated with the memory module to continue with normal, or substantially normal, operation while the image is being applied to the memory module. The image applied to the memory module may, for example, update the system, restore the system to a previous state (e.g., to its state at a previous point in time), or otherwise modify the system with which it is associated. | 2010-07-29 |
20100191905 | STORAGE DEVICE, CONTROL METHOD AND CONTROLLER - A storage device comprises a recording/reproducing module which positions a head at an arbitrary position of a storage medium to record or reproduce data and a nonvolatile memory in which a parameter storage area is defined. An adjustment module adjusts various types of parameters necessary for controlling a positioning control module and the recording/reproducing module. A parameter save processing module saves adjusted parameters obtained by the adjustment module in the nonvolatile memory during adjustment, while leaving the minimum number of the adjusted parameters necessary to access a system area of the storage medium at the end of the parameter adjustment, and saves the remaining adjusted parameters in the system area of the storage medium to form a free area in the parameter storage area of the nonvolatile memory. The free area processing module uses the free area of the nonvolatile memory as a storage area for firmware, a log or the like other than the parameters. | 2010-07-29 |
20100191906 | STORAGE CAPACITY MANAGEMENT SYSTEM IN DYNAMIC AREA PROVISIONING STORAGE - Provided is a capacity monitoring method used for a computer system including one or more application computers, one or more storage systems, and a management computer. The storage system includes a physical disk and a disk controller. In the capacity monitoring method, a storage area of the physical disk belongs to a storage pool, the storage system provides a volume, and the management computer monitors a used capacity of the storage pool, judges whether or not a storage capacity required for operating the application computer for a predetermined time period is present in the storage pool based upon an increasing speed of the used capacity of the storage pool to be monitored, and executes a predetermined process operation when the storage capacity required for operating the application computer for the predetermined time period is not present in the storage pool. Accordingly, the storage pool is properly operated and managed. | 2010-07-29 |
20100191907 | RAID Converter and Methods for Transforming a First RAID Array to a Second RAID Array Without Creating a Backup Copy - A system transforms data structures absent the need for a backup copy. The system transforms a first logical store in an initial logical arrangement to a desired logical arrangement where the data structures of the logical arrangements are different. The system uses a select sequence of data operations that moves data from its origin in the initial logical arrangement to a target location in the desired logical arrangement. The system generates and properly locates parity information when so desired. The system executes a subsequent data operation in accordance with an indication that the previous data operation was successful. Each subsequent data operation uses the source location from the previous data operation. A non-volatile memory element holds information concerning a present data operation to enable a rollback operation when a present data operation is unsuccessful. | 2010-07-29 |
20100191908 | Computer system and storage pool management method - Provided is a computer system comprising an application computer; a storage system which is coupled to the application computer, and which comprises at least one storage medium and a controller; and a management system which is coupled to the application computer and the storage system, and which comprises at least one computer. The management system monitors a capacity of the storage pool and transmits an allocation request to the storage system in a case where the capacity of the storage pool is equal to or smaller than a predetermined threshold value. The storage system allocates, in a case where the allocation request is received, a first logical storage area to the storage pool based on information included in the received allocation request. The management system displays information for judging whether or not the first certain logical storage area temporarily-allocated is to be associated with the storage pool. | 2010-07-29 |
20100191909 | Administering Registered Virtual Addresses In A Hybrid Computing Environment Including Maintaining A Cache Of Ranges Of Currently Registered Virtual Addresses - Administering registered virtual addresses in a hybrid computing environment that includes a host computer, an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining a cache of ranges of currently registered virtual addresses, the cache including entries associating a range of currently registered virtual addresses, a handle representing physical addresses mapped to the range of currently registered virtual addresses, and a counter; determining whether to register ranges of virtual addresses in dependence upon the cache of ranges of currently registered virtual addresses; and determining whether to deregister ranges of virtual addresses in dependence upon the cache of ranges of currently registered virtual addresses. | 2010-07-29 |
20100191910 | APPARATUS AND CIRCUITRY FOR MEMORY-BASED COLLECTION AND VERIFICATION OF DATA INTEGRITY INFORMATION - Apparatus and circuitry are provided for supporting collection and/or verification of data integrity information. A circuitry in a storage controller is provided for creating and/or verifying a Data Integrity Block (“DIB”). The circuitry comprises a processor interface for coupling with the processor of the storage controller. The circuitry also comprises a memory interface for coupling with a cache memory of the storage controller. By reading a plurality of Data Integrity Fields (“DIFs”) from the cache memory through the memory interface based on information received from the processor, the DIB is created in that each DIF in the DIB corresponds to a respective data block. | 2010-07-29 |
20100191911 | System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory - An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupled to external memory and to the on-chip communication network. The memory interface supports accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network. A portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon. | 2010-07-29 |
20100191912 | Systems and Methods for Memory Management on Print Devices - Systems and methods disclosed permit flexible optimization of printer cache memories by specify criteria for determining cache membership for objects derived from a print data streams, wherein the objects may be associated with distinct reference counts. In some embodiments, the method may comprise the steps of: assigning an initial value to the reference count associated with an object, if the object is not present in the cache; incrementing the reference count by a first weight, if the object is already present in the cache; decrementing the reference count by a second weight, in response to an end-of-page event; and removing the object from the cache if the reference count is below a threshold. | 2010-07-29 |
20100191913 | RECONFIGURATION OF EMBEDDED MEMORY HAVING A MULTI-LEVEL CACHE - A method of operating an embedded memory having (i) a local memory, (ii) a system memory, and (iii) a multi-level cache memory coupled between a processor and the system memory. According to one embodiment of the method, a two-level cache memory is configured to function as a single-level cache memory by excluding the level-two (L2) cache from the cache-transfer path between the processor and the system memory. The excluded L2-cache is then mapped as an independently addressable memory unit within the embedded memory that functions as an extension of the local memory, a separate additional local memory, or an extension of the system memory. | 2010-07-29 |
20100191914 | REGION COHERENCE ARRAY HAVING HINT BITS FOR A CLUSTERED SHARED-MEMORY MULTIPROCESSOR SYSTEM - A system and method for a multilevel region coherence protocol for use in Region Coherence Arrays (RCAs) deployed in clustered shared-memory multiprocessor systems which optimize cache-to-cache transfers (interventions) by using region hint bits in each RCA to allow memory requests for lines of a region of the memory to be optimally sent to only a determined portion of the clustered shared-memory multiprocessor system without broadcasting the requests to all processors in the system. A sufficient number of region hint bits are used to uniquely identify each level of the system's interconnect hierarchy to optimally predict which level of the system likely includes a processor that has cached copies of lines of data from the region. | 2010-07-29 |
20100191915 | SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DYNAMIC QUEUE SPLITTING FOR MAXIMIZING THROUGHPUT OF QUEUE BASED OPERATIONS WHILE MAINTAINING PER-DESTINATION ORDER OF OPERATIONS - A system for providing dynamic queue splitting to maximize throughput of queue entry processing while maintaining the order of queued operations on a per-destination basis. Multiple queues are dynamically created by splitting heavily loaded queues in two. As queues become dormant, they are re-combined. Queue splitting is initiated in response to a trigger condition, such as a queue exceeding a threshold length. When multiple queues are used, the queue in which to place a given operation is determined based on the destination for that operation. Each queue in the queue tree created by the disclosed system can store entries containing operations for multiple destinations, but the operations for a given destination are all always stored within the same queue. The queue into which an operation is to be stored may be determined as a function of the name of the operation destination. | 2010-07-29 |
20100191916 | Optimizing A Cache Back Invalidation Policy - A method and a system for utilizing less recently used (LRU) bits and presence bits in selecting cache-lines for eviction from a lower level cache in a processor-memory sub-system. A cache back invalidation (CBI) logic utilizes LRU bits to evict only cache-lines within a LRU group, following a cache miss in the lower level cache. In addition, the CBI logic uses presence bits to (a) indicate whether a cache-line in a lower level cache is also present in a higher level cache and (b) evict only cache-lines in the lower level cache that are not present in a corresponding higher level cache. However, when the lower level cache-line selected for eviction is also present in any higher level cache, CBI logic invalidates the cache-line in the higher level cache. The CBI logic appropriately updates the values of presence bits and LRU bits, following evictions and invalidations. | 2010-07-29 |
20100191917 | Administering Registered Virtual Addresses In A Hybrid Computing Environment Including Maintaining A Watch List Of Currently Registered Virtual Addresses By An Operating System - Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining, by an operating system, a watch list of ranges of currently registered virtual addresses; upon a change in physical to virtual address mappings of a particular range of virtual addresses falling within the ranges included in the watch list, notifying the system level message passing module by the operating system of the change; and updating, by the system level message passing module, a cache of ranges of currently registered virtual addresses to reflect the change in physical to virtual address mappings. | 2010-07-29 |
20100191918 | Cache Controller Device, Interfacing Method and Programming Method Using the Same - Disclosed are a cache controller device, an interfacing method and a programming method using the same. The cache controller device prefetching and supplying data distributed in a memory to a main processor, includes: a cache temporarily storing data in a memory block having a limited size; a cache controller circularly reading out the data from the memory block to a cache memory, or transferring the data from the cache memory to the cache; and a memory input/output controller controlling prefetching the data to the cache, or transferring the data from the cache to a memory. | 2010-07-29 |
20100191919 | APPEND-BASED SHARED PERSISTENT STORAGE - A shared storage system is described herein that is based on an append-only model of updating a storage device to allow multiple computers to access storage with lighter-weight synchronization than traditional systems and to reduce wear on flash-based storage devices. Appending data allows multiple computers to write to the same storage device without interference and without synchronization between the computers. Computers can also safely read a written page without using synchronization because the system limits how data can be changed once written. The system may record a log of append operations performed and ensure idempotence by storing a key specified by the caller in the log along with each log entry. The system also provides broadcasts about appended data to computers so that coordination between computers can occur without direct communication between the computers. | 2010-07-29 |
20100191920 | Providing Address Range Coherency Capability To A Device - In one embodiment, the present invention includes a method for receiving a memory request from a device coupled to an input/output (IO) interconnect, accessing a mapping table associated with the IO interconnect to determine if an address range including an address of the memory request is coherent, and if so, sending the memory request and a coherency indicator to indicate the coherent state of data at the address, otherwise sending the memory request and the coherency indicator to indicate a non-coherent state. Other embodiments are described and claimed. | 2010-07-29 |
20100191921 | REGION COHERENCE ARRAY FOR A MULT-PROCESSOR SYSTEM HAVING SUBREGIONS AND SUBREGION PREFETCHING - A Region Coherence Array (RCA) having subregions and subregion prefetching for shared-memory multiprocessor systems having a single-level, or a multi-level interconnect hierarchy architecture. | 2010-07-29 |
20100191922 | DATA STORAGE PERFORMANCE ENHANCEMENT THROUGH A WRITE ACTIVITY LEVEL METRIC RECORDED IN HIGH PERFORMANCE BLOCK STORAGE METADATA - A sequence of fixed-size blocks defines a page (e.g., in a server system, storage subsystem, DASD, etc.). Each fixed-size block includes a data block and a footer. A high performance block storage metadata unit associated with the page is created from a confluence of the footers. The confluence of footers has space available for application metadata. In an embodiment, the metadata space is utilized to record a “write activity level” metric, and a timestamp. The metric indicates the write frequency or “hotness” of the page, and its value changes over time as the activity level changes. Storage subsystem performance may be enhanced by mapping frequently accessed pages to higher performance physical disks and mapping infrequently accessed pages to lower power physical disks. This approach is advantageous in that the metric is recorded on a non-volatile basis and may be readily communicated between system components (e.g., between a host computer and a storage subsystem). | 2010-07-29 |
20100191923 | Data Processing In A Computing Environment - Methods, apparatus, and products for data processing in a computing environment including allocating, by an operating system for an application, a virtual address spaces with each virtual address space mapped to a same physical address space and each virtual address space associated with an operation; receiving, from the application, an instruction to store a value in a specific virtual address, the specific virtual address contained within one of the allocated virtual address spaces; identifying a physical address associated with the specific virtual address; performing, with the value and the contents of the identified physical address, the operation associated with the virtual address space containing the specific virtual address; and storing a result of the operation in the identified physical address. | 2010-07-29 |
20100191924 | METHOD AND SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING AMEMORY HUB ARCHITECTURE - A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules. | 2010-07-29 |
20100191925 | DEFERRED VOLUME METADATA INVALIDATION - A method, system, and computer program product for managing modified metadata in a storage controller cache pursuant to a recovery action by a processor in communication with a memory device is provided. A count of modified metadata tracks for a storage rank is compared against a predetermined criterion. If the predetermined criterion is met, a storage volume having the storage rank is designated with a metadata invalidation flag to defer metadata invalidation of the modified metadata tracks until after the recovery action is performed. | 2010-07-29 |
20100191926 | Remote copy system and path setting support method - A remote copy system includes: a host computer; a first storage system connected to the host computer; and a second storage apparatus connected to the first storage system. At least one of the first storage system and the second storage system holds, in a storage part thereof, path information used for performing a remote copy of data therebetween. The host computer references the path information in the storage part; determines whether or not a path required for conducting an operation instructed by a user exists, based on at least one of a type of the remote copy and a direction of the path; and, if the required path does not exist, displays, on a display part, that the necessary path does not exist and why the necessary path does not exist. | 2010-07-29 |
20100191927 | Method and Apparatus for Performing Volume Replication Using Unified Architecture - A method and apparatus for performing volume replication using a unified architecture are provided. Each volume has an exclusive volume log table (VLT) and an exclusive volume block update table (VBUT). The VLT is mainly used for recording the relationship between two volumes of a mirroring pair, and the VBUT is used for tracking the state of each data block of the volume itself. By means of the cross operations between the VLT and the VBUT, various volume replication processes such as volume copying and volume mirroring can be enabled under a unified architecture. Specifically, for each volume, different replication relationships with other volumes can be handled merely by administering its two exclusive tables. Hence, the method and apparatus provided by the present invention can advantageously simplify the architecture for synchronization replication and reduce the burdens of administrating tables, thereby making the operation of a storage system more efficient. | 2010-07-29 |
20100191928 | AUTOMATIC REGION-BASED VERIFICATION OF GARBAGE COLLECTORS - Systems and methods that add specifications to procedures in a garbage collector for indicating what each procedure does. Such annotations can be added in the source code, to indicate what the source code is to do when it runs—hence enabling an automatic verification of the garbage collector by a verification component. The specification can be presented as a logical formula that can be readily processed by a theorem prover, which is associated with the verification component. Such logical formulas can further employ regions to specify correctness of the garbage collector. | 2010-07-29 |
20100191929 | SYSTEM AND METHOD FOR RECLAIMING ALLOCATED MEMORY TO REDUCE POWER IN A DATA PROCESSING SYSTEM - A method of managing power in a data processing system includes monitoring a system parameter indicative of power consumption. Responsive to determining that the parameter differs from a specified threshold, a system guest, such as an operating system, is forced to release a portion of its allocated system memory. The portion of system memory released by the guest is then reclaimed by the system. The reclaimed system memory and the resulting decrease in allocated memory may enable the system to reduce system memory power consumption. The operating system may de-allocate a portion of system memory when a balloon code device driver executing under the operating system requests the operating system to allocate memory to it. The system memory allocated to the balloon device driver is then reclaimed by supervisory code such as a hypervisor. | 2010-07-29 |
20100191930 | TRANSACTIONAL MEMORY COMPATIBILITY MANAGEMENT - Transactional memory compatibility type attributes are associated with intermediate language code to specify, for example, that intermediate language code must be run within a transaction, or must not be run within a transaction, or may be run within a transaction. Attributes are automatically produced while generating intermediate language code from annotated source code. Default rules also generate attributes. Tools use attributes to statically or dynamically check for incompatibility between intermediate language code and a transactional memory implementation. | 2010-07-29 |
20100191931 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device includes performing a first LSB program operation on memory cells coupled to a selected word line in order to store least significant bit (LSB) data in the memory cells, performing a first most significant bit (MSB) program operation on the memory cells coupled to the selected word line, such that threshold voltages of the memory cells rise up to a temporary target voltage less than a target voltage, performing a second most significant bit (MSB) program operation on memory cells coupled to a neighboring word line neighboring the selected word line in order to store most significant bit (MSB) data in the corresponding memory cells, and performing a third most significant bit (MSB) program operation, after performing the second most significant bit (MSB) program operation, on the memory cells on which the first most significant bit (MSB) program operation has been performed, such that the threshold voltages of the memory cells coupled to the selected word line become higher than the target voltage. | 2010-07-29 |
20100191932 | ADDRESS GENERATION APPARATUS AND METHOD OF DATA INTERLEAVER/DEINTERLEAVER - Provided are an address generation apparatus and method of an interleaver/deinterleaver. By calculating coefficients of an address generator polynomial of an interleaver by determining exponents according to the number of prime factors forming a length of input data of the interleaver and generating an address of the deinterleaver using the calculated coefficients, errors generated when the address of the deinterleaver is generated can be removed, and right interleaver and deinterleaver addresses can be calculated. | 2010-07-29 |
20100191933 | APPARATUS FOR PROCESSING DATA AND METHOD FOR GENERATING MANIPULATED AND RE-MANIPULATED CONFIGURATION DATA FOR PROCESSOR - Some embodiments comprise an apparatus for processing data, the apparatus having a second configurable processor configured to process data using second configuration data, and a configuration data re-manipulator configured to retrieve manipulated second configuration data and first data of a first processor, to re-manipulate the manipulated second configuration data depending on the first data, and to feed the re-manipulated second configuration data to the second configurable processor as the second configuration data. | 2010-07-29 |
20100191934 | MICROCOMPUTER AND DIVIDING CIRCUIT - Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits. | 2010-07-29 |
20100191935 | Architecture and implementation method of programmable arithmetic controller for cryptographic applications - An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography. | 2010-07-29 |
20100191936 | Method and system for operating-system-independent power management using performance verifications - Systems and methods are disclosed for power management in information handling systems using processor performance data to validate changes to processor performance states. Processor utilization data and processor performance data is obtained during system operation. The processor utilization data is analyzed to determine a desired performance state for the processor. Before setting the actual performance state of the processor to this desired performance state, however, processor performance data is analyzed to determine if prior changes to the performance state have been effective. The performance state of the processor is then changed are maintained based upon this additional performance verification analysis. | 2010-07-29 |
20100191937 | Implied Storage Operation Decode Using Redundant Target Address Detection - A logic arrangement and method to support implied storage operation decode uses redundant target address detection, whereby target addresses of previous instructions are compared with the target address of the current instruction, and if equal, and the target addresses of previous instructions are not used as sources, the current instruction is decoded as a store instruction. This allows a redundant operation in an instruction set architecture to be redefined as a store instruction, freeing up opcodes normally used for store instructions to be used for other instructions. | 2010-07-29 |
20100191938 | INFORMATION PROCESSING DEVICE, ARITHMETIC PROCESSING METHOD, ELECTRONIC APPARATUS AND PROJECTOR - An information processing device including: a first arithmetic processing unit performing first arithmetic processing; a second arithmetic processing unit performing second arithmetic processing; input registers adapted to include a first input register allocated to the first arithmetic processing unit, and a second input register allocated to the second arithmetic processing unit; and output registers storing a processing results of the first arithmetic processing unit and a processing results of the second arithmetic processing unit, in each of given execution cycles, the first arithmetic processing unit performs the first arithmetic processing using stored data of the first input register and stores a processing result of the first arithmetic processing in the output registers and the second arithmetic processing unit performs the second arithmetic processing using stored data of the second input register and stores a processing result of the second arithmetic processing in the output registers. | 2010-07-29 |
20100191939 | TRIGONOMETRIC SUMMATION VECTOR EXECUTION UNIT - A unique instruction and exponent adjustment adder selectively shift outputs from multiple execution units, including a plurality of multipliers, in a processor core in order to scale mantissas for related trigonometric functions used in a vector dot product. | 2010-07-29 |
20100191940 | SINGLE STEP MODE IN A SOFTWARE PIPELINE WITHIN A HIGHLY THREADED NETWORK ON A CHIP MICROPROCESSOR - A hardware thread is selectively forced to single step the execution of software instructions from a work packet granule. A “single step” packet is associated with a work packet granule. The work packet granule, with the associated “single step” packet, is dispatched as an appended work packet granule to a preselected hardware thread in a processor core, which, in one embodiment, is located at a node in a Network On a Chip (NOC). The work packet granule then executes in a single step mode until completion. | 2010-07-29 |
20100191941 | FAILURE ANALYSIS APPARATUS, METHOD - A debugger is operated in a host PC, and in response to operation of the debugger, first and second microprocessors execute an identical debug operation in parallel via first and second debug I/F devices. The host PC obtains internal information (dump results) from the first and second microprocessors via the first and second debug I/F devices and compares internal information (dump results) from the first and second microprocessors to perform failure analysis. | 2010-07-29 |
20100191942 | Information processor and control method - A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction. | 2010-07-29 |
20100191943 | COORDINATION BETWEEN A BRANCH-TARGET-BUFFER CIRCUIT AND AN INSTRUCTION CACHE - A digital signal processor (DSP) having (i) a processing pipeline for processing instructions received from an instruction cache (I-cache) and (ii) a branch-target-buffer (BTB) circuit for predicting branch-target instructions corresponding to received branch instructions. The DSP reduces the number of I-cache misses by coordinating its BTB and instruction pre-fetch functionalities. The coordination is achieved by tying together an update of branch-instruction information in the BTB circuit and a pre-fetch request directed at a branch-target instruction implicated in the update. In particular, if an update of the branch-instruction information is being performed, then, before the branch instruction implicated in the update reenters the processing pipeline, the DSP initiates a pre-fetch of the corresponding branch-target instruction. | 2010-07-29 |
20100191944 | DATA STORAGE APPARATUS - According to one embodiment, a data storage apparatus includes: a storage element including a user data storage area and an area for storing multiplexed pre-boot authentication applications; and a controller connected to a host and performs read/write access to the user data area when an authentication by the pre-boot authentication application is verified. The controller determines whether the data storage apparatus is connected to the host in a form in which the host performs time-out monitoring or the data storage apparatus is connected to the host in a form in which the host does not perform the time-out monitoring. The controller performs, when the controller determines that the data storage apparatus is connected to the host in the form in which the host does not perform the time-out monitoring, mirroring synchronization of the multiplexed pre-boot authentication applications at the time of booting. | 2010-07-29 |
20100191945 | PORTABLE DEVICE WITH USER INTERFACE - A portable device ( | 2010-07-29 |