30th week of 2010 patent applcation highlights part 42 |
Patent application number | Title | Published |
20100190240 | REAGENTS FOR NUCLEIC ACID PURIFICATION - Embodiments of the present invention provide methods and kits for purifying nucleic acids. In particular, embodiments of the present invention provide methods and kits for purifying nucleic acids through the use of magnetic particles in binding buffers. | 2010-07-29 |
20100190241 | Bioactive carbon dioxide filter apparatus and method therefor - A bioactive filter is provided which comprises a transparent canister having gas permeable membranes as entry and exit ports. A source of carbon dioxide in gaseous form is allowed to enter the entry membrane and pass through a solution contained in the canister which supports a live colony of algae. The algae carries out photosynthesis thereby altering the carbon dioxide to oxygen and sugar. The oxygen is released through the exit port. | 2010-07-29 |
20100190242 | System for division of a volume of liquid into drops and subsequent drop recollection - We describe a system for the division or partition of a volume of fluid into droplets of assigned size and subsequent recollection of the drops. | 2010-07-29 |
20100190243 | siRNA-MEDIATED GENE SILENCING WITH VIRAL VECTORS - The present invention is directed to viral vectors encoding small interfering RNA molecules (siRNA) targeted against a gene of interest, and methods of using these viral vectors. | 2010-07-29 |
20100190244 | RIBOSWITCHES, METHODS FOR THEIR USE, AND COMPOSITIONS FOR USE WITH RIBOSWITCHES - It has been discovered that certain natural mRNAs serve as metabolite-sensitive genetic switches wherein the RNA directly binds a small organic molecule. This binding process changes the conformation of the mRNA, which causes a change in gene expression by a variety of different mechanisms. Modified versions of these natural “riboswitches” (created by using various nucleic acid engineering strategies) can be employed as designer genetic switches that are controlled by specific effector compounds. Such effector compounds that activate a riboswitch are referred to herein as trigger molecules. The natural switches are targets for antibiotics and other small molecule therapies. In addition, the architecture of riboswitches allows actual pieces of the natural switches to be used to construct new non-immunogenic genetic control elements, for example the aptamer (molecular recognition) domain can be swapped with other non-natural aptamers (or otherwise modified) such that the new recognition domain causes genetic modulation with user-defined effector compounds. The changed switches become part of a therapy regimen—turning on, or off, or regulating protein synthesis. Newly constructed genetic regulation networks can be applied in such areas as living biosensors, metabolic engineering of organisms, and in advanced forms of gene therapy treatments. | 2010-07-29 |
20100190245 | METHOD TO INCREASE DISSOLVED OXYGEN IN A CULTURE VESSEL - Basing on study of a previous discovered effective bioreactor system, a method to increase culture medium dissolved oxygen is disclosed. This method together with addition of an optimal mixing forms a theoretical foundation for effective bioreactor design and prototype construction. | 2010-07-29 |
20100190246 | METHOD FOR PREPARING BIOLOGICAL TISSUE - This invention provides a method for obtaining biological tissue having a three-dimensional structure of interest. The method of the invention comprises: adding a cell-containing culture solution to a culture vessel having an inner bottom surface, which is non-cell adhesive and comprises a concave-convex pattern provided thereon; performing cell culture under conditions in which intercellular adhesion takes place while centrifugal or magnetic force toward the inner bottom surface is applied to the cells that were added to the culture vessel to form tissue via intercellular adhesion; and detaching and collecting the resulting tissue from the inner bottom surface at the end in order to obtain tissue having a three-dimensional configuration using a concave-convex pattern as a template. | 2010-07-29 |
20100190247 | Methods of Generating Variant Proteins with Increased Host String Content - The present invention relates to novel methods for generating variant proteins with increased host string content, and proteins that are engineered using these methods. | 2010-07-29 |
20100190248 | Methods for the Cryopreservation of Animal Cells that Contain High Levels of Intracellular Lipids - A method for cryopreservation of animal cells with high level of intracellular lipid content, comprises the steps of conducting a delipation procedure using one or more lipolytic agent(s) and/or lipogenesis inhibitors during culture of the animal cells to stimulate the hydrolysis of intracellular lipids to reduce the lipid content, and vitrifying the treated animal cells using a modified vitrification solution and a modified warming solution. | 2010-07-29 |
20100190249 | METHOD AND DEVICE FOR FORMING A THREE-DIMENSIONAL ARRANGEMENT OF BIOLOGICAL CELLS - A method for forming a three-dimensional cell arrangement ( | 2010-07-29 |
20100190250 | Methods of Rejuvenating Cells In Vitro and In Vivo - The present invention provides methods for rejuvenating cells, tissues and the whole body. Also provided are rejuvenating buffers and agents as well as kits for rejuvenating cells. Also provided are methods for dedifferentiating somatic cells and differentiating the cells into other cell types. | 2010-07-29 |
20100190251 | Method for the differentiation of human adult stem cells into insulin-secreting cells - Disclosed is a method for differentiating human adult stem cells into insulin-secreting cells. Human adult stem cells, isolated from the subcutaneous adipose tissues around the eyes, are induced to differentiate into insulin-secreting cells in a medium in the presence of cytokines and growth factors including B27 supplement, fibroblast growth factor-2, epidermal growth factor, nicotinamide, glucagon-like peptide-1, activin A, insulin-like growth factor, betacellulin, etc., with a glucose shift from a high concentration to a low concentration. Having the ability to producing insulin and C-peptide at high levels, the insulin-secreting cells can be excellent curatives for type 1 diabetes mellitus. | 2010-07-29 |
20100190252 | METHODS FOR THE PREPARATION OF FIBROBLASTS - The invention relates to a process for generating fibroblasts, more particularly, to the culturing of fibroblasts in large numbers and of the heterogenic type. The invention is also directed to the use of fibroblasts in the preparation of heterotypic spheroids and a process for the preparation of such heterotypic spheroids. | 2010-07-29 |
20100190253 | CELL CULTURE CONTAINER AND CELL CULTURE METHOD - To provide a cell culture chamber and a cell culture method that are capable of effectively constructing an intercellular network in a culture space. A cell culture chamber ( | 2010-07-29 |
20100190254 | THREE-DIMENSIONAL POROUS HYBRID SCAFFOLD AND MANUFACTURE THEREOF - The present invention refers to a three-dimensional porous hybrid scaffold for tissue engineering and methods of its manufacture and use. | 2010-07-29 |
20100190255 | CROSS-LINKED GUMS FOR HEPATOCYTE CULTURE - This disclosure relates to cell culture surfaces derived from or contain gums including naturally occurring gums, plant gums, galactomannan gums or derivatives thereof including carboxyalkyl guar gum. Even more particularly, the disclosure relates to chemically or physically cross-linked modified gums where the gum surfaces are tuned to provide cell culture surfaces with physical and chemical characteristics particularly suited for hepatocyte culture. The disclosure also relates to articles of manufacture (e.g., cell culture vessels and labware) having such matrices, methods of making and providing the matrices to cell culture surfaces, and methods of using cell culture vessels having such matrices. | 2010-07-29 |
20100190256 | METHOD FOR CULTURING MAMMALIAN TASTE CELLS - The invention provides methods of culturing mammalian taste cells, including taste receptor cells. Cells are maintained for a duration of up to three months and longer while maintaining molecular and functional characteristics of mature taste cells. The cells are cultured on coated cell culture vessels and, from first replacement of medium onwards, the medium is replaced in intervals of at least 5 days. The invention further provides isolation and culturing methods of taste cells wherein the time that the cells are exposed to isolation solution and proteolytic enzymes is minimized and the cells are cultured in coated culture vessels with the medium replaced in intervals of at least 5 days from first replacement onwards. The invention further provides cultured taste cells, transfection and assay methods, and taste cell assay buffers with an osmolarity of about 300-320 and pH of about 7.0-7.3. | 2010-07-29 |
20100190257 | Self-Assembly of a Cell-Microparticle Hybrid - The present invention provides a fabrication method for the formation of a cell-microparticle hybrid. A biotin-avidin binding system also employs the use of a biodegradable polymer and any cell type that self-assemble to form a hybrid system. | 2010-07-29 |
20100190258 | METHOD OF PRODUCING RECOMBINANT BIOLOGICAL PRODUCTS - A method of producing a recombinant biological product, which method employs a mammalian producer cell culture, comprises the steps of generating a biomass of mammalian producer during an initial phase of cell culture, and causing an increase in a level of one or more of the miRNA molecules of Table 1 within the mammalian producer cells once a desired concentration of mammalian producer cells has been achieved. The method may also comprise the step of increasing a level of an inhibitor of one or more of the miRNA molecules of Table 1 within the mammalian producer cells at the start of or during an initial phase of culture. | 2010-07-29 |
20100190259 | Ethanol Production - The present invention relates to the production of ethanol as a product of bacterial fermentation. In particular this invention relates to a novel method of gene inactivation and gene expression based upon homologous recombination. The method is particularly useful in connection with species of | 2010-07-29 |
20100190260 | METHOD FOR IDENTIFYING NAPHTHENATES IN A HYDROCARBON CONTAINING LIQUID - A method for quantifying the presence of naphthenic acids in a hydrocarbon-comprising liquid that includes: contacting a hydrocarbon-comprising liquid with gaseous ammonia; isolating a reaction product produced by the contacting step; and analyzing the reaction product for the presence of naphthenates using a mass spectrometry technique. The naphthenic acids known to form commercial naphthenate deposits can be (i) ions of tetraprotic carboxylic acids having molecular weights ranging from 1225 to 1270 Daltons, (ii) n-alkyl or branched carboxylic acids having molecular weights ranging from 250 to 650 Daltons, or (iii) both. | 2010-07-29 |
20100190261 | PROTEIN ANALYSIS METHOD USING ISOTOPE COMPOUND AS LABEL - The present invention provides a protein analysis method using a combination of two or more kinds of stable isotopes of a compound represented by the formula (I): | 2010-07-29 |
20100190263 | Bubble Techniques for a Droplet Actuator - The present invention is directed to a droplet actuator and methods of making and using the droplet actuator including one or more substrates configured to form a droplet operations gap and including a physical or chemical feature that may be provided at a predetermined locus within or exposed to the droplet operations gap and configured to retain a bubble in position within the droplet operations gap. | 2010-07-29 |
20100190264 | Genetic Variants Increase the Risk of Age-Related Macular Degeneration - Age-related macular degeneration (AMD) is a leading cause of visual impairment and blindness in the elderly whose etiology remains largely unknown. Previous studies identified chromosome 1q32 as harboring a susceptibility locus for AMD, but it was not identified. We identified a strongly associated haplotype in two independent data sets. DNA sequencing of the complement factor II gene (CHI) within this haplotype revealed a coding variant, Y402II, that significantly increases the risk for AMD with odds ratios between 2.45 and 5.57. This identifies Complement factor II as involved in pathogenesis of AMD. This single variant alone is so common that it likely explains 43 percent of AMD in older adults. In addition, we have replicated and refined previous reports implicating a coding change in LOC387715 as the second major AMD susceptibility allele. The effect of rs10490924 appears to be completely independent of the Y402II variant in the CFH gene. The joint effect of these two susceptibility genes is consistent with a multiplicative model, and together, they may explain as much as 65% of the PAR of AMD. In contrast, the effect of rs10490924 appears to be strongly modified by cigarette smoking. Smoking and LOC387715 together may explain as much as 34% of AMD. Our data indicate that variant genotypes at rs10490924 confer a substantially larger AMD risk to cigarette smokers than non-smokers. This observation is supported by traditional case-control modeling, by ordered subset linkage analysis (OSA) incorporating pack-years of cigarette smoking as a covariate, and by family-based association analysis using a more homogeneous set of families as defined by OSA. | 2010-07-29 |
20100190265 | FLUIDICS DEVICE FOR ASSAY - The present invention relates to a device for use in performing assays on standard laboratory solid supports whereon chemical entities are attached. The invention furthermore relates to the use of such a device and a kit comprising such a device. The device according to the present invention is adapted to receive one or more replaceable solid support(s) (40) onto which chemical entities ( | 2010-07-29 |
20100190266 | METHOD FOR MEASURING BONDING ACTIVITY OF ANTIBODY WHICH MIMICS ANTIBODY-DEPENDENT CELL MEDICATED CYTOTOXIC ACTIVIY - The present invention provides a simple method which is capable of evaluating the binding activities of an antibody to both an antigen and an Fc receptor. | 2010-07-29 |
20100190267 | Miniature Chemical Analysis System - An apparatus, according to one aspect, may include a chromatograph and a bulk acoustic resonator. The chromatograph may include a channel that is defined at least partially in a monolithic substrate. The channel may have an inlet to receive a sample and an outlet. A chromatography material may be included in the channel. The bulk acoustic resonator may have a first electrode and a second electrode that has a chemically functionalized surface. The chemically functionalized surface may be included in a chamber that is defined at least partially in the monolithic substrate and that is coupled with the outlet of the channel. Methods of making and using such apparatus, and systems including such apparatus, are also disclosed. | 2010-07-29 |
20100190268 | Assay Device, System and Method - A system for treating a blood sample ( | 2010-07-29 |
20100190269 | DEVICE, SYSTEM AND METHOD OF DETECTING TARGETS IN A FLUID SAMPLE - The present invention provides a biochemical detection system that comprises an exchangeable cartridge unit with light guiding tubes pre-coated with capture agent(s) and an optical detection unit. Upon flowing the liquid or gaseous sample containing the target(s) through the cartridge unit, the target(s) bind(s) to the capture agent(s) and is (are) detected by the amount of light or the variation of its properties while guided through the tubes. The optical detection unit is comprised of a light emitting element(s), a light connecting element(s) and a light detecting element(s) that delivers the amount of target(s) in the sample under investigation. | 2010-07-29 |
20100190270 | SYSTEM AND METHODS FOR DETECTING A GASEOUS ANALYTE IN A GAS - Systems and methods for detecting a gaseous analyte utilize a micromechanical piezoelectric resonator having a functionalization layer configured to bind with the gaseous analyte. The functionalization layer may include a layer of carbon nanotubes affixed to the resonator and coated with biopolymers configured to bind with the gaseous analyte. The gaseous analyte may be detected by operating the micromechanical piezoelectric resonator and functionalization layer in the presence of the gas, detecting a change in the resonant frequency of the resonator, and determining the concentration of the gaseous analyte from the change in resonant frequency. Finally, the layer of carbon nanotubes may be grown on the piezoelectric resonator by depositing a catalyst on a piezoelectric structure, heating the piezoelectric structure and the catalyst to enhance the growth of the carbon nanotubes, and growing the carbon nanotubes at growth sites on the piezoelectric structure. | 2010-07-29 |
20100190271 | METHODS USING NOVEL CHEMILUMINESCENT LABELS - Methods using chemiluminescent label compounds and chemiluminescent labeled conjugates are provided. The compounds comprise an acridan ring bearing an exocyclic ketene dithioacetal group and further contain a labeling substituent which permits attachment to compounds of interest. The novel chemiluminescent compounds and labeled conjugates are convenient to prepare, are highly stable, and generate chemiluminescence rapidly on demand. The compounds and conjugates are useful in assays of an analyte in a sample and in assays employing labeled specific binding pairs. | 2010-07-29 |
20100190272 | REWORK METHOD OF METAL HARD MASK - A rework method of a metal hard mask layer is provided. First, a material layer is provided. A dielectric layer, a first metal hard mask layer, and a patterned first dielectric hard mask layer have been sequentially formed on the material layer. There is a defect on a region of the first metal hard mask layer, and therefore the region of the first metal hard mask layer is not able to be patterned. After that, the patterned first dielectric hard mask layer and the first metal hard mask layer are removed. A planarization process is then performed on the dielectric layer. Next, a second metal hard mask layer and a second dielectric hard mask layer are sequentially formed on the dielectric layer. | 2010-07-29 |
20100190273 | METHOD FOR MANUFACTURING HIGH-FREQUENCY SIGNAL TRANSMISSION CIRCUIT AND HIGH-FREQUENCY SIGNAL TRANSMISSION CIRCUIT DEVICE - A method for manufacturing a high-frequency signal transmission circuit includes the steps of forming a groove to surround a first region on a semiconductor substrate, filling the groove with a stopper material, forming a high-frequency transmission line on the semiconductor substrate so that the transmission line extends over the first region, and etching the first region of the semiconductor substrate using the stopper material as an etching stopper to form a recess in the first region. | 2010-07-29 |
20100190274 | RTP SPIKE ANNEALING FOR SEMICONDUCTOR SUBSTRATE DOPANT ACTIVATION - A semiconductor substrate has a plurality of active device patterns. At least some of the active device patterns comprise doped regions. The substrate has a plurality of surface regions, including the active device patterns and un-patterned regions, with respectively different reflectances for light in a near infrared wavelength. A first difference is determined, between a largest reflectance at the near infrared wavelength and a smallest reflectance at the near infrared wavelength. A second infrared wavelength is determined, for which a second difference between a largest reflectances a smallest reflectance is substantially less than the first difference at the near infrared wavelength. A rapid thermal processing (RTP) spike annealing dopant activation step is performed on the substrate using a second light source providing light at the second wavelength. | 2010-07-29 |
20100190275 | SCRIBING DEVICE AND METHOD OF PRODUCING A THIN-FILM SOLAR CELL MODULE - A laser scribing device is provided which comprises at least a laser light source. The laser light source may generate a laser beam for scribing cell lines to form a patterned solar cell module. Furthermore, the laser may emit a light beam for generating a light spot on the surface of the solar cell module. The light beam may be modulated compared with the light beam used for the scribing process. By means of the light spot a particular region of the active area of the solar cell module may be illuminated, and the voltage V | 2010-07-29 |
20100190276 | METHOD AND APPARATUS FOR IRRADIATING LASER - A laser irradiation process includes: scanning a substrate with laser having a predetermined lasing frequency at different irradiation intensities to form a plurality of first irradiation areas corresponding to the irradiation intensities; illuminating the first irradiation areas to reflected light receive from the first irradiation areas; determining microcrystallization intensity based on the received reflected light; and determining irradiation intensity based on the thus determined microcrystallization intensity. The laser irradiation process uses the irradiation intensity for irradiating a polycrystalline film in a product semiconductor device. | 2010-07-29 |
20100190277 | Power Network Stacked Via Removal For Congestion Reduction - A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded. | 2010-07-29 |
20100190278 | TESTING FOR CORRECT UNDERCUTTING OF AN ELECTRODE DURING AN ETCHING STEP - A probe electrode structure on a substrate is described, comprising a first probe electrode and a neighboring second probe electrode on a layer sequence that generally includes, in a direction from the substrate to the probe electrodes, an electrically conductive bottom layer, an electrically insulating center layer and a electrically conductive top layer. The probe-electrode structure of the invention provides a means to detect an undercutting of the first probe electrode in an etching step that aims at removing the top layer from regions outside the first probe electrode. An undercutting that exceeds an admissible distance from the first edge of the first electrode will remove the first top-layer probe section in the first probe opening, which causes a detectable change of the electrical resistance between the first and second probe electrodes. | 2010-07-29 |
20100190279 | LIGHT EMITTING DEVICE - Methods of making a light emitter are disclosed herein. An embodiment of a method comprises fabricating a line of first leads, the line of first leads comprising a plurality connected individual first leads; fabricating a line of second leads, the line of second leads comprising a plurality of connected individual second leads; physically connecting the line of first leads to the line of second leads, wherein a first individual first lead is adjacent a first individual second lead; attaching a light emitting device to the first individual first lead; electrically connecting the light emitting device to the first individual second lead; encapsulating a portion of the individual first lead and a portion of the individual second lead as a single unit; and separating the encapsulated first individual lead and the second individual lead from the first line of leads and the second line of leads. | 2010-07-29 |
20100190280 | MANUFACTURING METHOD OF LIGHT-EMITTING DIODE - A manufacturing method of an LED comprises attaching an LED epitaxial wafer (LED wafer) to an expanding tape, dicing the LED wafer on the expanding tape longitudinally and laterally to a certain element size to divide into a plurality of LED elements, expanding the expanding tape to a certain size to form an enlarged expanding tape, placing respective pairs of element electrodes of the plurality of LED elements that are attached to the enlarged expanding tape on respective pairs of electrodes on a printed-circuit board assembly collectively to perform a bonding, and removing the enlarged expanding tape from the plurality of the LED elements. | 2010-07-29 |
20100190281 | ORGANIC ELECTROLUMINESCENT DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - An organic electroluminescent device including an organic thin-film transistor element having at least an active layer made of an organic material; and an organic electroluminescent element driven by the organic thin-film transistor element. | 2010-07-29 |
20100190282 | METHOD FOR MANUFACTURING MULTIPLE-WAVELENGTH SEMICONDUCTOR LASER - A method for manufacturing a multiple-wavelength semiconductor laser comprises: forming a first bar having an array of first semiconductor chips, wherein at least two semiconductor lasers producing light of different wavelengths are monolithically formed; forming a second bar having an array of second semiconductor chips, wherein a semiconductor laser producing light having a different wavelength from the light produced by the semiconductor lasers of the first semiconductor chips is formed; forming a third bar by locating a laser-forming surface of said first bar facing a back surface of the second bar, and joining respective first semiconductor chips in the first bar to respective second semiconductor chips in the second bar; forming scribe lines by irradiating boundaries of the first semiconductor chips and boundaries of the second semiconductor chips with laser beams, and dividing the third bar along the scribe lines into respective chips. | 2010-07-29 |
20100190283 | METHOD TO FORM SEMICONDUCTOR LASER DIODE WITH MESA STRUCTURE BURIED BY CURRENT BLOCKING LAYER - A method to form a an LD with the buried mesa type is disclosed, in which the n-type current blocking layer is stably kept with a distance to the active layer in the buried mesa. The method of the invention includes a step to form the mesa by iterating the RIE and the ashing to obtain in a mesa side a steep edge with the (110) surface. A wet-etching process subsequent to the iterative etching and ashing removes residuals left on the mesa side. Then, the growth of the current blocking layer shows two modes of the horizontal growth of the (110) surface and the vertical growth of the (001) surface comparably. | 2010-07-29 |
20100190284 | METHOD OF FABRICATING NITRIDE-BASED SEMICONDUCTOR OPTICAL DEVICE - In the method of fabricating a nitride-based semiconductor optical device by metal-organic chemical vapor deposition, a barrier layer is grown at a first temperature while supplying a gallium source to a reactor. The barrier layer comprises a first gallium nitride-based semiconductor. After the growth of the barrier layer, a nitrogen material and an indium material are supplied to the reactor without supply of the gallium source to perform a preflow of indium. Immediately after the preflow, a well layer is grown on the barrier layer at a second temperature while supplying an indium source and the gallium source to the reactor. The well layer comprises InGaN, and the second temperature is lower than the first temperature. The gallium source and the indium source are supplied to the reactor during plural first periods of the step of growing the well layer to grow plural InGaN layers, respectively. The indium material is supplied to the reactor without supply of the gallium source during the second period of the step of growing the well layer. The second period is between the first periods. The well layer comprises the plural InGaN layers. | 2010-07-29 |
20100190285 | MICROELETROMECHANICAL SYSTEMS HAVING STORED CHARGE AND METHODS FOR FABRICATING AND USING SAME - Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed in a chamber. Various structures may be disposed in the chamber and employed in supplying, storing and/or trapping charge on the mechanical structure. In some aspects, a breakable link, a thermionic electron source and/or a movable mechanical structure are employed. The breakable link may comprise a fuse. In one embodiment, the movable mechanical structure is driven to resonate. In some aspects, the electrical charge enables a transducer to convert vibrational energy to electrical energy, which may be used to power circuit(s), device(s) and/or other purpose(s). In some aspects, the electrical charge is employed in changing the resonant frequency of a mechanical structure and/or generating an electrostatic force, which may be repulsive. | 2010-07-29 |
20100190286 | METHOD FOR MANUFACTURING SOLAR CELL - Disclosed is a method for manufacturing a solar cell, which includes the steps of: applying a first diffusing agent containing n-type impurities and a second diffusing agent containing p-type impurities onto a semiconductor substrate; forming a protective layer covering at least one of the first diffusing agent and the second diffusing agent; and diffusing at least one of the n-type impurities and the p-type impurities in a surface of the semiconductor substrate by heat treatment of the semiconductor substrate having the protective layer formed thereon. | 2010-07-29 |
20100190287 | SEMICONDUCTOR IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - A semiconductor image sensor includes: a semiconductor imaging element including an imaging area, a peripheral circuit area, and an electrode area; cylindrical electrodes provided on electrode terminals so as to be electrically connected with an external device; and a transparent resin layer provided on the upper surface of the semiconductor imaging element. The upper surface of each cylindrical electrode and the upper surface of the transparent resin layer are substantially of the same height. | 2010-07-29 |
20100190288 | THIN SILICON OR GERMANIUM SHEETS AND PHOTOVOLATICS FORMED FROM THIN SHEETS - Thin semiconductor foils can be formed using light reactive deposition. These foils can have an average thickness of less than 100 microns. In some embodiments, the semiconductor foils can have a large surface area, such as greater than about 900 square centimeters. The foil can be free standing or releasably held on one surface. The semiconductor foil can comprise elemental silicon, elemental germanium, silicon carbide, doped forms thereof, alloys thereof or mixtures thereof. The foils can be formed using a release layer that can release the foil after its deposition. The foils can be patterned, cut and processed in other ways for the formation of devices. Suitable devices that can be formed form the foils include, for example, photovoltaic modules and display control circuits. | 2010-07-29 |
20100190289 | SOLID-STATE IMAGING DEVICE - An n/p semiconductor substrate is formed in such a manner that an n type semiconductor layer is deposited on a p | 2010-07-29 |
20100190290 | SOLAR CELL PATTERNING AND METALLIZATION - Embodiments of the present invention generally provide methods for forming conductive structures on the surfaces of a solar cell. In one embodiment, conductive structures are formed on the front surface of a solar cell by depositing a sacrificial polymer layer, forming patterned lines in the sacrificial polymer via a fluid jet, depositing metal layers over the front surface of the solar cell, and performing lift off of the metal layers deposited over the sacrificial polymer by dissolving the sacrificial polymer with a water based solvent. In another embodiment, conductive structures are formed on the back surface of a solar cell by depositing a sacrificial polymer layer, forming patterned lines in the sacrificial polymer via a fluid jet, depositing a metal layer over the back surface of the solar cell, and performing lift off of the metal layer deposited over the sacrificial polymer by dissolving the sacrificial polymer with a water based solvent, and completing selective metallization of the remaining metal lines. | 2010-07-29 |
20100190291 | Semiconductor memory device with three dimensional solid electrolyte structure, and manufacturing method thereof - The semiconductor memory device includes a variable resistance device having a solid electrolyte in a three-dimensional structure. The variable resistance device includes a first electrode; the solid electrolyte, which has at least two regions with different heights, formed on the first electrode; and a second electrode made of a conductive material formed on the solid electrolyte to cover the regions with different heights. In addition, a multibit semiconductor memory device is provided which includes a bias circuit that can control the intensity of a current and time the current is supplied to the variable resistance device inside a memory cell in multiple steps to configure multibits. | 2010-07-29 |
20100190292 | METHOD FOR THE PREPARATION OF GROUP IB-IIIA-VIA QUATERNARY OR HIGHER ALLOY SEMICONDUCTOR FILMS - This invention relates to a method for producing group IB-IIIA-VIA quaternary or higher alloy semiconductor films wherein the method comprises the steps of (i) providing a metal film comprising a mixture of group IB and group IIIA metals; (ii) heat treating the metal film in the presence of a source of a first group VIA element (said first group VIA element hereinafter being referred to as VIA | 2010-07-29 |
20100190293 | Manufacturing Method of Semiconductor Device - The present invention has been achieved reflecting such situation, and its object is to provide a manufacturing method of a semiconductor device capable of continuously performing the mounting process which applies a so-called DBG process and a flip chip bonding method, and can contribute to simplify the manufacturing process and to improve the reliability with no void in the product. The manufacturing method of a semiconductor device according to the present invention comprises:
| 2010-07-29 |
20100190294 | METHODS FOR CONTROLLING WAFER AND PACKAGE WARPAGE DURING ASSEMBLY OF VERY THIN DIE - Various exemplary embodiments provide materials and methods for flip-chip packaging a thin TSV semiconductor die, which uses other packaging components, for example, a second die, as a packaging carrier to attach the thin TSV semiconductor die to a package substrate. Warpage and mis-alignment can be reduced or eliminated during the packaging process of the thin TSV die. | 2010-07-29 |
20100190295 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes the steps of: (a) providing a support including a plane having a first region for mounting a chip thereon and a second region provided around the first region; (b) forming an insulating resin layer in a semi-curing state on the plane; (c) forming, on the insulating resin layer, a first opening portion for exposing the first region; (d) fitting a chip in the first opening portion to mount the chip on the first region; and (e) completely curing the insulating resin layer after the step (d). | 2010-07-29 |
20100190296 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method of manufacturing a semiconductor device in which a thinned substrate of a semiconductor or semiconductor device is handled without cracks in the substrate and treated with heat to improve a contact between semiconductor back surface and metal in a high yield and a semiconductor device may be manufactured in a high yield. In the method of manufacturing a semiconductor device according to the present invention, a notched part is formed from a surface to a middle in a semiconductor substrate by dicing and the surface of the substrate is fixed to a support base. Next, a back surface of the substrate is ground to thin the semiconductor substrate and then a metal electrode and a carbon film that is a heat receiving layer are sequentially formed on the back surface of the substrate. Next, the carbon film is irradiated with light at a power density of 1 kW/cm | 2010-07-29 |
20100190297 | METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE HEAT SPREADER AND A CAVITY IN THE POST - A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a substrate on the adhesive including aligning the post with an aperture in the substrate, then flowing the adhesive into and upward in a gap located in the aperture between the post and the substrate, solidifying the adhesive, then etching the post to form a cavity in the post, then mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base and the semiconductor device extends into the cavity, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader. | 2010-07-29 |
20100190298 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base. | 2010-07-29 |
20100190299 | Semiconductor Device with Two or More Bond Pad Connections for Each Input/Output Cell and Method of Manufacture Thereof - A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least second bond pads, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component. | 2010-07-29 |
20100190300 | METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BASE HEAT SPREADER AND A CAVITY IN THE BASE - A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a substrate on the adhesive including aligning the post with an aperture in the substrate, then flowing the adhesive into and upward in a gap located in the aperture between the post and the substrate, solidifying the adhesive, then etching the post and the base to form a cavity that extends through the adhesive into the base, then mounting a semiconductor device on the base, wherein a heat spreader includes the base and the semiconductor device extends into the cavity, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader. | 2010-07-29 |
20100190301 | CAVITY CLOSURE PROCESS FOR AT LEAST ONE MICROELECTRONIC DEVICE - A process for closure of at least one cavity intended to encapsulate or be part of a microelectronic device, comprising the following steps:
| 2010-07-29 |
20100190302 | Electronic Packages with Fine Particle Wetting and Non-Wetting Zones - Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics. | 2010-07-29 |
20100190303 | Semiconductor device having sufficient process margin and method of forming same - According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed. | 2010-07-29 |
20100190304 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor storage device, has a first conductive type semiconductor region formed on a semiconductor substrate, a plurality of second conductive type semiconductor regions formed separately from each other on the first conductive type semiconductor region, a plurality of MOSFETs each formed on the plurality of second conductive type semiconductor regions, and element isolating regions each formed between the adjacent second conductive type semiconductor regions, a bottom surface of which being located in the first conductive type semiconductor region, wherein the number of crystal defects per unit volume in the first conductive type semiconductor region is larger than the number of the crystal defects per unit volume in the second conductive type semiconductor regions. | 2010-07-29 |
20100190305 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device of the present invention solves problems in a process for forming a fin type gate including a recess region, such as, a complicated process, low production margin, and difficulty in forming an accurate fin shape. In a process for forming an isolation dielectric film defining an active region, a nitride film pattern is formed in such a manner that the size of the nitride film is adjusted according to line width of a fin portion in a fin type active region formed in a subsequent process step, and an isolation dielectric film is formed in every region except for the nitride film pattern of a semiconductor substrate. Then, a recess is etched, and the isolation dielectric film is removed from a region where the line width of the nitride film pattern was reduced to a certain degree. Consequently, a process margin for forming a fin type active region is increased, and the shape of a fin shaped portion can be adjusted accurately, which together contribute to improved electrical properties in the semiconductor devices. | 2010-07-29 |
20100190306 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING IMPURITY CONCENTRATION REDUCTION IN DOPED CHANNEL REGION ARISING FROM FORMATION OF GATE INSULATING FILM - A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan | 2010-07-29 |
20100190307 | HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES - Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact. | 2010-07-29 |
20100190308 | ELECTRONIC DEVICE INCLUDING A FIN-TYPE TRANSISTOR STRUCTURE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE - An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher V | 2010-07-29 |
20100190309 | METHOD FOR ADJUSTING THE HEIGHT OF A GATE ELECTRODE IN A SEMICONDUCTOR DEVICE - By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions. | 2010-07-29 |
20100190310 | Gap-filling composition with excellent shelf life by end-capping - A composition with improved shelf life for filling small gaps in a semiconductor device is provided. The composition comprises an end-capped silicone polymer. The molecular weight of the end-capped silicone polymer is not varied during storage. In addition, the dissolution rate (DR) of the composition in an alkaline developing solution is maintained at a desired level during storage. That is, the composition is highly stable during storage. Therefore, the composition is suitable for use in a node separation process for the fabrication of a semiconductor capacitor. | 2010-07-29 |
20100190311 | Method of Forming a MEMS Topped Integrated Circuit with a Stress Relief Layer - The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices. | 2010-07-29 |
20100190312 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device which is higher functional and reliable and a technique capable of manufacturing the semiconductor device with a high yield at low cost without complexing the apparatus or process. At least one of a first conductive layer and a second conductive layer is formed containing one kind or plural kinds of indium, tin, lead, bismuth, calcium, manganese, or zinc; or oxidation treatment is performed at least one of interfaces between an organic compound layer and the first conductive layer and between the organic compound layer and the second conductive layer. The first conductive layer, the organic compound layer, and the second conductive layer which are formed over a first substrate with a peeling layer interposed therebetween can be peeled from the first substrate with the peeling layer, and transposed to a second substrate. | 2010-07-29 |
20100190313 | METHOD FOR MANUFACTURING NONVOLATILE STORAGE ELEMENT AND METHOD FOR MANUFACTURING NONVOLATILE STORAGE DEVICE - A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer, into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching. | 2010-07-29 |
20100190314 | Methods Of Forming Semiconductor Structures - Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode. | 2010-07-29 |
20100190315 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - There is provided a method of manufacturing a semiconductor memory device. According to the method, a tunnel insulating layer and a charge trap layer are formed in a cell region of a semiconductor substrate defining the cell region and a peripheral region. A gate insulation layer and a first conductive layer are formed over the semiconductor substrate of the peripheral region. A blocking insulating layer is formed on the charge trap layer of the cell region and the first conductive layer of the peripheral region. A second conductive layer is formed over the entire surface including the blocking insulating layer, thereby forming a capacitor having a stack structure of the first conductive layer, the blocking insulating layer, and the second conductive layer. | 2010-07-29 |
20100190316 | METHOD OF SELECTIVE OXYGEN IMPLANTATION TO DIELECTRICALLLY ISOLATE SEMICONDUCTOR DEVICES USING NO EXTRA MASKS - A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk silicon that is latch-up immune. | 2010-07-29 |
20100190317 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SILICON OXIDE FILM FORMING METHOD - A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches. | 2010-07-29 |
20100190318 | METHOD OF RECOVERING AND REPRODUCING SUBSTRATES AND METHOD OF PRODUCING SEMICONDUCTOR WAFERS - A method of recovering a first substrate, including the steps of: sticking a second substrate on a semiconductor layer epitaxially grown on the first substrate; and separating the semiconductor layer and the first substrate. Furthermore, a method of reproducing a first substrate, including the step of surface processing the first substrate separated. Furthermore, a method of reproducing a first substrate, including the step of homoepitaxially growing the first substrate surface processed. Furthermore, a method of producing a semiconductor wafer, including the step of epitaxially growing a semiconductor layer on a first substrate. Thus a group III nitride or similar, expensive substrate can be used to efficiently and economically, epitaxially grow a group III nitride or similar semiconductor layer. | 2010-07-29 |
20100190319 | METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER - Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another. | 2010-07-29 |
20100190320 | METHODS OF REMOVING WATER FROM SEMICONDUCTOR SUBSTRATES AND METHODS OF DEPOSITING ATOMIC LAYERS USING THE SAME - Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate. | 2010-07-29 |
20100190321 | METHOD OF FABRICATING PHASE-CHANGE MEMORY DEVICE HAVING TiC LAYER - Provided is a method of fabricating a phase-change memory device. The phase-change memory device includes a memory cell having a switching device and a phase change pattern. The method includes; forming a TiC layer on a contact electrically connecting the switching device using a plasma enhanced cyclic chemical vapor deposition (PE-cyclic CVD) process, patterning the TiC layer to form a lower electrode on the contact, and forming the phase-change pattern on the lower electrode. | 2010-07-29 |
20100190322 | COMPOUND SEMICONDUCTOR SUBSTRATE - A substrate for epitaxial growth, which is capable of improving a surface state of an epitaxial layer at microroughness level. In a substrate for epitaxial growth, when haze is defined as a value calculated by dividing intensity of scattered light obtained when light is incident from a predetermined light source onto a surface of a substrate, by intensity of the incident light from the light source, the haze is not more than 2 ppm all over an effectively used area of the substrate and an off-angle with respect to a plane direction is 0.05 to 0.10°. | 2010-07-29 |
20100190323 | Modifying catalytic behavior of nanocrystals - The present invention provides a method of providing a desired catalyst electron energy level. The method includes providing a donor material quantum confinement structure (QCS) having a first Fermi level, and providing an acceptor QCS material having a second Fermi level, where the first Fermi level is higher than the second Fermi level. According to the method the acceptor is disposed proximal to the donor to alter an electronic structure of the donor and the acceptor materials to provide the desired catalyst electron energy level. | 2010-07-29 |
20100190324 | REDUCING PHOTORESIST LAYER DEGRADATION IN PLASMA IMMERSION ION IMPLANTATION - A method of plasma immersion ion implantation of a workpiece having a photoresist mask on its top surface prevents photoresist failure from carbonization of the photoresist. The method includes performing successive ion implantation sub-steps, each of the ion implantation sub-steps having a time duration over which only a fractional top portion of the photoresist layer is damaged by ion implantation. After each one of the successive ion implantation sub-steps, the fractional top portion of the photoresist is removed while leaving the remaining portion of the photoresist layer in place by performing an ashing sub-step. The number of the successive ion implantation sub-steps is sufficient to reach a predetermined ion implantation dose in the workpiece. | 2010-07-29 |
20100190325 | SEMICONDUCTOR DEVICE HAVING MULTI-CHANNEL AND METHOD OF FABRICATING THE SAME - An embodiment of the present invention relates to a semiconductor device having a multi-channel and a method of fabricating the same. In an aspect, the semiconductor device includes a semiconductor substrate in which isolation layers are formed, a plurality of trenches formed within an active region of the semiconductor substrate, and a channel active region configured to connect opposite sidewalls within each trench region and having a surface used as a channel region. | 2010-07-29 |
20100190326 | Method for Fabricating Semiconductor Memory Device - A method for fabricating a semiconductor memory device includes: forming a lower conductive layer over a semiconductor substrate; forming an insulation layer over the lower conductive layer; etching the insulation layer to form a contact hole that exposes a portion of the lower conductive layer; forming a contact plug in the contact hole; doping the contact plug by performing a plasma doping process while varying a temperature of regions the semiconductor substrate; and forming an upper conductive layer connected with the lower conductive layer through the contact plug. | 2010-07-29 |
20100190327 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND DESIGN SUPPORT APPARATUS - A semiconductor device manufacturing method includes: forming a conductive film over a substrate; forming an assist pattern on the conductive film; forming a metal film to cover the conductive film and the assist pattern; etching back the metal film to form at least one side wall film on a side surface of the assist pattern; removing the assist pattern; forming at least one resist pattern to selectively expose a portion of the conductive film and a portion of the side wall film; performing etching using the resist pattern as a mask to remove the exposed portion of the side wall film; and etching the conductive film using the side wall film as a mask to form a gate electrode and a contact region electrically connected to the gate electrode. | 2010-07-29 |
20100190328 | Self Aligned Silicided Contacts - Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material. | 2010-07-29 |
20100190329 | METHOD AND STRUCTURE FOR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material. | 2010-07-29 |
20100190330 | NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR DEVICE - A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed. | 2010-07-29 |
20100190331 | System for Depositing a Film Onto a Substrate Using a Low Vapor Pressure Gas Precursor - A method for depositing a film onto a substrate is provided. The substrate is contained within a reactor vessel at a pressure of from about 0.1 millitorr to about 100 millitorr. The method comprises subjecting the substrate to a reaction cycle comprising i) supplying to the reactor vessel a gas precursor at a temperature of from about 20° C. to about 150° C. and a vapor pressure of from about 0.1 torr to about 100 torr, wherein the gas precursor comprises at least one organo-metallic compound; and ii) supplying to the reactor vessel a purge gas, an oxidizing gas, or combinations thereof. | 2010-07-29 |
20100190332 | Method of Forming a Copper Topped Interconnect Structure that has Thin and Thick Copper Traces - A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip. | 2010-07-29 |
20100190333 | METHOD OF FORMING CONNECTION TERMINAL - A method of forming a connection terminal may include preparing a substrate, forming a first conductor of a tube shape having an opened upper portion on the substrate, forming a second conductor on the first conductor, and annealing the second conductor so that a portion of the second conductor extends in an internal space of the first conductor through the opened upper portion. | 2010-07-29 |
20100190334 | THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor circuit structure includes a support substrate which carries an interconnect region and electronic circuitry. The semiconductor circuit structure includes a device substrate coupled to the interconnect region through a conductive bonding layer. The device substrate includes a planarized surface which faces the conductive bonding layer. The device substrate can carry laterally oriented semiconductor devices which are connected to the electronic circuitry carried by the support substrate. The device substrate can be processed to form vertically oriented semiconductor devices which are connected, through the interconnect region and conductive bonding layer, to the electronic circuitry carried by the support substrate. | 2010-07-29 |
20100190335 | Method of manufacturing semiconductor device - In a method of manufacturing a semiconductor device according to the present invention, a wiring trench is formed on the surface of an insulating film, and the inner surface of this wiring trench is thereafter coated with an alloy film made of an alloy material containing copper and a prescribed metallic element. After this coating with the alloy film, a copper film is laminated on the insulating film to fill up the wiring trench. Then, unnecessary portions of the copper film outside the wiring trench are removed, so that the surface of the copper film remaining in the wiring trench is generally flush with the surface of the insulating film. Thereafter heat treatment is performed. The prescribed metallic element is deposited on the wiring trench due to this heat treatment. Then, the prescribed metallic element deposited on the wiring trench is removed. | 2010-07-29 |
20100190336 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film. | 2010-07-29 |
20100190337 | Method of Forming Metal Wirings of Semiconductor Device - A method of forming metal wirings of a semiconductor device includes providing a semiconductor substrate having a number of underlying conductive patterns separated from each other with a first insulating layer interposed between the underlying conductive patterns. The method also includes forming auxiliary patterns over the underlying conductive patterns, respectively, forming a second insulating layer over the first insulating layer to fill a space between the auxiliary patterns, removing the auxiliary patterns to form damascene patterns through which the underlying conductive patterns are respectively exposed, and filling interiors of the damascene patterns with a metal material. | 2010-07-29 |
20100190338 | Method for manufacturing semiconductor device - An insulator layer is formed on a part of semiconductor substrate to form an isolation layer that insulates and separates active elements from each other in the first region, and to form a dummy portion which is composed of a base material of the semiconductor substrate exposed in the insulator layer in a second region. Active elements are formed in the first region. A silicide layer is formed on the first and second regions excluding at least a portion in which the TSV electrode should be formed. At least one TSV hole extending from a reverse surface side of the semiconductor substrate to an electrode pad via the second region is formed. A conductive film is formed on the inner wall of the TSV hole to form a TSV electrode electrically connected to the electrode pad. | 2010-07-29 |
20100190339 | COMPOSITIONS AND METHODS FOR CHEMICAL-MECHANICAL POLISHING OF PHASE CHANGE MATERIALS - The present invention provides a chemical-mechanical polishing (CMP) composition suitable for polishing a substrate comprising a phase change material (PCM), such as a germanium-antimony-tellurium (GST) alloy. The composition comprises a particulate abrasive material in combination with lysine, an optional oxidizing agent, and an aqueous carrier therefor. CMP methods for polishing a phase change material-containing substrate utilizing the composition are also disclosed. | 2010-07-29 |
20100190340 | Methods of forming fine patterns using a nanoimprint lithography - In a method of forming fine patterns, a photocurable coating layer is formed on a substrate. A first surface of a template makes contact with the photocurable coating layer. The first surface of the template includes at least two first patterns having a first dispersion degree of sizes, and at least one portion of the first surface of the template includes a photo attenuation member. A light is irradiated onto the photocurable coating layer through the template to form a cured coating layer including second patterns having a second dispersion degree of sizes. The second patterns are generated from the first patterns and the second dispersion degree is less than the first dispersion degree. The template is separate from the cured coating layer. A size dispersion degree of the patterns used in a nanoimprint lithography process may be adjusted by the light attenuation member, so that the fine patterns may be formed to have an improved size dispersion degree. | 2010-07-29 |