30th week of 2010 patent applcation highlights part 16 |
Patent application number | Title | Published |
20100187637 | BIPOLAR DEVICE COMPATIBLE WITH CMOS PROCESS TECHNOLOGY - The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the substrate with a predetermined distance from either the emitter or the collector, wherein the base, the emitter, the collector and the gate terminal are located in an active area defined by a hole in a surrounding isolation structure in the substrate. | 2010-07-29 |
20100187638 | ANTI-FUSE CELL AND ITS MANUFACTURING PROCESS - An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source ( | 2010-07-29 |
20100187639 | Semiconductor device and fabrication method - A semiconductor device has a semiconductor substrate in which first and second wells are formed. The substrate and wells are of the same conductivity type, but the second well has a higher impurity concentration than the first well. High-voltage MOS transistors are formed in the first well, and a low-voltage MOS transistor is formed in the second well. The high-voltage MOS transistors include a first transistor having a gate oxide layer with a first thickness and a second transistor having a gate oxide layer with a second thickness less than the first thickness. The low-voltage MOS transistor has a third gate oxide layer with a third thickness less than the first thickness. The second high-voltage MOS transistor provides efficient current conduction. | 2010-07-29 |
20100187640 | INSULATED GATE SEMICONDUCTOR DEVICE - A two-layer electrode structure is provided. A protection diode is provided not to overlap a gate pad portion. Cells and a first one of source electrode layers can be provided below the gate pad portion, so that the differences in resistance among various points in the source electrode layers can be decreased. In addition, the protection diode is positioned adjacent to a device region and at an end portion, of a chip, outward of the device region in such a way as to be in the closest proximity to the gate pad portion. A larger device region with efficient transistor operation can thus be secured, and the resistance of the first source electrode layer below a wiring portion can be reduced. | 2010-07-29 |
20100187641 | HIGH PERFORMANCE MOSFET - A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, the present invention provides a metal oxide semiconductor field effect transistor (MOFET) that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The inventive structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions. Such a well region may be referred to as a non-uniform super-steep retrograde well. | 2010-07-29 |
20100187642 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A body region is formed in a semiconductor material that has a major surface. A gate trench is formed in the epitaxial layer and a gate structure is formed on the gate trench. A source region is formed adjacent the gate trench and extends from the major surface into the body region and a field plate trench is formed that extends from the major surface of the epitaxial layer through the source and through the body region. A field plate is formed in the field plate trench, wherein the field plate is electrically isolated from the sidewalls of the field plate trench. A source-field plate-body contact is made to the source region, the field plate and the body region. A gate contact is made to the gate region. | 2010-07-29 |
20100187643 | METHOD FOR TUNING THE THRESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE - A metal gate and high-k dielectric device includes a substrate, an interfacial layer on top of the substrate, a high-k dielectric layer on top of the interfacial layer, a metal film on top of the high-k dielectric layer, a cap layer on top of the metal film and a metal gate layer on top of the cap layer. The thickness of the metal film and the thickness of the cap layer are tuned such that a target concentration of a cap layer material is present at an interface of the metal film and the high-k dielectric layer. | 2010-07-29 |
20100187644 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The transistor characteristics of a MIS transistor provided with a gate insulating film formed to contain oxide with a relative dielectric constant higher than that of silicon oxide are improved. After a high dielectric layer made of hafnium oxide is formed on a main surface of a semiconductor substrate, the main surface of the semiconductor substrate is heat-treated in a non-oxidation atmosphere. Next, an oxygen supplying layer made of hafnium oxide deposited by ALD and having a thickness smaller than that of the high dielectric layer is formed on the high dielectric layer, and a cap layer made of tantalum nitride is formed. Thereafter, the main surface of the semiconductor substrate is heat-treated. | 2010-07-29 |
20100187645 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed in the upper part of the semiconductor substrate so as to be spaced; a channel region formed in a part of the semiconductor substrate between the source region and the drain region; a first dielectric film formed on the channel region of the semiconductor substrate; a second dielectric film formed on the first dielectric film and having a higher permittivity than the first dielectric film; a third dielectric film formed on at least an end surface of the second dielectric film near the drain region out of end surfaces of the second dielectric film near the source and drain regions; and a gate electrode formed on the second dielectric film and the third dielectric film. | 2010-07-29 |
20100187646 | ULTRA LOW PRESSURE SENSOR AND METHOD OF FABRICATION OF SAME - A sensor including: a backplate of electrically conductive or semi-conductive material, the backplate including a plurality of backplate holes; a diaphragm of electrically conductive or semi-conductive material that is connected to, and insulated from the backplate, the diaphragm defining a flexible member and an air gap associated with the flexible member; a bond pad formed on an area of the backplate surrounding the cavity; and a bond pad formed on an area of the diaphragm surrounding the air gap; wherein the flexible member and air gap defined by the diaphragm extend beneath the plurality of backplate holes. | 2010-07-29 |
20100187647 | High Density Photodiodes - The present invention is a front-side contact, back-side illuminated (FSC-BSL) photodiode arrays and front-side illuminated, back-side contact (FSL-BSC) photodiode arrays having improved characteristics, including high production throughput, low-cost manufacturing via implementation of batch processing techniques; uniform, as well as high, photocurrent density owing to presence of a large continuous homogeneous, heavily doped layer; and back to front intrachip connections via the homogenous, heavily doped layers on the front and back sides of the substrate. | 2010-07-29 |
20100187648 | PHOTOELECTIC CONVERSION DEVICE AND MANUFACTURING METHOD - A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region and above the first pattern, and microlenses provided above the photoelectric conversion elements with the first and the second patterns provided therebetween. The photoelectric conversion device further has convex-shaped interlayer lenses in optical paths between the photoelectric conversion elements and the microlenses, the peak of each convex shape projecting in the direction from the electro-optical element to the microlens. | 2010-07-29 |
20100187649 | CHARGE RESERVOIR STRUCTURE - The present invention relates to a process for preparing semiconductor on insulator type structures that include a semiconductor layer of a donor substrate, an insulator layer and a receiver substrate. The process includes bonding of the donor substrate onto the receiver substrate, with at least one of the substrates being coated with an insulator layer, and forming at the bonding interface a so-called trapping interface of electrically active traps suitable for retaining charge carriers. The invention also relates to a semiconductor on insulator type structure that includes such a trapping interface. | 2010-07-29 |
20100187650 | INSULATED WELL WITH A LOW STRAY CAPACITANCE FOR ELECTRONIC COMPONENTS - A structure including at least one electronic component formed in a semiconductor stack comprising a heavily-doped buried silicon layer of a first conductivity type extending on a lightly-doped silicon substrate of a second conductivity type and a vertical insulating trench surrounding the component. The trench penetrates, into the silicon substrate, under the silicon layer, down to a depth greater than the thickness of the space charge region in the silicon substrate. | 2010-07-29 |
20100187651 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME - Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit. | 2010-07-29 |
20100187652 | METHOD AND STRUCTURES OF MONOLITHICALLY INTEGRATED ESD SUPPRESSION DEVICE - This present invention relates in general to protection of integrated circuit chips, and more particularly, to a micromachined suppression device for protecting integrated circuit chips from electrostatic discharges. The proposed ESD suppression device consists of conductive pillars are dispersed in a dielectric material. The gaps between each pillar behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed ESD suppression device is fabricated using micromachining techniques to be on-chip with device ICs. | 2010-07-29 |
20100187653 | SEMICONDUCTOR DEVICE - A conventional semiconductor device has a problem that an on-current of a parasitic transistor flows through a surface portion of a semiconductor layer and thus a semiconductor element undergoes thermal breakdown. In a semiconductor device according to the present invention, a protection element is formed with use of an isolation region and N type buried layers. A PN junction region in the protection element is formed on a P type buried layer of the isolation region. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of a semiconductor element to be protected. This structure allows an on-current of a parasitic transistor to flow into the protection element, and thereby the semiconductor element is protected. In addition, the on-current of the parasitic transistor flows through a deep portion of the epitaxial layer, and thereby the protection element is prevented from thermal breakdown. | 2010-07-29 |
20100187654 | Semiconductor device having capacitor and method of fabricating the same - A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process. | 2010-07-29 |
20100187655 | Integrated Circuit Capacitors Having Composite Dielectric Layers Therein Containing Crystallization Inhibiting Regions and Methods of Forming Same - Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers. | 2010-07-29 |
20100187656 | Bipolar Junction Transistors and Methods of Fabrication Thereof - Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region. | 2010-07-29 |
20100187657 | BIPOLAR TRANSISTOR WITH BASE-COLLECTOR-ISOLATION WITHOUT DIELECTRIC - The disclosed invention provides a method for the fabrication of a bipolar transistor having a collector region comprised within a semiconductor body separated from an overlying base region by one or more isolation cavities (e.g., air gaps) filled with low permittivity gas. In particular, a multilayer base-collector dielectric film is deposited over the collector region. A base region is formed onto the multilayer dielectric film and is patterned to form one or more base connection regions. The multilayer dielectric film is selectively etched during a plurality of isotropic etch processes to allow for the formation of one or more isolation region between the base connection regions and the collector region, wherein the one or more isolation regions comprise cavities filled with a gas having a low dielectric constant (e.g., air). The resultant bipolar transistor has a reduced base-collector capacitance, thereby allowing for improved frequency properties (e.g., higher maximum frequency operation). | 2010-07-29 |
20100187658 | MULTI-MATERIAL HARD MASK OR PREPATTERNED LAYER FOR USE WITH MULTI-PATTERNING PHOTOLITHOGRAPHY - A method of fabricating integrated circuits is described. A multi-material hard mask is formed on an underlying layer to be patterned. In a first patterning process, portions of the first material of the hard mask are etched, the first patterning process being selective to etch the first material over the second material. In a second patterning process, portions of the second material of the hard mask are etched, the second patterning process being selective to etch the second material over the first material. The first and second patterning processes forming a desired pattern in the hard mask which is then transferred to the underlying layer. | 2010-07-29 |
20100187659 | Semiconductor device and method for manufacturing semiconductor device - An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface. | 2010-07-29 |
20100187660 | Method To Create SOI Layer For 3D-Stacking Memory Array - A 3-D stacked semiconductor device is formed by forming a trench is formed through a top surface in a dielectric layer to expose the crystalline silicon layer having a (100) crystal plane, such that the trench walls are parallel to a <100> direction. Epitaxial silicon is grown between the trench walls to a level that is below the top surface of the dielectric layer. Epitaxial silicon is laterally grown using the top portion of the epitaxially grown silicon as a seed to form a laterally grown epitaxial layer having a (100) crystal plane on the dielectric layer. | 2010-07-29 |
20100187661 | Sintered Silicon Wafer - Provided is a sintered silicon wafer, wherein the ratio [I(220)/I(111) . . . (1)] of intensity of a (220) plane and intensity of a (111) plane measured by X-ray diffraction is 0.5 or more and 0.8 or less, and the ratio [I(311)/I(111) . . . (2)] of intensity of a (311) plane and intensity of a (111) plane is 0.3 or more and 0.5 or less. The provided sintered silicon wafer has a smooth surface in which its surface roughness is equivalent to a single crystal silicon. | 2010-07-29 |
20100187662 | Method for forming silicon film, method for forming pn junction and pn junction formed using the same - A method for forming a silicon film may be performed using a microheater including a substrate and a metal pattern spaced apart from the substrate. The silicon film may be formed on the metal pattern by applying a voltage to the metal pattern of the microheater to heat the metal pattern and by exposing the microheater to a source gas containing silicon. The silicon film may be made of polycrystalline silicon. A method for forming a pn junction may be performed using a microheater including a substrate, a conductive layer on the substrate, and a metal pattern spaced apart from the substrate. The pn junction may be formed between the metal pattern and the conductive layer by applying a voltage to the metal pattern of the microheater to heat the metal pattern. The pn junction may be made of polycrystalline silicon. | 2010-07-29 |
20100187663 | METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE THEREFOR - A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components. | 2010-07-29 |
20100187664 | ELECTRICAL CONNECTIVITY FOR CIRCUIT APPLICATIONS - According to example configurations herein, a leadframe includes a connection interface. The connection interface can be configured for attaching an electrical circuit to the leadframe. The leadframe also can include a conductive path. The conductive path in the leadframe provides an electrical connection between a first electrical node of the electrical circuit and a second electrical node of the electrical circuit. Prior to making the connection between the electrical circuit and the leadframe, the first electrical node and the second electrical node can be electrically isolated from each other. Subsequent to making connection of the electrical circuit with the leadframe, the conductive path of the leadframe electrically connects the first electrical node and the second electrical node together. Accordingly, the leadframe provides connectivity between nodes of an electrical circuit in lieu of having to provide such connectivity at, for example, a metal interconnect layer of an integrated circuit device. | 2010-07-29 |
20100187665 | Integral metal structure with conductive post portions - A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination. | 2010-07-29 |
20100187666 | LEAD FRAME AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame includes a welding portion to be welded to other lead frame, and a frame, wherein the welding portion has an island portion provided like an island, and a plurality of connection members which connect the island portion and the frame with each other; and one connection member is provided so that a straight line which connects a connection point of the island portion and one connection member, and a connection point of one connection member and the frame, inclines away from a portion of the outer circumference (edge, for example) of the island portion where the connection member is connected, and also from a portion of the inner circumference (edge, for example) of the frame where the connection member is connected. | 2010-07-29 |
20100187667 | Bonded Microelectromechanical Assemblies - A MEMS device is described that has a body with a component bonded to the body. The body has a main surface and a side surface adjacent to the main surface and smaller than the main surface. The body is formed of a material and the side surface is formed of the material and the body is in a crystalline structure different from the side surface. The body includes an outlet in the side surface and the component includes an aperture in fluid connection with the outlet. | 2010-07-29 |
20100187668 | NOVEL BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME - A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body. | 2010-07-29 |
20100187669 | PROCESS FOR PACKAGING COMPONENTS, AND PACKAGED COMPONENTS - A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions. | 2010-07-29 |
20100187670 | On-Chip Heat Spreader - A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader. | 2010-07-29 |
20100187671 | Forming Seal Ring in an Integrated Circuit Die - The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs. | 2010-07-29 |
20100187672 | ELECTRONIC APPARATUS AND CIRCUIT BOARD - According to an aspect of the present invention, there is provided an electronic apparatus including: a housing; a circuit board that is housed in the housing; a semiconductor package that includes a first surface on which solder balls are provided and a second surface opposite to the first surface and that is mounted on the circuit board so as to be electrically connected to the circuit board through the solder balls; a protective film that has a water repellency and that is applied on the circuit board so as to expose around the semiconductor package mounted on the circuit board; and a joint member that joins at least a part of a side surface of the semiconductor package and the circuit board. | 2010-07-29 |
20100187673 | ADHESIVE TAPE AND SEMICONDUCTOR PACKAGE USING THE SAME - Provided is an adhesive tape which adheres two members to each other and decreases problems that may occur due to contraction and expansion of the adhered members when the temperature of the adhered two members changes. The adhesive tape includes: a base film having insulating properties; and an adhesive agent that adheres on both sides of the base film, wherein a coefficient of thermal expansion of the base film is 10 ppm or lower, a coefficient of thermal expansion of the adhesive tape is lower than 17 ppm, and an occupation rate of the base film in the adhesive tape exceeds 50%. | 2010-07-29 |
20100187674 | PACKAGE SUBSTRATE STRUCTURE AND CHIP PACKAGE STRUCTURE AND MANUFACTURING PROCESS THEREOF - A chip package structure includes a substrate, chips and an elastic element. The substrate has a first surface, a second surface, a first patterned metal layer on the first surface and a second patterned metal layer on the second surface, wherein the substrate is suitable for being clipped between an upper mold chase and a lower mold chase of a package mold. The chips are disposed on the first surface, wherein the chips are suitable for being contained in containing spaces defined by the upper mold chase and the substrate. The elastic element is disposed on the second surface and surrounds the second patterned metal layer, wherein the elastic element is suitable for contacting the lower mold chase and is located between the lower mold chase and the substrate. In addition, a manufacturing process of the chip package and a package substrate structure are also provided. | 2010-07-29 |
20100187675 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This semiconductor device is a semiconductor device in which a semiconductor element is flip-chip mounted onto a circuit substrate and the semiconductor element is covered and sealed with a sealing resin. A recess portion is formed in the sealing resin on a surface opposite to the mounting surface of the semiconductor element. Warping of the semiconductor device is reduced by the action of this recess portion. | 2010-07-29 |
20100187676 | CUBE SEMICONDUCTOR PACKAGE COMPOSED OF A PLURALITY OF STACKED TOGETHER AND INTERCONNECTED SEMICONDUCTOR CHIP MODULES - A cube semiconductor package includes one or more stacked together and interconnected semiconductor chip modules. The cube semiconductor package includes a semiconductor chip module and connection members. The semiconductor chip module includes a semiconductor chip which has a first and second surface, side surfaces, bonding pads, through-electrodes and redistribution lines. The second surface faces away from the first surface. The side surfaces connect to the first and second surfaces. The bonding pads are placed on the first surface. The through-electrodes pass through the first and second surfaces. The redistribution lines are placed at least on one of the first and second surfaces and are electrically connected to the through-electrodes and the bonding pads, and have ends flush with the side surfaces. The connection members are placed on the side surfaces and electrically connected with the ends of the redistribution lines. | 2010-07-29 |
20100187677 | WAFER LEVEL PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a wafer level package can include: forming an indentation, by etching one side of a semiconductor chip, on one side of which a chip pad is formed; forming a rewiring pattern, which is electrically connected with the chip pad and which includes a post pad having a corrugated shape in correspondence with the indentation, by selectively adding a conductive material on one side of the semiconductor chip; forming a sacrificial layer on one side of the semiconductor chip such that a window is formed in the sacrificial layer that completely or partially uncovers the post pad; forming a conductive post on the post pad, by filling the window with a conductive material; and removing the sacrificial layer. This method can be used to produce a wafer level package having a post structure that provides greater strength against lateral shear stresses. | 2010-07-29 |
20100187678 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided. | 2010-07-29 |
20100187679 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. | 2010-07-29 |
20100187680 | Heat radiator - A radiator includes: an insulating substrate, a heating element or a semiconductor chip is mounted; and a heat sink that is provided the insulating substrate through a stress relaxation member that has a stress absorbing space, in which the heat sink dissipates heat from the semiconductor chip. The insulating substrate, the stress relaxation member, and the heat sink are braze-bonded to each other. The heat sink has: a top plate that is bonded to the stress relaxation member; and a bottom plate that is bonded to the top plate, and the top plate and the bottom plate forms a passage of coolant therebetween. A thickness proportion between the top plate and the bottom plate falls within a range of 1:3 to 1:5. | 2010-07-29 |
20100187681 | Silicon Substrate Having Through Vias and Package Having the Same - The present invention relates to a silicon substrate having through vias and a package having the same. The silicon substrate includes a substrate body, a plurality of through vias and at least one heat dissipating area. The substrate body has a surface, and the material of the substrate body is silicon. The through vias penetrate the substrate body, and each of the through vias has a conductive material therein. The heat dissipating area is disposed on the surface of the substrate body and covers at least two through vias. The heat dissipating area is made of metal, and the through vias inside the heat dissipating area have same electrical potential. Thus, the heat in the through vias is transmitted to the heat dissipating area, and since the area of the heat dissipating area is large, the silicon substrate has good heat dissipation efficiency. | 2010-07-29 |
20100187682 | ELECTRONIC PACKAGE AND METHOD OF ASSEMBLING THE SAME - An electronic package ( | 2010-07-29 |
20100187683 | 3-D ICs EQUIPPED WITH DOUBLE SIDED POWER, COOLANT, AND DATA FEATURES - Three dimensional integrated circuits with double sided power, coolant, and data features and methods of constructing same are provided. According to some embodiments, an integrated circuit package can generally comprise one or more semiconductor wafers and opposing end substrates. The semiconductor wafers can each have a top exterior surface and a bottom exterior surface. The plurality of semiconductor wafers can form a multi-dimensional wafer stack of die wafers such that adjacent wafers have facing surfaces. Each of the semiconductor wafers can comprise one or more channels formed through the wafers. A portion of the channels can extend generally between the top and bottom exterior surfaces of the semiconductor wafers. A portion of the channels can carry conductors for coupling the wafers and/or coolant for cooling the wafers. The opposing end substrates can be disposed proximate opposing ends of the multi-dimensional stack. The opposing end substrates can be configured to supply power, coolant, and data signals to opposing ends of the multi-dimensional wafer stack. Other embodiments are also claimed and described. | 2010-07-29 |
20100187684 | System and Method for 3D Integrated Circuit Stacking - A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit. | 2010-07-29 |
20100187685 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion ( | 2010-07-29 |
20100187686 | SEMICONDUCTOR PACKAGE COMPRISING ALIGNMENT MEMERS - A semiconductor package comprising alignment members is provided. The semiconductor package includes a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate including a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further includes a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member. | 2010-07-29 |
20100187687 | Underbump Metallization Structure - A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts. | 2010-07-29 |
20100187688 | REDUCED BOTTOM ROUGHNESS OF STRESS BUFFERING ELEMENT OF A SEMICONDUCTOR COMPONENT - The present invention relates to a stress buffering package ( | 2010-07-29 |
20100187689 | SEMICONDUCTOR CHIPS INCLUDING PASSIVATION LAYER TRENCH STRUCTURE - An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer. | 2010-07-29 |
20100187690 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring substrate having connection pads. A first semiconductor chip is mounted on the wiring substrate. A second semiconductor chip is stacked on the first semiconductor chip in a step-like shape. Electrode pads of the first semiconductor chip are electrically connected to the connection pads of the wiring substrate via first metal wires. Electrode pads of the second semiconductor chip are electrically connected to the electrode pads of the first semiconductor chip via second metal wires. One end of the second metal wire is connected from above metal bump formed on the first electrode pad. | 2010-07-29 |
20100187691 | CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE - A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer. | 2010-07-29 |
20100187692 | CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE - A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer. | 2010-07-29 |
20100187693 | DIFFUSION BARRIER LAYERS - Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have conductivity sufficient for direct electroplating of conductive materials without needing intermediate seed layers. Such barrier layers may be used with circuits lines that are less than 65 nm wide and, in certain embodiments, less than 40 nm wide. The barrier layer may be passivated to form easily removable layers including sulfides, selenides, and/or tellurides of the materials in the layer. | 2010-07-29 |
20100187694 | Through-Silicon Via Sidewall Isolation Structure - A system and method for an improved through-silicon via isolation structure is provided. An embodiment comprises a semiconductor device having a substrate with electrical circuitry formed thereon. One or more dielectric layers are formed over the substrate, and an opening is etched into the structure extending from a surface of the one or more dielectric layers through the one or more dielectric layers into the substrate; the opening having sidewalls. A low-K dielectric layer is formed over the sidewalls of the opening. The opening is filled with a conductive material and/or a barrier layer creating a through-silicon via that is isolated from the surrounding substrate by the low-K dielectric layer. | 2010-07-29 |
20100187695 | OUT-OF-PLANE SPRING STRUCTURES ON A SUBSTRATE - A structure has at least one structure component formed of a first material residing on a substrate, such that the structure is out of a plane of the substrate. A first coating of a second material then coats the structure. A second coating of a non-oxidizing material coats the structure at a thickness less than a thickness of the second material. | 2010-07-29 |
20100187696 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a contact landing pad and a method for manufacturing the semiconductor component. A trench having sidewalls is formed in a semiconductor material and a dielectric material is formed on the sidewalls of the trench. An electrically conductive material is formed on the sidewalls and fills the trench. A multi-layer dielectric structure is formed over the electrically conductive material in the trench, where the multi-layer dielectric material is comprised of a dielectric material of one type sandwiched between dielectric materials of a different type such that an etch rate of the middle layer of dielectric material is different from those of the outer layers of dielectric material. Portions of the middle layer of dielectric material are removed and replaced with electrically conductive material that, in combination with portions of the electrically conductive material in the trench, form a contact landing pad. | 2010-07-29 |
20100187697 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes. | 2010-07-29 |
20100187698 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first wiring layer, a first interlayer insulating film over the first wiring layer, a second wiring layer crossing the first wiring layer and provided on the first interlayer insulating film, a second interlayer insulating film over the second wiring layer, and a via conductor electrically connecting the first wiring layer and the second wiring layer together. The second wiring layer includes a space separating the second wiring layer into pieces, the space being located at a position where the second wiring layer crosses the first wiring layer. The via conductor passes through the separation space such that the separated pieces of the second wiring layer are electrically connected together, the via conductor extending to the first wiring layer through the second interlayer insulating film and the first interlayer insulating film. | 2010-07-29 |
20100187699 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line. | 2010-07-29 |
20100187700 | Method and apparatus for manufacturing an electronic module, and electronic module - A substrate which has at least one component, such as a semiconductor chip, arranged on it is manufactured from a film made of plastic material laminated onto a surface of the substrate and of the at least one component, where the surface has at least one contact area. First, the film to be laminated onto the surface of the substrate and the at least one component, or a film composite including the film, is arranged in a chamber such that the chamber is split by the film or film composite into a first chamber section and a second chamber section, which is isolated from the first chamber section so as to be gastight. A higher atmospheric pressure is provided or produced in the first chamber section than in the second chamber section; and contact is made between the surface of the substrate arranged in the second chamber section and the at least one component and the film or the film composite, which contact brings about the lamination of the film onto the surface. | 2010-07-29 |
20100187701 | Downflow mixers with gas injection devices and/or baffles - A downflow mixer with a gas injection device and/or a baffle plate is provided to improve performance of mixing and/or aeration in basins, lagoons or tanks, particularly as part of water or wastewater treatment. | 2010-07-29 |
20100187702 | Method for the creation of shaped plastic lenses from flat substrates through the application of a thin film coating - This disclosure describes a method for shaping flat plastic into curved lenses during the process of depositing a thin film coating that can be applied to any application requiring a shaped lens and a thin film coating. It can be applied to any type of eyewear including but not limited to glasses, goggles, contacts and face shields as well as non-ophthalmic applications. Some application examples are 3D glasses, Laser Protection glasses and Laser Hardening glasses. | 2010-07-29 |
20100187703 | SURFACE MOUNT OPTOELECTRONIC COMPONENT WITH LENS HAVING PROTRUDING STRUCTURE - The invention relates to a surface mount optoelectronic component with a lens attachment, the method for precising the lens position and the method to manufacture the whole component. | 2010-07-29 |
20100187704 | METHOD FOR MAKING PRISM SHEET - A method for making a prism sheet includes: providing a cutting device comprising a cutter, a table plate, and a control unit, the table plate controlled to move up and down by the control unit, and the cutter having a blade rotatable; providing a mold insert preform on the table plate, the mold insert preform having a flat surface; moving the cutter to etch the flat surface of the mold insert preform along a first direction, and simultaneously driving the table plate to move up and down by the control unit in a first predetermined manner to form first elongated depressions in the flat surface; moving the cutter to etch the flat surface of the mold insert preform along a second direction to form second elongated depressions in the flat surface, thereby forming a mold insert; using the mold insert to form the prism sheet by injection molding method. | 2010-07-29 |
20100187705 | PREPARATION METHOD FOR MICRO-CAPSULE USING A MICROFLUIDIC CHIP SYSTEM - A method for preparing microcapsules using a droplet-based microfluidic chip. Monodisperse microcapsules, which are hollow or can be loaded with a desired material, are prepared using a droplet-based microfluidic chip through the movement of a monomer molecule from the inside of droplets to the interface of droplets, the diffusion of a photoinitiator to the interface of droplets, and the suppression of radical activity by oxygen in droplets. The method involves the use of a simple microfluidic channel and selectively photopolymerizing the shell of the droplets without needing the use of a chemically treated microfluidic channel or a complex microfluidic channel. | 2010-07-29 |
20100187706 | WET GRANULATION TABLETING METHOD USING AQUEOUS DISPERSION OF LOW-SUBSTITUTED HYDROXYPROPYL CELLULOSE - Provided is a method for preparing a tablet having high tablet hardness and an excellent disintegration property even if low-substituted hydroxypropyl cellulose is added in a relatively small amount. More specifically, provided is a method for preparing a tablet comprising steps of granulating while spraying an aqueous dispersion of low-substituted hydroxypropyl cellulose having a degree of hydroxypropoxyl group substitution ranging from 5 to 16% by weight to a tablet-forming composition and tableting the resulting granules. | 2010-07-29 |
20100187707 | METHOD AND DEVICE FOR GRANULATING THERMOPLASTIC MATERIAL - The methods and apparatuses for granulating thermoplastic material emerging from nozzles in a perforated plate are provided. The apparatus can have a motor-driven cutter arrangement having at least one blade located opposite the perforated plate. The at least one blade can pass over the nozzles in the perforated plate and cuts pellets of the emerging thermoplastic material. | 2010-07-29 |
20100187708 | Disposal Method for Entirely Recycling Solid Refuse - A disposal method for entirely recycling solid refuse includes the following steps: sorting, crushing, drying, pressing with high pressure to shaped articles, producing charcoal from combustible refuse in high temperature and firing incombustible refuse in high temperature, at last cooling high temperature articles to obtain solid fuel with various shapes and bricks or board used for building. The method achieves entirely recycling house refuse, especial solid refuse. The method recycles solid refuse to obtain fuel and building material with economic value. The method is simple and its processing cost is low. | 2010-07-29 |
20100187709 | System and method for rapidly heating and cooling a mold - A portable mold-temperature control unit includes a local heating system, a first fluid duct, a second fluid duct, and a fluid exchange system. The local heating system includes a local heater for heating fluid that is used to rapidly heat a mold. The first fluid duct carries hot fluid heated by the local heating system. The second fluid duct carries cool fluid that is used to rapidly cool a mold. The fluid exchange system includes an outlet that permits fluid to flow from the first and second fluid ducts to the mold during heating and cooling, respectively. The fluid exchange system also includes an inlet that receives the fluid as it returns from the mold. In one embodiment, the heating system reheats the fluid returning from the mold and reuses it to heat the mold again. In a more particular embodiment, the heating system includes a steam generator that generates steam used to heat the mold. In another embodiment, the portable mold-temperature control system includes a local cooling system that cools the fluid used to cool the mold. In a more particular embodiment, the local cooling system cools fluid returning from the mold and reuses it to cool the mold. A method for using the portable mold-temperature control unit is also disclosed. | 2010-07-29 |
20100187710 | FOAM MOLDING METHOD AND APPARATUS - It is an object of the present invention to provide a foam molding method for foaming and molding a foamable material, which is free from problems, such as deformation of or continuation between closed cells. To achieve this object, there is provided a foam molding method for foaming a foamable material, comprising the steps of providing a mold having a cavity, placing the cavity of the mold under a pressurized condition, foaming the foamable material in the cavity of the mold under the pressurized condition, thus appropriately controlling foaming of the foamable material, and releasing the pressurized condition of the cavity of the mold. | 2010-07-29 |
20100187711 | MANUFACTURING METHOD OF A THERMALLY INSULATED HOUSING - A back surface of an outer case is formed by mutually overlapping left and right back panels. The overlapping edges on the front side and backside of the panels may be bent toward the opposite side at a blunt angle. A joint between the back panels is established in which the overlapping edge of one back panel is pressed against the overlapping edge of the other back panel. Spacers are mounted between the outer and inner case such that the overlapping edges are put in close contact with each other. The bends are deformed in order to prevent leakage from the joint after the injection of foam liquid. Due to the pressure of the foam, both of the overlapping edges are placed in closer contact while deforming the bends to be substantially flat. Consequently, the sealing properties of the joint after the completion of the thermally insulated housing are secured. | 2010-07-29 |
20100187712 | Method and Apparatus for Forming a Fibrous Media - Embodiments for methods and apparatuses for forming a nonwoven web are described herein. In one embodiment, an apparatus includes one or more sources configured to dispense a first fluid flow stream comprising a fiber and a second fluid flow stream also comprising a fiber. The apparatus also includes a mixing partition downstream from the one or more sources, where the mixing partition is positioned between the first and second flow streams from the one or more sources. The mixing partition defines one or more openings that permit fluid communication between the two flow streams. The apparatus also includes a receiving region situated downstream from the one or more sources and designed to receive at least a combined flow stream and form a nonwoven web by collecting fiber from the combined flow stream. | 2010-07-29 |
20100187713 | METHOD FOR PRODUCING CARBON COMPOSITE METAL OXIDE BRIQUETTES - A method for producing carbon composite metal oxide briquettes includes a mixing step of adding a binder to a metal oxide raw material and a carbonaceous material and mixing the metal oxide raw material, the carbonaceous material, and the binder by a mixer to prepare a powder mixture, and a forming step of forming the powder mixture into carbon composite metal oxide briquettes by using a briquetting machine, in which, in the mixing step, a batch mixer is used as the mixer. | 2010-07-29 |
20100187714 | PATTERN GENERATION METHOD, RECORDING MEDIUM, AND PATTERN FORMATION METHOD - A pattern generation method of generating a three-dimensional pattern to be formed at a template for use in a method of forming a pattern by filling a resist material in the three-dimensional pattern of the template includes performing at least one of adjustment of a depth of the three-dimensional pattern and division of the three-dimensional pattern, based on a relationship between a filling time of the resist material and a dimension or shape of the three-dimensional pattern. | 2010-07-29 |
20100187715 | CATALYST FOR CURING EPOXIDES - The use of 1,3-substituted imidazolium salts of the formula I | 2010-07-29 |
20100187716 | METHOD FOR PRODUCING LOWER SIZE, HIGH TENACITY AND HIGH MODULUS POLYETHYLENE FIBER - The present invention discloses a process for producing low-titer, high-strength and high-modulus polyethylene fibers, comprising the following steps: dissolving the ultra-high molecular weight polyethylene into paraffin oil with a low viscosity to form a spinning solution with a concentration of 3˜15%; extruding the spinning solution through a thin spinneret with at least 10 orifices having a diameter φ of 0.7˜0.8 mm and a length/diameter ratio of 10˜12, by applying a high pressure in the range of 2.5±1.0 MPa to the spinning solution, such that the fluid in the orifices is extruded at a shear rate of 200˜3 500 sec | 2010-07-29 |
20100187717 | METHOD FOR PRODUCING WOOD-PLASTIC COMPOSITE MATERIAL - The invention relates to a method for producing a wood-plastic composite material, by which means the composite material is provided with a pre-determined color and pre-determined material characteristics during the course of the method. The method according to the invention is characterized by the drying and treatment of the wood chips using chromophore substances and/or active substances in a fluidized bed appliance during one of the method steps preceding the extrusion. Following the treatment, sorted wood chips can be removed from the fluidized bed within a pre-selected dimension spectrum and extruded with plastic in the subsequent method step. | 2010-07-29 |
20100187718 | RE-CAPSULATION OF SYNTHETIC RUBBER POLYMER - A method for making a modified polymer is characterized by re-capsulating the polymer via extrusion. A cross-linking agent is mixed with particles of synthetic rubber material to form a mixture which is then heated and delivered to an extrusion device. The extrusion device further heats the mixture and produces strands of modified polymer material which are cooled and pelletized to form small pellets of re-capsulated modified polymer. A partitioning or anti-blocking agent is added to the pellets to prevent re-agglomerization of the modified polymer. When mixed with asphalt, a modified polymer asphalt is produced with enhanced Theological properties for high and low temperatures. | 2010-07-29 |
20100187719 | PROCESS AND APPARATUS FOR PRODUCTION OF COLORLESS TRANSPARENT RESIN FILM - A method for producing a colorless transparent resin film by a solution flow casting method containing: flow-casting an organic solvent solution of a polyamic acid or a polyimide on a support; and drying, the method containing at least the following step (1), step (2) and step (3) in this order, and an apparatus therefor:
| 2010-07-29 |
20100187720 | TAKE OUT AND COOLING SYSTEM AND METHOD - A take-out and cooling method and apparatus conveys molded plastic articles from a molding machine to and through a cooling station and preferably includes a take-out apparatus that has a main support, a conveyor carried by the main support for movement in an endless path, a cam adjacent to the support, a plurality of arms carried by the conveyor for movement with the conveyor along the endless path and including a follower responsive to the contour of the cam to vary the position of the arms relative to the support, and at least one holder carried by each arm. Each holder is adapted to receive and carry at least one molded article to facilitate in conveying the molded articles and is flexible and resilient to permit relative movement of at least a portion of the holder relative to its associated arm. | 2010-07-29 |
20100187721 | Resin infusion potting - A process for forcibly infusing liquid potting compound into the strands of a cable in order to attach an anchor to the cable. The process uses a strand cavity within an anchor that encloses the exposed strands. The strand cavity is sealed. Liquid potting compound is then forced into the strand cavity, where it runs around and through the exposed strands. A second venting passage is preferably employed, so that the liquid potting compound flows through the mold without trapping any substantial air pockets. | 2010-07-29 |
20100187722 | Injection Moulding Process - Method for moulding a multi-component manufactured product through injection of plastic materials in a mould comprising on the inside one or more movable parts, characterised in that the movable parts are moved into a first configuration in which at least two distinct mould cavities are made in the mould, plastic material is injected into each of the two distinct mould cavities to form two components of the manufactured product, the movable parts are moved into a second configuration, in which they make at least a third cavity in the mould the walls of which at least partially consist of the two components already injected, plastic material is injected into the third mould cavity to form a third component of the manufactured product that is thus welded to the first two. | 2010-07-29 |
20100187723 | METHOD FOR PRODUCING MULTILAYER MOLDED ARTICLE - A method for producing a multilayer molded article is proposed, whereby a thin cover layer can be formed widely on a substrate layer. The method has a first step of placing a substrate in a cavity formed between a pair of mold halves, and a second step of supplying a second thermoplastic resin material being in a molten state, at an injection rate of 200 cm | 2010-07-29 |
20100187724 | PROCESS FOR PRODUCING A FREE-FLOWING AND STORAGE-STABLE SOLID COMPRISING ESSENTIALLY ALPHA-ALANINE-N,N-DIACETIC ACID AND/OR ONE OR MORE DERIVATIVES OF ALPHA-ALANINE-N,N-DIACETIC ACID - A process is proposed for producing a free-flowing and storage-stable solid comprising essentially α-alanine-N,N-diacetic acid and/or one or more derivatives of α-alanine-N,N-diacetic acid proceeding from a powder of α-alanine-N,N-diacetic acid and/or one or more derivatives of α-alanine-N,N-diacetic acid by
| 2010-07-29 |
20100187725 | APPARATUS AND PROCESS FOR FILLING STRUCTURES WITH DIFFERENT CAVITIES - Process for industrially filling differently structured cavities in building blocks with mouldings, having the following features: a) the mouldings are cut in the form of differently configured mineral-wool pads ( | 2010-07-29 |
20100187726 | Stabilized rotomolded parts - Easy processing rotomolding resins which have a high melt index, I | 2010-07-29 |
20100187727 | METHOD OF VOID FREE FOR MOLDING PRODUCT - A method of removing voids from a molded product is disclosed, in which a main mold, is connected with an auxiliary mold, and molten material in the auxiliary mold moves toward the main mold by adjusting a cooling time between the main mold and the auxiliary mold, thereby preventing voids from occurring in the molded product having a large thickness, preventing sink marks from occurring. The method includes the steps of: preparing a main mold and an auxiliary mold connected with the main mold; introducing molten resin into the auxiliary mold and the main mold; and retarding cooling of the auxiliary mold such that negative pressure in the auxiliary mold is different from that in the main mold due to a cooling time difference and a temperature difference. The molten resin in the auxiliary mold moves toward the main mold, and then is filled in the main mold during cooling. | 2010-07-29 |
20100187728 | Systems, devices, and methods for making or administering frozen particles - Certain embodiments disclosed herein relate to compositions, methods, devices, systems, and products regarding frozen particles. In certain embodiments, the frozen particles include materials at low temperatures. In certain embodiments, the frozen particles provide vehicles for delivery of particular agents. In certain embodiments, the frozen particles are administered to at least one substrate. | 2010-07-29 |
20100187729 | METHOD FOR MANUFACTURING FINE POLYMER, AND FINE POLYMER MANUFACTURING APPARATUS - A method for manufacturing a fine polymer including: generating superheated steam by a superheated steam generating unit ( | 2010-07-29 |
20100187730 | INJECTION BLOW MOLDING MACHINE AND PROCESS FOR THE STRETCH BLOW MOLDING OF PLASTIC CONTAINERS - An injection blow molding machine having an injection molding rotor including a plurality of injection molding units with individual split mold cavities for preforms, a transfer rotor, a blow molding rotor including a plurality of blow molds, and a removal rotor, essentially within a shared operating plane, and split mobile neck molding parts which fit into each blow mold and each mold cavity and which are transferred with a preform and removed with a stretch-blown bottle from the blow mold. In the process, each preform is transferred in the neck molding part into the blow mold. | 2010-07-29 |
20100187731 | Alumina fiber aggregate and catalytic converter holder comprising the same - An alumina fiber aggregate which is minimized in scatter of fibers, excels in handling characteristics and working environmental hygiene and finds its useful application to support mats for catalytic converters and such is provided. | 2010-07-29 |
20100187732 | SOLDER RECOVERY DEVICE - A solder recovery device includes a melter which melts solder dross stored in a melting crucible, an agitation unit which agitates the melted solder dross, so as to separate the melted solder dross up and down into an oxidized residue and a recycled solder in the melting crucible, and a suction unit which sucks the oxidized residue generated by the agitation, the suction unit sucking the oxidized residue in an upper portion of the melting crucible to be removed. | 2010-07-29 |
20100187733 | ANTI-VIBRATION DEVICE - A diaphragm | 2010-07-29 |
20100187734 | Hydraulic Mount and Filling Device for the Same - A hydraulic mount and a filling device for the hydraulic mount are provided. The hydraulic mount ( | 2010-07-29 |
20100187735 | MOVABLE POLE EXTENSION FOR A MAGNETIC CLAMPING APPARATUS AND MAGNETIC CLAMPING APPARATUS HAVING SUCH MOVABLE POLE EXTENSION - The present invention relates to a movable pole extension ( | 2010-07-29 |
20100187736 | MAGNETIC TURNTABLE SYSTEM AND METHOD - A magnetic turntable system is described and shown. | 2010-07-29 |