30th week of 2012 patent applcation highlights part 29 |
Patent application number | Title | Published |
20120188790 | ILLUMINATING DEVICE AND DISPLAY DEVICE - An illuminating device ( | 2012-07-26 |
20120188791 | SUBSTRATE-GUIDED HOLOGRAPHIC DIFFUSER - A substrate-guided holographic diffuser has a light-guide section configured to in-couple light and transmit the light within itself via total internal reflection. It can also have a brightness enhancement section that recycles non-diffracted light within the light-guide section. A hologram section that receives light from the light-guide section has a holographic structure defining acceptance conditions and is positioned relative to the internally reflected light such that the internally reflected light meets the acceptance conditions of the holographic structure. The internally reflected light is out-coupled by the holographic structure as a projected image of light scattered from a diffuser. | 2012-07-26 |
20120188792 | LIGHT GUIDE PLATE AND LIGHT SOURCE MODULE - A light guide plate including a first surface, a second surface, at least one light incident surface, and a plurality of groove sets is provided. The light incident surface connects the first surface and the second surface. The groove sets are separately disposed on the second surface. Each of the groove sets includes a plurality of curved grooves. Each of the curved grooves has a curved inclined reflective surface and a curved back-to-light surface connected thereto. The curved inclined reflective surface is inclined with respect to the first surface. The curved grooves of each of the groove sets curve toward the same curving direction. The curved inclined reflective surface of one of two adjacent curved grooves is connected to the curved back-to-light surface of the other one of the two adjacent curved grooves through a connection surface. A light source module is also provided. | 2012-07-26 |
20120188793 | BACKLIGHT ASSEMBLY - A backlight assembly includes a light emitting module and a receiving container. The receiving container receives the light emitting module, and includes a first frame, a second frame and a heat dissipation channel. The first frame includes a first bottom, and first sidewalls connected to the first bottom. The second frame includes a second bottom which faces the first bottom and is sealed with the first frame. The first and second bottoms are spaced apart from each other and form the heat dissipation channel therebetween. | 2012-07-26 |
20120188794 | ADAPTIVE BLEEDER CIRCUIT - An adaptive bleeder circuit is applicable to a power converter, in which the power converter has a transformer primary side and a transformer secondary side, and the power converter enables input power to be selectively input or not input to the transformer primary side through a pulse-width-modulated signal. The adaptive bleeder circuit includes a switched bleeder circuit, and the bleeder circuit switch dynamically adjusts a turn on/off ratio (or referred to as duty ratio) of the switch element according to the TRIAC holding current and the converter input current of an alternating current (AC) TRIAC. When the input current is less than the holding current, the bleeder circuit increases conduction time ratio of the pulse-width-modulated signal, such that the input current recovers to the holding current to maintain normal conduction of the AC TRIAC. | 2012-07-26 |
20120188795 | Apparatus and System for Transformer Frequency Control - An apparatus and a system include a multiplier circuit for receiving a sensed voltage and current of a of a load resistance coupled to a rectified voltage from a transformer's output whose input is from a DC-to-AC converter being supplied from a DC power generator having an internal resistance. The multiplier outputs a product of the sensed voltage and current. A differentiator circuit outputs a rate of change of the product. An integrator circuit outputs an integrated voltage indicating an accumulative rate of change of the product. A voltage-to-frequency converter circuit generates a voltage waveform having a frequency determined by the integrated voltage. A driver circuit uses the voltage waveform to output a control signal for controlling a frequency of the DC-to-AC power converter where the apparatus substantially matches an input resistance of the transformer to the internal resistance, thereby maximizing power transfer to the load resistance. | 2012-07-26 |
20120188796 | POWER COUPLING SYSTEM AND METHOD - Systems and methods for the coupling of power through an isolation transformer. The systems generally include a primary side electrically connectable to the primary winding of an isolation transformer, a secondary side electrically connectable to the secondary winding of the isolation transformer, a primary side switch sending power pulses to the secondary side, and a secondary side feedback circuit sending a feedback signal to the primary side. A pulse detector sends power pulses to the secondary side in response to the feedback signal, while a watchdog timer sends a power pulse to the secondary side if a feedback signal is not detected within a predetermined period of time. Secondary side circuits including a slow-start circuit and a wake circuit portion manage initialization and low-load operating power requirements, respectively. | 2012-07-26 |
20120188797 | SWITCHING POWER SOURCE APPARATUS - A switching power source apparatus includes a first series circuit including a first switch element and a second switch element, a second series circuit including a resonant capacitor, a resonant reactor, and a primary winding of a transformer, a rectifying-smoothing circuit of a voltage of a secondary winding of the transformer, a controller of the first and second switch elements, a current detector detecting a current of the resonant capacitor Cri when the first switch element is ON, an integration circuit of the current of the current detector integrating the voltage signal over a period in which the voltage signal is equal to or greater than a first reference voltage, and an overcurrent protector of the first switch element if an output voltage of the integration circuit is equal to or greater than a second reference voltage. | 2012-07-26 |
20120188798 | SWITCHING POWER SOURCE AND IMAGE FORMING APPARATUS HAVING SWITCHING POWER SOURCE - In a converter, when an output voltage is set to a low voltage, a switching element is turned on according to a pulse voltage induced in an auxiliary winding having the same winding direction as that of a primary winding of a transformer. | 2012-07-26 |
20120188799 | METHOD AND APPARATUS FOR INCREASING THE POWER CAPABILITY OF A POWER SUPPLY - One example controller for a power supply includes an oscillator, a drive signal generator, and a restart circuit. The oscillator generates a clock signal and the drive signal generator controls switching of a switch to regulate an output of the power supply in response to the clock signal. The restart circuit generates a restart signal in response to a current through the switch and in response to an absolute maximum on time period. The oscillator generates the clock signal to have a fixed maximum frequency in response to the restart signal indicating that the current through the switch reaches a current limit threshold within the absolute maximum on time period. The oscillator also generates the clock signal to have a variable minimum frequency in response to the restart signal indicating that the current through the switch has not reached the current limit threshold within the maximum on time period. | 2012-07-26 |
20120188800 | ASYMMETRIC SWITCH FORWARD CONVERTER - A switching circuit for use in a power supply includes a first active switch coupled to a first terminal of a primary winding of a transformer. A second active switch is coupled to a second terminal of the primary winding of the transformer. An output capacitance of the first active switch is greater than an output capacitance of the second active switch. A first passive switch is coupled to the second active switch and to the second terminal of the primary winding. A second passive switch is coupled to the first active switch and to the first terminal of the primary winding. A reverse recovery time of the first passive switch is greater than a reverse recovery time of the second passive switch. A recovery circuit is coupled to receive a current from the first passive switch. | 2012-07-26 |
20120188801 | FLYBACK POWER SUPPLY SYSTEM - A flyback power system includes a rectifier and filter circuit, a pulse width modulation (PWM) controller, a feedback circuit, a master converter circuit, a slave converter circuit, and a slave converter control circuit. The master converter circuit continuously converts power signals from the rectifier and filter circuit into first direct current (DC) power signals to drive load according to PWM signals of the PWM controller when the flyback power system powered on. The slave converter circuit converts the power signals from the rectifier and filter circuit into second DC power signals according to the PWM signals, and superposes the second DC power signals to the first DC power signals to drive the load when the load is heavy. The slave converter control circuit detects whether the load is heavy, and controls the PWM signals whether to input into the slave converter circuit according to a state of the load. | 2012-07-26 |
20120188802 | Switch Controller, Switch Control Method, Converter Using the Same, and Driving Method Thereof - Disclosed are a switch controller, a switch control method, a converter using the same, and a driving method thereof. A first voltage is generated by using a voltage that is input to an input terminal, and a soft start signal is generated by using the first voltage during a soft start duration. A switching operation is controlled by using the soft start signal during the soft start duration. | 2012-07-26 |
20120188803 | CONVERTER WITH REACTIVE POWER COMPENSATION - A voltage source converter for a HVDC power transmission system is disclosed. According to one aspect, the voltage source converter includes at least one phase element having series connected diodes configured to interconnect, in use, a DC network and an AC network. The voltage source converter further includes at least one auxiliary converter configured to act as a waveform synthesizer to modify the DC voltage presented to the DC side of one or more phase elements. | 2012-07-26 |
20120188804 | CURRENT SUPPLY ARRANGEMENT FOR THE RECTIFYING THREE-PHASE AC CURRENT INTO MULTI-PULSE DC CURRENT - A current supply arrangement (A, B) for rectifying three-phase current into multi-pulse DC current with at least one three-phase AC current transformer with a transformer core or three single-phase AC current transformers, each having a transformer core, wherein the three-phase AC current transformer includes three first secondary-side coils (L | 2012-07-26 |
20120188805 | POWER SUPPLY CONVERSION CIRCUIT OF MULTI-PHASE POWER SUPPLY - A power supply conversion circuit includes a PWM chip and many sub-circuits. Each sub-circuit includes an inductor, a first capacitor connected to ground, a first resistor connected in series with the first capacitor to form a branch parallel to the inductor, a differential pair having a first differential signal trace and a second differential signal trace, a second resistor, and a second capacitor. The first trace is connected between the connection of the first resistor and the first capacitor and the PWM chip. The second resistor is connected between the connection of the first resistor and the inductor and the second capacitor. The second trace is connected between the connection of the second resistor and the second capacitor and the PWM chip. The ratios of the capacitances of each two second capacitors are the same as that of the lengths of the traces of each two corresponding differential pairs. | 2012-07-26 |
20120188806 | POWER DISTRIBUTION SYSTEM - A power distribution system includes a DC-DC converter which outputs a DC power after converting the DC power outputted from a DC power source to a desired voltage level. In the power distribution system, the DC-DC converter is controlled so as to operate only when the input voltage falls in a predetermined range. | 2012-07-26 |
20120188807 | STACKED STRUCTURE OF POWER CONVERSION APPARATUS - A stacked structure of a power converter is disclosed. The stacked structure has a power conversion circuit that provides an output or input of alternating current in three phases and is composed of odd-numbered parallel-connected power semiconductor element modules for each phase, and a heat sink for cooling the power semiconductor element modules. An odd number of the parallel-connected power semiconductor element modules are arranged in a first phase and a third phase, and an even number of the parallel-connected power semiconductor element modules are arranged in a second phase respectively in two rows on the heat sink relative to a ventilation direction of air for cooling the heat sink. | 2012-07-26 |
20120188808 | Timing Device without Neutral Line - A timing device without a neutral line is disclosed, comprising a hot line (L line) input, a hot line (L line) output, a second filter module, a triac, a current limiting module, a current rectifying module, a SCR, a first filter module, a MCU, a display module, an operation interface module, and a power input module provides the power required for entire operations. And, the operation interface module can input the control signal into the MCU and further output a signal to the second filter module for filtering to conduct the SCR and finally through the current rectifying module and the current limiting module to conduct the triac. Therefore, the current can enter into the AC output for providing electronic power. | 2012-07-26 |
20120188809 | POWER SOURCE CIRCUIT EFFICIENT IN CONVERSION FROM ALTERNATING CURRENT TO DIRECT CURRENT - A power source circuit which includes input portions, a limiting resistor connected to one of the input portions, a rectifier connected to the limiting resistor, a sampling resistor connected to the rectifier, output portions connected to the rectifier, a control circuit, and a switch circuit connected to the control circuit. The control circuit is connected to the two ends of the sampling resistor and the switch circuit is connected to the two ends of the limiting resistor. The control circuit is configured to output a first signal to the switch circuit if the current in the sampling resistor is greater than a predetermined value. The predetermined value is less than the level of current being consumed by a load in normal operation. The switch circuit is configured to isolate the sampling resistor when the first signal is received. | 2012-07-26 |
20120188810 | RECTIFIER SYSTEM - A rectifier system, e.g., for a generator, includes a bridge system having a predefined number of rectifier elements, at least one rectifier element being a rectifier element having at least one reverse-voltage dependent characteristic curve in a predefined range, and one of the negative diodes having a higher reverse saturation current than the associated positive diode, and at least one of the negative diodes being placed at a location in the rectifier in which the temperature is increased. | 2012-07-26 |
20120188811 | ASSOCIATIVE MEMORY - An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a pulse signal with an oscillating frequency corresponding to the distance obtained by the comparator circuit. Similarly, the oscillating circuits output pulse signals with oscillating frequencies according to the distance between the reference data in corresponding storage circuits and the search data. A WTA circuit receives the pulse signals. Reference data stored in a storage circuit corresponding to an oscillating circuit that outputs a pulse signal with the highest frequency is determined as the most similar reference data (Winner) to the search data. | 2012-07-26 |
20120188812 | HYBRID MRAM ARRAY STRUCTURE AND OPERATION - This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor | 2012-07-26 |
20120188813 | VERIFICATION ALGORITHM FOR METAL-OXIDE RESISTIVE MEMORY - Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided. | 2012-07-26 |
20120188814 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE - To provide a memory device which operates at high speed or a memory device in which the frequency of refresh operations is reduced. In a cell array, a potential is supplied from a driver circuit to a wiring connected to a memory cell. The cell array is provided over the driver circuit. Each of memory cells included in the cell array includes a switching element, and a capacitor in which supply, holding, and discharge of electric charge are controlled by the switching element. Further, a channel formation region of the transistor used as the switching element includes a semiconductor whose band gap is wider than that of silicon and whose intrinsic carrier density is lower than that of silicon. | 2012-07-26 |
20120188815 | TEMPORARY STORAGE CIRCUIT, STORAGE DEVICE, AND SIGNAL PROCESSING CIRCUIT - A temporary storage circuit including a reduced number of transistors is provided. The temporary storage circuit includes storage elements, each of which includes a first transistor and a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A signal potential corresponding to data is input to a gate of the second transistor through the first transistor which is turned on by a control signal input to a gate of the first transistor. Then, the first transistor is turned off by a control signal input to the gate of the first transistor, so that the signal potential is held in the gate of the second transistor. When one of a source and a drain of the second transistor is set to a first potential, the state between the source and the drain of the second transistor is detected, whereby the data is read out. | 2012-07-26 |
20120188816 | Row-Decoder Circuit and Method with Dual Power Systems - A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation. | 2012-07-26 |
20120188817 | Read Sensing Circuit and Method with Equalization Timing - A Magnetic Random Access Memory (MRAM) includes read sensing circuitry having an equalizer device configured between a bit cell output node and a reference node of the bit cell. The equalizer is turned on to couple the output node to the reference node during an initial portion of a read operation and to decouple the output node from the reference node after an equalization delay period. A sense amplifier is enabled to provide a data output from the bit cell only after the delay period and decoupling of the output node from the reference node to provide balanced sensing speed of data represented by parallel and antiparallel state magnetic tunnel junctions (MTJs). | 2012-07-26 |
20120188818 | Low-crystallization temperature MTJ for Spin-Transfer Torque Magnetic Random Access Memory (STTMRAM) - A spin-torque transfer memory random access memory (STTMRAM) element is disclosed and has a fixed layer, a barrier layer formed upon the fixed layer, and a free layer comprised of a low-crystallization temperature alloy of CoFeB—Z where Z is below 25 atomic percent of one or more of titanium, (Ti), yittrium (Y), zirconium (Zr), and vanadium (V), wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer. | 2012-07-26 |
20120188819 | METHODS AND SYSTEMS FOR MEMS CMOS PROGRAMMABLE MEMORIES AND RELATED DEVICES - Systems and methods for CMOS-based MEMS programmable memories are described. In one aspect, the systems and methods provide for a programmable memory having multiple memory cells. Each memory cell includes an electrode disposed within the memory cell, and a conductor material having two ends disposed proximate to the electrode. The programmable memory provides means for applying a voltage between the electrode and the conductor material, e.g., a voltage source. The applied voltage generates an electrostatic force sufficient to permanently alter the conductor material, thereby programming the memory cell. | 2012-07-26 |
20120188820 | SYSTEM AND METHOD FOR ADDRESSING THRESHOLD VOLTAGE SHIFTS OF MEMORY CELLS IN AN ELECTRONIC PRODUCT - Methods and systems for addressing threshold voltage shifts of memory cells. A method includes reading a pattern of data from a first plurality of memory cells, comparing the read of the pattern of data with a known pattern of data using a reference, and if the read of the pattern of data and the known pattern of data do not match, adjusting the reference to find a reference level that results in a matching of a read of the pattern of data and the known pattern of data. Thereafter, trim sector data is read into a second plurality of memory cells using the adjusted reference level. | 2012-07-26 |
20120188821 | METHOD FOR ACHIEVING FOUR-BIT STORAGE USING FLASH MEMORY HAVING SPLITTING TRENCH GATE - The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased. | 2012-07-26 |
20120188822 | CONTROL VOLTAGE GENERATION CIRCUIT AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME - A control voltage generation circuit for generating a control voltage for controlling a high-voltage transistor includes an input node configured to receive a first enable signal; an output node configured to generate the control voltage, a transferor configured to transfer a voltage of the input node to the output node in response to a transfer signal, an enabling voltage driver configured to drive the output node with a high voltage when the first enable signal is enabled, and a disabling voltage driver configured to drive the output node with a negative voltage when a second enable signal is enabled in a negative mode. | 2012-07-26 |
20120188823 | SEMICONDUCTOR DEVICE - A semiconductor device includes a charge pump circuit that generates a first voltage during a first period and a second voltage during a second period following the first period by a boosting operation, a load current application circuit that includes a first memory cell, and that applies the first voltage to the first memory cell, a memory circuit that includes a second memory cell, and that applies the second voltage to the second memory cell; and a voltage detection circuit that monitors a value of the first voltage to determine whether or not the first voltage is increased to the predetermined voltage, wherein the charge pump circuit stops the boosting operation if the first voltage is less than the predetermined voltage at an end of the first period. | 2012-07-26 |
20120188824 | PROGRAMMING NON-VOLATILE STORAGE WITH FAST BIT DETECTION AND VERIFY SKIP - A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target. | 2012-07-26 |
20120188825 | MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS - Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing. | 2012-07-26 |
20120188826 | MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS - In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell. | 2012-07-26 |
20120188827 | BURST ORDER CONTROL CIRCUIT - A burst order control circuit includes a signal transmitting unit transmitting a second address as first and second signals in response to a mode signal and a first address, a signal delay unit delaying a read command, the first signal, and the second signal to generate a delayed read command, a first delayed signal, and a second delayed signal, a signal generating unit configured to generate a burst signal in response to the first address and generate first and second transmission signals in response to the delayed read command and the first and second delayed signals, and an output unit sorting and outputting a plurality of data in response to the burst signal, the first transmission signal, and the second transmission signal. | 2012-07-26 |
20120188828 | DATA CAPTURE SYSTEM AND METHOD, AND MEMORY CONTROLLERS AND DEVICES - Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits. | 2012-07-26 |
20120188829 | CIRCUITS, DEVICES, SYSTEMS, AND METHODS OF OPERATION FOR CAPTURING DATA SIGNALS - Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first edge of the write strobe signal and at least a second digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each digit in substantially the same manner as the data capture circuit, and generates a latch control signal indicative of when each digit is latched. The latch control signal is provided to a write control circuit that determines which digit was latched first relative to a timing, and generates a select control signal to drive captured digits onto the bus in the order the digits were received. | 2012-07-26 |
20120188830 | SEMICONDUCTOR MEMORY DEVICE CORRECTING FUSE DATA AND METHOD OF OPERATING THE SAME - A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data. | 2012-07-26 |
20120188831 | POWER-OFF APPARATUS, SYSTEMS, AND METHODS - Some embodiments include apparatus, systems, and methods having a voltage generator to generate a voltage, a memory cell including a storage node associated with a storage node voltage, and a power controller to provide a signal to the voltage generator such that the voltage generated by the voltage generator rises from a voltage less than a reference voltage to a voltage less than the storage node voltage, and such that the voltage generated by the voltage generator is less than or equal to the storage node voltage, at least partially in response to the apparatus entering into a mode. Other embodiments are described. | 2012-07-26 |
20120188832 | MEMORY CHANNEL HAVING DESKEW SEPARATE FROM REDRIVE - A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The deskew circuit may be coupled between the plurality of redrive paths and the memory device to selectively deskew data received in the redrive circuit. | 2012-07-26 |
20120188833 | TIMING ADJUSTMENT CIRCUIT FOR A MEMORY INTERFACE AND METHOD OF ADJUSTING TIMING FOR MEMORY INTERFACE - According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal. | 2012-07-26 |
20120188834 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal. | 2012-07-26 |
20120188835 | INTEGRATED CIRCUIT WITH STAGGERED SIGNAL OUTPUT - A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request. | 2012-07-26 |
20120188836 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a bit line sense amplifier unit and a driving voltage supply unit. The bit line sense amplifier unit senses and amplifies a signal provided from a memory cell using a pull-up driving voltage provided through a pull-up power line and a pull-down driving voltage provided through a pull-down power line. The driving voltage supply unit supplies the pull-down driving voltage having a first pull-down driving force during a first amplification period, and supplies the pull-down driving voltage having a second pull-down driving force greater than the first pull-down driving force during a second amplification period after the first amplification period. | 2012-07-26 |
20120188837 | METHOD OF READING MEMORY CELL - A method for reading a memory cell ( | 2012-07-26 |
20120188838 | MEMORY WITH WORD-LINE SEGMENT ACCESS - A memory comprises a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells. A first word line segment driver is connected to the first plurality of bits cells. A second word line segment driver is connected to the second plurality of bits cells. The first and second word line segment drivers are selectively operable for activating one of the first and second pluralities of bit cells at a time to the exclusion of the other plurality of bit cells. A shared sense amplifier is coupled to at least one of the first plurality of bit cells and at least one of the second plurality of bit cells. The shared sense amplifier is configured to receive signals from whichever of the one first or second bit cell is activated by its respective word line segment driver at a given time. | 2012-07-26 |
20120188839 | BANK SELECTION CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A bank selection circuit includes a command latch unit configured to latch an input command at a time earlier than a rising edge of a clock by a setup time, a command decoder configured to decode a latched command and generate a row operation signal, a bank address latch unit configured to latch an input bank address at a time earlier than the rising edge of the clock by the setup time, a bank address decoder configured to decode a latched bank address and generate a bank selection signal, and a bank selection unit configured to receive the row operation signal and the bank selection signal and transfer the row operation signal to a bank selected by the bank selection signal. | 2012-07-26 |
20120188840 | EXTRUDER - An extruder is provided that has a housing with at least two axially parallel shafts which are capable of being driven in the same direction and with at least two-flight intermeshing conveying elements stripping each other at an axial distance (Ax) with a small clearance over the entire circumference. The extruder has a distance between the comb of the at least one further flight and the inner wall of the housing. Each conveying element has at least two conveying sections rotated through an angle, wherein each conveying section has an axial length corresponding to at most the outer diameter of the conveying element. | 2012-07-26 |
20120188841 | Hermetic Blender - A hermetic blender comprises a hermetic blender station, a base platform, a cup, and a holder. The hermetic blender station is connected to the base platform. The cup is inserted into the holder and the holder is attached to the hermetic blender station. The cup is sealed into a cup seal which is positioned in the hermetic blender station. A blade which is positioned inside the hermetic blender station mixes the ingredients which are filled inside the cup. Because of the air tight seal between the cup seal and the cup, and the unique movement of the blade, the hermetic blender is capable of mixing different viscosity products without introducing air into the product. | 2012-07-26 |
20120188842 | METER FLOW CONDITIONER - A fluid conditioner for a fluid traveling through a conduit, the conduit having a longitudinal axis and substantially circular cross-section. The fluid conditioner includes a static mixing element and a straightener plate. The plate is affixed to a substantially rectangular member located downstream of the static mixing element and oriented substantially perpendicularly to the longitudinal axis of the conduit, the plate substantially covering the cross-section of the conduit having a plurality of openings to facilitate the passage of the fluid within the conduit. | 2012-07-26 |
20120188843 | Axially Operating Stirring Element Manufactured from Sheet Metal - An axially operating stirring element, preferably a propeller manufactured from sheet metal, having propeller blades arranged radially around an axis (A) and in which at least one propeller blade has a sharpened edge on the discharge or trailing edge side. | 2012-07-26 |
20120188844 | ACOUSTIC REFLECTORS - An acoustic reflector comprises a shell surrounding a solid joint free core, said shell being capable of transmitting acoustic waves incident on the surface of the shell into the core to be focused and reflected from an area of the shell located opposite to the area of incidence so as to provide a reflected acoustic signal output from the reflector. The ratio of the speed of sound wave transmission in the shell to the average speed of the wave transmission in the core is preferably in the range of 2.74 to 3.4, inclusive or a multiple thereof with best result in the range of 2.74 to 2.86 inclusive. | 2012-07-26 |
20120188845 | Seismic Vibrator to Produce a Continuous Signal - A seismic vibrator receives a pilot signal having a predetermined waveform. The pilot signal causes vibrational actuation of at least one moveable element of the seismic vibrator. A continuous seismic signal having content in a first frequency bandwidth of multiple frequencies is generated by the seismic vibrator. | 2012-07-26 |
20120188846 | METHOD AND APPARATUS FOR PACKAGING SURFACE ACOUSTIC WAVE TRANSPONDER FOR DOWN-HOLE TOOLS - A method and apparatus for packaging a surface acoustic wave transponder for use in down-hole tool oil & gas environments is provided. An exemplary transponder comprises a surface acoustic wave piezoelectric device, wire bonds, an antenna element, an antenna substrate, a header, and protective coating. The exemplary surface acoustic wave piezoelectric device is attached into a header and wire bonded to the connection leads, which are connected to an antenna element, and then sealed by a protective coating. The header is hermetically sealed and withstands high pressure high temperature environment found in oil & gas down-hole environment. | 2012-07-26 |
20120188847 | POSITION DETECTION APPARATUS, POSITION DETECTION METHOD, MOBILE, AND RECEIVER - To detect the positions of the respective mobiles correctly without being affected by the ultrasonic waves from other mobile(s) in a case where plural mobiles are used simultaneously. | 2012-07-26 |
20120188848 | ULTRASONIC UNDERWATER PAGER - Disclosed herein is an underwater pager configured such that a hole is not formed in the outer wall of a casing. The ultrasonic underwater pager includes an ultrasonic transducer for transmitting or receiving ultrasonic signals. An electronic circuit unit generates an ultrasonic signal and analyzes a received ultrasonic signal. A switch unit is switched using a magnetic phenomenon and is configured to supply power to the electronic circuit unit and transmit external commands to the electronic circuit unit. A watertight casing is configured such that the ultrasonic transducer, the electronic circuit unit, and the switch unit are installed in the watertight casing, the ultrasonic transducer being installed in a raised position in the watertight casing using a molding process. A magnet is attached to a rubber cover connected to an outside of the watertight casing, and is configured to switch on/off the switch unit using a magnetic phenomenon. | 2012-07-26 |
20120188849 | ULTRASONIC SENSOR AND ELECTRONIC DEVICE - The ultrasonic sensor includes: a plurality of transmission/reception dual-use elements, first electrode switches connected to the first electrodes of the transmission/reception dual-use elements; second electrode switches connected to the second electrodes of the transmission/reception dual-use elements; a control circuit; a transmitting circuit; a receiving circuit; a common-electrode connection wiring; and serial connection wiring. When an ultrasonic signal is to be transmitted, the control circuit connects the first electrode switches to the transmitting circuit, connects the second electrode switches to the common-electrode connection wiring so that the transmission/reception dual-use elements are connected in parallel to the transmitting circuit and the common electrode. When an ultrasonic signal is to be received, the control circuit connects the first electrode switches and the second electrode switches to the serial connection wiring so that the transmission/reception dual-use elements are serially connected to the receiving circuit. | 2012-07-26 |
20120188850 | ULTRASONIC SENSOR UNIT AND ELECTRONIC DEVICE - An ultrasonic sensor unit includes a transmission base plate and a reception base plate. The transmission base plate includes an ultrasonic transmission sensor configured and arranged to transmit ultrasonic waves. The reception base plate includes an ultrasonic reception sensor configured and arranged to receive the ultrasonic waves. One of the transmission base plate and the reception base plate define a through-hole at a position corresponding to one of the ultrasonic transmission sensor and the ultrasonic reception sensor provided in the other of the transmission base plate and the reception base plate so that the one of the ultrasonic transmission sensor and the ultrasonic reception sensor is exposed through the through-hole. | 2012-07-26 |
20120188851 | Electronic apparatus, timepiece device, pedometer, and program - Provided is a timepiece device that includes a time measurement portion which measures a time, wherein, when a measured time passes a predetermined target time, and when information indicating that there is an input from a user is input, the time measurement portion sets the time to zero and restarts the measurement of the time. | 2012-07-26 |
20120188852 | ANNUAL CALENDAR DEVICE FOR A TIMEPIECE - The annual calendar device carries a date ring ( | 2012-07-26 |
20120188853 | ELECTRONIC DEVICE WITH TIME UPDATE FUNCTION AND TIME UPDATE METHOD - An electronic device with time update function includes a radio module, a clock module, an audio input port, a storage module, and a processing module. The radio module receives and outputs audible signals from the broadcasts of a broadcasting station. The audio input port receives audible sound generated by the radio module, and the clock module provides a source of real time. The processing module determines whether the signals received by the audio input port include current time information, and if so whether the system time is consistent with the current time information. The processing module updates the stored initial time with the current time information and adjusts the system time as necessary. A time update method is also provided. | 2012-07-26 |
20120188854 | Time Adjustment Device, Timekeeping Device With A Time Adjustment Device, And Time Adjustment Method - A time adjustment device can acquire time information in a short time, reduce power consumption, and display the correct time. A GPS wristwatch has a reception unit that receives satellite signals; a time information generating unit that generates internal time information; a reception control unit that controls the reception unit; and a time information adjustment unit that adjusts the internal time information. The time information adjustment unit has a first information time adjustment means that receives first information containing year, month, day, hour, minute, second, and satellite health information, and adjusts the internal time information; a second information time adjustment means that receives second information including leap second information, and adjusts the internal time information; a third information time adjustment means that receives third information of hour, minute, second information, and adjusts the internal time information. | 2012-07-26 |
20120188855 | TIMEPIECE - A timepiece according to a first aspect of the invention has a fan-shaped display unit including a display wheel that can rotate, a stepping motor that rotationally drives the display wheel in both forward and reverse directions, a reverse stop that limits reverse rotation of the display wheel, and an indication means that is attached to the display wheel; and a control unit that applies pulses to the stepping motor. The position of the reverse stop is set so that the orientation of one polar axis of the rotor of the stepping motor when the display wheel is stopped by the reverse stop at the reverse stop is within ±360°/(number of magnetic poles of rotor*2) from the static stable position of the polar axis. After stopping at the reverse stop, the polarity of the first pulse applied to the stepping motor by the control unit is constant. | 2012-07-26 |
20120188856 | Electronic apparatus, timepiece device and program - Provided is a timepiece device that includes a first time measurement portion which measures an elapsed time from a first timekeeping start operation; and a second time measurement portion which measures an elapsed time from a second timekeeping start operation, wherein a time measured by the first time measurement portion, and a time, which is a time measured by the second time measurement portion subtracted from an object time, are displayed on the display portion in a combined manner. | 2012-07-26 |
20120188857 | Comfort Watch - A watch comprising: a watch bezel; a watch case in communication with the watch bezel, the watch case comprising several vents which are generally configured to allow air to flow through the vents. | 2012-07-26 |
20120188858 | Wristwatch - A wristwatch includes a moulded plastics case upper having first snap-engagement protrusions. A moulded plastics case lower has second snap-engagement protrusions cooperative with the first snap-engagement protrusions to secure the case upper and case lower together. The case upper and case lower can be of mutually different colour. | 2012-07-26 |
20120188859 | THERMALLY-ASSISTED MAGNETIC HEAD - A thermally-assisted magnetic head that includes an air bearing surface facing a recording medium and that performs magnetic recording while heating the recording medium includes: a magnetic recording element including a pole of which one edge part is positioned on the air bearing surface and that generates magnetic flux traveling toward the magnetic recording medium; a waveguide configured with a core through which light propagates and a cladding, at least one part of which extends to the air bearing surface, surrounding the periphery of the core; a plasmon generator that faces a part of the core and that extends to the air bearing surface. The plasmon generator is configured with a first part and a second part that are joined; the first part that is positioned on the air bearing surface side and that is made of a high melting point material, and the second part that is positioned away from the air bearing surface and that is made of a material with a small value ∈″, which is an imaginary component of permittivity. | 2012-07-26 |
20120188860 | INFORMATION STORAGE MEDIUM AND RECORDING/REPRODUCING APPARATUS AND METHOD USING THE SAME - An information storage medium and a recording/reproducing apparatus and method, the information storage medium includes: an area for recording information regarding a predetermined function applied thereto, wherein the information regarding the predetermined function includes specific information in which set information regarding the predetermined function is set by a recording/reproducing apparatus that can recognize the predetermined function, and common information set by the recording/reproducing apparatus that can recognize the predetermined function based on corresponding information dependent upon the set information so that a recording/reproducing apparatus that cannot recognize the predetermined function can use the predetermined function. Accordingly, a recording/reproducing apparatus that cannot recognize a predetermined function can properly use a medium having the predetermined function. | 2012-07-26 |
20120188861 | POWER SAVING METHOD AND SYSTEM APPLIED IN OPTICAL DISK DRIVE - A power saving method and a power saving system are applied in an optical disk drive. The power saving system comprises a power controlling unit for differentiating the specific sets of circuits not being used at a specific operation rate and powering them down. The sets of circuits not being used will be powered up while the associated operation rate at which they are required to operate is nearly started. | 2012-07-26 |
20120188862 | APPARATUS AND METHOD FOR CERTIFYING A MAGNETIC RECORDING DISK - Apparatuses and methods for certifying a magnetic recording disk ( | 2012-07-26 |
20120188863 | OPTICAL RECORDING METHOD, OPTICAL RECORDING DEVICE, MASTER MEDIUM EXPOSURE DEVICE, OPTICAL INFORMATION RECORDING MEDIUM, AND REPRODUCING METHOD - An optical recording method includes the steps of: encoding record data to generate encoded data which is a combination of marks and spaces; classifying the encoded data according to a combination of a mark length of the mark, a space length of a first space that immediately precedes the mark, and a space length of a second space that immediately succeeds the mark; generating a write pulse train for forming the mark, in which at least one of a leading end edge position, a trailing end edge position and a pulse width of the write pulse train is changed according to a classification result; and irradiating the optical disc medium with the write pulse train generated to form the plurality of marks on the optical disc medium. | 2012-07-26 |
20120188864 | RECORDING MEDIUM AND REPRODUCING APPARATUS - A recording medium includes a photosensitive layer, a nonphotosensitive layer, and a recording layer formation region in which the photosensitive layer and the nonphotosensitive layer are laminated. The photosensitive layer includes a recording layer in which interference fringes formed in parallel with a recording medium surface are deleted or changed within a portion irradiated with focused light to record information or light reflected during irradiation of focused light is used to reproduce information. | 2012-07-26 |
20120188865 | Intelligent Patching Systems and Methods Using Phantom Mode Control Signals and Related Communications Connectors - Communications connectors are provided that include a plurality of input ports, a plurality of output ports and a plurality of conductive paths. Each of the conductive paths connects a respective one of the input ports to a respective one of the output ports. The conductive paths are arranged as a plurality of differential pairs of conductive paths that are each configured to carry a differential signal. These connectors further include a control signal input circuit that is configured to capacitively couple a phantom mode control signal onto at least a first and a second of the differential pairs of conductive paths. | 2012-07-26 |
20120188866 | COMMUNICATION CONTROL APPARATUS AND COMMUNICATION CONTROL METHOD - A communication control apparatus includes a storage unit and a processor. The storage unit stores, in association with a port number, first address information regarding apparatuses connected to a port identified by the port number. The processor receives a first affected address list containing second address information regarding apparatuses which may be affected by a trouble, extracts the first address information stored in the storage unit in association with a port number of a port via which the first affected address list has been received, selects third address information which is included in both the first and second address information, updates the first affected address list by replacing the second address information with the third address information to acquire a second affected address list, and transmits the second affected address list via each port other than the port via which the first affected address list has been received. | 2012-07-26 |
20120188867 | RECOVERY OF TRAFFIC IN A CONNECTION-ORIENTED NETWORK - A connection-oriented network ( | 2012-07-26 |
20120188868 | SYSTEM, METHOD, COMPUTER PROGRAM FOR MULTIDIRECTINAL PATHWAY SELECTION - The present invention is a system, method and computer program product operable to select a pathway for a communication signal within a network between two end points. The pathway may be selected based on one or more parameters that may be monitored or measured at either, or both, of the two end points. Should one or more of the parameters indicate an imminent network connection failure, the communication signal may be transferred from a primary communication connection to a second communication connection. The present invention may distinguish false from true positive detections and may undertake a transfer of a communication signal within a short response time, so as to support real-time applications. The present invention may manage the pathway to support communication between the two end points at any given time. Such communications may occur in two directions, therefore the management of the pathway can happen in two directions. | 2012-07-26 |
20120188869 | ADAPTIVE MULTI-REDUNDANT RING NETWORK SYSTEM AND METHOD FOR SELECTING DETOUR - Disclosed is an adaptive multi-redundant ring network system using a 2 port Ethernet communication module capable of selecting a path, the network system including a main network system including a first main control unit and a plurality of first slaves; and a sub-network system including a second main control unit and a plurality of second slaves, wherein each of the plurality of first slaves and each of the plurality of second slaves include 2-port Ethernet communication modules, and each of the plurality of first slaves, each of the plurality of second slaves, the first slave and the second slave are selectively connected via the 2-port Ethernet communication modules. | 2012-07-26 |
20120188870 | Discovery and Capability Exchange Management in a Virtualized Computing Platform - In various embodiments a traffic class manager is a resource within a virtualized computer systems trusted entity (e.g. a hypervisor, trusted partition, etc.) that maps requirements from a platform management and associated network capabilities onto an adapter (e.g. SR-IOV adapter, etc.) in order to appropriately allocate adapter and network resources to virtualized computer partitions. In various embodiments the traffic class manager defines network traffic classes that meet the objectives of a platform administrator based on the capabilities of the adapter and the network attached to the adapter ports. Once the traffic classes are defined, in various embodiments, the traffic class manager enforces the assignment of a traffic class to a virtual interface queue pair within a partition. | 2012-07-26 |
20120188871 | ETHERNET PORT SPEED CONTROL METHOD AND DEVICE - There is proposed a speed control method for controlling a link speed of an Ethernet port. The method comprises steps of detecting the amount of data to be sent via the Ethernet port, and controlling the link speed of the Ethernet port based on the detected amount of data. The step of controlling the link speed of the Ethernet port based on the detected amount of data further comprises steps of comparing the detected amount of data with a predefined threshold, and setting the link speed level of the Ethernet port based on the comparison. According to the solutions provided in the embodiments of the present invention, the present invention may set the Ethernet port to a lower speed when there is no large amount of data to be sent, and thus implements power saving without changes to the infrastructure of the Ethernet. | 2012-07-26 |
20120188872 | SYSTEM AND METHOD FOR MEASURING INTERFACE UTILIZATION USING POLICERS - An approach is provided for monitoring interface utilization. Bandwidth data for an interface is collected during a configurable time interval, and a peak utilization of the interface over the time interval is determined using a plurality of incremented policers to measure the collected bandwidth data. An implementation of which is system that includes a monitoring module configured to collect bandwidth data for an interface over a configurable time interval, a plurality of incremented policers configured to measure the collected bandwidth data, and an analysis module configured to determine a peak utilization of the interface over the time interval using the measurements of the plurality of incremented policers. | 2012-07-26 |
20120188873 | COMMUNICATION SYSTEM, COMMUNICATION METHOD, RECEIVING APPARATUS, AND TRANSMITTING APPARATUS - A communication system includes a transmitter that transmits a data flow through a single link or a parallel links, and a receiver that receives packets of the data flow, when the data flow of the received packets is transmitted through the parallel links, the received packets are aligned in order and output, and when the data flow of the received packets is transmitted through the single link, the received packets are output in a received sequence. | 2012-07-26 |
20120188874 | RELAY DEVICE AND RELAY METHOD - A relay device of relaying a communication packet is disclosed, which comprises: an input module configured to receive the communication packet as an input; a buffer configured to have a plurality of queues and temporarily accumulated the received communication packet; a sorter configured to sort the received communication packet to one of the plurality of queues, depending on a specific value obtained by a predetermined function that gives an aggregate output from an input which is transfer information regarding transfer of the communication packet; and a band controller configured to control a bandwidth for each of the plurality of queues and output communication packets accumulated in the plurality of queues for transmission of the communication packets. This ensures the quality of service, while saving the capacity of the buffer used for the queues. | 2012-07-26 |
20120188875 | METHOD AND APPARATUS FOR CARRIER IDENTITY DETERMINATION IN MULTI-CARRIER COMMUNICATION SYSTEMS - Systems and methods are described that facilitate the determination and request of resources a node may wish to reserve. The resources include a plurality of carriers that are shared with other nodes. In an approach, the node determines a condition related to the plurality of carriers; creates an ordering of the plurality of resources; and transmits a resource utilization message (RUM) for one or more of the plurality of resources based on the ordering and the condition. | 2012-07-26 |
20120188876 | Smart Connection Manager - A telecommunication device configured to perform at least one of adjusting a network polling frequency, prompting a user to select one of a plurality of networks, automatically connecting to one of the networks, or automatically disconnecting from one of the networks is described herein. The telecommunication device performs the adjusting, prompting, or connecting based at least on received device data or network data that is associated with the networks. | 2012-07-26 |
20120188877 | Methods and Apparatus to Perform Reference Signal Measurements in a TDD-LTE System From a TD-SCDMA System - Methods and apparatus are provided for performing measurement of reference signals in the proper subframes of a first radio access technology (RAT) while operating in a second RAT. For certain aspects, the first and second RATs may be Time Division Duplex Long Term Evolution (TDD-LTE) and Time Division—Synchronous Code Division Multiple Access (TD-SCDMA), respectively. By knowing the correct TDD-LTE downlink and uplink subframe configurations, a user equipment device (UE) may temporarily leave the TD-SCDMA network during an idle interval and perform expedited and accurate measurement of TDD-LTE reference signals without errors from trying to measure reference signals during uplink subframes. | 2012-07-26 |
20120188878 | UNIVERSAL BROADBAND BROADCASTING - A universal broadband broadcasting service is provided. A spectrum-sharing database stores attributes associated with a shared spectrum, a policy controller controls access to the shared spectrum by broadcast service entities, and a gateway receives IP multicast traffic from the broadcast service entities and communicates the IP multicast traffic to a broadcast single frequency network. | 2012-07-26 |
20120188879 | Service Monitoring and Service Problem Diagnosing in Communications Network - User equipment uses traces of service primitives of one or multiple service sessions to automatically discover a service sequence. Service sequences are refined by analyzing sequences captured during multiple sessions of the same service. A daemon receives from a plurality of user equipment the observed service sequences. The sequences from different user equipment are aggregated. The daemon sends back the refined service sequences to user equipment. User equipment sends a problem report to the daemon and/or a service monitor in the case of a service failure. The daemon or the service monitor aggregates such problem reports and discovers the causes of service degradations. | 2012-07-26 |
20120188880 | Method and System for Performing Multi-Layer, Multi-Dimensional Link Budget Analysis (LBA) Using Real-Time Network, Weather, Satellite Ephemeras and Ionospheric Information - Methods of dynamically modeling performance of a communications network that may include modeling a communications network using a processor by performing a link budget analysis (LBA) for a configuration of the communications network, receiving a plurality of layers of real-time information about the communications network, iteratively performing additional LBAs using one or more of the layers of real-time information from among the plurality of layers of real-time information, multi-dimensionally co-modeling a matrix comprising results of the iteratively performed additional LBAs, and determining one or more final communications network configuration parameters based on the multi-dimensionally co-modeled matrix. | 2012-07-26 |
20120188881 | Adaptive Transmission Systems and Methods - Abstract Spatial multiplexing and transmit diversity can improve the capacity of a wireless communication system. The system and method adapts communication schemes for communication systems with multiple antennas utilizing at least two transmission modes. The at least two transmission modes can, but are not necessarily, used for uplink communications. The two transmission modes may be chosen from the group consisting of a single antenna mode, a diversity mode a spatial multiplexed mode and a mixed diversity and spatial multiplexed mode. The at least two transmission modes may involve adaptation among multiple transmitters. At least one receiver may indicate a transmission mode to be used by a transmitter for a subsequent transmission. A transmitter may determine a transmission mode to be used for a subsequent transmission. The transmission mode can be based on channel sounding. | 2012-07-26 |
20120188882 | Determining Mobile Video Quality of Experience and Impact of Video Transcoding - Video data packets transmitted through a wireless network are captured by a network monitoring system. Video data sessions are detected from the video data packets. Key parameters are identified within the video data packets, such as video bit rate, resent or failed video packets, and video session duration. A Quality of Experience (QoE) is determined for some or all users associated with the video sessions based upon the key parameters. A header extension is added to the video data packets by a transcoding system. The header extension includes data associated with original and transcoded video data packets. The network monitoring system monitors the header extension and evaluates the effect of video transcoding upon the overall QoE for users. The monitoring system provides feedback to a transcoding policy engine based upon the effect of transcoding upon QoE. | 2012-07-26 |
20120188883 | NEGOTIATED CHANNEL INFORMATION REPORTING IN A WIRELESS COMMUNICATION SYSTEM - Techniques to enhance the performance in a wireless communication system using CQI feedback optimized to support different scenarios. According to one aspect, an access terminal may select a CQI feedback table based on the access terminals capability. According to another aspect, an access point may select a CQI feedback table based on an access terminals capability, system loading and the type of service provided by the access point. An access point which provides services that require high data rates may select a larger CQI feedback table to support the high data rates for access terminals which support the larger CQI feedback table. The same access point may select a smaller CQI feedback table for access terminals which do not have the capability or need for the high data rate services. | 2012-07-26 |
20120188884 | METHOD AND A NETWORK NODE FOR DETERMINING AN OFFSET FOR SELECTION OF A CELL OF A FIRST RADIO NETWORK NODE - A method and network node ( | 2012-07-26 |
20120188885 | METHOD AND SYSTEM FOR SELF-ADAPTING DYNAMIC POWER REDUCTION MECHANISM FOR PHYSICAL LAYER DEVICES IN PACKET DATA NETWORKS - A physical layer (PHY) in a network device may provide self-adapting power reduction based on monitoring of activity associated with an interface between the PHY and remaining components of the network device. The power management operations of the PHY may then be configured and/or adjusted based on that monitoring. The PHY may comprise an Ethernet PHY, which may support energy efficient Ethernet (EEE) features. The monitored interface may comprise a Media Independent Interface (MII) based interface. In instances where the monitored activity comprises outbound traffic, outbound data received via the interface may be buffered when at least one subcomponent of the PHY that is operable to support transmission of the outbound traffic is unavailable due to the power management operations. The buffering may be configured to last to allow sufficient time to reactivate the at least one subcomponent. | 2012-07-26 |
20120188886 | Allocation Method for Physical Downlink Control Channel, Base Station and User Terminal - The present invention discloses a method for configuring a Physical Downlink Control Channel (PDCCH), a base station and a UE, wherein the base station configures a component carrier or component carriers for monitoring the PDCCH for the UE and notifies the UE about information on the configured component carrier or component carriers so that the UE monitors the PDCCH only over the configured component carrier or component carriers. Stated otherwise, in this way, the UE will operate only over a necessary component carrier or component carriers without monitoring respective component carriers in an LTE-A system to thereby reduce the number of concurrently monitored component carriers, and in the case of nonconsecutive component carriers, also reduce the number of consequently enabled receivers and consequently the amount of consumed power of the UE for monitoring the PDCCH. | 2012-07-26 |
20120188887 | COMMUNICATION TERMINAL AND COMMUNICATION METHOD - In a situation where a communication line is busy in a TCP communication, or in a situation where TCP data is continuously received, divided transmission of TCP-ACK is suppressed. A communication terminal includes a transmission standby frequency estimation unit | 2012-07-26 |
20120188888 | METHOD AND DEVICE FOR CONTROLLING THE DOWNLINK TRANSMISSION IN THE COORDINATED MULTI-POINT TRANSMISSION SYSTEM - A method for controlling the downlink transmission and a device for the signal associated processing in the coordinated multi-point transmission system are provided, which relate to the mobile communication technology, for optimizing the downlink transmission control in the coordinated multi-point transmission system. The embodiment aims at the coordinated multi-point transmission system, and in the base station side according to the SINR1 level of the frequency domain resource block fed back by the user, the mating result of the user, the associated resource allocation result and the pretreatment weight value result, determines the Modulation and Coding Scheme (MCS) level of the scheduled user channel to provide the accuracy of the MCS level, thus optimizing the downlink resource configurations, further increasing the throughput of the system. | 2012-07-26 |
20120188889 | DYNAMIC ENABLING AND DISABLING OF CLTD OPERATION VIA HS SCCH ORDERS - Apparatus and methods of wireless communication include configuring a closed loop transmit diversity (CLTD) operation between a User Equipment (UE) and an access node, detecting a condition of an uplink from the UE to the access node, and disabling CLTD operation by the UE based upon the condition. Optionally, the apparatus and methods may further include detecting that the condition of the uplink has ended, and in response enabling the CLTD operation. | 2012-07-26 |