30th week of 2013 patent applcation highlights part 58 |
Patent application number | Title | Published |
20130191545 | INFORMATION SENDING METHOD, DEVICE, AND SYSTEM - Embodiments of the present invention disclose an information sending method, device, and system, which are applied in the field of communications technologies. In the embodiments of the present invention, a control point sends a connection request to a target user equipment, where the connection request includes a guidance identifier, so as to request the target user equipment to receive detail information sent by the control point; after displaying the guidance identifier to a user and receiving a guidance identifier selected by the user, the user equipment sends a connection request acceptance message to the control point; and the control point may send detail information that corresponds to the guidance identifier to the target user equipment, where the guidance identifier is selected by the user and included in the connection request acceptance message, thereby implementing information guidance for the user by the control point. | 2013-07-25 |
20130191546 | OPTIMIZING ELECTRONIC COMMUNICATION CHANNELS - A method, computer program product, and system for electronic communication is described. A first unified telephony session is selected. A first arbitrator associated with the first session is selected. A first set of participants associated with the first session is selected. The first arbitrator is directed to act as a proxy connection for a first channel associated with the first set of participants. | 2013-07-25 |
20130191547 | Processing STREAMS Messages Over a System Area Network - A computer implemented method processes STREAMS messages over an Infiniband system area network. STREAMS messages received at a STREAMS over Infiniband module from a STREAMS based application are encapsulated in Infiniband verbs to create an encapsulated STREAMS message. A STREAMS identifier header is appended onto the Infiniband verb. The STREAMS over Infiniband module forwards the encapsulated STREAMS message to a streams interface layer where the encapsulated STREAMS message is then forwarded to a host channel adapter of the Infiniband system area network. | 2013-07-25 |
20130191548 | Processing STREAMS Messages Over a System Area Network - A computer implemented method processes STREAMS messages over an Infiniband system area network. STREAMS messages received at a STREAMS over Infiniband module from a STREAMS based application are encapsulated in Infiniband verbs to create an encapsulated STREAMS message. A STREAMS identifier header is appended onto the Infiniband verb. The STREAMS over Infiniband module forwards the encapsulated STREAMS message to a streams interface layer where the encapsulated STREAMS message is then forwarded to a host channel adapter of the Infiniband system area network. | 2013-07-25 |
20130191549 | REDUNDANT MEDIA PACKET STREAMS - This invention concerns the transmitting and receiving of digital media packets, such as audio and video channels and lighting instructions. In particular, the invention concerns the transmitting and receiving of redundant media packet streams. Samples are extracted from a first and second media packet stream. The extracted samples are written to a buffer based on the output time of each sample. Extracted samples having the same output time are written to the same location in the buffer. Both media packet streams are simply processed all the way to the buffer without any particular knowledge that one of the packet streams is actually redundant. This simplifies the management of the redundant packet streams, such as eliminating the need for a “fail-over” switch and the concept of an “active stream”, The location is the storage space allocated to store one sample. The extracted sample written to the location may be written over another extracted sample from a different packet stream previously written to the location. These extracted samples written to the same location may be identical. | 2013-07-25 |
20130191550 | MEDIA STREAMING APPARATUS - An apparatus comprising at least one processor and at least one memory including computer program code the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform: determining at least a first signal and an associated second signal; storing the first signal in a first file; generating in the first file and associated with the first signal a reference pointer to a location; and storing at the location indicated by the reference pointer the second signal associated with the first signal. | 2013-07-25 |
20130191551 | METHOD AND SYSTEM FOR PROPAGATING STATISTICS BETWEEN FEDERATED CONTACT CENTER SITES FOR USE IN EVENT DISTRIBUTION - A routing system includes a router, a statistics server (Stat Server) coupled to the router, receiving, processing and storing statistics related to event handling, and providing information regarding the statistics for use by routing intelligence in the router, and a first proxy data server coupled to the Stat Server and to a second proxy data server at a remote contact center over a network. The system is characterized in that the Stat Server receives event statistics regarding the local queue, and through the coupled first and second proxy data servers, event statistics regarding the remote queue, provides information related to the statistics to the router, and the router determines to route incoming events to local queue or to the remote queue based on the information provided. | 2013-07-25 |
20130191552 | METHODS AND SYSTEMS FOR MAPPING FLOW PATHS IN COMPUTER NETWORKS - Methods and systems are provided for determining a flow path for a flow between a source host and a destination host on a computer network wherein the flow has a tuple associated therewith. In one embodiment, a method comprises receiving flow data from exporters on the network, finding one or more exporters that possibly carry the flow, and using the flow data to determine whether any of the one or more exporters that possibly carry the flow include the tuple. For any exporters that include the tuple, the flow data is used to determine a next hop for such exporter. Connection pairs are created between each exporter that includes the tuple and its next hop. The connection pairs are combined to define the flow path. | 2013-07-25 |
20130191553 | System and Method for Interconnection of Diverse Devices - A system and method for enabling communication is disclosed, wherein the system may include a plurality of media devices configured to cooperate within a media delivery environment; at least one of the media devices having a wireless communication transceiver coupled thereto; a database for storing device-specific command data for the plurality of media devices; and a computing system operable to (a) receive a request from a first media device to interact with a second media device; (b) convert the interaction request into device-specific command data for the second media device; and (c) transmit the device-specific command data to the second media device. | 2013-07-25 |
20130191554 | Online Indicator Adapter - A dongle adapter system is described that is configured to communicate in a first direction using a first communications protocol and to communicate in a second direction using a second communications protocol. Communications in the first direction employ a conventional communications protocol, such as the Universal Serial Bus (“USB”) protocol. Communications in the second direction employs an Auxiliary Interface Bus (“AIB”) protocol; in some embodiments, the employed AIB protocol may be proprietary. A translator associated with the dongle adapter translates communications between the first communications protocol and the second communications protocol. The dongle adapter allows a peripheral device organiclly configured for the second communications protocol to function without modification in computing networks whose communications operate on the first communications protocol. | 2013-07-25 |
20130191555 | INTELLIGENT STORAGE CONTROLLER - An intelligent storage controller operating in conjunction with a computer running an application that uses the data managed by the intelligent storage controller, and requires data transformation operations to be performed on the data. The intelligent storage controller is adapted to directly perform the data transformation operations on the data controlled by the controller, under the direction of the computer running the application, thereby offloading this processing entirely to the intelligent storage controller. The intelligent storage controller may also provide an application programming interface for the computer running the application to use in directing commands to the intelligent storage controller. To accommodate varying workloads on the intelligent storage controller, data transformation tasks may be load balanced between the intelligent storage controller, the computer running the application, and/or other hosts. | 2013-07-25 |
20130191556 | PLUG-AND-PLAY SENSOR PERIPHERAL COMPONENT FOR PROCESS INSTRUMENTATION - A plug-and-play sensor peripheral component includes an electrically conductive physical connector; an electrical connector; a transformer; and an RF communication and data storage circuit. The electrical connector is electrically connected to the physical connector by a first conductive path. The transformer is electrically connected to the RF communication and data storage circuit. The transformer and the RF communication and data storage circuit are electrically isolated from the physical connector and the electrical connector. Electrically connecting the physical connector to the electrical connector by other than the first conductive path inductively couples the RF communication and data storage circuit to the first conductive path. | 2013-07-25 |
20130191557 | ELECTRONIC SYSTEMS AND MANAGEMENT METHODS - A management method is provided, suitable for an electronic system having electronic devices connected in a daisy-chain configuration. The management method includes the steps of: arranging the order of the electronic devices, wherein universal unique identifiers corresponding to the electronic devices are obtained by sequentially connecting the electronic devices with the host; obtaining shapes and outward colors of the electronic devices according to the universal unique identifiers of the electronic devices; forming a chart according to the arrangement order, the shapes and the outward colors of the electronic devices; and displaying the chart on the monitor and/or the host to show a characteristic of each of the electronic devices. | 2013-07-25 |
20130191558 | CONTINUOUS READ BURST SUPPORT AT HIGH CLOCK RATES - A memory device includes a memory array, an output buffer, an initial latency register, and an output signal. Often times a host device that interfaces with the memory device is clocked at high rate such that data extraction rates of the memory device are not adequate to support a gapless data transfer. The output signal is operable to stall a transmission between the memory device and the host device when data extraction rates from the memory array are not adequate to support output rates of the output buffer. | 2013-07-25 |
20130191559 | PREVENTING THE DISPLACEMENT OF HIGH TEMPORAL LOCALITY OF REFERENCE DATA FILL BUFFERS - The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content. | 2013-07-25 |
20130191560 | METHOD AND APPARATUS FOR BUFFER INITIALIZATION - A method, apparatus and computer program product are provided herein to enable buffer initialization and/or clearance to occur on, for example, a mobile terminal. In some example embodiments, a method is provided that comprises receiving an indication that a buffer has been initialized by a host. The method of this embodiment may also include receiving source code from the host. In some example embodiments, the source code is received from a program running on the host and is configured to cause the buffer that has been initialized by the host to be cleared. The method of this embodiment may also include executing the source code such that the buffer that has been initialized by the host is cleared. | 2013-07-25 |
20130191561 | DATA READING DEVICE, COMMUNICATION DEVICE, DATA READING METHOD AND PROGRAM - The wireless communication device of the present invention is provided with a received data FIFO for temporarily storing received data, and a data reading section for reading received data from the received data FIFO. The data reading section, when received data to be read is stored in the received data FIFO, reads and outputs the stored received data. Meanwhile, when the received data to be read is not stored in the received data FIFO and a predetermined condition is fulfilled, the data reading section outputs dummy received data. Furthermore, when the received data to be read is not stored in the received data FIFO and the predetermined condition is not fulfilled, the data reading section outputs an error. | 2013-07-25 |
20130191562 | SYNCHRONIZED MULTICHANNEL UNIVERSAL SERIAL BUS - The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external source, and in another aspect comprising observing USB traffic and locking a local clock signal of a USB device to a periodic signal contained in USB data traffic, wherein the locking is in respect of phase and/or frequency. | 2013-07-25 |
20130191563 | TRANSMITTING DEVICE, TRANSMITTING METHOD, RECEIVING DEVICE, RECEIVING METHOD, TRANSMITTING/RECEIVING SYSTEM, AND CABLE - To enable signal transmission at a high data rate while securing backward compatibility. | 2013-07-25 |
20130191564 | METHOD FOR DISPLAYING DYNAMIC CONTENTS THROUGH USB STORAGE MEDIA - A presentation system includes a remote device with a dynamic storage subsystem that dynamically updates designated storage locations in actual or virtual memory with content for presentation at times associated with the presentation of the updated content by a presentation device. The presentation device, which is connected to the remote device by a data transport connection, accesses the content from the designated storage locations and presents the content as playback data. | 2013-07-25 |
20130191565 | MODIFIED I/OS AMONG STORAGE SYSTEM LAYERS - A method of managing I/Os in a storage system between a first storage layer and a second layer which is a logical abstraction over the first storage layer, comprising of maintaining within the first storage layer of the storage system validity status data indicating a validity status of each one of a plurality of first layer storage segments, in response to a write command that includes payload data which relates to part of an invalid segment providing the second layer with an unaligned write to an invalid segment indication, and in response to receiving the indication at the second layer, providing a modified write command for the invalid segment including initial values combined with the payload data. | 2013-07-25 |
20130191566 | Overcoming Limited Common-Mode Range for USB Systems - An intelligent level shifter may be added to adjust the voltage level on the data lines (D+ and D−) used for communications in USB systems, to address the issue of missing negative common-mode range as defined by the USB specification. The level shifter may be part of a port power controller that allows adaptive shifting of the signal level in accordance with the current levels drawn on the supply line by a device, for example during charging. The port power controller may be operated in systems enabled for battery charging, and may combine overcurrent sensing (current meter for VBus) and the routing of the D+ and D− lines (used for the battery charging protocol) into a single package. By varying the voltage levels on the D+ and D− data lines according to the drawn current levels, the performance of USB Hosts ports and USB Hub ports may be greatly increased. | 2013-07-25 |
20130191567 | Wireless Bus for Intra-Chip and Inter-Chip Communication, Including Data Center/Server Embodiments - Embodiments of the present invention are directed to a wire-free data center/server. The data center/server is wire-free in the sense that communication within a data unit of the data center/server (i.e., intra-data unit), between data units of the data center/server (inter-data unit), and between the data units and the backplane of the data center/server is performed wirelessly. | 2013-07-25 |
20130191568 | OPERATING M-PHY BASED COMMUNICATIONS OVER UNIVERSAL SERIAL BUS (USB) INTERFACE, AND RELATED CABLES, CONNECTORS, SYSTEMS AND METHODS - Operating M-PHY communications protocol over a USB interface and related devices, systems, and methods are disclosed. In one embodiment, an electronic device is configured to operate using a M-PHY standard. The device comprises a communications interface having a plurality of data paths conforming to the M-PHY standard and a USB connector having a plurality of pins. The plurality of pins comprises a first receive pin electrically coupled to a M-PHY RXDN data path of the communications interface. The plurality of pins comprises a second receive pin electrically coupled to a M-PHY RXDP data path of the communications interface. The plurality of pins comprises a first transmit pin electrically coupled to a M-PHY TXDN data path of the communications interface and a second transmit pin electrically coupled to a M-PITY TXDP data path of the communications interface. Additionally, various methods of insertion detection and power delivery are disclosed. | 2013-07-25 |
20130191569 | MULTI-LANE HIGH-SPEED INTERFACES FOR HIGH SPEED SYNCHRONOUS SERIAL INTERFACE (HSI), AND RELATED SYSTEMS AND METHODS - Multi-lane high speed interfaces for a modified High Speed Synchronous Serial (HSI) system, and related systems methods are disclosed. In one embodiment, electronic device using a modified HSI protocol comprises a transmit communications interface. The transmit communications interface comprises a data path configured to carry data from the electronic device, a ready path configured to carry an HSI protocol compliant READY signal, and a flag path configured to carry an HSI protocol compliant FLAG signal indicative of repeated bit values of data carried on the data path. The transmit communications interface further comprises one or more additional data paths configured to carry additional data from the electronic device in parallel with the data carried by the data path such that the data path and the one or more additional data paths carry HSI protocol compliant data striped across the data path and the one or more additional data paths. | 2013-07-25 |
20130191570 | MULTI-MEDIA USB DATA TRANSFER OVER DIGITAL INTERACTION INTERFACE FOR VIDEO AND AUDIO (DiiVA) - A system for delivering USB data over a DiiVA network may include a USB host controller, at least one USB device, a first DiiVA device connected to the USB host controller through an upstream USB port, a second DiiVA device connected to the USB device through a downstream USB port; and a network configured to transfer data between the first DiiVA device and the second DiiVA device according to USB protocol through a DiiVA bi-directional hybrid link in the network. The network is responsive to the USB host controller to deliver contents for the USB protocol through at least one line state information packet and at least one USB data packet transmitted through the hybrid link between the upstream USB port and the downstream USB port. | 2013-07-25 |
20130191571 | METHOD AND SYSTEM FOR DYNAMICALLY PROGRAMMABLE SERIAL/PARALLEL BUS INTERFACE - An apparatus, method, and system embodying some aspects of the present embodiments for arbitrating communication between multiple communication devices are provided. The arbitration system include two communication devices and a packet traffic arbiter. The communication devices can be configured to receive or transmit data transmissions. The data transmissions can comprise protocol information. The protocol information can comprise transmission coordination information, handover information, and spectrum information. The packet traffic arbiter can be configured to coordinate the data transmissions between the two communication devices. The coordination can reduce traffic collisions or interference between low-power activities of the two communication devices. | 2013-07-25 |
20130191572 | TRANSACTION ORDERING TO AVOID BUS DEADLOCKS - Methods and apparatus for transaction ordering to avoid bus deadlocks are provided. In an exemplary method, custom routing rules for data transport are defined for data transport between a plurality of masters and a plurality of slaves via a plurality of interconnects, based on a network topology and traffic profile. In an example, the customized rule allows a request address to arbitrate in a first phase of arbitration at a first interconnect in the plurality of interconnects prior to receiving write data associated with the request address at a second interconnect in the plurality of interconnects, and does not allow the request address to arbitrate during a subsequent second phase of arbitration unless the request address beats other competing address requests. | 2013-07-25 |
20130191573 | METHODS AND SYSTEMS FOR REDUCED SIGNAL PATH COUNT FOR INTERCONNECT SIGNALS WITHIN A STORAGE SYSTEM EXPANDER - Methods and systems for reducing the signal path count between circuits within a SAS expander used for establishing SAS connections. The system comprises a SAS expander. The SAS expander comprises a plurality of link layer control circuits, each link layer control circuit adapted to communicatively couple with a SAS device. The SAS expander further comprises a connection manager communicatively coupled with the link layer control circuits for routing communications between the link layer control circuits. Each of the plurality of link layer control circuits is adapted to establish a SAS connection with another link layer control circuit through the connection manager by segmenting a plurality of interconnect signals into multiple data segments for sequential transmission to the connection manager, (e.g., without impacting the performance of the connection manager). The connection manager interprets the data segments to extract the plurality of interconnect signals to establish the SAS connection. | 2013-07-25 |
20130191574 | AUDIO PLAYER - The audio player | 2013-07-25 |
20130191575 | METHODS AND SYSTEMS FOR PROVIDING ALTERNATIVE STORAGE RESOURCES - An engaged device that is only compatible with a specific retailer's operating system may be enclosed in a case together with a resource and/or other storage device so that content of the resource that is not compatible with the specific retailer's operating system, and that may not thereby be readily accessed by the engaged device, may be indirectly accessed by the engaged device. The engaged device may be coupled to a casing, and the casing may be coupled to a resource. As a result, the engaged device may indirectly access the resource. | 2013-07-25 |
20130191576 | COMPUTER SYSTEM AND METHOD FOR CONTROLLING ADDITIONAL CHASSIS ADDED TO COMPUTER SYSTEM - Regarding an additional storage chassis used by being connected to a basic chassis equipped with a storage controller, provided is a computer system capable of changing or updating a firmware environment of the additional storage chassis so that normal operation of the additional storage chassis can be secured on the user side even if the operation different from the operation, which was guaranteed at the time of factory shipment, is executed on the user. | 2013-07-25 |
20130191577 | INCREASING VIRTUAL-MEMORY EFFICIENCIES - Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which are located in two memory pages in a virtual memory system, such that one of the pages does not permit execution of the instructions located therein, are identified and then executed under temporary permissions that permit execution of the identified instructions. In various embodiments, the temporary permissions may come from modified virtual memory page tables, temporary virtual memory page tables which allow for execution, and/or emulators which have root access. In embodiments, per-core virtual memory page tables may be provided to allow two cores of a computer processor to operate in accordance with different memory access permissions. in embodiments, a physical page permission table may be utilized to provide for maintenance and tracking of per-physical-page memory access permissions. Other embodiments may be described and claimed. | 2013-07-25 |
20130191578 | STORING CACHED DATA IN OVER-PROVISIONED MEMORY IN RESPONSE TO POWER LOSS - A power loss condition is detected that affects volatile data that is cached in preparation for storage in a non-volatile, solid-state memory device. The volatile cached data is stored in an over-provisioned portion of the non-volatile, solid-state memory device in response to the power loss condition. | 2013-07-25 |
20130191579 | APPARATUS AND METHOD FOR ENHANCING FLASH ENDURANCE BY ENCODING DATA - Input bits are stored in memory cells by mapping the input bits into a larger number of transformed bits using a shaping encoding that has a downward asymptotic bias with respect to a mapping of bit patterns to cell states and programming some of the cells according to that mapping of bit patterns to cell states. The programmed cells are erased before being programmed to store any other bits. The invention sacrifices memory capacity to increase endurance. | 2013-07-25 |
20130191580 | Controller, System, and Method for Mapping Logical Sector Addresses to Physical Addresses - A controller of a flash memory device exchanges data pages with the memory device via a host-type NAND interface and exchanges data sectors with a host via a flash-type NAND interface. The data sectors are different in size than the data pages. A data storage system includes the controller and the memory device. Another data storage system includes a memory whose physical pages have a common size and circuitry for exporting a flash-type NAND interface for exchanging data sectors, that differ in size from the physical pages, with a host. A data processing system includes the data storage system and the host. | 2013-07-25 |
20130191581 | MULTI-LAYER INPUT/OUTPUT PAD RING FOR SOLID STATE DEVICE CONTROLLER - Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory devices, a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit, and a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads includes a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal. | 2013-07-25 |
20130191582 | Cache System Using Solid State Drive - A cache system for a storage device includes (i) one or more solid state drives (SSDs), (ii) one or more random access memories (RAMs), and (iii) a cache control device. The cache control device caches at least some of first data that is to be written to the storage device, and caches at least some of second data that is retrieved from the storage device. When caching first data or second data in one of the one or more RAMs, the cache control device writes to the one RAM non-sequentially with respect to a memory space of the one RAM. When caching first data or second data in one of the one or more SSDs, the cache control device writes to the one SSD sequentially with respect to a memory space of the one SSD. | 2013-07-25 |
20130191583 | CARD AND HOST APPARATUS - A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus. | 2013-07-25 |
20130191584 | DETERMINISTIC HIGH INTEGRITY MULTI-PROCESSOR SYSTEM ON A CHIP - Systems integrated into a single electronic chip are provided for. The systems include a primary shared bus, a secondary shared bus and an embedded dynamic random access memory (eDRAM) including a first port and a second port. The systems also include a primary processor in operable communication with the eDRAM via the first port; and a secondary processor in operable communication with the eDRAM via the secondary bus and the second port, wherein the primary and secondary processors are operating in synchronization. | 2013-07-25 |
20130191585 | SIMULATING A MEMORY STANDARD - An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept. | 2013-07-25 |
20130191586 | METHOD FOR OPERATING MEMORY CONTROLLER AND SYSTEM INCLUDING THE SAME - Methods of operating a memory controller include requesting data from each of a plurality of separate memory devices in response to an in-order multi-memory read request and then reading the requested data from the plurality of separate memory devices. The data read from the plurality of separate memory devices is then transmitted to a system bus along with at least one indication signal that identifies a relationship between an ordering of the requested data according to memory device and an ordering of the transmitted data according to memory device. | 2013-07-25 |
20130191587 | MEMORY CONTROL DEVICE, CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS - A memory control device includes a first memory, a second memory, a third memory longer in a delay time since start-up until an actual data access, and a control unit. The second memory stores at least a part of data from each data string among multiple data strings with a given number of data as a unit. The third memory stores all of data within the plurality of data strings therein. If a cache miss occurs in the first memory, the control unit conducts hit determination of a cache in the second memory, and starts an access to the third memory. If the result of the hit determination is a cache hit, the control unit reads the part of data falling under the cache hit from the second memory as leading data, reads data other than the part of data, of a data string to which the part of data belongs, from the third memory, and makes a response as subsequent data to the leading data. | 2013-07-25 |
20130191588 | SYSTEMS FOR AND METHODS OF IMPROVING THE EFFICIENCY OF AUTOMATED DATA STORAGE LIBRARIES - Described are systems for and methods of improving the efficiency of an automated data storage library. | 2013-07-25 |
20130191589 | Systems, Methods, and Computer Program Products Providing Snapshot Data Replication in a Distributed Analytic Computing System - A computer program product having a computer readable medium tangibly recording computer program logic for performing analytics on data at a data node, the computer program product including code to instruct a storage array to create a snapshot of the data, code to access the snapshot, by the data node, as an independent virtual volume, code to receive, at the data node, a command mapping a processing task to the data node, in which the processing task includes analysis on the data, and code to perform the processing task on the data by accessing the data through the snapshot. | 2013-07-25 |
20130191590 | PROCESSOR AGNOSTIC DATA STORAGE IN A PCIE BASED SHARED STORAGE ENVIRONMENT - Disclosed are a system, a method and/or an apparatus of processor agnostic data storage in a PCIE based shared storage environment. In one aspect, a method includes processing a storage based request received at an adapter circuit of a controller device associated with a disk array to direct the storage based request to at least one of a processor of the disk array and a plurality of storage devices of the disk array. The method also includes routing, through an interface circuit of the controller device, the data request in the other format compatible with the storage device directly to at least one storage device of the plurality of storage devices of the disk array coupled to the controller device agnostic to a processor of the disk array to store a data associated with the data request based on a mapping table. | 2013-07-25 |
20130191591 | METHOD FOR VOLUME MANAGEMENT - A computer-readable record medium which contains a volume management program is provided. The volume management program forms a plurality of storage devices into a plurality of layers of volume, and re-arranges a location of a layer where a data block is stored according to its access degree, thereby providing a volume management method having much lower power consumption of the storage devices. | 2013-07-25 |
20130191592 | REDUNDANT ARRAY OF INDEPENDENT DISKS RAID CONTROLLER AND SYSTEM - A redundant array of independent disks (RAID) controller includes a host interface, a processing core and a storage interface. The processing core is connected to a host and a hard disk. The RAID controller includes a halt control pin connected to the processing core and a control signal line in the host. The processing core receives a first level sent through the control signal line by the host when the hard disk is in a standby state, and halt an execution of a program in the processing core according to the first level; receives a second level sent through the control signal line by the host when the host receives a service request, and resume the execution of the program according to the second level; and receive the service request sent by the host and send the received service request to the hard disk to awaken the hard disk. | 2013-07-25 |
20130191593 | STORAGE SYSTEM, STORAGE APPARATUS, AND OPTIMIZATION METHOD OF STORAGE AREAS OF STORAGE SYSTEM - This invention is intended for the purpose of providing the storage system, the storage apparatus, and the storage system by which, even if the storage areas allocated to the virtual volume are managed in management units set by the RAID group, overhead for parity calculation does not become excessive. This invention, by releasing a specific management unit not fully utilized for page allocation from allocation to the virtual volume and migrating the allocated pages belonging to this specific management unit to the other management unit, makes the storage areas of the specific management unit available for the write accesses for the other virtual volumes from the host computer. | 2013-07-25 |
20130191594 | Direct Memory Address for Solid-State Drives - A storage device is provided for direct memory access. A controller of the storage device performs a mapping of a window of memory addresses to a logical block addressing (LBA) range of the storage device. Responsive to receiving from a host a write request specifying a write address within the window of memory-addresses, the controller initializes a first memory buffer in the storage device and associates the first memory buffer with a first address range within the window of memory addresses such that the write address of the request is within the first address range. The controller writes to the first memory buffer based on the write address. Responsive to the buffer being full the controller persists contents of the first memory buffer to the storage device using logical block addressing based on the mapping. | 2013-07-25 |
20130191595 | METHOD AND APPARATUS FOR STORING DATA - Embodiments of the present invention provide a method and an apparatus for storing data, which relate to the field of data processing. In the present invention, a current device is divided into different load modes in the process of service processing, and manners of storing various data in a Cache are dynamically adjusted, so that nodes with different characteristics in the current device may control operations on the Cache, thus achieving lower power consumption and optimum performance of a large-capacity system under a heavy load. | 2013-07-25 |
20130191596 | ADJUSTMENT OF DESTAGE RATE BASED ON READ AND WRITE RESPONSE TIME REQUIREMENTS - A storage controller that includes a cache receives a command from a host, wherein a set of criteria corresponding to read and write response times for executing the command have to be satisfied. The storage controller determines ranks of a first type and ranks of a second type corresponding to a plurality of volumes coupled to the storage controller, wherein the command is to be executed with respect to the ranks of the first type. Destage rate corresponding to the ranks of the first type are adjusted to be less than a default destage rate corresponding to the ranks of the second type, wherein the set of criteria corresponding to the read and write response times for executing the command are satisfied. | 2013-07-25 |
20130191597 | CACHE DEVICE, COMMUNICATION APPARATUS, AND COMPUTER PROGRAM PRODUCT - A cache device may include a first storage unit configured to store first cache data, a second storage unit configured to store a cache file that stores copy of the first cache data as second cache data; a reading unit configured to select and read out one of the first cache data, which has been stored in the first storage unit, and the second cache data, which has been stored in the cache file stored in the second storage unit, in response to a reference request from outside, and an instructing unit configured to determine probability of expecting future referencing request based on the frequency of past referencing requests, the instructing unit being configured to instruct that either the first cache data or the second cache data is to be selected and read out based on the probability. | 2013-07-25 |
20130191598 | DEVICE, SYSTEM AND METHOD OF ACCESSING DATA STORED IN A MEMORY - Device, system and method of accessing data stored in a memory. For example, a device may include a memory to store a plurality of data items to be accessed by a processor; a cache manager to manage, a cache within the memory, the cache including a plurality of pointer entries, wherein each pointer entry includes an identifier of a respective data item and a pointer to an address of the data item; and a search module to receive from the cache manager an identifier of a requested data item, search the plurality of pointer entries for the identifier of the requested data item and, if a pointer entry is detected to include an identifier of a respective data item that matches the identifier of the requested data item then, provide the cache manager with the point from the detected entry. Other embodiments are described and claimed. | 2013-07-25 |
20130191599 | CACHE SET REPLACEMENT ORDER BASED ON TEMPORAL SET RECORDING - A technique is provided for cache management of a cache. The processing circuit determines a miss count and a hit position field during a previous execution of an instruction requesting that a data element be stored in a cache. The miss count and the hit position field are stored for a data element corresponding to an instruction that requests storage of the data element. The processing circuit places the data element in a hierarchical order based on the miss count and/or the hit position field. The hit position field includes a hierarchical position related to the data element in the cache. | 2013-07-25 |
20130191600 | COMBINED CACHE INJECT AND LOCK OPERATION - A circuit arrangement and method utilize cache injection logic to perform a cache inject and lock operation to inject a cache line in a cache memory and automatically lock the cache line in the cache memory in parallel with communication of the cache line to a main memory. The cache injection logic may additionally limit the maximum number of locked cache lines that may be stored in the cache memory, e.g., by aborting a cache inject and lock operation, injecting the cache line without locking, or unlocking and/or evicting another cache line in the cache memory. | 2013-07-25 |
20130191601 | APPARATUS, SYSTEM, AND METHOD FOR MANAGING A CACHE - An apparatus, system, and method are disclosed for managing a cache. A cache interface module provides access to a plurality of virtual storage units of a solid-state storage device over a cache interface. At least one of the virtual storage units comprises a cache unit. A cache command module exchanges cache management information for the at least one cache unit with one or more cache clients over the cache interface. A cache management module manages the at least one cache unit based on the cache management information exchanged with the one or more cache clients. | 2013-07-25 |
20130191602 | CALCULATING READ OPERATIONS AND FILTERING REDUNDANT READ REQUESTS IN A STORAGE SYSTEM - Read messages are issued by a client for data stored in a storage system of the networked client-server architecture. A client agent mediates between the client and the storage system. Each sequence of read requests generated by a single thread of execution in the client to read a specific data segment in the storage is defined as a client read session. The client agent maintains a read-ahead cache for each client read session and generates read-ahead requests to load data into the read-ahead cache. Each read request and read-ahead request sent from the client agent to the storage system includes positions and a size for reading and a sequence id value. The storage system filters and modifies incoming read request and read-ahead requests based on sequence ID values, positions and sizes of the incoming read request and read-ahead requests. | 2013-07-25 |
20130191603 | Method And Apparatus For Accessing Physical Memory From A CPU Or Processing Element In A High Performance Manner - A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic. | 2013-07-25 |
20130191604 | MEMORY ACCESS FOR DIGITAL SIGNAL PROCESSING - Memory access in a digital signal processing system is described. In one example, the digital signal processing system comprises a multi-port memory that is constructed from a memory interface connected to a number of single-port memory devices. The memory interface provides access ports that processors can use to access data stored on the single-port memory devices using a single address space. A processor can be connected to several access ports, and use these to request access to data at several different memory addresses at the same time. The digital signal processing system is configured such that the total number of single-port memory devices connected to the memory interface is a prime number greater than or equal to three. Because a prime number of memory devices are used, the likelihood of the data for the different memory addresses being on the same single-port memory device is minimised, increasing memory access speed. | 2013-07-25 |
20130191605 | MANAGING ADDRESSABLE MEMORY IN HETEROGENEOUS MULTICORE PROCESSORS - Technologies described herein generally describe technologies for managing addressable memories in a heterogeneous multicore chip. Technologies may be adapted to determine whether swapping a first data segment and a second data segment is suitable. The first data segment may be stored in a first addressable memory, and the second data segment may be stored in a second addressable memory. If the swapping is determined to be suitable, then the technologies may be adapted to swap the first data segment and the second data segment. As a result of the swap, the first data segment will be stored in the second addressable memory, and the second data segment will be stored in the first addressable memory. The technologies may also be adapted to update corresponding swap status indicators to indicate that the first data segment and the second data segment have moved. | 2013-07-25 |
20130191606 | OFFLINE INITIALIZATION FOR A REMOTE MIRROR STORAGE FACILITY - An initial remote region of a first remote storage device of a remote storage system not matching a corresponding local region of a local storage device of a remote local system is detected. A subsequent remote region on the remote storage system—matching the initial remote region is identified. Data in the initial remote region is replaced with data from the subsequent remote region. | 2013-07-25 |
20130191607 | Using the Short Stroked Portion of Hard Disk Drives for a Mirrored Copy of Solid State Drives - Mechanisms for storing data to a storage system comprising a set of one or more solid state storage devices and a set of non-solid state storage devices are provided. A request to write data to the storage system is received and the data is written to the set of one or more solid state storage devices in response to receiving the request. Moreover, a mirror copy of the data is written to the set of non-solid state storage devices in response to receiving the request. Thus, the non-solid state storage devices serve as a mirror backup copy of the data stored to the solid state storage devices. | 2013-07-25 |
20130191608 | METHOD FOR NON-VOLATILE MEMORY REALLOCATION FOR INFORMATION STORAGE - A set-top box includes a non-volatile memory for storing application code images. To enable the memory to store an application code image larger than a designated storage area associated therewith, the application code image undergoes separation into primary and secondary parts. The memory undergoes reallocation to create a separate storage area for storing the secondary part of the received information, whereas, while the primary part of the received information gets stored in the designated storage area. | 2013-07-25 |
20130191609 | INFORMATION PROCESSING DEVICE INCLUDING HOST DEVICE AND SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information. | 2013-07-25 |
20130191610 | DATA STAGING AREA - An illustrative embodiment of a computer-implemented process for managing a staging area creates the staging area for identified candidate cold objects, moves the identified candidate objects into the staging area, tracks application access to memory comprising the staging area and determines whether frequency of use information for a specific object exceeds a predetermined threshold. Responsive to a determination that the frequency of use information for the specific object exceeds a predetermined threshold, move the specific object into a regular area and determine whether a current time exceeds a predetermined threshold. Responsive to a determination that the current time exceeds a predetermined threshold, the computer-implemented process moves remaining objects from the staging area to a cold area. | 2013-07-25 |
20130191611 | SUBSTITUTE VIRTUALIZED-MEMORY PAGE TABLES - Embodiments of techniques and systems for using substitute virtualized-memory page tables are described. In embodiments, a virtual machine monitor (VMM) may determine that a virtualized memory access to be performed by an instruction executing on a guest software virtual machine is not allowed in accordance with a current virtualized-memory page table (VMPT). The VMM may select a substitute VMPT that permits the virtualized memory access, In scenarios where a data access length for the instruction is known, the substitute VMPT may include full execute, read, and write permissions for the entire guest software address space. In scenarios where a data access length for the instruction is not known, the substitute VMPT may include less than full execute, read, and write permissions for the entire guest software address space, and may be modified to allow the requested virtualized memory access. Other embodiments may be described and claimed. | 2013-07-25 |
20130191612 | INTERFERENCE-DRIVEN RESOURCE MANAGEMENT FOR GPU-BASED HETEROGENEOUS CLUSTERS - Systems and methods are disclosed that share coprocessor resources between two or more applications in a computing cluster using a job selector to receive jobs from a job queue; a node selector coupled to the job selector; an off line profiler with an interference prediction model; a coprocessor dynamic interference detection module; and a coprocessor interference response module. | 2013-07-25 |
20130191613 | PROCESSOR CONTROL APPARATUS AND METHOD THEREFOR - Whether each of a plurality of processor cores is in a suspend state or operation state is detected. The processor utilization of a processor core of interest in the operation state is acquired. The number of processes assigned to the processor core of interest is obtained. The stop control or startup control of a processor core is performed based on the suspend state or operation state, the processor utilization, and the number of processes. | 2013-07-25 |
20130191614 | PERFORMING A CYCLIC REDUNDANCY CHECKSUM OPERATION RESPONSIVE TO A USER-LEVEL INSTRUCTION - In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed. | 2013-07-25 |
20130191615 | INSTRUCTIONS AND LOGIC TO PERFORM MASK LOAD AND STORE OPERATIONS - In one embodiment, logic is provided to receive and execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction. Other embodiments are described and claimed. | 2013-07-25 |
20130191616 | INSTRUCTION CONTROL CIRCUIT, PROCESSOR, AND INSTRUCTION CONTROL METHOD - In a vector processing device, a data dependence detecting unit detects a data dependence relation between a preceding instruction and a succeeding instruction which are inputted from an instruction buffer, and an instruction issuance control unit controls issuance of an instruction based on a detection result thereof. When there is a data dependence relation between the preceding instruction and the succeeding instruction, the instruction issuance control unit generates a new instruction equivalent to processing related to a vector register including the data dependence relation with the succeeding instruction in processing executed by the preceding instruction and issues the new instruction between the preceding instruction and the succeeding instruction, and thereby a data hazard can be avoided between the preceding instruction and the succeeding instruction without making a stall occur. | 2013-07-25 |
20130191617 | COMPUTER SYSTEM, COMPUTER SYSTEM CONTROL METHOD, COMPUTER SYSTEM CONTROL PROGRAM, AND INTEGRATED CIRCUIT - A computer system includes a memory having a secure area and a plurality of processors using the memory. When an access-allowed program unit executed by one of the processors starts an access to the secure area, the program unit subject to execution by the other processors is limited to the access-allowed program unit. | 2013-07-25 |
20130191618 | Systems and Methods for Dynamic Scaling in a Data Decoding System - Various embodiments of the present invention provide systems and methods for data processing using variable scaling. | 2013-07-25 |
20130191619 | MULTIFUNCTION HEXADECIMAL INSTRUCTION FORM SYSTEM AND PROGRAM PRODUCT - A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle. | 2013-07-25 |
20130191620 | HARDWARE DEBUGGING APPARATUS AND METHOD FOR SOFTWARE PIPELINED PROGRAM - Provided is a hardware debugging apparatus and method for a software-pipelined program. The hardware debugging apparatus and method overcome a currency problem caused during hardware debugging in the software-pipelined program by guarding certain execution blocks and restarting the processing of the software-pipelined program. | 2013-07-25 |
20130191621 | SYSTEM AND METHOD FOR PROVIDING MULTIPLE PROCESSOR STATE OPERATION IN A MULTIPROCESSOR PROCESSING SYSTEM - A computing system using a persistent, unique identifier may be used to authenticate the system that ensures software and configurations of systems are properly licensed while permitting hardware components to be replaced. The persistent, unique system identifier may be coupled to serial numbers or similar hardware identifiers of components within the computing system while permitting some of the hardware components to be deleted and changed. When components that are coupled to the persistent, unique identifier are removed or disabled, a predefined time period is provided to update the coupling of the persistent, unique identifier to alternate hardware component in the system. | 2013-07-25 |
20130191622 | METHOD FOR BOOTING COMPUTER AND COMPUTER - Provided is a method for temporarily skipping a secure boot function. A computer is configured so that a secure boot function is set as enabled by default. Depression of a power button of the computer in a power-off state generates a startup signal. At the time of startup from S4/S5 state, a switch is turned ON and PP bit indicating physical presence is set at a register. Depression of a specific key on a keyboard causes DE bit to be set at a register. When PP bit and DE bit are found, UEFI firmware stored in a firmware ROM temporarily skips integrity validation of a boot program only for boot this time. | 2013-07-25 |
20130191623 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM - An information processing apparatus capable of booting in a normal boot mode or a special boot mode includes an input unit configured to input a request for booting the information processing apparatus in the special boot mode in booting the information processing apparatus, and a control unit configured to control the information processing apparatus to be booted in the normal boot mode if the input unit has not input the request, and to control the information processing apparatus to be booted in the special boot mode if the input unit has input the request, wherein, in a case where the information processing apparatus is booted with a predetermined condition satisfied, the control unit controls the information processing apparatus to be booted in the normal boot mode even if the input unit has input the request. | 2013-07-25 |
20130191624 | FIRMWARE PROTECTION AND VALIDATION - A system for firmware protection and validation includes: a memory device, including firmware; a chipset, a microprocessor; a secure logic device in electrical communication with the chipset and the memory device; and a power on reset circuit in communication with the secure logic device, wherein, when the secure logic device receives a reset signal from the power on reset circuit, the secure logic device applies a hold signal to the chipset, when the hold signal is applied to the chipset, the power on reset circuit de-asserts the reset signal, when the reset signal is de-asserted, the secure logic device validates the content of the firmware in the memory device, and further wherein, when the content of the firmware is validated by the secure logic device, the secure logic device de-asserts the hold signal applied to the chipset. | 2013-07-25 |
20130191625 | DYNAMIC PARAMETER PROFILES FOR ELECTRONIC DEVICES - A method for dynamically modifying a characteristic for an electronic device. The method includes activating by a processor a first profile having a first characteristic setting and a first state for an input/output (IO) device. Once the first profile is activated, receiving an input by a sensor and communicating the input to the processor. The method then includes activating by the processor a second profile having a second characteristic setting and a second state for the IO device. The second profile modifies a component of the IO device to include a second characteristic setting and a second state. | 2013-07-25 |
20130191626 | RECORDING DEVICE, TERMINAL DEVICE, AND CONTENT TRANSMISSION SYSTEM - A content transmission system transmits content, using a cloud computing system. A recording device records the content to a local storage or a cloud storage. When the local storage is selected as a recording destination, the recording device generates an encryption key, encrypts the content with the key, and generates management information associating the key with an address of the cloud storage. The recording device furthermore determines whether a portable recording medium is connected thereto. If connected, the recording device records the key and the management information to the portable recording medium. The terminal device first reads the key and the management information from the portable recording medium. The terminal device then accesses the cloud storage without performing user authentication, referring to the management information, and downloads the encrypted content from the cloud storage. Furthermore, the terminal device decrypts the content from the encrypted content, using the key. | 2013-07-25 |
20130191627 | Controlling and auditing SFTP file transfers - Encrypted SFTP file transfers and other encrypted file transfers may be audited and what files can be transferred may be controlled at a firewall or other gateway. Transferred files may be subjected to data loss prevention analysis and/or virus checks. | 2013-07-25 |
20130191628 | Media Path Monitoring Over a Secure Network - Techniques are provided for obtaining header information from a packet configured for real-time communications transport over a network. The header information is used to monitor network performance of one or more secure portions of the network. The packet is encrypted using a security protocol and encapsulated using a transport protocol to produce a transport packet for transmission over the network. The transport packet header information is inserted into the transport packet prior to transmission over the network. The header information is used by a downstream network device or network analyzer to determine performance metrics for the network without decrypting the encrypted packet. | 2013-07-25 |
20130191629 | SECURE GROUP-BASED DATA STORAGE IN THE CLOUD - Methods of securely storing documents electronically for access by members of a workgroup, methods of changing membership in the workgroup, and systems for providing secure data storage for a workgroup of changeable membership. Various embodiments use an encrypting vault key for a workgroup to encrypt the data files or session keys, and then encrypt the decrypting vault key, which corresponds with the encrypting vault key, using the public key of each member of the workgroup. If the workgroup membership is changed, the decrypting vault key can be re-encrypted with the public keys of each member of the workgroup without needing to download or re-upload the encrypted files associated with that workgroup. Other embodiments are disclosed. | 2013-07-25 |
20130191630 | Auditing and controlling encrypted communications - Use of one or more computer systems may be audited by performing a man-in-the-middle attack against a cryptographic protocol (e.g., SSH) at one or more interceptors, transmitting audit data to a centralized audit server. Operations performed using the encrypted connection may be controlled and restricted. | 2013-07-25 |
20130191631 | Auditing and policy control at SSH endpoints - SSH sessions and other protocol sessions (e.g., RDP) may be audited using an interceptor embedded within an SSH server or other protocol server. Operations performed over an SSH connection may be controlled, including controlling what files are transferred. | 2013-07-25 |
20130191632 | SYSTEM AND METHOD FOR SECURING PRIVATE KEYS ISSUED FROM DISTRIBUTED PRIVATE KEY GENERATOR (D-PKG) NODES - A system and method where the “dealer” of a split Master Secret becomes the Master Key Server, whose role is to initially compute the Master Secret, create and distribute shares of the Master Secret to two Distributed Private Key Generators (D-PKG), initialize and route the inter-process communication between the nodes, co-ordinate and computationally participate in the User System's IBE Private Key generation process. | 2013-07-25 |
20130191633 | SYSTEM AND METHOD FOR SUPPORTING MULTIPLE CERTIFICATE STATUS PROVIDERS ON A MOBILE COMMUNICATION DEVICE - A method and system for supporting multiple digital certificate status information providers are disclosed. An initial service request is prepared at a proxy system client module and sent to as proxy system service module operating at a proxy system. The proxy system prepares multiple service requests and sends the service requests to respective multiple digital certificate status information providers. One of the responses to the service requests received from the status information providers is selected, and a response to the initial service request is prepared and returned to the proxy system client module based on the selected response. | 2013-07-25 |
20130191634 | Resource Restriction Systems and Methods - Resource restrictions are associated with a user identifier. A resource restriction agent receives operating system calls related for resources and provides resource request data to a resource agent. The resource agent determines whether the resource is restricted based on the resource request data and resource restriction data and generates access data based on the determination. The resource restriction agent grants or denies the system call based on the access data. | 2013-07-25 |
20130191635 | WIRELESS AUTHENTICATION TERMINAL - A wireless authentication terminal that connects to a network via a wireless base station, the wireless authentication terminal comprises a communication unit that performs communication compliant with IEEE802.15.4, an authentication processing unit that transmits and receives communication messages and performs authentication processing for connecting to a network, a filter processing unit that changes the communication messages allowed to pass through between the communication unit and the authentication processing unit, an encryption level determination unit that determines a level at which the communication unit encrypts the communication message, and a control unit that controls an operation state of the filter processing unit and the encryption level determination unit based on the phase of the authentication processing in the authentication processing unit. | 2013-07-25 |
20130191636 | STORAGE DEVICE, HOST DEVICE, AND INFORMATION PROCESSING METHOD - A storage device includes a storage module, an authentication process execution module, an encryption processor and a security setting module. The storage module stores an encryption key, a flag indicating whether the encryption key can be used, a password used for authentication associated with the encryption key and the flag, and user data. The authentication process execution module uses a password to authenticate a connected host device. The encryption processor uses an encryption key stored being associated with a flag indicating permission to use the encryption key in accordance with an instruction from the host device, and encrypts user data received from the host device or decrypts the user data stored in the storage module. On encryption or decryption, the security setting module changes the setting of a flag stored being associated with the encryption key used for the encryption or the decryption. | 2013-07-25 |
20130191637 | METHOD AND APPARATUS FOR AUTHENTICATED ENCRYPTION OF AUDIO - The invention provides for a method of encoding data and a method for decoding encrypted and authenticity protected data. Furthermore, the invention provides for an encoding and a decoding equipment. For encoding the data is encrypted by using AES encryption ( | 2013-07-25 |
20130191638 | SYSTEM AND METHOD FOR SECURE TWO-FACTOR AUTHENTICATED ID-BASED KEY EXCHANGE AND REMOTE LOGIN USING AN INSECURE TOKEN AND SIMPLE SECOND-FACTOR SUCH AS A PIN NUMBER - A system and method of authenticated ID-based key exchange and remote login with insecure token and PIN number can provide an authenticated key agreement protocol based on an elliptic curve bilinear type-3 pairing. A server acts as an Authentication Service to Clients and a Trusted Authority (TA) issues identity based secret numbers to Clients and Authentication Services. Included in the system and method is the capability for the Client to split their secret number into two parts, a Client selected PIN number, and the larger number, the Token. | 2013-07-25 |
20130191639 | SYSTEM AND METHOD FOR SECURING COMMUNICATIONS BETWEEN DEVICES - A system and method for providing an improved way to secure messages being transmitted between communicating devices. Security mechanisms, operating below the session establishment level, provide fast encryption that is unconditionally secure or becomes stronger over time as devices continue to communicate. After random or arbitrary characters are used to encrypt an initial message, each new message communicated between two devices is encrypted with the most recent message communicated there-between as well as the changing key. Moreover, an exclusive dyadic relationship between the devices is obtained which prevents the cloning or piracy of the devices or the data communicated between them. The disclosed system and method also provide a multi-threading capability, thereby reducing the likelihood of a denial of service of attack. | 2013-07-25 |
20130191640 | INFORMATION SYSTEM AND METHOD INCORPORATING A PORTABLE DIGITAL MEDIA DEVICE - A method of reading a readable element, such as a two dimensional bar code or an RFID chip, that has encrypted information with a portable device, such as a digital media device or RFID reader, includes storing a decryption key in the portable device, and scanning the readable element with the portable device. The method further includes communicating with a remote server storing a decryption key database, validating the decryption key stored in the portable device, and decrypting information from the readable element using the portable device. The decrypted information may then be displayed. | 2013-07-25 |
20130191641 | CAPTCHA (COMPLETELY AUTOMATED PUBLIC TEST TO TELL COMPUTERS AND HUMANS APART) DATA GENERATION METHODS AND RELATED DATA MANAGEMENT SYSTEMS AND COMPUTER PROGRAM PRODUCTS THEREOF - CAPTCHA (Completely Automated Public Test to tell Computers and Humans Apart) data generation methods for use in an electronic device and related management systems are provided. First, the electronic device determines a first data set according to at least one first data corresponding to an operation to be performed, wherein the first data represents sensitive data corresponding to the operation. Then, the electronic device generates a group of CAPTCHA data corresponding to the first data set according to the first data. The electronic device may be a server or a client. When the electronic device is the client, the client obtains at least one generation module from the server to determine the first data set, and generate the CAPTCHA data. In some embodiments, during a data transmission procedure, the client performs the operation with the server using the CAPTCHA data. | 2013-07-25 |
20130191642 | NESTED DIGITAL SIGNATURES WITH CONSTANT FILE SIZE - A system and method are provided for implementing a digital signature scheme for embedding and validating multiple nested digital signatures in digitally produced documents without modifying a file size of the digitally produced and signed documents or otherwise corrupting previously-embedded digital signatures. A number of fixed fields are included in a digitally produced document, upfront, that will be populated with multiple digital signatures. With the fixed fields in the digitally produced documents, the entire file is cryptographically “hashed” and the individual digital signatures are independently verifiable via simple cryptographic schemes. Multiple digital signatures are embedded in documents including complex file formats in a manner that does not corrupt the documents. Known cryptographic techniques such as, for example, a known hash algorithm, are applied to the digitally produced documents including the multiple sequentially input digital signatures in a process that is independently verifiable. | 2013-07-25 |
20130191643 | ESTABLISHING A CHAIN OF TRUST WITHIN A VIRTUAL MACHINE - According to an aspect of an embodiment, a method of establishing a chain of trust into a virtual machine on a hardware system is described. The method may include measuring an immutable portion of a virtual machine image configured to instantiate as the virtual machine to generate a trust anchor measurement. The method may also include storing the trust anchor measurement in a sealed memory. | 2013-07-25 |
20130191644 | SYSTEMS AND METHODS FOR WATERMARKING SOFTWARE AND OTHER MEDIA - Systems and methods are disclosed for embedding information in software and/or other electronic content such that the information is difficult for an unauthorized party to detect, remove, insert, forge, and/or corrupt. The embedded information can be used to protect electronic content by identifying the content's source, thus enabling unauthorized copies or derivatives to be reliably traced, and thus facilitating effective legal recourse by the content owner. Systems and methods are also disclosed for protecting, detecting, removing, and decoding information embedded in electronic content, and for using the embedded information to protect software or other media from unauthorized analysis, attack, and/or modification. | 2013-07-25 |