29th week of 2011 patent applcation highlights part 56 |
Patent application number | Title | Published |
20110179238 | STORAGE CONTROLLER AND STORAGE CONTROL METHOD FOR ACCESSING STORAGE DEVICES IN SUB-BLOCK UNITS - Provided are a storage controller and storage control method capable of improving the transaction performance. This storage controller includes a disk controller for receiving a read command and a write command from a host computer, and an external disk controller and an internal disk device for sending and receiving data to and from the disk controller. A storage device of the external disk controller or the internal disk controller processes the access from the disk controller in physical sub-block units. When the disk controller is to access the storage device of the external disk controller or the internal disk device in logical sub-block units in which an additional code containing a guarantee code is added to user data, it makes such access in minimum common multiple units of logical sub-blocks and physical sub-blocks, and changes the guarantee code length. | 2011-07-21 |
20110179239 | SEMICONDUCTOR MEMORY DEVICE AND INFORMATION DATA PROCESSING APPARATUS INCLUDING THE SAME - A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a control circuit. In a first access mode, the control circuit simultaneously accesses the multiple banks in response to a single read-out command or to a single write-in command from outside. In the first access mode, the selector coordinates a plurality of data input/output pins with the multiple banks in a predetermined relationship. | 2011-07-21 |
20110179240 | ACCESS SCHEDULER - Embodiments of the present invention provide a system for scheduling memory accesses for one or more memory devices. This system includes a set of queues configured to store memory access requests, wherein each queue is associated with at least one memory bank or memory device in the one or more memory devices. The system also includes a set of hierarchical levels configured to select memory access requests from the set of queues to send to the one or more memory devices, wherein each level in the set of hierarchical levels is configured to perform a different selection operation. | 2011-07-21 |
20110179241 | STORAGE SYSTEM AND ITS INITIAL COPY METHOD - Upon starting the initial copy process, a pair creation command is issued from a primary disk subsystem to a secondary disk subsystem. The secondary disk subsystem sets a target area of a second disk drive to an unwritten status, and thereafter writes update data that was updated in a primary site into a designated area of the second disk drive. Subsequently, when data of a first disk drive is backed up to an external medium, the external memory medium is transported to a secondary site, and then connected to a host computer. Unwritten data among the backup data recorded in the external memory medium is thereafter restored to the first disk drive, and the initial copy is completed on the condition that all data in the first disk drive has been copied to the second disk drive. | 2011-07-21 |
20110179242 | Multi-Stage Multiplexing Operation Including Combined Selection and Data Alignment or Data Replication - A multi-stage multiplexing operation that includes combined selection and data alignment or data replication is disclosed. In a particular embodiment, a method includes performing a first stage of a multi-stage multiplexing operation. During the first stage, a first data source is selected from a first plurality of data sources. At least one of a first data alignment operation and a first data replication operation is also performed on first data from the selected first data source during the first stage. | 2011-07-21 |
20110179243 | Asymmetric Data Mirroring - An asymmetric data mirroring method with a local storage device and a remote storage device being separated by large distances is disclosed. A server determines a predetermined time period associated with a round trip latency between the server and a remote storage device. The server submits a request to a local storage device, a remote storage device and a memory device disposed between the server and the remote storage device. The server submits additional requests to the local and remote storage devices during the predetermined time period. The server stores a copy of each request submitted by the server to the remote storage device in a memory disposed between the server and the remote storage device while the server waits for whether an acknowledgement associated with the request has been received from the remote storage device during the predetermined time period. The server resubmits the request and the additional requests to the remote storage device if the acknowledgement is not received. If an acknowledgement is received, the server continues submission of additional new requests to the local and remote storage devices. | 2011-07-21 |
20110179244 | STORAGE APPARATUS AND DATA WRITING METHOD - A storage apparatus is disclosed which includes: a memory configured to have a plurality of pages to which data can be written in units of a page, the memory being further configured to have a plurality of pages of write data stored into each page in multi-valued form; and a control section configured to select pages to which to write the data from among the plurality of pages of the memory, the control section being further configured to write to the selected pages of the memory the data of at least two bits in multi-valued form for a plurality of pages including the selected pages; wherein, when writing the plurality of pages of the write data, the control section puts the write data into multi-valued form per page before writing the data to a plurality of different unused pages of the memory on a page-by-page basis. | 2011-07-21 |
20110179245 | INDEPENDENT LINK AND BANK SELECTION - Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller. | 2011-07-21 |
20110179246 | APPARATUS AND METHOD FOR PROCESSING DATA IN A MASSIVELY PARALLEL PROCESSOR ARRAY SYSTEM - An apparatus and method for processing data in a Massively Parallel Process Array (MPPA) system are provided, in which a scheduling processor determines an array processor and an initial memory, and requests halt release to the array processor, which requests allocation of an additional memory or return of used memory to an address conversion controller, if allocation of additional memory or return of used memory is needed during program execution. The address conversion controller controls, upon receipt of the request for allocation of additional memory, conversion of a base address of additional memory to a physical address and, upon receipt of the request for return of used memory, deletes registered information from the address conversion table. The array processor requests return of additional memory to the address conversion table and transmits a terminal signal to the scheduling controller, upon completion of the program. | 2011-07-21 |
20110179247 | STORAGE SYSTEM AND UTILIZATION MANAGEMENT METHOD FOR STORAGE SYSTEM - A storage system | 2011-07-21 |
20110179248 | ADAPTIVE BANDWIDTH ALLOCATION FOR MEMORY - A device and methods are provided for adaptive bandwidth allocation for memory of a device are disclosed and claimed. In one embodiment, a method includes receiving, by a memory interface of the device, a memory access request from a first client of the memory interface, and detecting available bandwidth associated with a second client of the memory interface based on the received memory access request. The method may further include loading a counter, by the memory interface, for fulfilling the access request, wherein the counter is loaded to include bandwidth associated with the first client and the available bandwidth associated with the second client, and granting the memory access request for the first client based on bandwidth allocated for the counter. | 2011-07-21 |
20110179249 | Data Storage Device and Method for Handling Data Read Out from Memory - The invention provides a method for handling data read out from a memory. In one embodiment, a controller corresponding to the memory comprises a ping-pong buffer. First, a first sector read time period required by the memory to read and output a data sector to the ping-pong buffer is calculated. A second sector read time period required by a host to read a data sector from the ping-pong buffer is calculated. A page switch time period required by the memory to switch a target read page is obtained. A total sector number is determined according to the first sector read time period, the second sector read time period, and the page switch time period. When the memory outputs data to the ping-pong buffer, a first buffer and a second buffer of the ping-pong buffer are switched to receive the data output by the memory according to the total sector number. | 2011-07-21 |
20110179250 | I/O CONVERSION METHOD AND APPARATUS FOR STORAGE SYSTEM - A storage system comprises a storage apparatus which includes a processor, storage disks, and a memory storing a page mapping table, a page mapping program, and a page-filename mapping program. A file system manages a file tree of files with filenames. The page mapping table specifies a relationship between data volumes in the storage apparatus and the storage disks and the file system, the data volumes each including pages, each page including segments, each segment including sectors. The file tree has for each storage apparatus a hierarchy of directories and files based on relationships among the data volumes, the pages, and the segments. The page mapping program and the page-filename mapping program are executable by the processor to specify, by page, a location of data contained in the I/O request by referring to the page mapping table and the file tree. | 2011-07-21 |
20110179251 | POWER SAVING ASYNCHRONOUS COMPUTER - A computer array ( | 2011-07-21 |
20110179252 | METHOD AND APPARATUS FOR A GENERAL-PURPOSE, MULTIPLE-CORE SYSTEM FOR IMPLEMENTING STREAM-BASED COMPUTATIONS - A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based computing device is disclosed. The computing device includes a plurality of processing cores coupled to each other. A memory stores stream-domain code including a stream defining a stream destination module and a stream source module. The stream source module places data values in the stream and the stream conveys data values from the stream source module to the stream destination module. A runtime system detects when the data values are available to the stream destination module and schedules the stream destination module for execution on one of the plurality of processing cores. | 2011-07-21 |
20110179253 | EFFICIENT MULTI-CORE PROCESSING OF EVENTS - A computer implemented method for handling events in a multi-core processing environment is provided. The method comprises handling an event by a second application running on a second core, in response to determining that the event is initiated by a first application running on a first core; and running a third application on the first core, while the first application is waiting for the event to be handled by the second application. | 2011-07-21 |
20110179254 | LIMITING SPECULATIVE INSTRUCTION FETCHING IN A PROCESSOR - The described embodiments relate to a processor that speculatively executes instructions. During operation, the processor often executes instructions in a speculative-execution mode. Upon detecting an impending pipe-clearing event while executing instructions in the speculative-execution mode, the processor stalls an instruction fetch unit to prevent the instruction fetch unit from fetching instructions. In some embodiments, the processor stalls the instruction fetch unit until a condition that originally caused the processor to operate in the speculative-execution mode is resolved. In alternative embodiments, the processor maintains the stall of the instruction fetch unit until the pipe-clearing event has been completed (i.e., has been handled in the processor). | 2011-07-21 |
20110179255 | Data processing reset operations - A processor | 2011-07-21 |
20110179256 | PROCESSING BYPASS DIRECTORY TRACKING SYSTEM AND METHOD - A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at. | 2011-07-21 |
20110179257 | IMAGE FORMING DEVICE, IMAGE FORMING METHOD AND COMPUTER READABLE MEDIUM - A data processing device including a reception unit, an instruction unit and a storage unit. The reception unit receives instructions for processing at a processing execution device. The instruction unit instructs the processing execution device to cancel a power saving state of the processing execution device and execute the processing corresponding to an instruction received by the reception unit. The storage unit stores data relating to received instructions. If the processing corresponding to the received instruction is a pre-specified process, data relating to the instruction is stored by the storage unit. If the processing corresponding to the received instruction is not a pre-specified process, the instruction unit instructs the processing execution device to execute both the processing corresponding to this instruction and processing based on data relating to instructions stored in the storage unit. | 2011-07-21 |
20110179258 | PRECISE DATA RETURN HANDLING IN SPECULATIVE PROCESSORS - The described embodiments provide a system for executing instructions in a processor. In the described embodiments, upon detecting a return of input data for a deferred instruction while executing instructions in an execute-ahead mode, the processor determines whether a replay bit is set in a corresponding entry for the returned input data in a miss buffer. If the replay bit is set, the processor transitions to a deferred-execution mode to execute deferred instructions. Otherwise, the processor continues to execute instructions in the execute-ahead mode. | 2011-07-21 |
20110179259 | METHOD FOR INTEGRATING OPERATING SYSTEM INTO BIOS CHIP AND METHOD FOR BOOTING OPERATING SYSTEM INTEGRATED INTO BIOS CHIP - A method for integrating an operating system (OS) into a basic input output system (BIOS) chip and to boot a computer using programs stored in the BIOS. A bootable image file of the OS is integrated with a virtual disk program and other BIOS instructions and stored into the BIOS chip. When the computer is powered up and upon the condition that an OS in a hard disk of a computer system is damaged, the OS in the BIOS chip is executed. | 2011-07-21 |
20110179260 | METHOD FOR INTEGRATING OPERATING SYSTEM INTO BIOS CHIP AND METHOD FOR BOOTING OPERATING SYSTEM FROM SERVER - A method for integrating an operating system (OS) into a basic input output system (BIOS) chip and to boot a computer system using an image file stored in a server. A bootable image file of the OS is integrated with a virtual disk program and other BIOS instructions and stored into the BIOS chip. When the computer system is powered up, the OS stored in the BIOS can be booted to allow the another OS stored in the server to be downloaded into the harddisk and executed. The BIOS OS can also allow an OS stored on the local drive to be executed. | 2011-07-21 |
20110179261 | METHOD FOR CONTROLLING NETWORK CONTROLLER, NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM, AND INFORMATION PROCESSING APPARATUS - A method for controlling a network controller, including: preferentially booting a network controller assignment controlling driver before at least one of a network controller controlling driver for EFI and a network controller controlling driver for legacy BIOS initializes the network controller, the network controller assignment controlling driver deciding whether to operate the network controller by either of the EFI or the legacy BIOS, based on preset setting data of the network controller; and exclusively acquiring a driver providing a protocol used for initialization of the network controller by the network controller assignment controlling driver when the setting data of the network controller is an instruction to initialize the network controller for the legacy BIOS. | 2011-07-21 |
20110179262 | APPARATUS AND METHOD FOR BOOTING IN COMPUTER DEVICE WITH BUILT-IN COMMUNICATION MODULE - An apparatus and method control booting in a mobile device with a built-in communication module to prevent a service user from using the mobile device for other purposes and to prevent the service user from subscribing to another service provider. A method includes determining, during a booting operation, whether the communication module is mounted with a USIM. A forced booting termination message is displayed if the communication module is not mounted with the USIM. And power supply is interrupted after a predetermined time from displaying the forced booting termination message. | 2011-07-21 |
20110179263 | STORAGE SYSTEM FOR A STORAGE POOL AND VIRTUAL VOLUMES - This invention provides a storage system to store data used by computers. A storage system coupled to a computer and a management apparatus, includes storage devices accessed by the computer and a control unit that controls the storage devices, in which the control unit performs the following operations: setting, in the storage devices, a first virtual device including a first logical device; setting a second virtual device which including a second logical device, which is a virtual volume accessed by the computer; allocating an address of the first logical device to the second logical device; and changing the allocation to change storage areas of the virtual volume. | 2011-07-21 |
20110179264 | Clearing Secure System Resources In A Computing Device - Systems and methods of clearing system resources are disclosed. One example method includes the step of detecting a failure to clear a secure portion of a system resource in a device. The method also includes the step of powering off the system resource for a period of power-off time that is sufficient to clear data from the system resource, where the power off is responsive to the failure detection. The method also includes the step of unlocking the secure portion of the system resource, where the unlock is responsive to the period of power-off time having elapsed. | 2011-07-21 |
20110179265 | DATA PROCESSING DEVICE - It is assumed that the image data inputted are subjected to run-length compression and compressed encoding based on Huffman encoding. The first step configuration configured on a reconfigurable circuit includes run-length compression circuits | 2011-07-21 |
20110179266 | Method for secure transmission using a fax server, system and computer program for implementing this method - The present invention relates to a method for secure transmission using a fax server, comprising the following steps: a step of transmitting the document to be faxed, by the sender to a server, in the form of a digital file in a non-fax format, as well as information relative to the identity of the recipient, a step of calculating a Tiff format file from said digital file on the one hand, the creation date and time of said file and an informative file on the other hand and modifying said Tiff file to be transmitted to insert a signature and information allowing the recipient to access the recorded files. This file is then transmitted by the server to the telephone address of the recipient of said file, according to a fax standard. The invention also relates to a computer system and program for implementing this method. | 2011-07-21 |
20110179267 | METHOD, SYSTEM AND SERVER FOR IMPLEMENTING SECURITY ACCESS CONTROL - A method for implementing network security access control is provided, including: receiving and decrypting terminal identity information that is encrypted in a bi-directional encryption mode and forwarded by a switch, and authenticating the decrypted terminal identity information; returning an authentication result to the switch so that the switch controls access of a terminal to a network according to the authentication result; encrypting the decrypted terminal identity information in a solo-directional encryption mode and authenticating the encrypted terminal identity information; returning an authentication result to a security access control gateway so that the security access control gateway controls access of the terminal to network resources according to the authentication result; delivering a security policy to a security control module on the terminal so that the security control module controls the terminal according to the security policy. A server is provided, including a first authentication module and a second authentication module. A system for implementing network security access control is provided, including a server, a switch, a security access control gateway and a terminal. | 2011-07-21 |
20110179268 | PROTECTING APPLICATIONS WITH KEY AND USAGE POLICY - One or more files of an application are obtained and configured as a virtual storage volume. An application package is generated by encrypting, using a key, the one or more files configured as a virtual storage volume. A license generation module generates a license including both a usage policy for the application and the key. A computing device, to run the application, obtains and attempts to authenticate the application package. If the application package is authenticated, then a license associated with the application package is obtained and at least part of the application package is decrypted using the key in the license. A virtual storage volume that includes the application is mounted, and the application is executed in accordance with the usage policy in the license. However, if the application is not authenticated, then the application is not executed. | 2011-07-21 |
20110179269 | SIGNATURE SYSTEMS - A signature system includes a public key certificate obtainment device | 2011-07-21 |
20110179270 | Data Retrieval System - A method is disclosed for retrieving data from a wireless device over a wireless network for submission to an application provided on a user terminal. The method includes the steps of detecting for a wireless device having a data file stored thereon when the application is running on the user terminal; and if a data file is detected, in response to an attempt by a user at the user terminal to access a document accessible through the application where data is required to complete a request for access to the document, determining whether the required data exists on the data file; retrieving the required data from the data file and submitting the retrieved data to the application for generation of an access request. | 2011-07-21 |
20110179271 | SECURE DATA PARSER METHOD AND SYSTEM - The present invention provides a method and system for securing sensitive data from unauthorized access or use. The method and system of the present invention is useful in a wide variety of settings, including commercial settings generally available to the public which may be extremely large or small with respect to the number of users. The method and system of the present invention is also useful in a more private setting, such as with a corporation or governmental agency, as well as between corporation, governmental agencies or any other entity. | 2011-07-21 |
20110179272 | Method for Forming an Electronic Group - Method for managing an electronic group comprising two or more group members ( | 2011-07-21 |
20110179273 | Application Server, Control Method Thereof, Program, and Computer-Readable Storage Medium - An application server ( | 2011-07-21 |
20110179274 | Shared secret verification method and system - Method for shared secret verification e.g. to be applied in secure data exchange, in which at least two parties, hereinafter indicated as Alice and Bob, each have a secret while their challenge is to find out whether they share the same secret or not, however, without disclosing the secret itself to each other or to any third party. The method comprises the following steps. In step 1, Alice picks a random number RA, encrypts it using Bob's public key PUB, adds the value of her secret SA, and sends the result K to Bob. In step 2 Bob receives K, subtracts his secret SB, and performs a decryption using his own private key PRB. In step 3 Bob performs the one-way function H on L and sends the result M to Alice. In step 4 Alice receives M, takes her original random number RA, performs the same one-way function H and verifies whether the result equals the received M. In step 5 Alice sends her original random number RA to Bob. In step 6 Bob receives RA and verifies whether it equals to his earlier result L and concluding that, if the answer is “no”, Alice knows that Bob has the same secret and that, if the answer is “yes” Bob knows Alice doesn't have the same secret. Instead of performing the steps 6 and 7, Alice and Bob may repeat steps 1 to 5 where it is Bob who starts the exchange. | 2011-07-21 |
20110179275 | TOOLS FOR GENERATING PKI EMAIL ACCOUNTS - The present invention provides systems and methods for allowing an Email User to create a Public Key Infrastructure (PKI) Email Account and thereafter to digitally sign, send, verify and receive PKI encrypted emails over a computer network, such as the Internet. The systems and methods preferably include a Web-based Email System and a Certificate Authority that coordinate their actions to make the process of creating, maintaining and using the PKI Account as easy as possible for the Email User. In a preferred embodiment, a Keystore System may also be used to enhance the management and use of digital keypairs. | 2011-07-21 |
20110179276 | COMMUNICATION APPARATUS - A communication apparatus performs data communication with a communication device, and includes an authentication processing portion configured to perform authentication processing, including a round trip time (RTT) test on authentication requests received from one or more unauthenticated communication devices and a data communication portion configured to perform data communications with the communication device authenticated by the authentication processing portion. If, in authentication processing of a current authentication request, a prior RTT test is being performed corresponding to a prior authentication request originating from the same communication device, the current RTT test is not performed, and authentication processing waits for the completion of the prior RTT test. If the result of the prior RTT test is successful, authentication processing uses the result of the prior RTT test as the result corresponding to the current authentication request. | 2011-07-21 |
20110179277 | Key Distribution to a Set of Routers - Before actually communicating information/data between two endpoints (C, S) connected to a network a secure and confidential distribution of a special key (K h) is performed to nodes (R j) along a path in the network. This is allowed by performing a path handshaking procedure in which first a hint token is forwarded along the path in a first direction and then a disclosure token is forwarded in the opposite direction. In forwarding the disclosure token it is verified in the nodes against the already received hint token. This assures that only nodes on the particular path will receive the special key or possibly some other information related thereto. | 2011-07-21 |
20110179278 | APPARATUS AND METHOD OF A PORTABLE TERMINAL AUTHENTICATING ANOTHER PORTABLE TERMINAL - Provided is an apparatus and method of a portable terminal authenticating another portable terminal. The portable terminal may receive a seed generated by the other portable terminal, issue an authentication certificate generated using the seed to the other portable terminal, authenticate the other portable terminal based on the authentication certificate, and provide a secure communication. | 2011-07-21 |
20110179279 | DEVICE AND METHOD FOR A BACKUP OF RIGHTS OBJECTS - A common backup format of a backup rights object according to embodiments of the present invention has the following features: License information that is not critical for cryptographic security of the rights object is kept in “plain text” with a well defined syntax in a first data container, license information that is critical for cryptographic security of the rights object is stored in cryptographically protected form that is specific for the originating device to which the rights object is bound to in a second data container, and the rights object is cryptographically signed by the originating device such that it may not be manipulated. The signature is stored in a third data container. | 2011-07-21 |
20110179280 | Software development and distribution workflow employing meta-object time stamping - A method and system facilitating the development and distribution of software is provided. The system includes a database provided on a computing device, the computing device configured to enable users to provide an update to an element of the database, wherein the element is associated with an object. The system further includes time stamp tracking software configured to enable revisions to elements of the database by establishing time stamps for each stored element changed at a specified time and an assembler configured to enable a user to assemble elements for execution based on time stamping. | 2011-07-21 |
20110179281 | HASH FUNCTION USING A QUASI-GROUP OPERATION - In the computer data security field, a cryptographic hash function process is embodied in a computer system or computer software or logic circuitry and is keyless, but highly secure. The process is based on (mathematical) quasi-group operations such as in the known “EDON-R” hash function. But here one or more blank rounds (iterations) of the quasi-group operation are concatenated to the EDON-R hash function operations, to overcome perceived security weaknesses in EDON-R. | 2011-07-21 |
20110179282 | INTEGRITY PROTECTED SMART CARD TRANSACTION - Systems, methods, and technologies for configuring a conventional smart card and a client machine, and for performing a smart card authorization using the configured smart card and client. Further, the combination of methods provides for mutual authentication—authentication of the client to the user, and authentication of the user to the client. The authentication methods include presenting a specified token to the user sufficient to authenticate the client to the user and thus protect the user-provided PIN. Security is strengthened by using an integrity key based on approved client system configurations. Security is further strengthened by calculating a PIN′ value based on a user-specified PIN and a modifier and using the PIN′ value for unlocking the smart card. | 2011-07-21 |
20110179283 | INTEGRITY PROTECTED SMART CARD TRANSACTION - Systems, methods, and technologies for configuring a conventional smart card and a client machine, and for performing a smart card authorization using the configured smart card and client. Further, the combination of methods provides for mutual authentication—authentication of the client to the user, and authentication of the user to the client. The authentication methods include presenting a specified token to the user sufficient to authenticate the client to the user and thus protect the user-provided PIN. Security is strengthened by using an integrity key based on approved client system configurations. Security is further strengthened by calculating a PIN′ value based on a user-specified PIN and a modifier and using the PIN′ value for unlocking the smart card. | 2011-07-21 |
20110179284 | Information processing apparatus and information managing method - An information processing apparatus includes a chip implemented therein to independently perform a predetermined process. The chip includes a storage unit that stores user unique information in which biometric information of a user and unique information for use when a unique process corresponding to the user is performed are associated with each other, and an information processing unit that retrieves, when biometric information of the user is obtained, unique information corresponding to the obtained biometric information from the user unique information and performs a predetermined process by using the retrieved unique information. | 2011-07-21 |
20110179285 | Computer system, client device and method - A computer system includes a network. The system includes a first client device in communication with the network having a transaction description for a transaction t. The first client device sends the transaction description to a second client device. The second client device receives the transaction description from the first client device. One of the first or second client devices executes the transaction description and creates a second transaction description for transaction t and then sends the second transaction description to a client device. A client device of a computer system having a network and a second client device. A method of a computer system. A method of a client device of a computer system having a network and a second client device. | 2011-07-21 |
20110179286 | COMPUTER IMPLEMENTED METHOD FOR PERFORMING CLOUD COMPUTING ON DATA BEING STORED PSEUDONYMOUSLY IN A DATABASE - The invention relates to a computer implemented method for performing cloud computing on data of a first user employing cloud components, the cloud components comprising a first database and a data processing component, wherein an asymmetric cryptographic key pair is associated with the first user, said asymmetric cryptographic key pair comprising a public key and a private key, the data being stored pseudonymously non-encrypted in the first database with the data being assigned to an identifier, wherein the identifier comprises the public key, the method comprising retrieving the data from the first database by the data processing component, wherein retrieving the data from the first database comprises receiving the identifier and retrieving the data assigned to the identifier from the first database, wherein the method further comprises processing the retrieved data by the data processing component and providing a result of the analysis. | 2011-07-21 |
20110179287 | SECURE DATA PARSER METHOD AND SYSTEM - The present invention provides a method and system for securing sensitive data from unauthorized access or use. The method and system of the present invention is useful in a wide variety of settings, including commercial settings generally available to the public which may be extremely large or small with respect to the number of users. The method and system of the present invention is also useful in a more private setting, such as with a corporation or governmental agency, as well as between corporation, governmental agencies or any other entity. | 2011-07-21 |
20110179288 | Technique for Content Management using Group Rights - A technique for content management using group rights is described. The technique facilitates a flexible management for a group of content files mainly by effecting a change of group memberships for subsets of the group and a partial update of the content files. As one aspect, a content file manager ( | 2011-07-21 |
20110179289 | METHOD AND DEVICE FOR ELECTRONICALLY CAPTURING A HANDWRITTEN SIGNATURE USING EMBEDDING TECHNIQUE - A method and apparatus for encrypting an electronic document involves a computer having a first monitor and a signature capture apparatus configured to capture a handwritten signature on a second monitor. A hash sum of the electronic document generated in the computer is transmitted to the signature capture apparatus. The electronic document and the first hash sum thereof are displayed on the first monitor. The first hash sum is also displayed on the second monitor. After electronically capturing the handwritten signature, the signature data are encrypted using the first hash sum. A digital signature image is generated in the signature capture apparatus and the first hash sum is embedded therein. The embedded first hash sum is then extracted in the computer. If the extracted hash sum is identical to the first hash sum generated in the computer apparatus, the encrypted signature data and the signed document are stored. | 2011-07-21 |
20110179290 | AUTHENTICATING A CHIP CARD INTERFACE DEVICE - A system is configured for authenticating a chip card interface device (CCID) during a transaction with the CCID. The system has a communication device configured for communicating with the CCID over a network and a processing device coupled with the communication device. The processing device is configured for receiving a transaction initiation communication from the CCID and instructing the communication device to communicate a request for authentication information including a random number to the CCID. The CCID encrypts the random number with a unique chip key (UCK) previously created with a master chip key (MCK). Then, the CCID communicates the encrypted random number to the system along with a serial number. The system recalculates the UCK using the serial number, encrypts a copy of the random number using the recalculated UCK and compares the encrypted copy with the encrypted random number received from the CCID to authenticate the CCID. | 2011-07-21 |
20110179291 | POWER ADAPTOR DETECTION SYSTEM - A power adaptor detection system includes a power adaptor device configured to receive electrical power at a first voltage and to convert the electrical power to a second voltage. The second voltage has a lower value than the first voltage. An identification generating circuit is coupled to the power adaptor device. The identification generating circuit is configured to convert a portion of the electrical power to a substantially constant value electrical current. An identification detection circuit is configured to detect the second voltage. Detecting the second voltage causes the identification circuit to determine the value of a pulse of the electrical current, wherein the value of the electrical current is an identification attribute of the power adaptor device. | 2011-07-21 |
20110179292 | SOFT START WITH ACTIVE RESET - A power supply input circuit includes an input node configured to removeably couple to an electrical source. A solid state switch is coupled between the input node and a capacitive load. An RC soft start circuit is coupled to the input node and the switch. The soft start circuit has a capacitor that causes the switch to increasingly pass electrical power from the source to the load as the capacitor charges from the source. An active reset circuit is coupled to the soft start circuit. The reset circuit is configured to detect when the source is removed from the input node and in response to the source being removed from the input node, the reset circuit discharges the capacitor to reset the soft start circuit. | 2011-07-21 |
20110179293 | APPARATUS AND METHOD FOR SYSTEM RESET USING ETHERNET FRAME IN WIRELESS COMMUNICATION SYSTEM - A Base Station (BS) includes an apparatus capable of performing a system reset using an Ethernet frame. The BS includes an Ethernet switch, a Programmable Logic Device (PLD), and a power unit. The Ethernet switch sorts an Ethernet frame capable of including a power reset command. The PLD attempts to detect a reset pattern at the Ethernet frame capable of including the power reset command, and determines the generation or non-generation of the power reset command depending on the detection or non-detection of the reset pattern. The power unit resets a power of a BS if the generation of the power reset command is notified from the PLD. | 2011-07-21 |
20110179294 | MULTIFUNCTIONAL DEVICE AND CONTROL METHOD - In a multifunctional device, a packet analysis unit determines whether a received packet contributes to inhibition of a power saving mode, stores the time at which a packet is received and information indicating whether a packet is received during the power saving mode as information about the packet determined as contributing to the inhibition thereof, and calculates a period of access by a plurality of packets based on the stored information about the packet and a factor analysis unit classifies the access of which the calculated period is shorter than the waiting time of the power saving mode into an access inhibiting a shift to the power saving mode and classifies the access of which the period is not shorter than the waiting time of the power saving mode and which is made by the packet received during the power saving mode, into an access returning from the power saving mode. | 2011-07-21 |
20110179295 | METHOD, APPARATUS AND SYSTEM TO DYNAMICALLY CHOOSE AN OPTIMUM POWER STATE - Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described. | 2011-07-21 |
20110179296 | SYSTEMS, METHODS AND DEVICES FOR LIMITING CURRENT CONSUMPTION UPON POWER-UP - Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each memory device of the multi-chip package includes a power level detector used to compare an internal voltage signal to a threshold. A current limiter controls the ramping rate of the internal voltage signal in response to the power level detector as the internal voltage signal ramps up towards the threshold. | 2011-07-21 |
20110179297 | EXTERNAL DEVICE POWER CONTROL DURING LOW POWER SLEEP MODE WITHOUT CENTRAL PROCESSING UNIT INTERVENTION - An integrated circuit device controls power up of an external device used for sensing a process variable independently of whether the integrated circuit device is in a low power sleep mode. Once the external device becomes operational the integrated device, even when still in the low power sleep mode, samples the process variable status of the external device. Low power timing circuits operational during the low power sleep mode control the power up of the external device and sampling of the process variable status thereof. After the sample of the process variable status is taken, the integrated circuit device may be brought out of the low power sleep mode to an operational mode when appropriate as determined from the sampled process variable status. | 2011-07-21 |
20110179298 | METHOD FOR CONTROLLING VOLTAGES SUPPLIED TO A PROCESSOR - A power supply unit for supplying power to a processor is disclosed. The power supply unit includes a smoothing capacitor, a controller, and an arithmetic circuit. The controller controls an output voltage according to each power state of a processor operating in a transition state where a power state of the processor transitions between an active state and a predetermined sleeping state at a predetermined transition frequency. The arithmetic circuit determines a transition stop condition based on power consumption of the processor and charging loss generated at the smoothing capacitor during the transition of the active state, and outputs a transition stop signal to stop transition to the predetermined sleeping state. | 2011-07-21 |
20110179299 | Power Management In A System Having A Processor And A Voltage Converter That Provide A Power Voltage To The Processor - A system has a processor and a voltage converter to provide a power voltage to the processor. The processor is able to transition among different power modes, Wherein the voltage converter receives indications to specify different voltage levels of the power voltage for at least two of the power modes. A controller detects a transition of the processor to a tower one of the power modes, and in response to detecting transition of the processor to the lower one of the power modes, disables at least one portion of the voltage converter. | 2011-07-21 |
20110179300 | ELECTRONIC DEVICE THAT IS ABLE TO BE CONNECTED TO AN EXTERNAL DEVICE AND OPTICAL DISK REPRODUCING APPARATUS - An electronic device (e.g. an optical disk reproducing apparatus) can be connected to an external apparatus (e.g. a display apparatus) and has a standby state as a power state. The electronic device includes a movable member (e.g. a disk tray) which is provided to be ejectable from and retractable into a body of the electronic device and be movable between an ejected position and a refracted position; a driver which drives the movable member, a detector which detects whether the movable member is at the retracted position, a communication unit which receives various control signals from the external apparatus, a power controller which controls the power state of the electronic device, a controller which controls the driver to locate the movable member to the retracted position when the power state of the electronic device is changed to the standby state by the power controller. The power controller controls whether to change the power state to the standby state according to a result of the detection by the detector, when the communication unit receives a predetermined control signal. | 2011-07-21 |
20110179301 | AUTOMATIC DISCOVERY OF SERVER TO POWER-CIRCUIT CONNECTIONS - In a data center which includes a plurality of servers, a discovery computer, a power measurement system (PMS), and a plurality of power-circuits which supply power to the servers, the discovery computer performs the following actions for each server. It transmits a first command to the server causing the server to start generating a power consumption signature if the server is able to do so. Upon receiving a SUCCESS response from the server, it instructs the PMS to start measuring the power consumption from each power-circuit. After a prescribed interval of time has elapsed, it collects the measurements from the PMS and analyzes the measurements to look for the presence of the signature. Upon detecting the signature in the measurement taken from a particular power-circuit, the discovery computer concludes that the server is connected to the particular power-circuit and creates a mapping there-between. | 2011-07-21 |
20110179302 | METHODS AND APPARATUS PROVIDING ADVANCED CLASSIFICATION FOR POWER OVER ETHERNET - A system conducts a plurality of cycles on the powered device. Each cycle has a detection phase and a classification phase. A classification voltage is applied to the conductors during each cycle. The system measures a current in the conductors while the classification voltage is applied. The system determines a final class responsive to a plurality of measured currents. The final class utilized to determine an amount of inline power to deliver to the powered device. | 2011-07-21 |
20110179303 | PERSISTENT APPLICATION ACTIVATION AND TIMER NOTIFICATIONS - The present invention extends to methods, systems, and computer program products for persistent application activation and timer notifications. A durable instance manager, instance execution hosts, and an instance store interoperate to transition instances between executing and persisted states. System properties are associated with an instance. System properties can define re-activation conditions, that when satisfied, indicate that an instance is to be re-activated for execution. System properties can define timers as well as indications that instances are in a persisted but ready to run state. | 2011-07-21 |
20110179304 | SYSTEMS AND METHODS FOR MULTI-TENANCY IN CONTACT HANDLING SYSTEMS - One example embodiment includes a method for providing multi-tenancy in a computing environment. The method includes receiving a script in a computing environment, where the script includes one or more actions to be completed by the computing environment. The method further includes providing one or more computing resources in the computing environment and building an action list for the one or more computing resources, where the action list is a data structure that contains a list of one or more actions to be executed by the one or more computing resources. The method further includes transmitting a first action to one of the one or more computing resources, where the first action is one of the one or more actions. The method further includes executing the first action in the one of the one or more computing resources and indicating to the action list the completion of the first action. | 2011-07-21 |
20110179305 | PROCESS FOR SECURE BACKSPACING TO A FIRST DATA CENTER AFTER FAILOVER THROUGH A SECOND DATA CENTER AND A NETWORK ARCHITECTURE WORKING ACCORDINGLY | 2011-07-21 |
20110179306 | Data Read Method for Flash Memory - The invention provides a data read method. In one embodiment, a flash memory comprises a plurality of pages, and predetermined information is written into each of the pages of the flash memory. First, a target address of the flash memory is read according to a source read voltage to obtain source data and a source error correction code. When error bits of the source data cannot be corrected according to the source error correction code, the predetermined information corresponding to the source data is read from the flash memory according to the source read voltage to obtain correction information. The source data and the source error correction code are then amended according to the difference between the predetermined information and the correction information to obtain an amended data and an amended error correction code. Error bits of the amended data are then corrected according to the amended error correction code. | 2011-07-21 |
20110179307 | FAILOVER METHOD AND SYSTEM FOR A COMPUTER SYSTEM HAVING CLUSTERING CONFIGURATION - A failover control method for a virtual computer system including a plurality of virtual computers including: monitoring a second virtual computer via a first line by a first virtual computer among the plurality of virtual computers; detecting a malfunction of the second virtual computer by the first virtual computer; receiving from the other virtual computers a notification including a monitoring result for the second virtual computer in the other virtual computers among the plurality of virtual computers by the first virtual computer; relating the monitoring result to the detected malfunction of the second virtual computer to correspond to each other; judging whether or not the correspondence between the monitoring result and the detected malfunction of the second virtual computer satisfies a predetermined condition; and giving the second computer a reset instruction via a second line, when the predetermined condition is satisfied. | 2011-07-21 |
20110179308 | Auxiliary circuit structure in a split-lock dual processor system - A multiple-processor system | 2011-07-21 |
20110179309 | Debugging a multiprocessor system that switches between a locked mode and a split mode - A data processing system | 2011-07-21 |
20110179310 | STORAGE SYSTEM DETECTING PHYSICAL STORAGE DEVICE SUFFERING FAILURE, AND METHOD OF PERFORMING PROCESSING FOR ADDITIONAL STORAGE DEVICE PROVISION - In a storage system, a first loop and a second loop are connected to a controller, and at least one of the first loop and the second loop is connected to existing storage devices (which are physical storage devices other than additional storage devices, which are physical storage devices which are additionally provided). In processing for additional provision, after having disconnected all of the existing storage devices from the first loop, the controller connects an additional storage device to the first loop. And the controller acquires, via said first loop, an address acquired by this additional storage device, and makes a first suitability decision as to whether or not this address is appropriate. And, if the result of this first suitability decision is negative, then the controller blocks up this additional storage device whose address has been acquired. | 2011-07-21 |
20110179311 | INJECTING ERROR AND/OR MIGRATING MEMORY IN A COMPUTING SYSTEM - In some embodiments a request is received to perform an error injection or a memory migration, a mode is entered that blocks requests from agents other than a current processor core or thread, the error is injected or the memory is migrated, and the mode that blocks requests from the agents other than the current processor core or thread is exited. Other embodiments are described and claimed. | 2011-07-21 |
20110179312 | System and Method for Recovery From Uncorrectable Bus Errors in a Teamed NIC Configuration - A method for recovery from uncorrectable errors in an information handling system including an operating system (OS) and one or more network interface cards (NICs) is provided. The method may include detecting an uncorrectable error; determining whether the uncorrectable error is isolated to a particular NIC; determining whether the particular NIC is teamed with one or more other NICs; and notifying the OS of a successful recovery from the uncorrectable error if it is determined that (a) the uncorrectable error is isolated to a particular NIC, and (b) the particular NIC is teamed with one or more other NICs. | 2011-07-21 |
20110179313 | System and Method for Correlating Empirical Data with User Experience - A method includes receiving at a computing system empirical data related to one or more information technology entities. The method further includes receiving at the computing system one or more user experience indicators, the user experience indicators indicative of a user's experience using a computer application. The method further includes correlating by the computing system the empirical data with the one or more user experience indicators to determine a quality of service delivered to a user for a plurality of time periods. The method further includes determining by the computing system, based on the correlation, whether one or more issues with one of the one or more information technology entities are related to the quality of service delivered to the user. | 2011-07-21 |
20110179314 | METHOD AND SYSTEM OF ERROR LOGGING - Method and system of error logging. At least some of the illustrative embodiments are methods including detecting assertion of an error pin by a processor system, (comprising at least a main processor and a chipset, the assertion of the error pin an indication to reboot the processor system) the detecting by a reset circuit, notifying a management processor (distinct from the main processor) that the error pin is asserted (the notifying by the reset circuit), writing to a plurality of registers in the chipset (the writing by the management processor), de-asserting a reset pin of the main processor, and then executing by the main processor an error-handling code to generate an error log. | 2011-07-21 |
20110179315 | SERDES LINK ERROR MANAGEMENT - Techniques for dynamically measuring and monitoring error rate in Serializer/Deserializer (SerDes) links In one set of embodiments, a method includes polling a SerDes link status of a SerDes link at a predetermined rate. The method also includes storing a predetermined polling results in a memory, determining a number of polling results indicating one or more errors occurred in said SerDes link, determining an action to be taken if said number of polling results exceed a threshold. | 2011-07-21 |
20110179316 | DATA PROCESSING SYSTEM COMPRISING A MONITOR - A data processing system | 2011-07-21 |
20110179317 | VOLUME AND FAILURE MANAGEMENT METHOD ON A NETWORK HAVING A STORAGE DEVICE - A SAN manager acquires configuration information from devices constituting a SAN and produces a corresponding relationship between a host computer and a virtual volume (virtual volume mapping) and a corresponding relationship between the host computer and a real volume (real volume mapping). Based on those pieces of mapping information, the SAN manager outputs a corresponding relationship between virtual and real volumes. Meanwhile, the failure notification messages received from the in-SAN devices are construed to detect and output an influence of the failure upon the access to a real or virtual volume. Furthermore, when receiving a plurality of failure notifications from the devices connected to the SAN, the plurality of failure notifications are outputted with an association based on the corresponding relationship between real and virtual volumes. | 2011-07-21 |
20110179318 | APPARATUS, A METHOD AND A PROGRAM THEREOF - An apparatus and method for efficiently processing memory faults. A faulty memory is exchanged with a spare memory when the total number of faults in the memories is over a threshold. After the switching, when the number of faults in a single cache line is over a threshold, a memory page corresponding to the single cache line is blocked. | 2011-07-21 |
20110179319 | FIELD PROGRAMMABLE REDUNDANT MEMORY FOR ELECTRONIC DEVICES - An electronic device is provided including an input/output (I/O) interface, a plurality of memory elements, a controller coupled to the I/O interface and the plurality of memory elements. In the device, the controller configured for operating the plurality of memory elements during a normal operating mode of the electronic device, where responsive to receiving a command for replacing a selected memory sector in the electronic device during the normal operating mode, the controller is configured for identifying one or more available spare memory sectors in the electronic device and modifying at least one memory map in the electronic device to replace the selected memory sector with the one of the available spare memory sectors. | 2011-07-21 |
20110179320 | METHOD FOR RECEIVING DATA STREAMS AND CORRESPONDING METHOD FOR TRANSMISSION - The present invention relates to the domain of reception and transmission of data streams, for example audio and video. More specifically, the invention relates to the optional use of an error correction stream associated with a data stream. | 2011-07-21 |
20110179321 | INFORMATION STORAGE DEVICE AND TEST METHOD THEREFOR - A method of testing the operational margin of an information storage device having marked random variations, and an information storage device having the function of self-diagnosing the operational margin, are provided. The test method includes testing an information storage device including a plurality of memory bits as the test condition is set so as to be outside a range of conditions that may be presupposed in real use of the information storage device and of counting the number of memory bits that fail in operation. The test method also includes verifying the size of the operational margin of the information storage device based on the count value. The test condition is made severe and the reference value is set to a fairly large value to enable the operational margin against the noise to be tested highly accurately. | 2011-07-21 |
20110179322 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAM VERIFICATION CIRCUIT - A program verification circuit comprises a failed state counting unit and a failed bit counting unit. The failed state counting unit counts failed program states among a plurality of program states, and generates a first program mode signal indicating whether counting of failed bits is required. The failed bit counting unit selectively counts failed bits in response to the first program mode signal, and generates a second program mode signal indicating whether a program operation is completed. | 2011-07-21 |
20110179323 | Memory with Self-Test Function and Method for Testing the Same - The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources. | 2011-07-21 |
20110179324 | TESTING APPARATUS AND METHOD FOR ANALYZING A MEMORY MODULE OPERATING WITHIN AN APPLICATION SYSTEM - A testing apparatus for analyzing a memory module under test operating within an application system, wherein the memory module under test is coupled to a processor of the application system, is disclosed herein. In at least one embodiment, the testing apparatus comprises a first interface for coupling to the application system, a second interface for coupling to a reference memory module, a controller coupled to the first and second interfaces, at least one comparator, and a data logging unit. The data logging unit is configured to receive logging data from the controller and at least one test result from the at least one comparator, and to record, in a memory, at least a subset of the logging data, such that more specific details of memory errors revealed during behavioral testing of memory modules may be identified, examined, and stored for subsequent analysis. | 2011-07-21 |
20110179325 | SYSTEM FOR BOUNDARY SCAN REGISTER CHAIN COMPRESSION - A system for testing input/output pads of an integrated circuit includes boundary scan register chains, a test control unit and a test data processing unit. Input test data is provided to the test control unit, which then provides the test data to the test data processing unit. The test data processing unit processes the test data to obtain processed test data. Thereafter, the processed data is loaded in each of the boundary scan register chains in parallel. The processed test data is propagated sequentially through the plurality of boundary scan register chains to obtain output test data. The output test data is used to detect faults present in the input/output pads of the integrated circuit. | 2011-07-21 |
20110179326 | The Performance Of Signature-Based Diagnosis For Logic BIST - Techniques are disclosed for reducing the set of initial candidates in signature based diagnosis methodology. These techniques are based on a unique way of making optimum use of information from logic back-cone tracing along with equations that describe the test response compactor. | 2011-07-21 |
20110179327 | COMPUTER-IMPLEMENTED METHOD FOR CORRECTING TRANSMISSION ERRORS USING LINEAR PROGRAMMING - A computer-implemented method for correcting transmission errors. According to the method, a transmitted vector corrupted by error can be recovered solving a linear program. The method has applications in the transmission of Internet media, Internet telephony, and speech transmission. In addition, error correction is embedded as a key building block in numerous algorithms, and data-structures, where corruption is possible; corruption of digital data stored on a hard-drive, CD, DVD or similar media is a good example. In short, progress in error correction has potential to impact several storage and communication systems. | 2011-07-21 |
20110179328 | System and Method for Ingesting Media Content in a Peer-to-Peer Network - The invention relates to a method and system hardware for ingesting media content in a peer-to-peer network from a data stream. The data stream is made up of a sequence of packets of media data, and each packet is identified by a sequence identifier. The method includes commencing caching of the data packets from the data stream. A missing data packet is identified using the sequence identifiers of the packets and the size of the missing data packet is determined. A portion of the memory medium is skipped to provide a skipped portion of medium having no data cached therein. The skipped portion has a size corresponding to the determined size of the missing data packet. The missing data packet is then retrieved and inserted into the skipped portion of the memory medium. The system includes an ingestion element configured to receive the content in a data stream, to define blocks of media data that make up the content, to generate metadata associated with each block, the metadata identifying the construction of the block from the data stream, and to transmit the data stream as a multicast stream to other network nodes. The other network nodes include at least one cache element configured to construct at least one of the blocks from the multicast data stream in accordance with the metadata, and to cache the data block. The system also includes a database accessible to network nodes, the database recording a location of each of the cached data blocks in the network. | 2011-07-21 |
20110179329 | APPARATUS AND METHOD FOR SETTING HYBRID AUTOMATIC REPEAT REQUEST AND AUTOMATIC REPEAT REQUEST PARAMETER IN MOBILE COMMUNICATION SYSTEM - An apparatus is capable of setting HARQ and ARQ parameters in a mobile communication system. The apparatus sets HARQ and ARQ parameters in a mobile communication system. The apparatus sets a default HARQ parameter based on the determined default HARQ parameter setting condition determined by using a plurality of QCIs. The apparatus sets a default ARQ parameter based on the determined default ARQ parameter setting condition determined by using the plurality of QCIs, and updates the set default HARQ parameter and the set default ARQ parameter according to a channel status of a UE. | 2011-07-21 |
20110179330 | WIRELESS COMMUNICATION TERMINAL AND COMMUNICATION CONTROL METHOD - A wireless communication terminal having a plurality of antennas with a variable relative distance includes a decoder for iterative decoding of reception signals including an error-correcting code received by the plurality of antennas) and a control unit for controlling an iteration count of decoding by the decoder in accordance with a distance between the antennas detected by an antenna distance detection unit for detecting the distance between the plurality of antennas. | 2011-07-21 |
20110179331 | METHOD FOR MAPPING PHYSICAL HYBRID AUTOMATIC REPEAT REQUEST INDICATOR CHANNEL - A method for mapping a physical hybrid automatic repeat request indicator channel (PHICH) is described. The method for mapping a PHICH includes determining an index of a resource element group transmitting a repetitive pattern of the PHICH, according to a ratio of the number of available resource element groups in a symbol in which the PHICH is transmitted and the number of available resource element groups in a first or second OFDM symbol, and mapping the PHICH to the symbol according to the determined index. In transmitting the PHICH, since efficient mapping is performed considering available resource elements varying with OFDM symbols, repetition of the PHICH does not generate interference between neighbor cell IDs and performance is improved. | 2011-07-21 |
20110179332 | Method For Automatic Repeat Request Operation, Transceiver Arrangement, And Computer Program - A method for automatic repeat request operation of a plurality of simultaneous automatic repeat request processes is disclosed. The method comprises receiving a transmission comprising at least one transport block; storing soft bits of the transport block in a buffer; and transmitting an automatic repeat request process signal, wherein the transmitting of the automatic repeat request process signal comprises one of: transmitting an acknowledgment signal if the transport block is determined to be properly received, transmitting a negative acknowledgement signal if the transport block is determined to contain an error, and transmitting a blocking indication signal if there is not room enough for the soft bits in the buffer. A transceiver arrangement and a computer program are also disclosed. | 2011-07-21 |
20110179333 | LOWER-COMPLEXITY LAYERED BELIEF PROPAGATION DECODING LDPC CODES - Low density parity check (LDPC) decoders are described utilizing a sequential schedule called Zigzag LBP (Z-LBP), for a layered belief propagation (LBP) architecture. Z-LBP has a lower computational complexity per iteration than variable-node-centric LBP (V-LBP), while being simpler than flooding and check-node-centric LBP (C-LBP). For QC-LDPC codes where the sub-matrices can have at most one “1” per column and one “1” per row, Z-LBP can perform partially-parallel decoding with the same performance as C-LBP. The decoder comprises a control circuit and memory coupled to a parity check matrix. Message passage is performed within Z-LBP in a first direction on odd iterations, and in a second direction on even iterations. As a result, a smaller parity check matrix can be utilized, while convergence can be more readily attained. The inventive method and apparatus can also be implemented for partially-parallel architectures. | 2011-07-21 |
20110179334 | DIGITAL TELEVISION TRANSMITTER/RECEIVER AND METHOD OF PROCESSING DATA IN DIGITAL TELEVISION TRANSMITTER/RECEIVER - A digital television (DTV) transmitter and a method of processing data in the DTV transmitter are disclosed. A pre-processor pre-processes the enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded enhanced data. A data formatter generates enhanced data packets including the pre-processed enhanced data and for inserting known data to at least one of the enhanced data packets. A first multiplexer multiplexes the enhanced data packets with main data packets including the main data. An RS encoder RS-codes the multiplexed main and enhanced data packets, the RS encoder adding systematic parity data to each main data packet and adding RS parity place holders to each enhanced data packet. And, a data interleaver interleaves the RS-coded main and enhanced data packets, wherein a known data sequence is included in every Nth enhanced data segment outputted from the data interleaver. | 2011-07-21 |
20110179335 | METHOD AND APPARATUS FOR CONFIGURING PROTOCOL HEADER IN WIRELESS COMMUNICATION SYSTEM - Provided are a method of configuring a protocol header in a wireless communication system, and a communication apparatus and method using the protocol header configuration method. The protocol header configuration method may include: configuring a variable length physical layer (PHY) header and a fixed length PHY header; encoding the fixed length PHY header according to a first coding scheme; generating a Header Check Sequence (HCS) to check an error regarding a combination of the fixed length PHY header, the variable length PHY header, and a Media Access Control (MAC) header; scrambling the MAC header and an HCS to generate a scrambled MAC header and HCS; and encoding the variable length PHY header and the scrambled MAC header and HCS according to a second coding scheme. | 2011-07-21 |
20110179336 | MODE SELECTION FOR DATA TRANSMISSION IN WIRELESS COMMUNICATION CHANNELS BASED ON STATISTICAL PARAMETERS - A method and communication system for selecting a mode for encoding data for transmission in a wireless communication channel between a transmit unit and a receive unit. The data is initially transmitted in an initial mode and the selection of the subsequent mode is based on a selection of first-order and second-order statistical parameters of short-term and long-term quality parameters. Suitable short-term quality parameters include signal-to-interference and noise ratio (SINR), signal-to-noise ratio (SNR), power level and suitable long-term quality parameters include error rates such as bit error rate (BER) and packet error rate (PER). The method of the invention can be employed in Multiple Input Multiple Output (MIMO), Multiple Input Single Output (MISO), Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) communication systems to make subsequent mode selection faster and more efficient. Furthermore the method can be used in communication systems employing various transmission protocols including OFDMA, FDMA, CDMA, TDMA. | 2011-07-21 |
20110179337 | MEMORY UTILIZATION METHOD FOR LOW DENSITY PARITY CHECK CODE, LOW DENSITY PARITY CHECK CODE DECODING METHOD AND DECODING APPARATUS THEREOF - A memory utilization method of low density parity check code (LDPC), a LDPC decoding method and a decoding apparatus thereof are provided, applicable for a decoding process in a wireless receiver. The memory utilization method of LDPC includes the following steps. First, variable node processes (VNPs) or check node processes (CNPs) required to be executed at a same time stage are determined. Next, the VNPs or the CNPs executed at the same time stage are allocated in different VNP groups or different CNP groups. Further, a folding factor of memory units is determined according to a desired data throughput. Then, according to the folding factor and the allocated VNP groups or the allocated CNP groups, the memory units are connected serially as a plurality of parallel processing memory modules. | 2011-07-21 |