29th week of 2011 patent applcation highlights part 27 |
Patent application number | Title | Published |
20110176335 | RESONANT CONVERTERS AND BURST MODE CONTROL METHOD THEREOF - A burst mode control method for a resonant converter is provided, in which at least one first regulation pulse is provided to pre-adjust a magnetizing inductor current and a resonant capacitor voltage in a resonant circuit during a burst mode working period. After the first regulation pulse is completed, at least one pulse group including a plurality of driving pulses is provided to intermittently turn on switching elements of a square wave generator. The first regulation pulse adjusts the magnetizing inductor current and the resonant capacitor voltage, such that the magnitude of the magnetizing inductor current is essentially the same and the magnitude of the resonant capacitor voltage is essentially the same at each rising edge of each driving pulse of the pulse group. | 2011-07-21 |
20110176336 | Isolated current regulated DC-DC converter - The isolated current regulated DC-DC converter is composed of the step down switch SA, free wheel diode DA, step down inductor L, switches S | 2011-07-21 |
20110176337 | Single-Cycle Charge Regulator for Digital Control - A single-cycle charge regulator (SCCR) may be used in operating a power converter at a constant frequency without requiring compensation. The SCCR may include a first control loop to generate an error value based on the output voltage of the power converter and a reference voltage, and to generate a first control value based on the error value to control steady-state behavior of the output of the power converter. A second control loop may generate a second control value based on the error value, to regulate response of the power converter to a transient deviation on the output voltage. A third control loop may operate to adjust a current (affected by the output voltage of the power converter) subsequent to the transient deviation, according to a third control value derived from previous values of the first control value, the second control value, and the third control value, to keep the adjusted current commensurate with the current that was present prior to the transient deviation, while keeping the output voltage of the power converter at its desired steady-state value. | 2011-07-21 |
20110176338 | Electrical power adaptor with self-adjusting output voltage regulation - The present invention relates to an electrical power adaptor with self-adjusting output voltage regulation which comprises a switching power supply circuit for converting an alternate current into a direct current, and a power supply return circuit connecting with the switching power supply circuit. The switching power supply circuit comprises an EMI filter circuit, a full-bridge rectifier circuit, a switching transformer, a secondary rectification filter circuit, a PWM control circuit and an optocoupler feedback control circuit. The power supply return circuit comprises an output line, output adaptor and an MCU main control circuit. The MCU main control circuit is connected with the switching power supply circuit. The output adaptor is disposed with a signal resistor. The MCU main control circuit controls the output voltage of the switching power supply circuit according to the signal resistor of the output adaptor. The electrical adaptor of the present invention provides a wider range of output voltages with higher precision. Furthermore, by connecting a signal resistor to an output adaptor and altering feedback resistance of a feedback network according to feedback signals of the signal resistor, the signal resistor is not required to meet a very high standard of precision. The design of the present invention is safer and more personalized. | 2011-07-21 |
20110176339 | Signal Transmission Arrangement - A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement. | 2011-07-21 |
20110176340 | POWER CONVERTER, CONTROL METHOD THEREOF, AND DIRECT MATRIX CONVERTER - A voltage control rate of an inverter has a DC component and an AC component. This AC component has a frequency which is six times a fundamental frequency of an AC voltage outputted by the inverter. Even when there are not only a fifth-order harmonic component but also a seventh-order harmonic component of a load current, a ratio between the magnitude of the AC component and the DC component can be appropriately set. | 2011-07-21 |
20110176341 | START-UP CIRCUIT TO DISCHARGE EMI FILTER OF POWER SUPPLIES - A start-up circuit to discharge EMI filter is developed for power saving. It includes a detection circuit detecting a power source for generating a sample signal. A sample circuit is coupled to the detection circuit for generating a reset signal in response to the sample signal. The reset signal is utilized for discharging a stored voltage of the EMI filter. | 2011-07-21 |
20110176342 | Converter Device and Method for Converting Electrical Power - A converter device (for power conversion in e.g. a power plant such as a wind turbine is disclosed. An individual controller is provided for each phase of an electrical output power of the converter. If a voltage of one phase is indicated as being out of a predetermined voltage band, an active current of this phase is set to zero and optionally a reactive component of this phase is set to a value that depends on the indicated voltage. | 2011-07-21 |
20110176343 | POWER CONVERTING APPARATUS - A power converter stabilizes a voltage by controlling leading of an AC current and performs maximum charging within contracted power reception amount when connected to a weak power system. The power converter comprises Magnetic Energy Recovery Switch comprising a bridge circuit including at least two reverse conductive type semiconductor switches and a magnetic energy accumulating capacitor with a small capacity connected between DC terminals of the bridge circuit. The power converter uses the Magnetic Energy Recovery Switch to perform power conversion from AC to DC or vise versa. Plurality of secondary battery charging devices each comprising the power converter have a DC part connected to a common DC bus bar, so that power is accommodated among the secondary battery charging devices. | 2011-07-21 |
20110176344 | Power Supply with an Interface for AC and DC signals - A power supply includes an AC-to-DC circuit, a DC-to-DC circuit, an interface used by both of the AC-to-DC circuit and the DC-to-DC circuit, and a control circuit for controlling the interface. The interface includes an ACL/DC+ input terminal, an ACN/DC− input terminal and a ground. The control circuit includes an AC/DC detecting circuit for determining whether an input voltage is AC or DC, an AC/DC converting circuit for selectively conducting AC or DC, and a conversion-controlling circuit for controlling the direction of the input voltage based on the determination in the AC/DC detecting circuit. | 2011-07-21 |
20110176345 | ELECTRONIC APPARATUS - An electronic apparatus is provided. A PCB has first and second signal paths therein. First and second fingers are disposed on the first and second signal paths, respectively. A controller is coupled to a first memory via the first finger and a second memory via the second finger, and accesses the first and second memories through the first and second signal paths, respectively. The first and second signal paths share a common segment between the controller and a branch point. First and second components are disposed between the first finger and the branch point and between the second finger and the branch point, respectively. The distances between the first component and the branch point and between the second component and the branch point are smaller than or equal to the distance between the first component and the first finger and between the second component and the second finger, respectively. | 2011-07-21 |
20110176346 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, semiconductor memory device including: a circuit substrate in which a circuit pattern is formed; a plurality of semiconductor memories mounted via a solder on both surfaces of the circuit substrate; a connector disposed at one end part of the circuit substrate for connection with a host device; and a resin mold part that seals the both surfaces of the circuit substrate. The resin mold part does not seal a region in which the connector is disposed and collectively seals regions in which the plurality of semiconductor memories are disposed. | 2011-07-21 |
20110176347 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING SEMICONDUCTOR MEMORY - According to one embodiment, a memory cell array includes memory cells arranged at crossing points of bit lines and word lines. The bit lines include first, second, third, and fourth bit lines sequentially arranged. A first sense circuit is arranged on a first end side of the memory cell array, electrically connected to the first and third bit lines. A second sense circuit is arranged on a second end side of the memory cell array, electrically connected to the second and fourth bit lines. A first hookup region is arranged between the memory cell array and the first sense circuit and includes a first transfer transistor connected to the first bit line and the first sense circuit. A second hookup region is arranged between the first hookup region and the first sense circuit and includes a second transfer transistor connected to the third bit line and the first sense circuit. | 2011-07-21 |
20110176348 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device in which stored data can be retained even when power is not supplied, and there is no limitation on the number of write cycles. The semiconductor device includes a source line, a bit line, a first signal line, a second signal line, a word line, a memory cell connected between the source line and the bit line, a first driver circuit electrically connected to the bit line, a second driver circuit electrically connected to the first signal line, a third driver circuit electrically connected to the second signal line, and a fourth driver circuit electrically connected to the word line and the source line. The first transistor is formed using a semiconductor material other than an oxide semiconductor. The second transistor is formed using an oxide semiconductor material. | 2011-07-21 |
20110176349 | Low-cost high-density rectifier matrix memory - A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers. | 2011-07-21 |
20110176350 | RESISTANCE-BASED MEMORY WITH REDUCED VOLTAGE INPUT/OUTPUT DEVICE - A resistance-based memory with a reduced voltage I/O device is disclosed. In a particular embodiment, a circuit includes a data path including a first resistive memory cell and a first load transistor. A reference path includes a second resistive memory cell and a second load transistor. The first load transistor and the second load transistor are input and output (I/O) transistors adapted to operate at a load supply voltage similar to a core supply voltage of a core transistor within the circuit. | 2011-07-21 |
20110176351 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a memory layer and a control unit. The memory layer includes a first conductive layer, a second conductive layer and a resistance change layer. The resistance change layer is provided between the first and second conductive layers and transits between a high resistance state and a low resistance state by at least one of an applied electric field and an applied current. The control unit is electrically connected to the first and second conductive layers and configured to apply a first signal with a first polarity between the first and second conductive layers prior to applying a second signal with a second polarity different from the first polarity between the first and second conductive layers to cause the resistance change layer to transit from the high resistance state to the low resistance state. | 2011-07-21 |
20110176352 | NONVOLATILE MEMORY CELL OPERATING BY INCREASING ORDER IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL - A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate. | 2011-07-21 |
20110176353 | Memristive Device Having a Porous Dopant Diffusion Element - A memristive device ( | 2011-07-21 |
20110176354 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of times of writing operations. A semiconductor device includes a source-bit line, a first signal line, a second signal line, a word line, and a memory cell connected between the source-bit lines. The memory cell includes a first transistor, a second transistor, and a capacitor. The second transistor is formed including an oxide semiconductor material. A gate electrode of the first transistor, one of a source and drain electrodes, and one of electrodes of the capacitor are electrically connected to one another. The source-bit line and a source electrode of the first transistor are electrically connected to each other. Another source-bit line adjacent to the above source-bit line and a drain electrode of the first transistor are electrically connected to each other. | 2011-07-21 |
20110176355 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node. | 2011-07-21 |
20110176356 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - A semiconductor device comprises a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell. Thereby, the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced. | 2011-07-21 |
20110176357 | SIGNAL PROCESSING CIRCUIT AND METHOD FOR DRIVING THE SAME - It is an object to provide a memory device for which a complex manufacturing process is not necessary and whose power consumption can be suppressed and a signal processing circuit including the memory device. In a memory element including a phase-inversion element by which the phase of an input signal is inverted and the signal is output such as an inverter or a clocked inverter, a capacitor which holds data and a switching element which controls storing and releasing of electric charge in the capacitor are provided. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. The memory element is applied to a memory device such as a register or a cache memory included in a signal processing circuit. | 2011-07-21 |
20110176358 | Reading Phase Change Memories - A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element. | 2011-07-21 |
20110176359 | CARBON NANOTUBE-BASED NEURAL NETWORKS AND METHODS OF MAKING AND USING SAME - Physical neural networks based nanotechnology include dendrite circuits that comprise non-volatile nanotube switches. A first terminal of the non-volatile nanotube switches is able to receive an electrical signal and a second terminal of the non-volatile nanotube switches is coupled to a common node that sums any electrical signals at the first terminals of the nanotube switches. The neural networks further includes transfer circuits to propagate the electrical signal, synapse circuits, and axon circuits. | 2011-07-21 |
20110176360 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) UTILIZING MAGNETIC FLIP-FLOP STRUCTURES - Non-volatile magnetic random access memory (MRAM) devices that include magnetic flip-flop structures that include a magnetization controlling structure; a first tunnel barrier structure; and a magnetization controllable structure that includes a first polarizing layer; and a first stabilizing layer, wherein the first tunnel barrier structure is between the magnetization controllable structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the first tunnel barrier structure, wherein the magnetic flip-flop device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization so that the device reaches one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current; a second tunnel barrier structure and a reference layer, wherein the second tunnel barrier structure is between the magnetic flip-flop device and the reference layer. MRAM cells that include such devices and arrays including such cells are also disclosed. | 2011-07-21 |
20110176361 | METHOD AND APPARATUS FOR INCREASING MEMORY PROGRAMMING EFFICIENCY THROUGH DYNAMIC SWITCHING OF BIT LINES - A method of efficiently programming charge-trapping memory cells includes sense amplifiers being dynamically connected to cells to be programmed, by switching bit lines. The method increases a number of cells that can be programmed simultaneously, such that an optimal use of sense amplifier resources is obtained. | 2011-07-21 |
20110176362 | SEMICONDUCTOR STORAGE DEVICE CAPABLE OF REDUCING ERASURE TIME - According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The distribution state of the threshold voltages of the memory cells is monitored by the read operation, the distribution state of the threshold voltages of the memory cells after the soft erasure is monitored, and an erase voltage is set based on the monitored results. Thus, the erase voltage can be precisely set without depending on the threshold voltage distribution of the memory cell before the erasure. | 2011-07-21 |
20110176363 | JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES - A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. | 2011-07-21 |
20110176364 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a semiconductor substrate which includes a well. A memory cell array includes memory cells each including a floating gate electrode above the well and a control gate electrode above the floating gate electrode, and is configured to write data in units of pages each including memory cells connected in series and to erase data in units of blocks each includes a plurality of the pages. A control gate line is selectively electrically connected to the control gate electrodes of at least one of the blocks. A first switching element includes a current path having ends connected to the control gate line and a ground end. The well is charged, and the first switching element is turned off before the end of the discharge of the well. | 2011-07-21 |
20110176365 | TWO TERMINAL PROGRAMMABLE HOT CHANNEL ELECTRON NON-VOLATILE MEMORY - A programmable two terminal non-volatile device uses a floating gate that can be programmed by a hot electron injection induced by a potential between a source and drain. The floating gate layer can also function as a FET gate for other circuits in an integrated circuit containing an array of the devices. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 2011-07-21 |
20110176366 | SEMICONDUCTOR STORAGE DEVICE AND READING METHOD THEREOF - An embodiment of the invention provides a semiconductor storage device including a NAND string, a SEN node, and a capacitor. The NAND string includes plural series-connected memory cells, and one end of the NAND string is connected to a bit line while the other end is connected to a common source line. The SEN node is configured to be able to be electrically connected to a voltage source and the bit line. In the capacitor, one end is connected to the SEN node while the other end is connected to a CLK node to which a voltage within a predetermined range is applied. A discharge rate of the SEN node is enhanced by decreasing a capacitance during discharge of the SEN node only when a selected memory cell selected from the plural memory cells is an on-cell. | 2011-07-21 |
20110176367 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines; bit lines; and a control circuit configured to write multi-value data in the memory cells. The control circuit sets either even-ordinal-number bit lines or odd-ordinal-number bit lines as selected bit lines while setting the other as unselected bit lines; applies a write inhibiting voltage to the unselected bit lines; applies a write voltage to the selected bit lines corresponding to unwritten memory cells to be given one of threshold voltage distributions representing different written states; and applies the write inhibiting voltage to the selected bit lines corresponding to unwritten memory cells to be given any other of the threshold voltage distributions representing the different written states, memory cells already written, and memory cells to be maintained in a threshold voltage distribution representing an erased state, thereby executing a write operation. | 2011-07-21 |
20110176368 | MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE - A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state. | 2011-07-21 |
20110176369 | ERASE VERIFICATION METHOD OF FLASH MEMORY APPARATUS - A suitable erase verification (ERSV) method of a flash memory apparatus is provided, which is different from the conventional ERSV method. That is, by managing the ERSV operation on the flash memory after at least once of erase operation, a flash memory controller in the flash memory apparatus selectively assigns at least one of de-selected sectors instead of all of the de-selected sectors to perform the ERSV. Therefore, by managing the ERSV operation on the flash memory, the time for the ERSV operation thereon is reduced. | 2011-07-21 |
20110176370 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory comprises a memory cell array in which a plurality of memory cell transistors capable of storing data according to a threshold voltage; a row decoder having a plurality of transfer MOS transistors connected at first ends to a plurality of word lines which are respectively connected to control gate electrodes of the plurality of memory cell transistors; and a word line driver which selects supplied voltages and supplies the selected voltages to second ends of the plurality of transfer MOS transistors. The nonvolatile semiconductor memory further comprises a voltage generation circuit which supplies voltages to the word line driver; and a control circuit which controls operation of the row decoder, the word line driver and the voltage generation circuit. | 2011-07-21 |
20110176371 | MEMORY MODULE INCLUDING MEMORY BUFFER AND MEMORY SYSTEM HAVING THE SAME - A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal. | 2011-07-21 |
20110176372 | MEMORY INTERFACE - The memory interface includes: a first data latch unit that delays a strobe signal from a memory device, through a first variable delay unit and reads the strobe signal as a first data signal; and a second data latch unit that delays the same strobe signal through the second variable delay unit and reads the strobe signal as a second data signal. The memory interface uses the data read by the first data latch unit in a normal memory access operation, detects a boundary of the delay amount by comparing the data with the data read by the second data latch unit, and reflects the boundary on the delay amount of the first variable delay unit. Thereby, the delay amount can be corrected without suspending the normal memory access operation. | 2011-07-21 |
20110176373 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a memory cell array composed of electrically rewritable memory cells; an internal voltage generating circuit having a boosting circuit for generating a voltage boosted from a supply voltage, and a voltage detecting circuit for detecting an output voltage of the boosting circuit as a monitor voltage and controlling on/off of the boosting circuit for holding the output voltage of the boosting circuit at a specified level, the internal voltage generating circuit outputting the output voltage of the boosting circuit as an internal voltage; a control circuit for controlling the internal voltage generating circuit; and a writing circuit for applying the internal voltage to the memory cell as a writing voltage when writing data into the memory cell, wherein the control circuit controls the internal voltage to a first voltage necessary for writing data into the memory cell when writing data into the memory cell, and to a second voltage lower than the first voltage in a write verify operation following the data write operation. | 2011-07-21 |
20110176374 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal. A phase detector determines a phase difference between the selected internal data strobe input signal and the selected phase shifted data strobe output signal and outputs a phase difference value. | 2011-07-21 |
20110176375 | SEMICONDUCTOR MEMORY DEVICE FOR REDUCING RIPPLE NOISE OF BACK-BIAS VOLTAGE AND METHOD OF DRIVING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line. | 2011-07-21 |
20110176376 | LOW POWER SYNCHRONOUS MEMORY COMMAND ADDRESS SCHEME - A synchronous memory array includes: a command receiver, for receiving a command signal; an address receiver, for receiving an address signal corresponding to the command signal where the address signal is delayed with respect to the command signal and the address receiver is initially in an off state; and a decoder, coupled to the command receiver and the address receiver, for decoding the command signal to selectively generate a receiver enable signal for turning on the address receiver. | 2011-07-21 |
20110176377 | SEMICONDUCTOR MEMORY DEVICE - A driver circuit having a redundant control function to store address data of a defective memory cell is provided to compensate a defect of a memory cell array. In other words, address data of a defective memory cell is stored not by using part of the memory cell array, but by using a non-volatile memory, which is provided in a memory controller, to store address data of a defective memory cell. The memory controller storing the address data of a defective memory cell contributes an increase in process speed, because it is not necessary to access the memory cell array in order to obtain the address data of the defective memory cell. | 2011-07-21 |
20110176378 | Memory Program Discharge Circuit - A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation. | 2011-07-21 |
20110176379 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF - A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line. | 2011-07-21 |
20110176380 | PAIRED PROGRAMMABLE FUSES - A plurality of fuses are arranged in pairs and configured such that each pair of fuses represents a data bit when one fuse of the pair is blown; represents an un-programmed bit when no fuse of the pair is blown; and represents a zero-ized bit when both fuses of the pair are blown. A fuse programming system programs the fuses of the pairs such that each pair represents a bit, comprising blowing a first fuse of a pair to represent a “1” bit, blowing a second fuse of a pair to represent a “0” bit, and blowing both fuses of a pair to represent a zero-ized pair, whereby if neither fuse of a pair is blown represents a null, un-programmed bit. | 2011-07-21 |
20110176381 | MEMORY HAVING A DISABLING CIRCUIT AND METHOD FOR DISABLING THE MEMORY - A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the data input/output end to the output end according to the signal of the output enable end. When the fuse is blown, the disabling circuit generates a tri-state to the output end. Therefore, external circuits cannot perform actions of reading or writing to access the memory matrix. | 2011-07-21 |
20110176382 | Systems and Methods for Mixing Fluids - A syringe-to-syringe mixing apparatus comprises first and second syringes adapted to be coupled at their respective outlets to fluidly connect the syringes. The first syringe includes a plunger having a hollow plunger barrel and a distal end defining a lumen therethrough. The lumen is initially closed by a septum, which in one embodiment is an elastomeric stopper mounted over the end of the plunger. The mixing apparatus further includes a third syringe slidably disposed within the plunger barrel. The third syringe includes a hollow needle adapted to pierce the septum to allow fluid from the third syringe to be injected into fluid within the coupled first and second syringes. | 2011-07-21 |
20110176383 | METHOD AND APPARATUS FOR ACCURATE PLACEMENT OF OCEAN BOTTOM SEISMIC INSTRUMENTATION - Embodiments described herein relate to an apparatus and method for deployment and retrieval of one or more seismic devices in a deep water marine environment. In one embodiment, a method for deploying and positioning ocean bottom equipment is described. The method includes attaching at least one article having a negative buoyancy to a support cable, lowering the at least one article into the water column from two or more points of suspension on a surface of the water column, at least one of the two or more points of suspension being movable relative to the other point of suspension, and manipulating tension of the support cable, length of the support cable, position of the support cable, and distance between the two or more points of suspension to cause the at least one article to fall to a bottom of the water column at a predetermined location on the bottom. | 2011-07-21 |
20110176384 | Method and Device for Processing Seismic Data - Apparatus, computer instructions and method for processing seismic data related to a subsurface of a body of water. The method includes inputting data indicative of recordings made by detectors provided on a curved profile in response to an acoustic wave reflected from the subsurface; applying a matched mirror migration procedure to the data, where (i) actual positions of the detectors on the curved profile and corresponding recordings, and (ii) fictitious mirror positions of the actual detectors on the curved profile and corresponding recordings with a changed sign are added in the matched mirror migration; and generating a final image of the subsurface based on the matched mirror migration procedure. | 2011-07-21 |
20110176385 | DUAL-SENSOR NOISE-REDUCTION SYSTEM FOR AN UNDERWATER CABLE - A system and a method for rejecting noise in an underwater sensor cable, such as a towed streamer or an ocean-bottom cable. An adaptive hydrodynamic model of the cable produces an estimated sensor signal from a raw sensor signal from a particle-motion sensor, such as an accelerometer. The estimated sensor signal represents an estimate of the response of the underwater cable to cable motion absent seismic events. A noise-reduced response to particle motion alone is produced by subtracting the estimated sensor signal from the raw sensor signal to reject cable motion and other noise effects in the raw sensor signal. A seismic event detector uses a hydrophone signal from an acceleration-canceling hydrophone to disable the adapting of the hydrodynamic model during seismic events. The hydrophone signal is combined with the response to particle motion by PZ summation to produce a deghosted seismic response signal. | 2011-07-21 |
20110176386 | WAVE EQUATION ILLUMINATION - A method for generating an illumination map. The method includes receiving an earth model that represents one or more properties of the earth. The method then includes receiving a target area in the earth model and propagating one or more wavefields from the target area to a potential seismic data acquisition region in the earth model. After propagating the wavefields, the method includes decomposing the propagated wavefields into one or more subsets of the propagated wavefields and creating the illumination map based on the subsets of the propagated wavefields. The illumination map may indicate one or more contributions of one or more synthetic source and receiver pairs for illuminating the target area in the earth model. The method may then include creating a seismic survey design based on the contributions. | 2011-07-21 |
20110176387 | BI-DIRECTIONAL WIRELESS ACOUSTIC TELEMETRY METHODS AND SYSTEMS FOR COMMUNICATING DATA ALONG A PIPE - A bi-directional acoustic telemetry system is presented for communicating data and/or control signals between a first modem and a second modem along tubing. The system includes a communication channel defined by the tubing, a transducer of the first modem, and a transducer of the second modem. The transducer of each modem are configured to transmit and receive data and/or control signals, and are further configured to electrically communicate with a power amplifier characterized by an output impedance Zs and a signal conditioning amplifier characterized by an input impedance Zr. The system also includes a reciprocal response along the communication channel between the output impedance Zs and the input impedance Zr. | 2011-07-21 |
20110176388 | SWITCHING POWER SUPPLY - The patent application describes a switching power supply, wherein the supply has a first output voltage, wherein the first output voltage was generated by a first working voltage with a first frequency and a first phase, wherein the supply is adapted to configure the first frequency and/or the first phase in such a way that disturbances m devices powered by the supply are reduced, wherein the disturbances are caused of electromagnetic interferences. In an embodiment the switching power supply is adapted to configure the first frequency in such a way that the first frequency and its harmonies are different from the operating frequency of the powered device. | 2011-07-21 |
20110176389 | DEVICE FOR MEASURING DISTANCE AND METHOD FOR OPERATING SAID TYPE OF DEVICE - A hand-held device ( | 2011-07-21 |
20110176390 | LOW PIN COUNT HIGH VOLTAGE ULTRASOUND TRANSMITTER AND METHOD THEREFOR - An integrated single channel or multi-channel ultrasound transmitter that minimizes the number of input connections to a controller such as an FPGA, field programmable gate array, or a custom integrated circuit in an ultrasound system. The method is accomplished by integrating, in low voltage logic, a means to store and or program the patterns required for the transmitter output. The number of logic input connections can be further reduced by further integrating, in low voltage logic, programmable individual time delays and frequency divider for each transmitter output. | 2011-07-21 |
20110176391 | LOW FREQUENCY ACOUSTIC DETERRENT SYSTEM AND METHOD - The disclosed embodiments provide an acoustic deterrent system and a method for repelling sea mammals from a region of water. The system consists of one or more acoustic impulse sources spatially distributed underwater around the perimeter of the fish farm or other region to be protected. Each source is capable of generating an acoustic signal and a controller determines the firing time for each source to produce signals, which may include precisely timed wave trains of superimposed tones on a broadband low frequency signal, which are believed most effective in deterring seals, sea lions and other carnivorous mammals. The system may further include a sensing device to determine the presence of marine mammals so that the acoustic deterrent can be initiated on demand. | 2011-07-21 |
20110176392 | SIGNAL TRANSMITTER DEVICE COMPRISING AN ELECTRICAL ACOUSTIC SIGNAL TRANSMITTER - A signal transmitter device comprises an electrical acoustic signal transmitter signal, which has a piezoceramic disk on a metal membrane, on a printed circuit board. The printed circuit board has an opening in the region of the piezoceramic disk or the metal membrane, wherein the metal membrane extends over the opening for the purpose of bearing on the printed circuit board in an edge region of the opening. The piezoceramic disk arranged on the metal membrane is arranged towards the opening and substantially in the region of the opening, wherein a contact projection as part of the printed circuit board for electrical contact-connection to the signal transmitter is provided at the edge region of the opening. Separate parts can thus be obviated. | 2011-07-21 |
20110176393 | BATTERY-LESS ENVIRONMENTAL FRIENDLY QUARTZ TIMEPIECES - This present invention discloses a quartz timepiece which can be operated without battery, which comprises an environmental-friendly electricity supply component and a quartz clock movement connected to each other, and a super capacitor serially connected to the environmental-friendly electricity supply component. The present environmental-friendly quartz timepiece operates with the super capacitor and other natural power supply unit (such as light absorbing plate and hydro-power supply device) to supply power to the timing component of the timepiece. The charge and discharge cycles of the super capacitor can reach up to a million times and are sufficient to maintain the operational life of the timepiece, and so users do not need to replace the standard battery. As a result, the timepiece is relatively simple and reasonable in structure, energy saving and environmental-friendly. The environmental-friendly quartz timepiece further provides an electricity monitoring unit in the power supply circuit. According to the light intensity of the LED indicator, users can determine the remaining electricity of the super capacitor by visual observation. It is easy to use, effective in avoiding power supply interruption and thus is safer and more reliable to operate. The light absorbing plate and the hydro-power supply device are disposed in parallel with each other and so provide enough electricity to support the alarm function and the LED back light function. It can light up the timepiece surface and the users can see the time clearly when in need. | 2011-07-21 |
20110176394 | TIMEPIECE CROWN INCLUDING AN UNCOUPLING MECHANISM - Winding crown for a timepiece, said crown ( | 2011-07-21 |
20110176395 | MODULAR MOVEMENT THAT IS FULLY FUNCTIONAL STANDALONE AND INTERCHANGEABLE IN OTHER PORTABLE DEVICES - A method for manufacturing an interchangeable movement includes assembling parts into a movement subassembly, such that the subassembly is a complete working mechanism; enclosing the subassembly in a body; integrating a glass with the body, wherein the body comprises a single shell with only an opening that receives the glass, sealing the glass and the single shell to enclose the body, thereby creating a water resistant modular movement; and wherein the modular movement is insertable into a case of a portable device having a receptacle for removably receiving the modular movement without tools and in a manner where the glass of the modular movement is visible through the case when the modular movement is inserted. | 2011-07-21 |
20110176396 | TIMEPIECE COVER GLASS AND TIMEPIECE - A timepiece cover glass used in a timepiece with a solar battery is provided. The timepiece cover glass covers the solar battery. The timepiece cover glass includes an antireflective layer is formed on at least both sides of the timepiece cover glass. A formula (1) is satisfied. f(x, y, z)≦40 (1), where (f(x, y, z) expresses the absolute value of the difference between the maximum value and minimum value among x, y, and z, where z=550.), xnm represents a wavelength exhibiting a minimum reflectance in a reflectance curve based on the antireflective layer, ynm represents a maximum sensitivity wavelength of the solar battery, and znm represents a maximum visible sensitivity wavelength, and the luminous reflectance is 0.6% or less. | 2011-07-21 |
20110176397 | Method for Providing an Interactive, Personalized Radio Network - An interactive radio network enables users to interact with the content of a radio broadcast, including commercials or messages, and to selectively save, store, review, fast forward, rewind, pause, forward, and respond to the radio programs and/or the commercials. The interactive radio network provides a widespread, international, and economical access to the radio stations, and reduces the need for advertisement billboards. It provides the users with an opportunity to selectively inquire about the products or services being advertised. Furthermore, the interactive radio network allows the users as well as various sectors of the advertisement industry to interact with the content of the radio broadcast. The advertisements are no longer limited to audio messages, but can further include elaborate video, text, and data information. The interactive radio network enables the users to communicate and interact with each others, based on the broadcast content. It also provides a widely accessible and affordable avenue for mass marketing and broadcasting of commercials to mobile users. | 2011-07-21 |
20110176398 | Thermally-Assisted Magnetic Recording Head Having Near-Field Optical Device with Propagation Edge - A thermally-assisted magnetic recording head includes a waveguide through which a light for exciting surface plasmon propagates, a near-field optical device configured to be coupled with the light in a surface plasmon mode and to emit near-field light from a near-field-light-generating end surface that forms a portion of an opposed-to-medium surface, and a magnetic pole for generating write field from its end on the opposed-to-medium surface side. The near-field optical device includes a contact-to-waveguide surface having a contact to the waveguide, and a propagation edge provided on a side opposite to the contact-to-waveguide surface, extending to the near-field-light-generating end surface, and configured to propagate there on the surface plasmon excited by the light. A gap between a near-field optical device-opposed surface of the magnetic pole and the propagation edge of the near-field optical device is larger at a section far from the end on the opposed-to-medium surface side than that at a section near the on the opposed-to-medium surface side. | 2011-07-21 |
20110176399 | Multi-layer recordable optical disk, recording device, and recording method - Disclosed herein is a multi-layer optical recording medium having n recording layers (n≧3) in which recording and reproduction of information are carried out by laser light, the multi-layer optical recording medium including: a file system area configured to be disposed near a last logical address in an area used as a logical address space in which stream data is recorded, wherein in the other recording layers different from the recording layer in which the file system area near the last logical address is disposed, the logical address space is not allocated to an area overlapping with the file system area in a layer stacking direction. | 2011-07-21 |
20110176400 | METHOD OF SERVO SPIRAL SWITCHING DURING SELF SERVO-WRITE FOR A DISK DRIVE - A recording medium for a disk drive has a plurality of tracks defined by servo wedges that are written using a first servo spiral set, a second servo spiral set, and a correction factor that accounts for the differences in the first set of spirals and the second set of spirals. The differences may be differences in position values decoded from the first set of spirals and position values decoded from the second set of spirals or differences in timing values decoded from the first set of spirals and timing values decoded from the second set of spirals. The first servo spiral set is used in writing components of the servo wedges that define a first set of tracks. The second servo spiral set and the correction factor are used in writing components of the servo wedges that define a second set of tracks. | 2011-07-21 |
20110176401 | SYSTEM AND METHOD FOR SUPPRESSING JITTER - A system and method for suppressing jitter in a digital data signal in a signal processor system. The digital data signal has spaced apart byte allocation units wherein such spacing is increased such that unallocated bytes can be identified and removed from the digital data signal. The byte allocation units of the digital data signal are suppressed with a digital data signal being outputted from the signal processor system having suppressed byte allocation units to suppress the occurrence of jitter. | 2011-07-21 |
20110176402 | FOCUS CONTROL APPARATUS, FOCUS CONTROL METHOD, OPTICAL PICKUP APPARATUS, DRIVE APPARATUS, AND OPTICAL RECORDING MEDIUM - [PROBLEMS] To perform highly accurate focus control in an optical recording medium of multilayer structure having an interface of each layer with a reflectance reduced as much as possible. | 2011-07-21 |
20110176403 | OPTICAL HEAD DEVICE, OPTICAL INFORMATION PROCESSING DEVICE, AND SIGNAL DETECTION METHOD - An optical head device includes a light source ( | 2011-07-21 |
20110176404 | OPTICALLY-READABLE DISK WITH COPY PROTECTION DEVICE - An optically-readable disk includes a device that disrupts readability of the disk when the disk is spun at an angular velocity substantially greater than required to play the disk in its intended playing device, or when a defined integral of velocity and time is exceeded. The device may include a fluid container that disperses a data-disruptive fluid. The device may include a membrane or layer that is disrupted when the disk is rotated above a defined angular velocity, or when a defined integral of velocity and time is exceeded. The device may include an electro-optical material that is activated by an electrical signal from a controller in response to an input from a sensor responsive to motion of the disk. | 2011-07-21 |
20110176405 | METHOD AND APPRATUS FOR RATE MATCHING WITHIN A COMMUNICATION SYSTEM - A method and apparatus for rate matching is described. During operation of a transmitter, multiple data streams are received and individually interleaved with a permutation of a same length K | 2011-07-21 |
20110176406 | Efficient Zadoff-Chu Sequence Generation - The present invention generates exponents of elements of a Zadoff-Chu sequence representing a preamble for uplink synchronization of mobile stations or a mobile station reference signal by first obtaining (S | 2011-07-21 |
20110176407 | SYSTEM AND METHOD OF RELEASING RESOURCES IN A TELECOMMUNICATION NETWORK - A system, method, and node for releasing resources in a telecommunications network. The method begins by a node assigning a resource-Identification (ID) to an internal resource within the node. At least one internal resource is allocated by the node for a specific Packet Data Network (PDN) connection. Next, a first message containing a resource-ID of the allocated internal resource is sent to one or more peer nodes. The peer nodes store the received resource-ID from the first message. When a node determines that a malfunction of the allocated internal resource of the node occurs, the node sends a second message containing the resource-ID of the malfunctioning internal resource to the peer nodes. The peer nodes then tear down the PDN connection. | 2011-07-21 |
20110176408 | NETWORK CODING ENHANCEMENTS - A method performed by a base station is provided. The method includes receiving, at the base station, a signal containing a transmitted first signal including a network coded message and a transmitted second signal including a non-network coded message, where the second signal is transmitted according to at least one transmission parameter. The method further includes receiving, at the base station, the at least one transmission parameter and determining, by the base station, an interference to the transmitted first signal caused by the transmitted second signal, where the interference is determined using the at least one transmission parameter. The method further includes removing the determined interference from the signal to recover the transmitted first signal. | 2011-07-21 |
20110176409 | Method for Implementing Permanent Ring Network Protection in an MESH Network - A method for implementing permanent ring network protection in an MESH network, the method includes the following steps: a node in a ring network protection group informing, when detecting a certain span fails, other nodes in the ring network protection group of the failure information ( | 2011-07-21 |
20110176410 | VIRTUAL ROUTER FAILOVER DAMPENING - A virtual router spans a number of physical routing devices. One of the physical routing devices is designated as master, and the other physical routing devices are designated as backups to the master. A failover protocol that includes both a non-dampened state and a dampened state can be implemented. According to the failover protocol, an attempt to designate one of the backups as master in place of the current master is permitted while the virtual router is in the non-dampened state, while such an attempt is suppressed while the virtual router is in the dampened state. | 2011-07-21 |
20110176411 | METHOD FOR PROTECTING A PSEUDO-WIRE - A method and apparatus are provided for establishing a first pseudo-wire between a first item of input terminal equipment and an item of output terminal equipment, used by the first item of input terminal equipment. The method includes a step of transmitting a first message requesting establishment of the first pseudo-wire to an item of switching equipment, the first pseudo-wire to be established consisting of a first link between the first item of input terminal equipment and the item of switching equipment and of a second link between the item of switching equipment and the item of output terminal equipment. In such a method, the first establishment-request message also includes a request to establish at least one backup pseudo-wire consisting of the second link and of a third link to be established between the item of switching equipment and a second item of input terminal equipment. | 2011-07-21 |
20110176412 | DISTRIBUTED VIRTUAL FIBRE CHANNEL OVER ETHERNET FORWARDER - A virtual Fibre Channel over Ethernet (FCoE) forwarder (vFCF) distributed in the core layer of an FCoE environment between two or more FCoE-enabled core switches by using a single virtual domain ID for the FCoE forwarders (FCFs) in a fabric is provided. In this manner, the network problem of having a single point of failure in a fabric is eliminated without needing to double the number of core switches in the FCoE environment for redundancy. Because the login and state information is distributed between the FCoE-enabled core switches of a fabric, the loss or failure of a core switch no longer means that the fabric goes down. Instead, when a core switch fails, the hosts and initiators may stay logged in through the other core switches. | 2011-07-21 |
20110176413 | MOBILE COMMUNICATION METHOD, NETWORK DEVICE, AND EXCHANGE - Provided is a mobile communication method which includes: a step in which a first exchange station MME#a allocates a temporary identifier TMSI for identifying a mobile station UE# | 2011-07-21 |
20110176414 | CONGESTION CONTROL FOR INTERWORKING BETWEEN NETWORKS - A congestion indication is introduced to indicate the congestion status of the circuit-switched network to a packet-switched network, such as an LTE network. The congestion indication is transmitted from an interworking function in the circuit-switched network to the LTE network. The congestion indication and/or other congestion information is transmitted with a circuit services signaling message that is otherwise being sent. Piggy-backing the congestion information with other circuit services signaling messages reduces the amount of signaling over the LTE network. | 2011-07-21 |
20110176415 | OPTIMIZED CONNECTION ADMISSION CONTROL FOR SYSTEMS USING ADAPTIVE MODULATION AND CODING TECHNIQUES - A method is proposed for controlling the admission of connections in a wireless communication system between a base station and a subscriber unit, in which the modulation and coding scheme of the uplink and downlink can be varied over time. The method comprises the steps of receiving a request for a connection and of admitting the connection and updating the available bandwidth, if the available bandwidth corresponding to the current AMC scheme is greater than the admission bandwidth of the connection. Moreover the method periodically evaluates if the current admission bandwidth can be changed for a plurality of active connections: if this is the case, and there is not enough bandwidth to allow the change, the method stops the admission of new connections, suspends at least one active connection of said plurality of active connections or changes the AMC scheme of such at least one active connection. On the other hand, if the current admission bandwidth can be changed and there is enough bandwidth to allow the change, the method updates the current admission bandwidth for the plurality of active connections and updates the available bandwidth. | 2011-07-21 |
20110176416 | Method for Discovering Multiple Routes in Sensor Networks - Multiple routes from a data source node to multiple data destination nodes in a large scale multi-hop mesh network are discovered. Nodes discover multiple routes to two destinations in an initial discovery phase that includes only two network-wide flooding of packets. The method can also work with one destination. The method can be extended to include more destinations with a proportional increase in the communication overhead. After the completion of the discovery phase, nodes can communicate or forward their own or received data by using any of the available routes. | 2011-07-21 |
20110176417 | ACCESS POINT, WIRELESS COMMUNICATION TERMINAL AND SERVER - Provided is an access point capable of handling a connection request exceeding the throughput while maintaining a communication state of a wireless communication terminal. The access point has a notification unit | 2011-07-21 |
20110176418 | ADAPTIVE TRAFFIC MANAGEMENT VIA ANALYTICS BASED VOLUME REDUCTION - A method of managing traffic over a communication link between a transmitting node and a receiving node is provided herein. The method includes: determining momentary traffic shaping constraints; accumulating incoming messages at the transmitting node into a data queue, based on the momentary traffic shaping constraints; transmitting the messages from the data queue to the receiving node over the communication link based on the momentary traffic shaping constraints; estimating a desired amount of data that needs to be discarded from messages in the data queue, based on: (a) the size of the data queue and (b) the momentary traffic shaping constraints; sorting data in the data queue by an order of importance, based on analytic objects; discarding, based on the analytic objects, the desired amount of data from the messages in the queued data, such that the discarded data is ranked lowest by the order of importance. | 2011-07-21 |
20110176419 | ANALYSIS AND CONTROL OF TRAFFIC BASED ON IDENTIFIED PACKET CONTROL FUNCTIONS - A device receives packet control function (PCF) load information associated with a packet data serving node (PDSN), and determines PCF Internet protocol (IP) address information and a number of sessions per PCF based on the PCF load information. The device also receives IP information from an IP network associated with the PDSN, and determines PCF identity information based on the IP information. The device further generates control information based on the PCF IP address information, the number of sessions per PCF, and the PCF identity information, and provides the control information to the PDSN to control operation of the PDSN. | 2011-07-21 |
20110176420 | WIRELESS TRANSMISSION DEVICE, WIRELESS TRANSMISSION METHOD, PROGRAM, AND INTEGRATED CIRCUIT - A wireless transmission device ( | 2011-07-21 |
20110176421 | METHODS FOR INTELLIGENT NIC BONDING AND LOAD-BALANCING - Methods, devices, and media for intelligent NIC bonding and load-balancing including the steps of: providing a packet at an incoming-packet port of a gateway; attaching an incoming-port identification, associated with the incoming-packet port, to the packet; routing the packet to a processing core; passing the packet through a gateway processing; sending the packet, by the core, to the operating system of a host system; and routing the packet to an outgoing-packet port of the gateway based on the incoming-port identification. Preferably, the gateway processing includes security processing of the packets. Preferably, the step of routing the packet to the outgoing-packet port is based solely on the incoming-port identification. Preferably, an outgoing-port identification, associated with the outgoing-packet port, has an identical bond-index to the incoming-port identification. Preferably, the gateway includes a plurality of incoming-packet ports, a plurality of respective incoming-port identifications, a plurality of processing cores, and a plurality of outgoing-packet ports. | 2011-07-21 |
20110176422 | Method and Arrangement in a Communication System - The present invention proposes a solution in the area of HSDPA flow control. It proposes an improvement to transport network congestion detection and avoidance. The improvement proposes to use a measurement of incoming bitrate to determine the reduction of bitrate after a transport network congestion event. The advantage is that high bitrate reduction is only used when it is necessary; otherwise only small bitrate reduction is used, which results in small oscillation, and consequently higher transport network utilization. | 2011-07-21 |
20110176423 | SYSTEM AND METHOD FOR CONGESTION CONTROL SIGNALING - Systems and methods for controlling congestion on a packet data network are provided. The congestion control may be implemented between any two network nodes where a regulation of a data flow is desired to prevent a device overload from occurring. In order to provide regulation of a data flow, congestion control states are used where each state regulates the data flow in a specified manner. State transitions may occur in response to messages that include congestion information detected at a network node. | 2011-07-21 |
20110176424 | LOAD BALANCING IN A MOBILE COMMUNICATIONS SYSTEM - Load balancing in a mobile communications system comprising dynamically setting of a representation of a mapping table for mapping data to a respective UE priority list of two or more access layers is disclosed. In accordance with example embodiments, UE and/or network capabilities are input to the setting. | 2011-07-21 |
20110176425 | Load-Balancing Structure for Packet Switches and Its Constructing Method - This invention provides a load-balancing structure for packet switches and its constructing method. In this method, the structure based on self-routing concentrators is divided into two stages, that is, a first stage and a second stage fabric. A virtual output group queue (VOGQ) is appended to each input group port of the first stage fabric, and a reordering buffer (RB) is configured behind each output group port of the second stage fabric. Packets stored in the VOGQ are combined into data blocks with preset length, which is divided into data slices of fixed size, finally each data slice is added an address tag and is delivered to the first stage fabric for self-routing. Once reaching the RB, data slices are recombined into data blocks. This invention solves the packet out-of-sequence problem in the load-balancing Birkhoff-von Neumann switching structure and improves the end-to-end throughput. | 2011-07-21 |
20110176426 | Method and Apparatus for Handling Stale PDN Context - Apparatus and methods are described herein for managing data network connections. When a gateway or user equipment receives a message indicating the active data network connections associated with the sending party, the gateway or user equipment checks a locally stored list of active data network connections to determine whether there is a match. If at least one active data network connection does not match, the receiving device sends a message to the sending party indicating the locally stored active data network connections. | 2011-07-21 |
20110176427 | Monitoring Performance of Telecommunications Network - A method of monitoring performance of a telecommunications network transmitting in real time multimedia data from a content provider to a device operating in the network is disclosed. The method comprises the steps of receiving said multimedia data; collecting information about the connection used to receive the multimedia data; producing a receiver report; appending said report with an identifier of a segment of the telecommunications network in which the device operates and transmitting said report to said telecommunications network. | 2011-07-21 |
20110176428 | SYSTEM FOR INTEGRATING A PLURALITY OF MODULES USING A POWER/DATA BACKBONE NETWORK - A Virtual Electrical and Electronic Device Interface and Management System (VEEDIMS) support architecture is provided. In one example, the VEEDIMS support architecture includes a vehicle layer and a shop layer. The vehicle layer has a module and a controller positioned in a vehicle. The module is configured to couple to a device via an input/output (I/O) interface compatible with the device and configured to couple to the controller via a cable adapted to simultaneously carry bi-directional data and uni-directional power to the module. The shop layer is separate from the vehicle layer and has a browser configured to communicate with an HTTP server in the module and an analysis tool configured to receive and analyze event driven and time series data from the controller. | 2011-07-21 |
20110176429 | METHOD, ARRANGEMENT AND SYSTEM FOR MONITORING A DATA PATH IN A COMMUNICATION NETWORK - A probing method, arrangement, and system for estimating a condition, such as available bandwidth, of a data path in a communication network including multiple nodes are described. A probe-packet sender node transmits probe packets with a sent inter-packet separation and a time-to-live towards an intermediate node. Control message packets are generated by the intermediate node when the time-to-live expires. The probe-packet sender node receives the control message packets and calculates a received inter-packet separation. An estimate of the data path condition can be generated based on the sent inter-packet separation and the received inter-packet separation. | 2011-07-21 |
20110176430 | METHOD AND APPARATUS FOR TRIGGERING MEASUREMENTS OF OTHER RADIO ACCESS TECHNOLOGIES (RATS) - Automatic setting and/or adjusting of the threshold(s) for triggering measurements of signal strength/quality of other RATs that are needed for IRAT mobility is described. The setting and/or adjusting of the threshold(s) triggering IRAT measurements is automatically optimized and preferably performed for each BS. Initially, constraints on the optimization of the IRAT measurement triggering threshold(s) are set, and a start value for the optimization of the IRAT measurement triggering threshold(s) is provided or determined. Input information needed for the optimization of the IRAT measurement triggering threshold(s) are then collected, and new IRAT measurement triggering threshold(s) are determined and set or existing IRAT measurement triggering threshold(s) are adjusted if appropriate. Operator expenses for adjusting the IRAT measurement triggering threshold(s) to appropriate values are thereby reduced as compared to manual setting, and the efficiency loss caused by non-optimized IRAT measurement triggering threshold(s) is reduced or minimized. | 2011-07-21 |
20110176431 | PHYSICAL LAYER LOOPBACK - In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed. | 2011-07-21 |
20110176432 | Radio Communication System Including Radio Terminal Apparatuses Each Arranged At Previously Determined Position - A radio communication system includes radio terminal apparatuses each arranged at a previously determined position, radio base station apparatuses for holding radio communications with these apparatuses, and a communication system controller for communicating with the respective radio terminal apparatus via the respective radio base station apparatuses connected thereto via a LAN. The communication system controller stores therein an ad-hoc radio communication permission table indicating permission or non-permission of each of direct radio communications between the respective radio terminal apparatuses, judges whether or not the direct radio communication is permitted based on the ad-hoc radio communication permission table, in response to a request signal for a direct radio communication with a further radio terminal apparatuses received from each radio terminal apparatuses via the radio base station apparatuses, and transmits a notice signal including a result of the judgment to the radio terminal apparatus which transmitted the request signal. | 2011-07-21 |
20110176433 | Method of controlling resource usage in communication systems - In one embodiment, the method includes receiving, at the communication node, resource usage price information. The resource usage price information characterizes a cost associated with the communication node using a resource. The communication node determines an amount of the resource to use based on the received resource usage price information. | 2011-07-21 |
20110176434 | ACQUIRING A SIGNAL PARAMETER FOR A NEIGHBORING ACCESS POINT - In an example embodiment, a wireless device is configured to associate with a first access point on a first frequency. The wireless device listens for a predefined frame, which may be sent by neighboring access points or other wireless devices. When the wireless device receives a signal comprising a predefined frame, the wireless device acquires a parameter, such as signal strength, for the signal. The wireless device sends the parameter for the signal to the first access point. | 2011-07-21 |