| 29th week of 2012 patent applcation highlights part 27 |
| Patent application number | Title | Published |
|---|
| 20120182776 | DRAM DEVICE WITH BUILT-IN SELF-TEST CIRCUITRY - A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells. | 2012-07-19 |
| 20120182777 | MEMORY MODULE CUTTING OFF DM PAD LEAKAGE CURRENT - A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode. | 2012-07-19 |
| 20120182778 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - Such a device is disclosed that includes a first semiconductor chip including a plurality of first terminals, a plurality of second terminals, and a first circuit coupled between the first and second terminals and configured to control combinations of the first terminals to be electrically connected to the second terminals, and a second semiconductor chip including a plurality of third terminals coupled respectively to the second terminals, an internal circuit, and a second circuit coupled between the third terminals and the internal circuit and configured to activate the internal circuit when a combination of signals appearing at the third terminals indicates a chip selection. | 2012-07-19 |
| 20120182779 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a substrate, an interconnect layer, a memory layer, a circuit layer, first and second contact interconnects. The interconnect layer is provided on the substrate and includes first and second interconnects. The memory layer is provided between the substrate and the interconnect layer and includes first and second memory cell array units. The first and second memory cell array units include a plurality of memory cells. The circuit layer is provided between the memory layer and the substrate and includes a first circuit unit. The first contact interconnect is provided between the first and second memory cell array units and electrically connects one end of the first circuit unit to the first interconnect. The second contact interconnect electrically connects a second end of the first circuit unit different from the first end to the second interconnect. | 2012-07-19 |
| 20120182780 | Memory System with Multi-Level Status Signaling and Method for Operating the Same - A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level. | 2012-07-19 |
| 20120182781 | MAGNETIC SHIFT REGISTER MEMORY DEVICE - In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains. | 2012-07-19 |
| 20120182782 | METHODS FOR TESTING UNPROGRAMMED OTP MEMORY - Methods for testing unprogrammed single transistor and two transistor anti-fuse memory cells include testing for connections of the cells to a bitline by comparing a voltage characteristic of a bitline connected to the cell under test to a reference bitline having a predetermined voltage characteristic. Some methods can use test cells having an access transistor identically configured to the access transistor of a normal memory cell, but omitting the anti-fuse device found in the normal memory cell, for testing the presence of a connection of the normal memory cell to the bitline. Such a test cell can be used in a further test for determining the level of capacitive coupling of the wordline voltage to the bitlines relative to that of a normal memory cell under test. | 2012-07-19 |
| 20120182783 | PROGRAMMING AN ARRAY OF RESISTANCE RANDOM ACCESS MEMORY CELLS USING UNIPOLAR PULSES - Subject matter disclosed herein relates to a memory device, and more particularly to programming a non-volatile memory device. | 2012-07-19 |
| 20120182784 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M | 2012-07-19 |
| 20120182785 | MEMORY UNIT AND METHOD OF OPERATING THE SAME - A memory unit includes memory cells each having a memory element and a transistor, word lines and first and second bit lines, and a drive section. In performing setting operation for a first memory element located on one word line and in performing resetting operation for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference. | 2012-07-19 |
| 20120182786 | BIDIRECTIONAL RESISTIVE MEMORY DEVICES USING SELECTIVE READ VOLTAGE POLARITY - A memory device includes a memory cell array including a plurality of memory cells, each including a bidirectional variable resistance element and an input/output circuit configured to determine a polarity for a read voltage to be applied to a selected memory cell among the plurality of memory cells and to apply the read voltage with the determined polarity to the selected memory cell. The input/output circuit may include a polarity determination circuit configured to determine the polarity responsive to a determination mode signal and a driver circuit configured to apply the read voltage with the determined polarity to the selected memory cell. | 2012-07-19 |
| 20120182787 | CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY - Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed. | 2012-07-19 |
| 20120182788 | STORAGE ELEMENT, STORAGE DEVICE, SIGNAL PROCESSING CIRCUIT, AND METHOD FOR DRIVING STORAGE ELEMENT - A storage element capable of retaining data even after supply of power supply voltage is stopped is provided. In the storage element retaining data in synchronization with a clock signal, with the use of a capacitor and a transistor having a channel in an oxide semiconductor layer, the data can be retained even after supply of power supply voltage is stopped. Here, when the transistor is turned off while the level of the clock signal is kept constant before the supply of power supply voltage is stopped, the data can be retained accurately in the capacitor. By applying such a storage element to each of a CPU, a memory, and a peripheral control device, supply of power supply voltage can be stopped in the entire system, so that the power consumption of the entire system can be reduced. | 2012-07-19 |
| 20120182789 | MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND DETECTING METHOD - To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching element for controlling supply, storage, and release of charge in the first capacitor and the second capacitor. The capacitance of the first capacitor is thousand or more times the capacitance of the second capacitor, preferably ten thousand or more times the capacitance of the second capacitor. In normal operation, charge is stored using the first capacitor and the second capacitor. In performing verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, charge is stored using the second capacitor. | 2012-07-19 |
| 20120182790 | SEMICONDUCTOR MEMORY DEVICE - The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material. | 2012-07-19 |
| 20120182791 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A memory circuit is included. The memory circuit includes n field-effect transistors (n is a natural number of 2 or more) and n capacitors each including a pair of electrodes. A digital data signal is input to one of a source and a drain of the first field-effect transistor. One of a source and a drain of the k-th field-effect transistor (k is a natural number of greater than or equal to 2 and less than or equal to n) is electrically connected to the other of a source and a drain of the (k−1)-th field-effect transistor. One of the pair of electrodes of the m-th capacitor (m is a natural number of n or less) is electrically connected to the other of a source and a drain of the m-th field-effect transistor of the n field-effect transistors. At least two of the n capacitors have different capacitance values. | 2012-07-19 |
| 20120182792 | BIASING CIRCUIT AND TECHNIQUE FOR SRAM DATA RETENTION - A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply. | 2012-07-19 |
| 20120182793 | ASYMMETRIC SILICON-ON-INSULATOR SRAM CELL - A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric. | 2012-07-19 |
| 20120182794 | Multi-Terminal Phase Change Devices - Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active terminals, with control of the connection being effected using a separate terminal or terminals Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals, allowing use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. Programming control can be placed outside of main signal path through the phase change device, reducing impact of associated capacitance and resistance of the device. | 2012-07-19 |
| 20120182795 | EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks. | 2012-07-19 |
| 20120182796 | STORAGE ELEMENT AND MEMORY DEVICE - A storage element includes a storage layer which has magnetization vertical to the film surface and of which the direction of magnetization changes, a magnetization fixed layer which has magnetization vertical to the film surface serving as a reference of information, and an insulating layer, and the direction of magnetization of the storage layer changes by injecting spin-polarized electrons in the laminated direction of the layer structure so as to perform information recording, the size of an effective demagnetizing field that the storage layer receives is configured to be smaller than a saturated magnetization amount of the storage layer, and a ferromagnetic layer material constituting the storage layer has CoFeB as the base material and an anti-corrosive element is added to the base material. | 2012-07-19 |
| 20120182797 | SENSE OPERATION IN A MEMORY DEVICE - Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell. | 2012-07-19 |
| 20120182798 | Non-Volatile Semiconductor Memory - A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. | 2012-07-19 |
| 20120182799 | DATA PATH FOR MULTI-LEVEL CELL MEMORY, METHODS FOR STORING AND METHODS FOR UTILIZING A MEMORY ARRAY - Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array. | 2012-07-19 |
| 20120182800 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PREVENTING A SHIFT OF THRESHOLD VOLTAGE - A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls a potential of the word line and the bit line in accordance with input data, and writs data in the memory cell. The control circuit applies a write voltage corresponding to write data to a memory cell. The write voltage differs for each write data. A verify operation is executed for each write data after a write voltage application operation ends with respect to all n levels. | 2012-07-19 |
| 20120182801 | Memory Architecture of 3D NOR Array - A 3D memory device includes a plurality of ridge-shaped stacks of memory cells. Word lines are arranged over the stacks of memory cells. Bit lines structures are coupled to multiple locations along the stacks of memory cells. Source line structures are coupled to multiple locations along each of the semiconductor material strips of the stacks. The bit line structures and the source line structures are between adjacent ones of the word lines. | 2012-07-19 |
| 20120182802 | Memory Architecture of 3D Array With Improved Uniformity of Bit Line Capacitances - A 3D integrated circuit memory array has a plurality of plane positions. Multiple bit line structures have a multiple sequences of multiple plane positions. Each sequence characterizes an order in which a bit line structure couples the plane positions to bit lines. Each bit line is coupled to at least two different plane positions to access memory cells at two or more different plane positions. | 2012-07-19 |
| 20120182803 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IMPROVING FAILURE-RELIEF EFFICIENCY - According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a drive circuit. When a failure exists within a corresponding first logical block, the latch circuits store a flag indicating the failure. The drive circuit inhibits driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which the selected word lines belong, and allows the driving of the word lines belonging to the physical block including the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong. | 2012-07-19 |
| 20120182804 | ARCHITECTURE FOR A 3D MEMORY ARRAY - Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines. | 2012-07-19 |
| 20120182805 | STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME - Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed. | 2012-07-19 |
| 20120182806 | Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures - A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines. | 2012-07-19 |
| 20120182807 | Three-Dimensional Stacked and-Type Flash Memory Structure and Methods of Manufacturing and Operating the Same Hydride - A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, wherein one set of channels is sandwiched between the adjacent sets of bit lines and source lines. | 2012-07-19 |
| 20120182808 | Memory Device, Manufacturing Method and Operating Method of the Same - A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element. | 2012-07-19 |
| 20120182809 | Data State-Dependent Channel Boosting To Reduce Channel-To-Floating Gate Coupling In Memory - In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states. | 2012-07-19 |
| 20120182810 | METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES - The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells. | 2012-07-19 |
| 20120182811 | METHOD OF ERASING A FLASH EEPROM MEMORY - A method for erasing a flash EEPROM memory device is disclosed. The memory device has a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics. The method comprises the steps of: applying a first voltage bias to both the well electrode and the second semiconductor region and a second bias to the control gate electrode for a duration of F/N tunneling; applying a third voltage bias to the well electrode and the second semiconductor region and a first zero voltage bias to the control gate electrode for a duration of traps depopulation; and, after the duration of traps depopulation, applying a fourth voltage bias to the control gate electrode and a second zero voltage bias to the well electrode and the second semiconductor region for a duration of traps assisted tunneling. | 2012-07-19 |
| 20120182812 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device that may perform a second operation during a first operation comprises a command decoder for generating a decoded command signal, a suspend pulse and a resume pulse, and a storage unit for storing the decoded address signal, the decoded command signal and a data signal in response to the suspend pulse and providing the decoded address signal, the decoded command signal and the decoded data signal as a stored address signal, a stored command signal and a stored data signal, respectively, in response to the resume pulse. | 2012-07-19 |
| 20120182813 | POWER SUPPLY CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE POWER SUPPLY CIRCUIT - According to one embodiment, a power supply circuit, which generates a power supply voltage which is applied to a memory cell array including a plurality of memory cells disposed at intersections between a plurality of word lines and a plurality of bit lines, comprises a first boost circuit configured to boost an input voltage, a first voltage step-down circuit having an input connected to an output of the first boost circuit, and a voltage control circuit configured to control the first boost circuit and the first voltage step-down circuit. The voltage control circuit is configured to generate, not via the first voltage step-down circuit, a voltage which is boosted by the first boost circuit, when a first voltage is transferred to a non-selected memory cell. | 2012-07-19 |
| 20120182814 | PROGRAMMING CIRCUIT USING ANTIFUSE - A programming circuit using an antifuse includes a fuse signal generation unit including an antifuse which connects a node with a low voltage in response to a test address when the node is driven to a level of a high voltage, and configured to output a signal of the node as a fuse signal in response to a test mode signal; and a programming signal generation unit configured to buffer the fuse signal in response to a power-up signal and generate a programming signal. | 2012-07-19 |
| 20120182815 | Memory Devices Having Controllers that Divide Command Signals Into Two Signals and Systems Including Such Memory Devices - A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving a first operation command signal, dividing the first operation command signal into at least two paths pulse signals corresponding to at least two paths, based on a pre-determined criterion, and then supplying the at least two path pulse signals to the access block. The access block operates based on an output signal of the controller block. | 2012-07-19 |
| 20120182816 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Such a device is disclosed that includes: a row redundancy circuit and a column redundancy circuit for replacing defective sub word lines and defective bit lines included in a memory cell array, respectively; first and second electrical fuse circuits that store the addresses of the defective sub word lines and the defective bit lines, respectively; and a fuse select circuit that selects, in a first operation mode, either one of the first and second electrical fuse circuits based on an address signal supplied when a determination signal is activated, and selects, in a second operation mode, the other of the first and second electrical fuse circuits based on the address signal supplied when the determination signal is activated. According to the present invention, it is possible to flexibly switch between replacement using redundant word lines and replacement using redundant bit lines. | 2012-07-19 |
| 20120182817 | REDUNDANT MEMORY ARRAY FOR REPLACING MEMORY SECTIONS OF MAIN MEMORY - Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array. | 2012-07-19 |
| 20120182818 | LOW POWER AND HIGH SPEED SENSE AMPLIFIER - A sense amplifier circuit includes a precharge circuit configured to precharge a bit line coupled to a sensing node in response to a precharge control signal and a sense output circuit. The sense output circuit includes a sense output inverter coupled to the sensing node. The sense output inverter is disabled during bit line precharging and for a period after bit line precharging is complete, and thereafter the sense output inverter is enabled. | 2012-07-19 |
| 20120182819 | RECYCLING CHARGES - A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised. | 2012-07-19 |
| 20120182820 | LOCAL POWER DOMAINS FOR MEMORY SECTIONS OF AN ARRAY OF MEMORY - Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be operated by decoupling row decoder circuitry from receiving electrical power while the memory array is not being accessed. Portions of the memory array to be accessed are determined from external memory addresses and the row decoder for the portions of the memory array to be accessed are selectively provided with electrical power. The section of memory is then accessed. One such array includes memory section voltage supply rails having decoder circuits coupled to receive electrical power, and further includes memory section power control logic. The control logic selectively couples the memory section voltage supply rail to a primary voltage supply to provide electrical power to the memory section voltage supply rail in response to being selected based on memory addresses. | 2012-07-19 |
| 20120182821 | MEMORY SYSTEM COMPONENTS THAT SUPPORT ERROR DETECTION AND CORRECTION - A memory system that includes a memory device and a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. The memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first row address and the second row address to a first row decoder and a second row decoder in the memory bank, respectively. Finally, the memory device uses the first row decoder to decode the first row address to access the first row and concurrently uses the second row decoder to decode the second row address to access the second row. | 2012-07-19 |
| 20120182822 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - Such a device is disclosed that includes a first chip outputting a bank address signal and an active signal, and a plurality of second chips stacked on the first chip. Each of the second chips includes a plurality of memory banks each selected based on the bank address signal. Selected one or ones of the memory banks is brought into an active state in response to the active signal. Each of the second chips activates a local bank active signal when at least one of the memory banks included therein is in the active state. The first chip activates a bank active signal when at least one of the local bank active signals is activated. | 2012-07-19 |
| 20120182823 | TREATMENT ELEMENT FOR TREATING MATERIAL IN A MULTI-SHAFT WORM MACHINE AND MULTI-SHAFT WORM MACHINE - A treatment element to treat material in a multi-shaft worm machine has an outer contour with at least one outer contour portion, the associated evolute of which is a quantity of at least three points, each of the points lying outside the longitudinal axis and within the outer radius of the treatment element and two respective adjacent points having a spacing from one another, which is less than half the core radius. The treatment element ensures high flexibility during the adjustment of shear and/or extensional flows on the material to be treated. | 2012-07-19 |
| 20120182824 | AUTOMATIC MILK PREPARING DEVICE - An automatic milk preparing device is provided, including a microcontroller fixed in the automatic milk preparing device for controlling the operation of same, a powder box connected with the microcontroller and provided with a powder output gate in the front of the powder box for controlling the powder to be added according to the signal from the microcontroller, a water tank connected with the microcontroller for controlling the water to be added according to the signal from the microcontroller, a stirring structure fixed under the powder output gate, connected with the water tank through a first water pipe and provided with a milk outlet at the lower part of the stirring structure, and a weight measuring structure fixed below the stirring structure and connected with the microcontroller for laying a milk bottle, weighing water and/or milk powder in the bottle and feeding the result of weight back to the microcontroller. | 2012-07-19 |
| 20120182825 | BEVERAGE MACHINES WITH SIMPLIFIED SERVICING - A machine for a given geographical market and for preparing a beverage from a combination of a first ingredient and a second ingredient. The machine includes first and second containers, container arranged for storing one of these ingredients or a packaging thereof. Such machine is so arranged as to let a user select a quantity ratio of the first and second ingredients for preparation of a beverage. The containers have normal storage volumes for their respective ingredient or packaging. The first and second normal storage volumes of the containers have a volume ratio equivalent to a ratio of respective normal volumes necessary for storing the first and second ingredients or packaging thereof used in an estimated average quantity ratio for preparing such beverage in the given geographical market. | 2012-07-19 |
| 20120182826 | COOLING STICK FOR A BLENDER AND METHOD OF USING SAME - A cooling stick for a blender includes a cylindrical member designed to fit tightly through a circular aperture extending through the blender lid. The member has a lower portion and an upper portion with a surrounding rim of a diameter larger than the circular aperture. The lower portion has a lower end sized and shaped to avoid contact with the blender blade assembly. The cylindrical member has an interior chamber, an opening extending from an exterior of the member to the chamber and means for sealing the opening. A cooling fluid is located within the interior chamber. The fluid is cooled or frozen when the cooling stick is located in a cooling environment. When the chilled cooling stick is mounted to the lid of the blender, the cooling stick will cool contents of the blender when the blender is operated. The cooling stick also cools the blender contents after operation. | 2012-07-19 |
| 20120182827 | PROCESS FOR CONTINUOUS DRY CONVEYING OF CARBONACEOUS MATERIALS SUBJECT TO PARTIAL OXIDIZATION TO A PRESSURIZED GASIFICATION REACTOR - The present invention demonstrates a continuous process for dry conveying of powdered coal either a blend of carbonaceous material subject to partial oxidization whereby the conveying feed will be transferred via a suitable conveyer from an atmospheric silo to a or a number of extruder's LP Feeder Vessel and be fed over extruder's inlet chute in continuo to a or a number of extruder(s), in which the dry feed material will be densificated along the compression zone of that extruder up to high pressure and will be discharged over outlet chute into a downstream said First Pressurized Vessel, wherefrom the feeding precursor will be transported via a or a number of in series pressurized tubular-drag conveyor to the said Second Pressurized Vessel, which is equipped with one or more Reactor Feeding Unit(s), referred to Splitter(s), each one consisting of a Star Valve, Reactor-Feed-Line and a said Injection-Line for pneumatic conveying individually, whereby the feed carbonaceous material will be exposed to with injection gaseous media (saturated steam, superheated steam, inter gases, natural gas, N2, CO2, purge gas from synthesis section of ammonia, methanol plant, purge gas from PSA of hydrogen purification section, hydrogen or a blend of those gaseous media in any composition) by the formation of any pneumatic bulk conveying mechanism into a downstream pressurized reactor, preferably a gasification reactor, wherein the transported precursor will be converted chemically under high temperature and elevated pressure via partial oxidization reactions to process gas, slag and ash. | 2012-07-19 |
| 20120182828 | MIXER OF COMBUSTIBLE GAS AND COMBUSTION SUPPORTING GAS | 2012-07-19 |
| 20120182829 | Process and Device for Mixing a Heterogeneous Solution into a Homogeneous Solution - The present invention relates to a process for mixing a heterogeneous solution containing at least two different liquids and, optionally, at least one solid entity, so as to obtain a homogeneous solution, the process comprising the following steps:
| 2012-07-19 |
| 20120182830 | MIXING SCREW - An auger for a vertical feed mixer with a lifting surface that is upwardly angle from an inner edge toward an outer edge. A fliting portion to form a part of an auger for a vertical feed mixer, the fliting portion including an outer edge that is positioned higher than a radially positioned inner edge. An auger for a vertical feed mixer that in rotation defines an hourglass shape. | 2012-07-19 |
| 20120182831 | ACOUSTIC VELOCITY MEASUREMENTS USING TILTED TRANSDUCERS - Apparatus, systems, and methods may operate to emit acoustic pulses into a drilling fluid in a well bore, using a first acoustic transducer in a downhole tool, and detecting the acoustic pulses after reflection from the wall of the well bore, using a second acoustic transducer in the downhole tool. The faces of the first and second acoustic transducers are non-parallel. Further activities include emitting additional acoustic pulses into the drilling fluid using the second acoustic transducer, and detecting them using the second acoustic transducer. The acoustic velocity of the drilling fluid can be determined based on respective travel times. Additional apparatus, systems, and methods are described. | 2012-07-19 |
| 20120182832 | SEISMIC DATA ACQUISITION SYSTEMS AND METHOD UTILIZING A WIRELINE REPEATER UNIT - A system and methods for acquiring seismic data is provided. In one aspect, the system and methods utilize a plurality of field service units placed over a region of interest, a repeater unit that wirelessly communicates with the field service units and a remote unit for controlling and processing the seismic data acquired by the field service units. In one aspect, the system and methods determine a condition associated with each of a plurality of attributes relating to acquisition of the seismic data at each field service unit, generate messages at each field service unit when the condition of a particular attribute meets a selected criterion, transmit the generated messages, receive the messages transmitted by at least a group of field service units at a repeater unit placed in the region of interest, analyze the messages received from the group of field service units at the repeater unit and then transmit information relating to the received messages to the remote unit for further processing. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2012-07-19 |
| 20120182833 | ULTRASONIC ID READER - A method for identifying a warhead in an aircraft launch tube includes providing a pattern of grooves on the surface of a warhead, with the pattern of grooves being associated with an identification code identifying the warhead or a characteristic of it, providing the warhead in an aircraft launch tube, providing a piezoelectric transducer on the launch tube, emitting an ultrasonic wave from the piezoelectric transducer to the pattern of grooves, where the wave encounters the pattern of grooves at an angle of less than 90° so that waves striking the interior of a groove are reflected back to the transducer as echo waves, while waves not striking the interior of a groove are reflected away from the transducer, and reading the pattern of returning echo waves to determine the identification code indicated by the pattern of grooves on the warhead. | 2012-07-19 |
| 20120182834 | WEARABLE SHOOTER LOCALIZATION SYSTEM - A wearable shooter localization system including a microphone array, processor, and output device for determining information about a gunshot. The microphone array may be worn by on the upper arm of the user. A second array, which may operate cooperatively or independently from the first array, may be worn on the other arm. The microphone array is sensitive to the acoustic effects of gunfire and provides a set of electrical signals to the processing unit, which identifies the origin of the fire. The system may include orientation and/or motion detection sensors, which the processor may use to either initially compute a direction to the origin of a projectile in a frame of reference meaningful to a wearer of the system or to subsequently update that direction as the wearer moves. | 2012-07-19 |
| 20120182835 | Systems and Methods for Acquiring and Characterizing Time Varying Signals of Interest - Methods or systems for identifying seismic or acoustic signals of interest originating with moving motorized vehicles or footstep movement or stationary or moving machinery. A related system for monitoring an area includes a plurality of sensing devices each comprising a frame and a piezo-electric sensor element. A monitoring device is coupled to receive information from each of the sensing devices. One method includes providing a processing chain coupled to receive signal data from a sensor device which receives the signals, including a detection stage, a Joint Time Frequency (JTF) domain stage, and a classification stage. The detection stage identifies presence of signals that emerge from the background. The JTF domain stage estimates the state of the signals of interest over time. The classification stage assesses the previously derived information to form a decision about source identity. In one embodiment, the detector stage performs detections on a single cycle basis. | 2012-07-19 |
| 20120182836 | COMMUNICATION SYSTEM USING ULTRASONIC WAVES - Disclosed is a technology for performing a communication using an ultrasonic wave in an environment where an electromagnetic shielding is so severe that a wireless communication using an electromagnetic is difficult. In the environment where the electromagnetic shielding is severe, an ultrasonic terminal according to the present invention may transmit the ultrasonic wave using a solid structure as a medium, and an ultrasonic base station may receive the ultrasonic wave using the solid structure as the medium. | 2012-07-19 |
| 20120182837 | Systems and methods of locating weapon fire incidents using measurements/data from acoustic, optical, seismic, and/or other sensors - Systems and methods are disclosed for locating a weapon fire incident such as an acoustic transient from a gunshot, explosion, weapons launch, etc. In one exemplary implementation, there is provided a method of locating the incident from a combination of propagation phenomena including a discharge time of the weapon fire incident. Moreover, the method may include obtaining a first propagation parameter of the incident from one or more first sensors, obtaining the discharge time from another sensor, and processing the data to determine a location using a common time basis among sensor measurements. According to further exemplary implementations, the discharge time may include a transient event that has a different propagation velocity than that of sound in the atmosphere. | 2012-07-19 |
| 20120182838 | QUICK CORRECTOR FOR A TIME RELATED MAGNITUDE INDICATOR FOR A TIMEPIECE - A corrector ( | 2012-07-19 |
| 20120182839 | Timepiece With Indication of the Time Zone Corresponding to a Chosen Time - The invention concerns a timepiece comprising, in addition to the usual hour and minute hands, a disc on which there is represented a circular map of the world divided into time zones and a pointer designating one particular time zone corresponding to a time chosen by the user. | 2012-07-19 |
| 20120182840 | Motor drive device, timepiece device, and electronic device - A motor drive device includes a charging detection and reverse current prevention portion and a pulse selection control portion. The charging detection and reverse current prevention portion detects a charging state of a secondary battery that is charged by an electromotive force of a solar battery, the charging state indicating whether the secondary battery is being charged. The pulse selection control portion causes a first drive pulse for driving a motor to be generated and, in a case where the charging state that is detected by the charging detection and reverse current prevention portion is different after the first drive pulse has been output from what it was before the first drive pulse was output, causes a second drive pulse for driving the motor to be generated. | 2012-07-19 |
| 20120182841 | TIMEPIECE - Timepiece, characterised in that it primarily consists of a baseplate ( | 2012-07-19 |
| 20120182842 | THERMAL-ASSISTED-MAGNETIC-RECORDING HEAD AND MAGNETIC RECORDING SYSTEM EQUIPPED WITH THE SAME - Provided is a thermal-assisted-magnetic-recording head capable of irradiating a magnetic recording medium with light with a spot size reduced on the submicron order with high utilization efficiency. A spot size converter | 2012-07-19 |
| 20120182843 | DEVICES AND METHODS FOR PROTECTING LASER DIODES FROM ELECTROSTATIC DISCHARGE - In accordance with certain embodiments, an apparatus has a depletion-mode transistor electrically connected to a laser diode. The transistor provides a low impedance path for diverting electrostatic current away from the laser diode. In accordance with certain embodiments, a method for protecting a laser diode from an electrostatic charge includes providing a transistor that is electrically connected to a laser diode and has a drain and a source. The method further includes redirecting the electrostatic charge through a low impedance path from the drain to the source during a powered-on state. | 2012-07-19 |
| 20120182844 | Optical unit protection on HGA - An optical laser-activated TAMR (Thermal Assisted Magnetic Recording) slider, when normally mounted on a flexure, has an optical laser as well as other elements of its optical system exposed and subject to damage by mechanical shocks. The stand-off protective device disclosed herein, formed separately and attached to the flexure, or formed as part of the flexure itself, can protect the optical elements of such a slider from these shocks, particularly from inadvertent contacts with adjacent sliders or mechanical limiters. | 2012-07-19 |
| 20120182845 | OPTICAL DISC DEVICE AND LASER BEAM POWER CONTROLLING METHOD FOR OPTICAL DISC DEVICE - Erroneous data erasure owing to radiation of laser beam with excessive power to the recording layer of the multilayered optical disc upon servo-off while reproducing data of the disc is prevented. When detecting the servo-off based on the amplitude of the tracking error signal or the focus error signal, the laser beam power is reduced to a predetermined minimum value, and the laser beam power value is set again based on the address of the recording medium, which has been obtained later for reproduction. The laser beam power value is changed by applying an offset to the drive current or changing the target value under APC. | 2012-07-19 |
| 20120182846 | Device for Recording, Erasing and Reading Data on a Multi-Layer Optical Disc - The invention relates to three-dimensional optical memory devices and can be used in all areas of computing in which it is necessary to record large data files on compact carriers, and also for recording, erasing and reading video data, for example, in independent video viewing systems. The device comprises an optical disc positioning system, a source of radiation with two different wavelengths that is optically coupled to a focusing system, focusing system positioning means, and an optical sensor that is optically coupled to the focusing system via a spectrum splitter and an controlled spectrum selector placed between the source of radiation with two different wavelengths and the spectrum splitter, wherein the focusing system is designed with longitudinal chromatic aberration at the given wavelengths. | 2012-07-19 |
| 20120182847 | OBJECTIVE LENS AND OPTICAL PICK-UP DEVICE USING THE SAME - Provided is an objective lens that allows securing of a long working distance for a laser beam with a long wavelength and has a predetermined thickness or larger, and an optical pickup apparatus including the objective lens. In an objective lens of the present invention, a first region that focuses laser beams of a BD, DVD, and CD standards, a second region that focuses the laser beams of the DVD and CD standards, and a third region that focuses the laser beams of the BD and the DVD standards are provided in this order from a center portion of the objective lens. An optical super resolution with the laser beam of the BD standard is achieved by preventing a portion of the laser beam of the BD standard transmitted through the second region from contributing to spot formation. | 2012-07-19 |
| 20120182848 | DATA STORAGE - A data storage apparatus and method. The apparatus comprises a mounting structure, a motor mechanically attached to mounting structure, and a data storage platter mechanically attached to the motor. The apparatus additionally comprises a single actuator arm comprising a first and second read/write data head or multiple radial movement mechanisms each comprising a read/write data head. The single actuator arm is configured to move axially along an arc and across a top surface of the data storage platter such that the first read/write data head has access to a first section and a second section of the data storage platter and the second read/write data head only has access to the second section of data storage platter. Each radial movement mechanism moves a different read/write data head radially all along a radius of the data storage platter and over and across different sections of the data storage platter. | 2012-07-19 |
| 20120182849 | METHOD AND APPARATUS FOR CENTRING A DISK ON A SPINDLE, METHOD OF TESTING WITH A SPINSTAND AND SPINSTAND - There is disclosed herein a method and apparatus for centring a disk on a spindle, a spinstand and a method of testing with a spinstand. The method of centring includes attaching the disk to the spindle with a stick-slip clamp. A vector is determined by which the centre of the disk is displaced from the spindle axis and the vector is aligned with a movably mounted piezo actuator. A voltage is then applied to the piezo actuator to cause the piezo actuator to apply an impulse to the edge of the disk to cause the disk to slip in the clamp and reduce the displacement of the disk. | 2012-07-19 |
| 20120182850 | Optical Pickup Apparatus and Disc Apparatus Including the Same - An optical pickup apparatus includes at least: a light emitting element capable of emitting at least first wavelength light and second wavelength light; and a diffraction grating configured to split the first wavelength light into at least a first main beam and a first sub-beam and to split the second wavelength light into at least a second main beam and a second sub-beam, a following expression (1) being satisfied: | 2012-07-19 |
| 20120182851 | OPTICAL RECORDING MEDIUM AND RECORDING METHOD - Techniques for recording and reading information to/from a recording medium based on positions of a plurality of marks are described herein. Each of the plurality of marks may have the same length. The information may be recorded based on a mark interval between successive marks. Apparatus and a recording medium suitable for use with such techniques are also disclosed. | 2012-07-19 |
| 20120182852 | OBJECTIVE LENS, OPTICAL HEAD, OPTICAL DISK APPARATUS, AND INFORMATION PROCESSING APPARATUS - An objective lens, an optical head, an optical disk apparatus and an information processing apparatus which can suppress deterioration of a focal spot caused by a drop in the diffraction efficiency are provided. An inner circumference area ( | 2012-07-19 |
| 20120182853 | Device for Recording and Reading Data on a Multi-Layer Optical Disc - A three-dimensional optical memory device comprises an optical disc positioning system, two sources of radiation with wavelengths | 2012-07-19 |
| 20120182854 | Objective Lens for Optical Pickup Device, Optical Pickup Device, and Optical Information Recording and Reproducing Device - Provided is an optical pickup device capable of ensuring the compatibility among three types of optical discs, i.e., BDs, DVDs, and CDs, with a common objective lens and, in addition, capable of ensuring a sufficient working distance for CDs, and also provided are an optical information recording and reproducing device and an objective lens suitable for the optical information recording and reproducing device. On the objective lens, there is arranged a first optical path difference providing structure formed such that: the direction of step differences of a basic structure wherein the diffraction order of a blue-violet laser light flux become an odd order faces toward the opposite direction of the optical axis; the direction of step differences of a basic structure wherein the diffraction order of the blue-violet laser light flux become an even order faces toward the optical axis; and both the basic structures are overlapped together. | 2012-07-19 |
| 20120182855 | Objective Lens and Optical Pickup Device - Provided is an objective lens that enables the suppression of molding defects in a high NA lens, and an optical pickup device. As the objective lens (OBJ) includes a thick-flange section (FT), a thick-flange-section forming section ( | 2012-07-19 |
| 20120182856 | SPINDLE MOTOR - A spindle motor includes a rotor including a rotary shaft and magnets, a stator including a bearing, which supports the rotary shaft, and an armature corresponding to the magnets. The rotor is caused to rotate by an electromagnetic force generated by the magnets and the armature. The stator includes a plate having a stepped portion in a portion thereof, which faces the rotary shaft. | 2012-07-19 |
| 20120182857 | Sounding Reference Signal Processing for LTE - A wireless communication receiver including a serial to parallel converter receiving an radio frequency signal, a fast Fourier transform device connected to said serial to parallel converter converting N | 2012-07-19 |
| 20120182858 | TERMINAL DEVICE AND RETRANSMISSION CONTROL METHOD - Provided are a terminal device and a retransmission control method that make it possible to minimize increases in overhead in an uplink control channel (PUCCH), even if channel selection is used as the method to transmit response signals during carrier-aggregation communication using a plurality of downlink unit bands. On the basis of the generation status of uplink data and error-detection results obtained by a CRC unit ( | 2012-07-19 |
| 20120182859 | PACKET RESTORATION METHOD, PACKET RESTORATION SYSTEM, AND MOBILE TERMINAL AND INTERMEDIATE DEVICE USED IN THE METHOD - The present invention discloses a technique for providing a packet recovery method, and the like, capable of starting packet recovery processing without waiting for a wasteful latency (time-out) at a mobile terminal by giving notice of information on a packet discard in a gateway device in real time, thereby enabling improvement in communication quality and communication efficiency. According to the technique, there is provided a packet recovery method for recovering a packet discarded by an intermediate device positioned on a communication path between a mobile terminal and a correspondent node of the mobile terminal among packets exchanged between the mobile terminal and correspondent node, the method including: a step of causing the intermediate device to transmit a discard notification message to the mobile terminal based on information on a communication flow for which transmission of the discard notification message indicating that the packet has been discarded is required; and a step of causing the mobile terminal to transmit the correspondent node a retransmission request message for requesting retransmission of the discarded packet based the discard notification message. | 2012-07-19 |
| 20120182860 | METHOD AND APPARATUS FOR HOP-BY-HOP RELIABLE MULTICAST IN WIRELESS NETWORKS - A method and apparatus are described including performing hop-by-hop multicasting including network coding of data packets of a portion of content, wherein network coding further includes encoding data packets of a portion of content, multicasting said network coded data packets to downstream receivers, determining if an acknowledgement message has been received from at least one of the downstream receivers, determining if acknowledgement messages have been received from all of the downstream receivers responsive to the first determination. | 2012-07-19 |
| 20120182861 | METHOD AND MEANS FOR STATE TRANSITION OF ETHERNET LINEAR PROTECTION SWITCHING - The present invention relates to state transition, especially relates to method and means for state transition of Ethernet linear protection switching. It is provided a method of state transition for a local end of a protection group of Ethernet linear protection switching in a local network element, and the method comprises receiving a first message configured to change the state of the local end with a first state, the first message being overridden by the first state; receiving a second message configured to change the state of the local end; determining a second state of the local end on the basis of the first message and the second message; and changing the state of the local end into the second state. In this way, there will be no unnecessary state transition and then no traffic loss caused by the unnecessary state transition. | 2012-07-19 |
| 20120182862 | Method and Apparatus for Improving Data Integrity During a Router Recovery Process - An apparatus and method for enhancing data integrity during router recovery using dual-homed host configuration are disclosed. A process of routing resumption, in one embodiment, is able to recover or reset a network element (“NE”) such as a primary router from system failure. A first link configured to transmit data packets between the NE and a network device is reestablished. Upon reestablishing a second link configured to transmit data packets between the NE and other NEs, a network discovery process utilizing network reachability protocol is initiated to identify routing paths associated with the NE. A routing table in the NE is updated in accordance with the routing paths. A ready message is issued from the NE to the network device when the routing table is at least partially completed. | 2012-07-19 |
| 20120182863 | PROTOCOL FOR CLOCK DISTRIBUTION AND LOOP RESOLUTION - In response to a network topology change, a clock root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to the network node from a clock source of higher or equal stratum relative to that network node. The root node then sends a network message to each node indicating the new path that the node should use. Each node receives the message and compares the new path with the existing path. If the paths are different then the node acquires the new path just received in the message. If the paths are the same then the node does nothing and discards the message. | 2012-07-19 |
| 20120182864 | SYSTEM AND METHOD FOR LOAD BALANCING NETWORK RESOURCES USING A CONNECTION ADMISSION CONTROL ENGINE - A system and method for load balancing network resources. Network performance information regarding data flow through a network is gathered using performance information packet data packets. The data flow is distributed through access points of the network using connection control admission control engines. The distributing includes routing the data flow to more efficiently use the network resources based on the PIP data packets. | 2012-07-19 |
| 20120182865 | Systems, Methods, and Apparatuses for Managing the Flow of Traffic in Data Networks - Methods or systems for management and/or optimization of at least a portion of a data network by generating a set of paths between each origin and destination pair, pruning the set of paths to generate a pruned set of paths; and computing an optimum path between each origin and destination pair. Methods and systems for generating a diverse set of path options for the routing of traffic within at least a portion of a network comprising: generating a set of paths between each origin and destination pair; and pruning the set of paths to generate a pruned set of diverse path options within at least a portion of a network. | 2012-07-19 |
| 20120182866 | SYSTEM AND METHOD FOR VIRTUAL FABRIC LINK FAILURE RECOVERY - Aggregation switches are connected to an edge node by a multi-chassis link aggregation group and a virtual fiber link provides a connection for exchange of information between the aggregation switches regarding MAC addressing to synchronize MAC address tables across the aggregation switches. When failure of the virtual fiber link is detected, the multi-chassis link aggregation group is reconfigured into two or more link aggregates with each link aggregate connecting the edge node to one of the aggregation switches. A spanning tree protocol is initiated over the link aggregates to prevent loops in the network. MAC address tables are flushed and relearned with the two or more link aggregates. | 2012-07-19 |
| 20120182867 | Adaptive Medium Access Control - Bandwidth allocation configuration and fully decentralized adaptive medium access control (AMAC) systems and methods with support for time critical applications, spectrum efficiency, scalability enhancements, and fair allocation of bandwidth among nodes sharing a common channel. The methods fully integrate TDMA and CSMA/CA channel access approaches and incorporate adaptive congestion and collisions avoidance scheme to reduce bandwidth wastage and diminish adverse cross layers interactions. AMAC improves support for multi-media traffic while allowing higher transmission incidents from large number of transmitting devices sharing a common channel, with fair distribution of the available bandwidth, to enable improved multi-level-security connectivity over a common multi-hop wireless network, provide end-to-end performance enhancement for constant bit rate traffic, variable bit rate traffic, and distribute bandwidth fairly amongst competing TCP traffic flows that traverse varying length paths in multi-hop ad-hoc wireless networks. | 2012-07-19 |
| 20120182868 | Multiple Bearer Support Upon Congestion Situations - The embodiments herein relates to a method for enabling multiple bearer support upon congestion situations in a communication network. The PCC architecture is enabled to determine whether separate bearers need to be established for service(s) that demand MBR>GBR when no ECN support is provided. This is provided in nodes and methods receiving, using a receiving unit ( | 2012-07-19 |
| 20120182869 | MOBILE COMMUNICATION METHOD AND MOBILE STATION - A mobile communication system according to the present invention includes: a step A in which a radio base station eNB notifies a mobile station UE of a predetermined range; a step B in which the mobile station UE receives an uplink scheduling grant (uplink scheduling) including CB-RNTI (predetermined identification information that is not identification information of a designated mobile station), within the notified predetermined range; and a step C in which the mobile station UE transmits an uplink data signal, by using a shared uplink resource designated by the uplink scheduling grant, to the radio base station eNB. | 2012-07-19 |
| 20120182870 | System And Method For Implementing Periodic Early Discard In On-Chip Buffer Memories Of Network Elements - An advance is made over the prior art in accordance with the principles of the present invention that is directed to a new approach for a system and method for a buffer management scheme called Periodic Early Discard (PED). The invention builds on the observation that, in presence of TCP traffic, the length of a queue can be stabilized by selection of an appropriate frequency for packet dropping. For any combination of number of TCP connections and distribution of the respective RTT values, there exists an ideal packet drop frequency that prevents the queue from over-flowing or under-flowing. While the value of the ideal packet drop frequency may quickly change over time and is sensitive to the series of TCP connections affected by past packet losses, and most of all is impossible to compute inline, it is possible to approximate it with a margin of error that allows keeping the queue occupancy within a pre-defined range for extended periods of time. The PED scheme aims at tracking the (unknown) ideal packet drop frequency, adjusting the approximated value based on the evolution of the queue occupancy, with corrections of the approximated packet drop frequency that occur at a timescale that is comparable to the aggregate time constant of the set of TCP connections that traverse the queue. | 2012-07-19 |
| 20120182871 | LOAD BALANCING IN A DOCSIS SYSTEM BASED ON WEIGHTING UPSTREAM AND DOWNSTREAM CHANNEL LOADING CONDITIONS - Methods and apparatuses for balancing a network load are provided. A control attribute that allows a system operator to prioritize upstream and downstream channel loading conditions relative to each other for load balancing decisions is used to balance the network load. | 2012-07-19 |
| 20120182872 | METHODS FOR PACKET FORWARDING THROUGH A COMMUNICATION LINK OF A DISTRIBUTED LINK AGGREGATION GROUP USING MESH TAGGING - A method for packet forwarding through a communication link of a distributed link aggregation group (LAG) in a mesh network using a path tag is described herein. A packet is received on a non-mesh port of a first network device of the mesh network. A Media Access Controller (MAC) destination address of the packet that is associated with a plurality of network devices in the mesh is determined. Each network device of the plurality of network devices includes a link grouped in the distributed LAG. A destination mesh device from the plurality of network devices is selected. A plurality of available paths between the first network device and the destination mesh device are determined. A path of the plurality of available paths is selected. A tag associated with the selected path is inserted into the packet, and the packet is forwarded along the selected path. | 2012-07-19 |
| 20120182873 | System and method for tree assessment - Tree assessment systems and methods are disclosed. An example of a method includes building a system tree in computer-readable medium, the system tree having a plurality of nodes, each node in the system tree representing a characteristic of a component of a system under consideration. The method also includes comparing nodes of the system tree stored in computer-readable medium, with nodes in other trees to identify at least one similar node for identifying similar trees. The method also includes extracting extracting a most similar tree from the similar trees based on the at least one similar node. The method also includes assigning characteristics from the most similar tree to the system tree. | 2012-07-19 |
| 20120182874 | Method and Apparatus for Compensating Signal Timing Measurements for Differences in Signal Frequencies | 2012-07-19 |
| 20120182875 | COGNITIVE MULTI-USER OFDMA - A computing device operating according to a frequency division multiplexed protocol in which communication occurs over a signal formed from a plurality of sub-channels selected from anywhere in a frequency spectrum. A computing device may select sub-channels cognitively by using information about sub-channels previously deemed suitable or unsuitable by that computing device or other computing devices. A described technique for determining sub-channel suitability includes analyzing radio frequency energy in the sub-channel to detect signals generated by another computing device or high noise levels. Information may also be used to cognitively select sub-channels to be analyzed, such as by first selecting for analysis previously-used sub-channels. | 2012-07-19 |
