28th week of 2011 patent applcation highlights part 43 |
Patent application number | Title | Published |
20110171735 | Apparatus and Methods for Effecting Chemical Assays - There is disclosed apparatus and a system for effecting testing on a sample, such as for medical testing. The apparatus includes a sample chip ( | 2011-07-14 |
20110171736 | FLUORESCENT ISOTOPE TAGS AND THEIR METHOD OF USE - The present invention provides novel reactive fluorescent compounds that incorporate stable isotopic (deuterium, 13-carbon, 15-nitrogen, 18-oxygen) substitutions. The invention includes the use of these compounds, in combination with non-isotopically substituted analogs, for the purification, identification and relative quantification of proteins, peptides, saccharides, metabolites, and other biologically important compounds by combining liquid chromatography (LC) and mass spectrometry (MS). Fluorescent labeling of target compounds in this manner provides orders-of-magnitude sensitivity enhancement over traditional stable isotope labels, and also affords the possibility of simultaneous multiplexed analysis due to the multiwavelength nature of different fluorophores. | 2011-07-14 |
20110171737 | PROTEIN ENGINEERING - Methods of optimizing mRNA sequences for expression in host cells are provided. Methods of determining the stability of a protein are also provided. Methods of determining the affinity of a ligand for a protein are also provided. | 2011-07-14 |
20110171738 | METHOD FOR ESTIMATING THE AMOUNT OF IMMOBILIZED PROBES AND USE THEREOF - The present invention provides a method for estimating an amount of immobilized probes, including the successive steps of: providing a sample on a substrate to form one or more spots of the sample on the substrate, the sample containing particulate substances and probes in a predetermined ratio, the probes being reactive with a predetermined target; measuring the number of the particulate substances contained in at least one of the spots; and estimating the amount of the probes contained in the at least one of the spots from the thus measured number of the particulate substances. | 2011-07-14 |
20110171739 | LIGANDS FOR AGGREGATED TAU MOLECULES - Provided are certain benzothiazole, imidazothiazole, imidazopyrimidine and imidazopyridine compounds, including, for example: formula (I) and pharmaceutically and physiologically acceptable salts, hydrates, and solvates thereof. Such compounds can be used as diagnostic ligands or labels of tau protein and PHF. | 2011-07-14 |
20110171740 | BIOASSAYS BASED ON POLYMERIC SEQUENCE PROBE - Polymeric sequence probes and methods are described that enhance the speed and sensitivity of detection of target analytes by combining a multiplicity of binding moieties specific for analyte, at least two of which are linearly arranged and optionally a multiplicity of detectable labels. | 2011-07-14 |
20110171741 | DNA INTEGRITY ASSAY (DIA) FOR CANCER DIAGNOSTICS, USING CONFOCAL FLUORESCENCE SPECTROSCOPY - The present invention relates, e.g., to a method for determining the size distribution of DNA molecules in a sample comprising cell-free nucleic acid, comprising labeling the DNA with a fluorescent dye in a stoichiometric manner, subjecting the DNA to molecular spectroscopy (e.g., cylindrical illumination confocal spectroscopy), analyzing suitable fluorescent burst parameters of the labeled DNA, and conducting single molecule DNA integrity analysis of the labeled DNA molecules in the sample. In one embodiment of the invention, the method is used as a diagnostic method for detecting cancer. | 2011-07-14 |
20110171742 | PYRIDINIUM BORONIC ACID QUENCHERS FOR USE IN ANALYTE SENSORS - Novel pyridinium salts functionalized with boronic acid and methods of making them are disclosed. When combined with a fluorescent dye, the compounds are useful in the detection of polyhydroxyl-substituted organic molecules. | 2011-07-14 |
20110171743 | DETECTION OF HALOGENS - A method of measuring the concentration of a halogen in a gas stream using measurement means unsuitable for the direct measurement of halogens in a gas stream, comprising the step of passing a gaseous conversion compound to the halogen containing gas stream to convert the halogen to a detectable gaseous compound. | 2011-07-14 |
20110171744 | DISPENSING DEVICE - Provided is a dispensing device capable of removing bubbles reliably. In this dispensing device, deaerated water is fed by a water feed pump to the inside of a pipeline up to the vicinity of the leading end of a dispensing nozzle. A water feed valve disposed near a dispensing pump is closed to establish a deaerated water space opened on the leading end side of the dispensing nozzle. The dispensing pump is activated on the space, thereby causing the dispensing nozzle to perform suction and exhaust actions. The dispensing device comprises a vacuum means connected to the space through the water feed valve thereby maintaining a vacuum state. In case the deaerated water space is cleared of the bubbles, the cleared water space is brought, by opening a change-over valve, into communication with a pipeline having a vacuum means connected thereto, thereby bringing the space into the vacuum state. | 2011-07-14 |
20110171745 | HALOGEN AND HEAVY METAL-FREE HUMIDITY INDICATING COMPOSITION AND HUMIDITY INDICATOR CARD CONTAINING THE SAME - The disclosed invention is a humidity indicating composition comprising
| 2011-07-14 |
20110171746 | Variable Penetration Depth Biosensor Methods - A surface plasmon resonance sensor system including a high refractive index prism, a sensor chip, a light source having multiple wavelengths over a broad range of wavelengths, optical lenses, a photodetector, a data acquisition unit, and as defined herein. The sensor chip can include, for example, a thin layer of silicon and gold on one face of a transparent substrate and the prism adjacent to the opposite face of the transparent substrate. Such an arrangement provides variable penetration depths up to about 1.5 micrometers with a dynamic range for sensing index of refraction changes in a sample that are several times greater than that of a conventional SPR sensor. The disclosure provides methods for using the surface plasmon resonance sensor system for cell assay or chemical assay related applications. | 2011-07-14 |
20110171747 | BACTERIORHODOPSIN-BASED PHOTOCHROMIC SENSOR FOR DETECTION OF CHEMICAL AND ENVIRONMENTAL TOXINS - A bacteriorhodopsin based chemical sensing architecture based upon the collective response of bacteriorhodopsin and a number of its mutants; the wild type protein and a selection of genetically-engineered variants was able to respond differentially to a selection of amines. The observable response to the presence of a target chemical was manifested through a modulation of bacteriorhodopsin's photokinetic properties, which are monitored through pump-probe techniques using a custom prototype flash photolysis system. Differential responsivity exists at two levels; (1) bacteriorhodopsin proteins (wild-type and genetically-engineered variants) respond differentially upon exposure of a target chemical, and (2) the response pattern exhibited by the proteins differs from chemical to chemical. This dichotomy forms the basis for a BR-mediated chemical sensing technology that is highly sensitive and selective and may therefore discriminate between different chemicals. | 2011-07-14 |
20110171748 | Device And Method For Making Discrete Volumes Of A First Fluid In Contact With A Second Fluid, Which Are Immiscible With Each Other - Various embodiments described in the application relate to an apparatus, system, and method for generating, within a conduit, discrete volumes of one or more fluids that are immiscible with a second fluid. The discrete volumes can be used for biochemical or molecular biology procedures involving small volumes, for example, microliter-sized volumes, nanoliter-sized volumes, or smaller. The system can comprise an apparatus comprising at least one conduit operatively connected to one or more pumps for providing discrete volumes separated from one another by a fluid that is immiscible with the fluid(s) of the discrete volumes, for example, aqueous immiscible-fluid-discrete volumes separated by an oil. | 2011-07-14 |
20110171749 | NANOPARTICLE TRACER-BASED ELECTROCHEMICAL DNA SENSOR FOR DETECTION OF PATHOGENS-AMPLIFICATION BY A UNIVERSAL NANO-TRACER (AUNT) - The present invention relates to methods and compositions for identifying a pathogen. The inventions provide an antibody-based biosensor probe comprising (AUNT) in combination with a polymer-coated magnetic nanoparticle. In particular, a nanoparticle-based biosensor was developed for detection of | 2011-07-14 |
20110171750 | MARKER FOR GRAFT FAILURE AND MORTALITY - Subject of the present invention is a biomarker for graft failure and/or mortality after organ transplantation. Procalcitonin was found to be a useful marker for the prediction or risk stratification for graft failure and/or mortality of a subject who has received an organ transplant and monitoring and therapy guidance of such subject. | 2011-07-14 |
20110171751 | RECOMBINANT POLYPEPTIDES FOR DIAGNOSING INFECTION WITH TRYPANOSOMA CRUZI - Recombinant polypeptides are disclosed that are useful for diagnosing American trypanosomiasis, or Chagas disease, a disease caused by the infectious agent | 2011-07-14 |
20110171752 | Methods and Systems for Detecting MHC Class I binding peptides - The present invention is based on the discovery that MHC heavy chain monomers immobilized to a solid surface are still capable of forming detectable conformational epitopes and being detected by conformation-dependent antibodies. Methods for detecting peptide binding to HLA monomers, and methods for measuring the relative degree of binding between two MHC-binding peptides as well as a method of measurement for the rate of dissociation of peptides from MHC complexes are provided. The present invention also provides systems and kits useful for conducting the methods of the present invention. | 2011-07-14 |
20110171753 | MODIFIED ANTI-HEPARIN/PF4 COMPLEX ANTIBODY AND HIT ANTIBODY STANDARD - Provided is a modified antibody which enables the quantitative measurement of the amount of a heparin/PF4 complex, an onset factor of heparin-induced trombocytopenia (HIT), without the influence of the presence of PF4, and which can be used as an HIT antibody standard specific for the heparin/PF4 complex. The modified antibody is prepared by linking a human IgG, or an antibody fragment derived from a human IgG, to a monoclonal antibody obtained by immunizing an animal (excluding a human) with the heparin/PF4 complex. | 2011-07-14 |
20110171754 | ANALYSIS SYSTEM - An analysis system comprises a sampling cartridge ( | 2011-07-14 |
20110171755 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE HAVING MEMORY ELEMENT WITH PROTECTIVE FILM - To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH | 2011-07-14 |
20110171756 | REWORKABLE ELECTRONIC DEVICE ASSEMBLY AND METHOD - An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts. | 2011-07-14 |
20110171757 | METHOD OF MANUFACTURING PHOTOVOLTAIC CELL - Provided is a method of manufacturing a photovoltatic cell according to the present invention, the photovoltatic cell including a substrate, and a structure in which a first conductive layer, a photoelectric conversion layer and a second conductive layer are superposed on the substrate in this order; the structure is electrically separated by a predetermined size to form a plurality of compartment elements; and the compartment elements adjacent to each other are electrically connected to each other, the method including: a defect region specifying step of specifying a region in which a structural defect exists from the plurality of compartment elements; and a repairing step of irradiating the region or the periphery thereof with a laser beam to remove the structural defect, wherein the repairing step includes a step α of irradiating the structure with a first laser to remove or separate the region, and a step β of irradiating an end portion of the structure generated by the removal or separation with a second laser to clean the end portion, and wherein the second laser uses a laser obtained by defocusing the first laser so that a focus position thereof is away from the substrate. | 2011-07-14 |
20110171758 | RECLAMATION OF SCRAP MATERIALS FOR LED MANUFACTURING - A method for reclamation of scrap materials during the formation of Group III-V materials by metal-organic chemical vapor deposition (MOCVD) processes and/or hydride vapor phase epitaxial (HVPE) processes is provided. More specifically, embodiments described herein generally relate to methods for repairing or replacing defective films or layers during the formation of devices formed by these materials. By periodic testing of the layers during the formation process, low-quality layers that may result in low-quality or defective devices may be detected prior to completion of the device. These low-quality layers may be partially or completely removed and redeposited to reclaim the substrate and any remaining high-quality layers that were previously deposited under the low-quality layer. | 2011-07-14 |
20110171759 | Lithographic Apparatus and Device Manufacturing Method - Data from the piezo-electric sensors in the mounts for the projection system can be used in the control loops for other parts of the lithographic apparatus, for example the mask table, the substrate table or the air mounts for the frame bearing the projection system. Information from, for example, a geophone, which is used to measure the absolute velocity of the frame bearing the projection system, can be used in the control loop for the piezo-electric actuator in the mount for the projection system. | 2011-07-14 |
20110171760 | Method for manufacturing thin film transistor and display device - A method for manufacturing a thin film transistor includes: forming a source electrode and a drain electrode on a substrate by depositing a metal layer on the substrate at a first temperature and etching the metal layer; forming a protective layer on the source and drain electrodes; and performing a heat treatment on the protective layer at a second temperature higher than the first temperature. | 2011-07-14 |
20110171761 | METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE WITH FLUORESCENT LAYER - A method of manufacturing a light-emitting device includes disposing a light-emitting element on a supporting member, dispersing a fluorescent substance having a particle diameter of 20 to 45 μm in a material of the light-transmitting member at a concentration of 40 to 60 wt %, dripping raw material for the fluorescent layer on the light-emitting element while lowering the viscosity of the raw material, and thermally curing the coated layer. | 2011-07-14 |
20110171762 | Phosphor-Converted LED - A light source and method for fabricating the same are disclosed. The light source includes a die, a light conversion component, and a scattering ring. The die emits light of a first wavelength through a top surface of the die and one or more side surfaces of the die, and is bonded to a mounting substrate. The light conversion component converts light of the first wavelength to light of a second wavelength, the light conversion component having a bottom surface bonded to the top surface of the die. The light conversion component has lateral dimensions such that a space exists around the die, the space being bounded by the substrate and the light conversion component. The scattering ring is positioned in the space such that a portion of the light emitted from the side surfaces of the die is scattered into the light conversion component. | 2011-07-14 |
20110171763 | METHOD OF FORMING ORGANIC THIN FILM PATTERN AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY DEVICE BY USING THE METHOD OF FORMING ORGANIC THIN FILM PATTERN - A method of manufacturing an organic thin film pattern, the method including: forming a dummy organic thin film on a substrate; radiating light on the dummy organic thin film pattern the dummy organic thin film; forming a main organic thin film, having a sublimation temperature is higher than that of the dummy organic thin film, on the substrate and the patterned dummy organic thin film; and heating patterned the dummy organic thin film and the main organic thin film, to sublimate the dummy organic thin film and thereby pattern the main organic thin film. | 2011-07-14 |
20110171764 | ENCAPSULATED ELECTRONIC DEVICE AND METHOD OF MANUFACTURING - An encapsulated electronic device is described comprising:
| 2011-07-14 |
20110171765 | MULTI-FIELD ARRANGING METHOD OF LED CHIPS UNDER SINGLE LENS - A multi-field arranging method of LED chips under a single lens includes the steps of: setting a first concentric circle on a bottom of a hemispherical lens, wherein the first concentric circle is centered at an axis of the hemispherical lens; and equidistantly arranging at least one first color chip, at least one second color chip and at least one third color chip on the first concentric circle in sequence. The present invention allows the color chips to present symmetrical light patterns through the hemispherical lens, thereby obtaining a light field with evener color mixture. | 2011-07-14 |
20110171766 | LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a liquid crystal display (LCD) device and a method for manufacturing the same, capable of maintaining a cell gap and preventing press defects caused by application of a predetermined external pressure via the use of ball spacers. | 2011-07-14 |
20110171767 | MANUFACTURING METHOD FOR A THIN FILM TRANSISTOR-LIQUID CRYSTAL DISPLAY - A pixel unit of TFT-LCD array substrate and a manufacturing method thereof is disclosed. In the manufacturing method, besides a first insulating layer and a passivation layer, a second insulating layer is adopted to cover the gate island, and forms an opening on the gate island to expose the channel region, the source region and the drain region of the TFT. A gray tone mask and a photoresist lifting-off process are utilized to perform patterning, so that the TFT-LCD array substrate can be achieved with just three masks. | 2011-07-14 |
20110171768 | MASK FRAME ASSEMBLY FOR THIN LAYER DEPOSITION AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICE BY USING THE MASK FRAME ASSEMBLY - A mask frame assembly for thin film deposition includes a frame including an opening portion, and a plurality of unit mask strips that are fixed to the frame after a tensile force is applied to both of end portions of the unit mask strips in a lengthwise direction of the unit mask strips. Each of the plurality of unit mask strips includes a plurality of unit masking pattern portions each including a plurality of opening patterns. Before the tensile force is applied to both of the end portions of the unit mask strips in the lengthwise direction and the unit mask strips are fixed to the frame, a width of each of the unit masking pattern portions in a widthwise direction perpendicular to the lengthwise direction increases as a function of a closeness of a portion of the unit masking pattern portion where the width is measured to a central portion of each of the unit masking pattern portions. | 2011-07-14 |
20110171769 | LASER MASK AND CRYSTALLIZATION METHOD USING THE SAME - A crystallization method includes providing a substrate having a silicon thin film; positioning a laser mask having first to fourth blocks on the substrate, each block having a periodic pattern including a plurality of transmitting regions and a blocking region; and crystallizing the silicon thin film by irradiating a laser beam through the laser mask. A polycrystalline silicon film crystallized by this method is substantially free from a shot mark, and has uniform crystalline characteristics. | 2011-07-14 |
20110171770 | MANUFACTURING METHOD OF A PHOTOELECTRIC CONVERSION DEVICE - A manufacturing method of a photoelectric conversion device included a first step of forming a gate electrode, a second step of forming a semiconductor region of a first conductivity type, a third step of forming an insulation film, and a fourth step of forming a protection region of a second conductivity type, which is the opposite conductivity type to the first conductivity type, by implanting ions in the semiconductor region using the gate electrode of the transfer transistor and a portion covering a side face of the gate electrode of the transfer transistor of the insulation film as a mask in a state in which the semiconductor substrate and the gate electrode of the transfer transistor are covered by the insulation film, and causing a portion of the semiconductor region of the first conductivity type from which the protection region is removed to be the charge accumulation region. | 2011-07-14 |
20110171771 | Method for Producing a Photovoltaic Module - A method for producing a photovoltaic module by forming solar cells on a glass plate and contacting at least one layer of liquid encapsulant with the solar cells. The liquid encapsulant has two components. The first component is an acrylic polyol having an average number of hydroxy-functional monomer units per polymer chain from 2 to 25 and Mn from 1,000 to 10,000. The second component is a polyisocyanate with an average functionality of at least two. The molar ratio of non-terminal hydroxy groups in the polyol to isocyanate groups in the polyisocyanate is from 0.5:1 to 1:0.5. | 2011-07-14 |
20110171772 | Method for Producing a Photovoltaic Module - A method for producing a photovoltaic module by contacting at least one layer of liquid encapsulant and a plurality of solar cells. The liquid encapsulant has two components. The first component is an acrylic polyol having a terminal hydroxy group, an average number of hydroxy-functional monomer units per polymer chain from 2 to 25 and Mn from 1,000 to 10,000. The second component is an aliphatic polyisocyanate with an average functionality of at least two. The molar ratio of non-terminal hydroxy groups in the polyol to isocyanate groups in the aliphatic polyisocyanate is from 0.5:1 to 1:0.5. | 2011-07-14 |
20110171773 | Method for Making a Planar Concentrating Solar Cell Assembly with Silicon Quantum Dots - Disclosed is a method for making a silicon quantum dot planar concentrating solar cell. At first, silicon nitride or silicon oxide mixed with silicon quantum dots is provided on a transparent substrate. By piling, there is formed a planar optical waveguide for concentrating sunlit into a small dot cast on a small solar cell. | 2011-07-14 |
20110171774 | CLEANING OPTIMIZATION OF PECVD SOLAR FILMS - Embodiments of the present invention generally provide a method for forming a plurality of thin film single or multi-junction solar cell in a substrate processing chamber. In one embodiment, a method for processing a plurality of thin film solar cell substrates includes depositing sequentially a first undoped layer and a first doped layer over a surface of a first substrate and a chamber component in a single processing chamber, removing the substrate having the doped and undoped layers from the processing chamber, removing the second doped layer deposited on the chamber component to expose underlying first undoped layer which serves as a seasoning layer for a second substrate to be processed in the processing chamber, and depositing sequentially a second undoped layer and a second doped layer on the second substrate in the processing chamber. In one example, the first undoped layer is amorphous silicon or microcrystalline silicon. A full cleaning process may be performed at desired intervals to expose the surfaces of the chamber component before a regular seasoning process and the subsequent depositions are proceeded in the processing chamber. | 2011-07-14 |
20110171775 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first insulating film over an underlying film by plasma polymerization of cyclic siloxane, and forming a second insulating film on the first insulating film by plasma polymerization of the cyclic siloxane continuously, after forming the first insulating film. The deposition rate of the first insulating film is slower than the deposition rate of the second insulating film. | 2011-07-14 |
20110171776 | IC CHIP, ANTENNA, AND MANUFACTURING METHOD OF THE IC CHIP AND THE ANTENNA - An antenna used for an ID chip or the like is disclosed with planarized antenna unevenness and an IC chip having such the antenna with a flat surface is disclosed. Manufacturing an integrated circuit mounted with an antenna is facilitated. A laminated body formed by stacking a conductive film | 2011-07-14 |
20110171777 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Chip cracking that occurs when a dicing step using a blade is carried out to acquire semiconductor chips with the reduced thickness of a semiconductor wafer is suppressed. When the semiconductor wafer is cut at the dicing step for the semiconductor wafer, a blade is advanced as follows: in dicing in a first direction (Y-direction in FIG. | 2011-07-14 |
20110171778 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like. | 2011-07-14 |
20110171779 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A BGA substrate which has a back surface to which a heat radiating plate is attached and an opening for accommodating a relay wiring substrate therein, which is provided in the center of its surface, is used. The relay wiring substrate to which an ASIC chip and a memory chip are flip-chip connected, is bonded to the heat radiating plate in the opening with a thermal conductive bonding material. Further, each of the back surfaces of the ASIC chip and the memory chip is connected to a metal cap for sealing the opening through a thermal conductive material interposed therebetween. | 2011-07-14 |
20110171780 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Of three chips ( | 2011-07-14 |
20110171781 | METHOD OF FABRICATING A 3-D DEVICE - A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern. | 2011-07-14 |
20110171782 | METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE HAVING A GROUND PLANE - A method of placing a die includes providing an embedded plane. The embedded plane has a openings, grid lines, and protruding portions. Each of the plurality of openings are surrounding by a subset of the plurality of grid lines. At least one of the protruding portions extends into one of the openings. A die is placed into one of the openings and at least one of the protruding portions bends during such placement so that it is in contact with at least a portion of a minor surface of the die. | 2011-07-14 |
20110171783 | METHOD FOR MAKING CONTACTLESS PORTABLE OBJECTS - The invention relates to a method for manufacturing contactless portable objects with an integrated circuit. The method of the invention is characterized in that it comprises the steps of: providing a silicon wafer ( | 2011-07-14 |
20110171784 | SUBASSEMBLY THAT INCLUDES A POWER SEMICONDUCTOR DIE AND A HEAT SINK HAVING AN EXPOSED SURFACE PORTION THEREOF - The semiconductor assembly includes a first subassembly having a heat sink. Solder material is disposed on the exposed portion of a first surface of heat sink. A power semiconductor die is located on the first surface of the heat sink and is thermally coupled thereto by the solder material. A packaging patterned polymer layer is disposed on a second surface of the heat sink opposing the first surface and defines an interior surface portion of the heat sink. A semiconductor package is provided in which the first subassembly, solder material and die are located such that the interior surface portion of the second surface of the heat sink is not enclosed by the semiconductor package. | 2011-07-14 |
20110171785 | METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND AN INVERTED CAVITY IN THE BUMP - A method of making a semiconductor chip assembly includes providing a bump and a ledge, mounting an adhesive on the ledge including inserting the bump into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the bump with an aperture in the conductive layer, then flowing the adhesive between the bump and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, then mounting a semiconductor device on the bump opposite a cavity in the bump, wherein a heat spreader includes the bump and a base that includes a portion of the ledge adjacent to the bump, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader. | 2011-07-14 |
20110171786 | Mold resin sealing device and molding method - A mold resin sealing device for sealing a surface of a semiconductor wafer with a mold resin, includes: a first mold die; and a second mold die disposed opposite to the first mold die, the second mold die having a second surface; wherein the first mold die includes a first part having a first surface facing the second surface of the second mold die and having an opening in a central region of the first surface; and a first step-like movable part capable of moving in the opening in both directions so that the first step-like movable part moves toward and away from the second mold die. | 2011-07-14 |
20110171787 | MULTIPLE-LAYER NON-VOLATILE MEMORY DEVICES, MEMORY SYSTEMS EMPLOYING SUCH DEVICES, AND METHODS OF FABRICATION THEREOF - In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs. | 2011-07-14 |
20110171788 | Fabrication of Field Effect Devices Using Spacers - A method for forming a field effect device includes forming a gate portion on a silicon-on-insulator layer (SOI), forming first spacer members on the SOI layer adjacent to the gate portion, depositing a layer of spacer material on the SOI layer, the first spacer members, and the gate portion, removing portions of the layer of spacer material to form second spacer members on the SOI layer adjacent to the first spacer members, forming a source region and a drain region on the SOI layer by implanting ions in the SOI layer, and etching to remove the second spacer members. | 2011-07-14 |
20110171789 | LIGHT-EMITTING NANOPARTICLES AND METHOD OF MAKING SAME - A method for the production of a robust, chemically stable, crystalline, passivated nanoparticle and composition containing the same, that emit light with high efficiencies and size-tunable and excitation energy tunable color. The methods include the thermal degradation of a precursor molecule in the presence of a capping agent at high temperature and elevated pressure. A particular composition prepared by the methods is a passivated silicon nanoparticle composition displaying discrete optical transitions. | 2011-07-14 |
20110171790 | Selective Floating Body SRAM Cell - A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed. | 2011-07-14 |
20110171791 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A single crystal semiconductor substrate including an embrittlement layer is attached to a base substrate with an insulating layer interposed therebetween, and the single crystal semiconductor layer is separated at the embrittlement layer by heat treatment; accordingly, a single crystal semiconductor layer is fixed over the base substrate. The single crystal semiconductor layer is irradiated with a laser beam so that the single crystal semiconductor layer is partially melted and then is re-single crystallized, whereby crystal defects are removed. In addition, an island-shaped single crystal semiconductor layer for forming an n-channel transistor is channel-doped using a photomask and then is etched back using the photomask so that the island-shaped single crystal semiconductor layer for forming an n-channel transistor is thinner than the island-shaped single crystal semiconductor layer for forming a p-channel transistor. | 2011-07-14 |
20110171792 | BACK-GATED FULLY DEPLETED SOI TRANSISTOR - A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner. | 2011-07-14 |
20110171793 | LIQUID CRYSTAL DISPLAY DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a display includes providing a first substrate divided into a pixel part and first and second pad parts, forming a gate electrode and a gate line in the pixel part of the first substrate and forming a gate pad line in the first pad part of the first substrate, forming a first insulation film and a semiconductor film over the gate electrode, the gate line and the gate pad line, forming an active pattern over the gate electrode from the semiconductor film with the first insulation film interposed therebetween and forming a contact hole exposing a portion of the gate pad line using a single mask, forming source and drain electrodes in the pixel part, forming a pixel electrode in the pixel part, forming a gate pad electrode electrically connected with the gate pad line via the contact hole, forming a second insulation film over the pixel electrode and the gate pad electrode, exposing a portion of the pixel electrode and at least one portion of the gate pad electrode, and attaching the first substrate and a second substrate. | 2011-07-14 |
20110171794 | TRANSISTOR FORMATION USING CAPPING LAYER - A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures is provided, the method including: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET); depositing a capping layer directly over the conductive layer; etching the capping and conductive layers to form a capped gate conductor to gates of the nFET and pFET, respectively; ion-implanting the nFET transistor with a first dopant; and ion-implanting the pFET transistor with a second dopant, wherein ion-implanting a transistor substantially dopes its source and drain regions, but not its gate region. | 2011-07-14 |
20110171795 | FinFET LDD and Source Drain Implant Technique - A method of forming an integrated circuit includes providing a semiconductor wafer; and forming a fin field-effect transistor (FinFET) including implanting the semiconductor wafer using a hot-implantation to form an implanted region in the FinFET. The implanted region comprises a region selected from the group consisting essentially of a lightly doped source and drain region, a pocket region, and a deep source drain region. | 2011-07-14 |
20110171796 | VERTICAL WRAP-AROUND-GATE FIELD-EFFECT-TRANSISTOR FOR HIGH DENSITY, LOW VOLTAGE LOGIC AND MEMORY ARRAY - A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning. | 2011-07-14 |
20110171797 | NAND FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings. | 2011-07-14 |
20110171798 | LDMOS WITH SELF ALIGNED VERTICAL LDD BACKSIDE DRAIN - A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region. | 2011-07-14 |
20110171799 | METHOD OF FORMING POWER MOSFET - A method of forming a power MOSFET is described. An epitaxial layer of first conductivity type is formed on a substrate of first conductivity type. A body layer of second conductivity type is formed in the epitaxial layer. A plurality of mask patterns are formed on the substrate. A plurality of trenches are formed in the body layer and the epitaxial layer between the mask patterns. An oxide layer is formed on surfaces of the trenches. A conductive layer is formed in the trenches. A trimming process is performed to the mask patterns to reduce the line width of each mask pattern. Two source regions of first conductivity type are formed in the body layer beside each trench by using the trimmed mask patterns as a mask. A plurality of dielectric patterns are formed on the conductive layer and between the trimmed mask patterns. The trimmed mask patterns are removed. | 2011-07-14 |
20110171800 | METHOD OF FORMING SEMICONDUCTOR DEVICES WITH BURIED GATE ELECTRODES AND DEVICES FORMED BY THE SAME - A polycrystalline semiconductor layer is formed on a cell active region and a peripheral active region of a substrate. A buried gate electrode is formed in the substrate in the cell active region at a level below the polycrystalline semiconductor layer after forming the polycrystalline semiconductor layer. A gate electrode is formed on the substrate in the peripheral active region from the polysilicon semiconductor layer after forming the buried gate electrode. | 2011-07-14 |
20110171801 | METHOD OF FABRICATING MULTI-FINGERED SEMICONDUCTOR DEVICES ON A COMMON SUBSTRATE - A method of fabricating p-type metal oxide semiconductor (PMOS) transistor devices on a common substrate is presented. The method provides a first portion of semiconductor material and a second portion of semiconductor material on the common substrate. The first portion of semiconductor material and the second portion of semiconductor material are insulated from each other. The method continues by creating first PMOS transistor devices using the first portion of semiconductor material. The first PMOS transistor devices include stressor regions that impart compressive stress to channel regions of the first PMOS transistor devices. The method also creates second PMOS transistor devices using the second portion of semiconductor material. The second PMOS transistor devices do not include channel stressor regions. | 2011-07-14 |
20110171802 | Methods of Making a Semiconductor Memory Device - One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held. | 2011-07-14 |
20110171803 | INTEGRATED MEMORY DEVICE HAVING COLUMNS HAVING MULTIPLE BIT LINES - A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions. | 2011-07-14 |
20110171804 | Multilayer Hard Mask - A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of film stacks, each film stack having a silicon oxide layer and a carbon-containing material layer, each film stack having a thickness equal to or less than about 10 angstrom; patterning the multi-layer hard mask layer, forming an opening of the multi-hard mask layer; etching the gate material layers within the opening of the multi-layer hard mask layer, forming a gate structure; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein a first remaining thickness of the multi-layer hard mask layer is less than a first thickness; and thereafter performing an epitaxy growth to the semiconductor substrate, wherein a second remaining thickness of the multi-layer hard mask layer is greater than a second thickness. | 2011-07-14 |
20110171805 | System and Method for Source/Drain Contact Processing - System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin. | 2011-07-14 |
20110171806 | Integrated electronic device and method of making the same - An integrated electronic device includes a substrate, passive components, pads for external connection, and three-dimensional wiring. The passive components includes a multi-stage coil inductor provided on the substrate. The multi-stage coil inductor has a plurality of coils disposed in several layers. Mutually adjacent coil wires are spaced-apart from each other. The three-dimensional wiring includes a first wiring portion which extends on the substrate, a second wiring portion which extends off the substrate but along the substrate, and a third wiring portion connecting with the first wiring portion and the second wiring portion. | 2011-07-14 |
20110171807 | METHOD FOR FABRICATING CAPACITOR - A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial pattern is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer in the peripheral region is etched to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed. | 2011-07-14 |
20110171808 | METHOD FOR FABRICATING A CAPACITOR - A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. A sacrificial pattern is formed over the isolation layer and covers the cell region. The isolation layer is etched in the peripheral region to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed. | 2011-07-14 |
20110171809 | METHOD FOR FABRICATING HIGH DENSITY PILLAR STRUCTURES BY DOUBLE PATTERNING USING POSITIVE PHOTORESIST - A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern. | 2011-07-14 |
20110171810 | METAL GATE TRANSISTOR AND RESISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor. | 2011-07-14 |
20110171811 | METHOD FOR FABRICATING A RESISTOR FOR A RESISTANCE RANDOM ACCESS MEMORY - A method for fabricating a resistor for a resistance random access memory (RRAM) includes: (a) forming a first electrode over a substrate; (b) forming a variable resistance layer of zirconium oxide on the first electrode under a working temperature, which ranges from 175° C. to 225° C.; and (c) forming a second electrode of Ti on the variable resistance layer. | 2011-07-14 |
20110171812 | FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SEMICONDUCTOR MATERIAL - The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal expansion of the support substrate and of the working layer. In another embodiment, the method includes providing a source substrate with a weakened zone defining a nucleation layer, bonding a support substrate to the source substrate, detaching the nucleation layer and support substrate at the weakened zone by applying laser irradiation stress, depositing a semiconductor material upon the nucleation layer, bonding a target substrate to the deposited layer and removing the support substrate and nucleation layer. The result is a semiconductor substrate that includes the layer of semiconductor material on a support or target substrate. | 2011-07-14 |
20110171813 | Release Strategies for Making Transferable Semiconductor Structures, Devices and Device Components - Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components. | 2011-07-14 |
20110171814 | SILICON EPITAXIAL WAFER AND PRODUCTION METHOD FOR SAME - A method for preparing a silicon epitaxial wafer that includes a silicon single crystal wafer sliced from a CZ silicon ingot doped with carbon in a concentration range of not less than 5×10 | 2011-07-14 |
20110171815 | PATTERNING METHOD FOR HIGH DENSITY PILLAR STRUCTURES - A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features. | 2011-07-14 |
20110171816 | SYNTHESIS OF GERMANIUM SULFIDE AND RELATED COMPOUNDS FOR SOLID ELECTROLYTIC MEMORY ELEMENTS AND OTHER APPLICATIONS - A method for making high purity GeS and related compounds such as Germanium Silicon Sulfide (GeSiS); Copper Sulfide (CuS); Silicon Sulfide (SiS); Zinc Sulfide (ZnS) and Iron Sulfide (FeS) at low temperatures and pressures in a Chemical Vapor Deposition (CVD) process for solid electrolyte memory elements and other applications. Disclosed is a method of generating a proper chemical and energy environment for the formation of GeS and related compounds on a specific surface. The produced films have utility in memory and other devices. The technology offers cost savings and the advantage of low temperature film creation through the use of plasma assisted deposition—increasing its compatibility for use not only on silicon (or ceramic or glass) non metal substrates as well as polymer or thin metal foil substrates which would be damaged by higher temperature processes. | 2011-07-14 |
20110171817 | Aromatic Molecular Carbon Implantation Processes - Methods for implanting an aromatic carbon molecule or a selected ionized lower mass byproduct into a workpiece generally includes vaporizing and ionizing aromatic carbon molecule in an ion source to create a plasma and produce aromatic carbon molecules and its ionized lower mass byproducts. The ionized aromatic carbon molecules and lower mass byproducts within the plasma are then extracted to form an ion beam. The ion beam is mass analyzed with a mass analyzer magnet to permit selected ionized aromatic carbon molecules or selected ionized lower mass byproducts to pass therethrough and implant into a workpiece. | 2011-07-14 |
20110171818 | METHODS OF FORMING A GATE STRUCTURE - A method of forming a gate structure can be provided by forming a tunnel insulation layer on a substrate and forming a floating gate on the tunnel insulation layer. A dielectric layer pattern can be on the floating gate and a control gate can be formed on the dielectric layer pattern, which can be provided by forming a first conductive layer pattern on the dielectric layer pattern. A metal ohmic layer pattern can be formed on the first conductive layer pattern. A diffusion preventing layer pattern can be formed on the metal ohmic layer pattern. An amorphous layer pattern can be formed on the diffusion preventing layer pattern forming a second conductive layer pattern on the amorphous layer pattern. The floating gate can be further formed by forming an additional first conductive layer pattern on the tunnel insulation layer. An additional metal ohmic layer pattern can be formed on the additional first conductive layer pattern. An additional diffusion preventing layer can be formed pattern on the additional metal ohmic layer pattern. An additional amorphous layer pattern can be formed on the additional diffusion preventing layer pattern and an additional second conductive layer pattern can be formed on the additional amorphous layer pattern. | 2011-07-14 |
20110171819 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film. | 2011-07-14 |
20110171820 | METHOD OF FORMING A METAL GATE - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method. | 2011-07-14 |
20110171821 | Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features. | 2011-07-14 |
20110171822 | METHOD OF MANUFACTURING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE - A method of manufacturing an interconnect structure for a semiconductor device having a device substrate is provided. The semiconductor device includes an electrically-conductive pad formed overlying the device substrate and an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity. The electrically-conductive platform has a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion. The semiconductor device also includes a cushioning material disposed in the cavity. | 2011-07-14 |
20110171823 | DIELECTRIC SPACERS FOR METAL INTERCONNECTS AND METHOD TO FORM THE SAME - A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers adjacent to neighboring metal interconnects are discontiguous from one another. In another embodiment, the dielectric spacers may provide a region upon which un-landed vias may effectively land. | 2011-07-14 |
20110171824 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect. | 2011-07-14 |
20110171825 | Method of Fabricating Integrated Circuitry - The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated. | 2011-07-14 |
20110171826 | Reducing Resistivity in Interconnect Structures of Integrated Circuits - An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening. | 2011-07-14 |
20110171827 | Three Dimensional Integration and Methods of Through Silicon Via Creation - A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure. | 2011-07-14 |
20110171828 | SEMICONDUCTOR DEVICE WITH A LINE AND METHOD OF FABRICATION THEREOF - A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained. | 2011-07-14 |
20110171829 | Method for Forming a Via in a Substrate and Substrate with a Via - The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method for forming a via in a substrate includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that has a side wall and a bottom wall on the first surface of the substrate; (c) forming a first conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming a center insulating material in the central groove; (e) forming an annular groove that surrounds the first conductive metal on the first surface of the substrate; (f) forming a first insulating material in the annular groove; and (g) removing part of the second surface of the substrate to expose the first conductive metal, the center insulating material and the first insulating material. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even. | 2011-07-14 |
20110171830 | SUBSTRATE PROCESSING METHOD, SYSTEM AND PROGRAM - A substrate processing method is used for a substrate processing system having a substrate processing device and a substrate transfer device. The substrate processing method includes a substrate transfer step of transferring a substrate and a substrate processing step of performing a predetermined process on the substrate. The substrate transfer step and the substrate processing step include a plurality of operations, and at least two operations among the plurality of the operations are performed simultaneously. Preferably, the substrate processing device includes an accommodating chamber, a mounting table placed in the accommodating chamber to be mounted thereon the substrate, and a heat transfer gas supply line for supplying a heat transfer gas to a space between the substrate mounted on the mounting table and the mounting table. | 2011-07-14 |
20110171831 | FABRIC CONTAINING NON-CRIMPED FIBERS AND METHODS OF MANUFACTURE - A chemical-mechanical planarization pad for semiconductor manufacturing is provided. The pad comprises synthetic fibers that are non-crimped fibers which are present in an amount of 1.0% by weight to 98.0% by weight in the mat and wherein the non-crimped fibers have a length of 0.1 cm to 127 cm and a diameter of 1.0 to 1000 micrometers. | 2011-07-14 |
20110171832 | Chemical-Mechanical Polishing Formulation and Methods of Use - The invention is directed to a chemical-mechanical polishing formulation that includes: an abrasive particulate component; iodic acid; and water. The invention is also directed to a method for polishing a metal-containing substrate, the method including the steps of polishing the metal-containing substrate with a polishing pad at a suitable polishing pressure while the metal-containing substrate is in contact with the above polishing formulation. | 2011-07-14 |
20110171833 | DRY ETCHING METHOD OF HIGH-K FILM - An object of the invention is to provide a dry etching method of a metal oxide High-k film having etching characteristics which achieve a small etching rate difference and a small profile difference between open area and dense area while keeping a high selectivity to a polysilicon underlying film. In the method of dry-etching a High-k film by using a plasma, a small amount of fluorocarbon gas having a high carbon ratio is added to a BCl | 2011-07-14 |
20110171834 | SILICON ETCHANT AND ETCHING METHOD - In etching processing of silicon, in particular anisotropic etching processing of silicon in a manufacturing step of MEMS parts, an etchant having a long life of etchant and an etching method are provided by suppressing a lowering of an etching rate at the time of warming which is characteristic of a hydroxylamine-containing etchant. | 2011-07-14 |