28th week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120175677 | PHOTOCELL - A photocell which operates at multiple wavelengths for efficient power generation from broadband incident radiation. According to a preferred embodiment, the photocell is a multi-layer device that includes a first outer layer, a middle layer and an inner layer disposed on a substrate. All three layers are formed from II-VI semiconductor layers. The device is arranged such that the outer layer has a high band gap, the middle layer has a band gap which is less than half the band gap of the outer layer and the inner layer has a band gap which is less than half that of the substrate. Thus, there is a step change in band gap between various layers. | 2012-07-12 |
20120175678 | REPLACEMENT SPACER FOR TUNNEL FETS - A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess. | 2012-07-12 |
20120175679 | Single structure cascode device - A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a MOS configuration with a drift region and an additional gate that modulates the carrier density in the drift region, so that the control on the carrier transport is enhanced and the specific on-resistance per area is reduced. This characteristic enables the use of short gate lengths while maintaining the electric field under the gate within reasonable values in high voltage applications, without increasing the device on-resistance. It offers the advantage of extremely lower on-resistance for the same silicon area while improving on its dynamic performances with respect to the standard CMOS technology. Another inherent advantage is that the switching gate losses are smaller due to lower V | 2012-07-12 |
20120175680 | ENHANCEMENT MODE GALLIUM NITRIDE POWER DEVICES - Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices. | 2012-07-12 |
20120175681 | Method and Layer Structure for Preventing Intermixing of Semiconductor Layers - A semiconductor device includes an etch-stop layer between a first layer of a field-effect transistor and a second layer of a bipolar transistor, each of which includes at least one arsenic-based semiconductor layer. A p-type layer is between the second layer and the etch-stop layer, and the device can include an n-type layer deposited between the etch-stop layer and p-type layer. The p-type layer provides an electric field that inhibits intermixing of the InGaP layer with layers in the first and second layers. | 2012-07-12 |
20120175682 | OHMIC CONTACT TO SEMICONDUCTOR DEVICE - Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm). | 2012-07-12 |
20120175683 | Basic Cell Architecture For Structured ASICs - A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs. | 2012-07-12 |
20120175684 | TRANSISTOR INCLUDING REDUCED CHANNEL LENGTH - A transistor includes a substrate. A first electrically conductive material layer, having a thickness, is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer overhangs the first electrically conductive material layer. An electrically insulating material layer, having a thickness, is conformally positioned over the second electrically conductive material layer, the first electrically conductive material layer, and at least a portion of the substrate. The thickness of the first electrically conductive material layer is greater than the thickness of the electrically insulating material layer. | 2012-07-12 |
20120175685 | IMAGE SENSOR BASED ON DEPTH PIXEL STRUCTURE - An image sensor based on a depth pixel structure is provided. The image sensor may include a pixel including a photodiode, and the photodiode may include a transfer gate to transfer, to a floating diffusion node, an electron generated by a light reflected from an object. | 2012-07-12 |
20120175686 | SOLID-STATE IMAGING DEVICE AND CAMERA - A solid-state imaging device including: a substrate; a light-receiving part; a second-conductivity-type isolation layer; a detection transistor; and a reset transistor. | 2012-07-12 |
20120175687 | System and Method for Manufacturing a Temperature Difference Sensor - An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor. | 2012-07-12 |
20120175688 | Semiconductor Package with Reduced On-Resistance and Top Metal Spreading Resistance with Application to Power Transistor Packaging - Some exemplary embodiments of a semiconductor package including a semiconductor device having electrodes on opposite major surfaces connectable to a planar support surface without a bondwire and a control electrode disposed in a corner position for reducing top-metal spreading resistance and device on-resistance have been disclosed. One exemplary structure comprises a semiconductor device having a first major surface including a first electrode and a second major surface including a second electrode and a control electrode, wherein the control electrode is disposed in a corner of the second major surface, and wherein the first electrode, the second electrode, and the control electrode are electrically connectable to a planar support surface without a bondwire. The pads of the device may be arranged in a balanced grid to maintain device stability during integration. A minimum gap distance between die pads allows the placement of vias in the planar support surface. | 2012-07-12 |
20120175689 | HYDROGEN PASSIVATION OF INTEGRATED CIRCUITS - An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer. | 2012-07-12 |
20120175690 | SI PHOTODIODE WITH SYMMETRY LAYOUT AND DEEP WELL BIAS IN CMOS TECHNOLOGY - A silicon photodiode with symmetry layout and deep well bias in CMOS technology is provided. The silicon photodiode includes a substrate, a deep well, and a PN diode structure. The deep well is disposed on the substrate, where an extra bias is applied to the deep well. The region surrounded by the deep well forms the main body of the silicon photodiode. The PN diode structure is located in the region surrounded by the deep well, where the silicon photodiode has a symmetry layout. The deep well is adopted when fabricating the silicon photodiode, and the extra bias is applied to the deep well to eliminate the interference and effect of the substrate absorbing light, and further greatly improve speed and bandwidth. Furthermore, the silicon photodiode has a symmetry layout, so that uniform electric field distribution is achieved, and the interference of the substrate noise is also reduced. | 2012-07-12 |
20120175691 | HOLE-BASED ULTRA-DEEP PHOTODIODE IN A CMOS IMAGE SENSOR AND A PROCESS THEREOF - A hole-based ultra-deep photodiode in a CMOS image sensor and an associated process are disclosed. A p-type substrate is grounded or connected to a negative power supply. An n-type epitaxial layer is grown on the p-type substrate, and is connected to a positive power supply. An ultra-deep p-type photodiode implant region is formed in the n-type epitaxial layer. Thermal steps are added to insure a smooth and deep doping profile. | 2012-07-12 |
20120175692 | Interconnection Wiring Structure of a Semiconductor Device - A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; and forming storage node contact lines which fill the second damascene trenches. | 2012-07-12 |
20120175693 | SEMICONDUCTOR DEVICE ENABLING FURTHER MICROFABRICATION - A semiconductor device includes a plurality of MOS transistors and wiring connected to a source electrode or a drain electrode of the plurality of MOS transistors and, the wiring being provided in the same layer as the source electrode and the drain electrode in a substrate, or in a position deeper than a surface of the substrate. | 2012-07-12 |
20120175694 | STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM - A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor. | 2012-07-12 |
20120175695 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to an embodiment includes a memory cell comprising a charge accumulate layer above a semiconductor substrate and a control gate above the charge accumulate layer. The charge accumulate layer is capable of accumulating charges therein. The control gate is configured to control an amount of the charges accumulated in the charge accumulate layer. The control gate comprises a lower-layer control gate part of metal or metallic silicide which is processable by etching, and an upper-layer control gate part of a material different from that of the lower-layer control gate part. | 2012-07-12 |
20120175696 | MULTILAYER FLOATING GATE FIELD-EFFECT TRANSISTOR (FET) DEVICES AND RELATED METHODS - Multilayer floating gate field-effect transistor (FET) devices and related methods are provided. A multilayer floating gate FET device can include a first floating gate separated via a first dielectric layer from a channel of the device and a second floating gate separated via a second dielectric layer from the first floating gate. The second dielectric layer between the first floating gate and the second floating gate permits a redistribution of charge between the first and second floating gates from one of the floating gates to the other when under the influence of a first electrical field from a first voltage. In some embodiments, a redistribution of charge between the first and second floating gates with electrons being supplied through a channel to the first and second floating gates can occur when under the influence of a second electrical field from a second voltage that is greater than the first voltage. | 2012-07-12 |
20120175697 | MULTI-STATE NON-VOLATILE MEMORY CELL INTEGRATION AND METHOD OF OPERATION - A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device. | 2012-07-12 |
20120175698 | SEMICONDUCTOR DEVICE - A semiconductor device which includes a gate electrode electrically connected to a gate portion made of a polysilicon film provided inside of a plurality of grooves formed in a striped form along a direction of a chip region. The gate electrode is formed as a film at the same layer level as a source electrode electrically connected to a source region formed between adjacent stripe-shaped grooves. The gate electrode is constituted of a gate electrode portion formed along a periphery of the chip region and a gate finger portion arranged to divide the chip region into halves. The source electrode is constituted of an upper portion and a lower portion relative to the gate finger portion, and the gate electrode and the source electrode are connected to a lead frame via a bump electrode. | 2012-07-12 |
20120175699 | TRENCH MOSFET WITH SUPER PINCH-OFF REGIONS AND SELF-ALIGNED TRENCHED CONTACT - A power semiconductor device having a self-aligned structure and super pinch-off regions is disclosed. The on-resistance is reduced by forming a short channel without having punch-through issue. The on-resistance is further reduced by forming an on-resistance reduction implanted drift region between adjacent shield electrodes, having doping concentration heavier than epitaxial layer without degrading breakdown voltage with a thick oxide on bottom and sidewalls of the shield electrode. Furthermore, the present invention enhance the switching speed comparing to the prior art. | 2012-07-12 |
20120175700 | TRENCH MOS RECTIFIER - A semiconductor device comprising trench MOSFET as MOS rectifier is disclosed. For ESD capability enhancement and reverse recovery charge reduction, a built-in resistor in the semiconductor device is introduced according to the present invention between gate and source. The built-in resistor is formed by a doped poly-silicon layer filled into multiple trenches. | 2012-07-12 |
20120175701 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, in which a gate formed over a device isolation film is an inner gate inserted into a recess so that device operation characteristics are improved. A semiconductor device includes a recess formed in a device isolation film of a semiconductor substrate including an active region and the device isolation film, a gate formed over the recess and having a width smaller than that of the recess, and a capping film formed over a sidewall of a gate including the recess exposed by the gate. | 2012-07-12 |
20120175702 | METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING TRENCHED DIFFUSION REGION AND METHOD OF FORMING SAME - An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region. | 2012-07-12 |
20120175703 | SEMICONDUCTOR DEVICE - A source region and a drain region are disposed in a substrate. A gate insulating film is disposed on the substrate. A gate electrode is disposed on the gate insulating film. The gate electrode may include a first gate portion adjacent to the source region and a second gate portion adjacent to the drain region. The first and second gate portions have different work functions from each other. | 2012-07-12 |
20120175704 | Monolithically-Integrated New Dual Surge Protective Device and Its Fabrication Method - A monolithically-integrated dual surge protective device and its fabrication method are disclosed. The exemplary dual surge protective device includes a LDMOS device and a diode assembly which is consisted. of multiple diodes series-wound on back-to-back basis and whose one end is connected to drain electrode of the LDMOS device and the other-end is connected to gate electrode of the LDMOS device. The diode assembly can be fabricated directly in the gate electrode area of the LDMOS device after fabrication of the LDMOS device is completed. The protective device is equivalent to combination of diodes and LDMOS in respect to operating principles and structures, with the advantage of enhanced effect of surge prevention and cost reduction of surge device as it can be integrated into a chip. | 2012-07-12 |
20120175705 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a MOS semiconductor device. In the method, a gate electrode is formed on a gate insulating film provided on a channel region which is a part of an Si layer and which is interposed between a source/drain region, and a film mainly includes of Ge is made to grow on the source/drain region. Then, and the film mainly includes of Ge is made to react with a metal, forming an intermetallic compound film having a depthwise junction position identical to a growth interface of the film mainly includes of Ge. | 2012-07-12 |
20120175706 | Chip-Exposed Semiconductor Device - A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices. | 2012-07-12 |
20120175707 | SEMICONDUCTOR DEVICE INCLUDING METAL SILICIDE LAYER AND FABRICATION METHOD THEREOF - A semiconductor device comprises a substrate, a gate structure formed on the substrate, a channel region below the gate structure in the substrate, a first source/drain region and a second source/drain region located at opposite side of the gate structure, a first lightly-doped drain (LDD) junction region formed between the first source/drain region and one end of the channel region, a second lightly-doped drain (LDD) junction region formed between the second source/drain region and the other end of the channel region, a metal silicide layer having a first metal formed on the first and second source/drain regions, an insulating layer formed on the metal silicide layer and the gate structure having a first opening to expose the metal silicide layer, and a conductive layer having the first metal and filling the first opening to contact the metal silicide layer. | 2012-07-12 |
20120175708 | Semiconductor Discharge Devices and Methods of Formation Thereof - In one embodiment, a method of forming a semiconductor device includes forming a well region within a substrate. A plurality of transistors is formed within and/or over the well region. The method further includes forming a first discharge device within the substrate. The first discharge device is coupled to the well region and a low voltage node. During subsequent processing, the first discharge device discharges charge from the well region. | 2012-07-12 |
20120175709 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device capable of ensuring a sufficient area of a peripheral region by forming a gate spacer to have a uniform thickness in the peripheral region and reducing a fabrication cost by simplifying a mask process and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a gate disposed over a semiconductor substrate; a first spacer disposed over sidewalls of the gate; an insulating layer pattern disposed over sidewalls of the first spacer; and a second spacer disposed over the first spacer and the insulating pattern. | 2012-07-12 |
20120175710 | INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS - An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having ( | 2012-07-12 |
20120175711 | Self-Aligned Contacts for High k/Metal Gate Process Flow - A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed. | 2012-07-12 |
20120175712 | Multiple Vt Field-Effect Transistor Devices - Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate. | 2012-07-12 |
20120175713 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures. | 2012-07-12 |
20120175714 | Embedded Microelectromechanical Systems Sensor and Related Devices and Methods - Embodiments of embedded MEMS sensors and related methods are described herein. Other embodiments and related methods are also disclosed herein. | 2012-07-12 |
20120175715 | ENCAPSULATED MICRO-ELECTROMECHANICAL SYSTEM SWITCH AND METHOD OF MANUFACTURING THE SAME - Encapsulated MEMS switches are disclosed along with methods of manufacturing the same. A non-polymer based sacrificial layer is used to form the actuation member of the MEMS switch while a polymer based sacrificial layer is used to form the enclosure that encapsulates the MEMS switch. The first non-polymer based sacrificial layer allows for highly reliable MEMS switches to be manufactured while also protecting the MEMS switch from carbon contamination. The polymer based sacrificial layer allows for the manufacture of more spatially efficient encapsulated MEMS switches. | 2012-07-12 |
20120175716 | STORAGE ELEMENT AND STORAGE DEVICE - A storage element includes: a storage layer which has magnetization perpendicular to a film surface, the direction of the magnetization being changed in accordance with information; a magnetization fixed layer which has magnetization perpendicular to a film surface used as a base of information stored in the storage layer; and an insulating layer of a nonmagnetic substance provided between the storage layer and the magnetization fixed layer. In the storage element described above, the magnetization of the storage layer is reversed using a spin torque magnetization reversal generated by a current flowing in a lamination direction of a layer structure including the storage layer, the insulating layer, and the magnetization fixed layer to store information, the storage layer is directly provided with a layer at a side opposite to the insulating layer, and this layer includes a conductive oxide. | 2012-07-12 |
20120175717 | STORAGE ELEMENT AND STORAGE DEVICE - A storage element includes: a storage layer which has magnetization perpendicular to a film surface, the direction of the magnetization being changed in accordance with information; a magnetization fixed layer which has magnetization perpendicular to a film surface used as a base of information stored in the storage layer; and an insulating layer of a nonmagnetic substance provided between the storage layer and the magnetization fixed layer. In the storage element described above, the magnetization of the storage layer is reversed using a spin torque magnetization reversal generated by a current flowing in a lamination direction of a layer structure including the storage layer, the insulating layer, and the magnetization fixed layer to store information, and the storage layer has a laminate structure including a magnetic layer and a conductive oxide. | 2012-07-12 |
20120175718 | BIPOLAR SELECT DEVICE FOR RESISTIVE SENSE MEMORY - A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate, a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, an emitter contact layer disposed in a second side of the semiconductor substrate, and a base layer separating the plurality of collector contacts from the emitter contact layer. Each collector contact is electrically isolated from each other. A resistive sense memory cells is electrically coupled to each collector contacts and a bit line. The base layer and the emitter contact layer provide an electrical path for the plurality of collector contacts. | 2012-07-12 |
20120175719 | X-Y ADDRESS TYPE SOLID STATE IMAGE PICKUP DEVICE AND METHOD OF PRODUCING THE SAME - In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein, and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. Wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced. | 2012-07-12 |
20120175720 | CMOS IMAGE SENSORS AND RELATED DEVICES AND FABRICATION METHODS - An image sensor device includes a substrate including a light sensing region therein and a reflective structure on a first surface of the substrate over the light sensing region. An interconnection structure having a lower reflectivity than the reflective structure is provided on the first surface of the substrate adjacent to the reflective structure. A microlens is provided on a second surface of the substrate opposite the first surface. The microlens is configured to direct incident light to the light sensing region, and the reflective structure is configured to reflect portions of the incident light that pass through the light sensing region back toward the light sensing region. Related devices and fabrication methods are also discussed. | 2012-07-12 |
20120175721 | Methods And Materials Useful For Chip Stacking, Chip And Wafer Bonding - Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues. | 2012-07-12 |
20120175722 | SEAL RING SUPPORT FOR BACKSIDE ILLUMINATED IMAGE SENSOR - A backside illuminated imaging sensor with a seal ring support includes an epitaxial layer having an imaging array formed in a front side of the epitaxial layer. A metal stack is coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor. An opening is included that extends from the back side of the epitaxial layer to a metal pad of the seal ring to expose the metal pad. The seal ring support is disposed on the metal pad and within the opening to structurally support the seal ring. | 2012-07-12 |
20120175723 | INFRARED IMAGING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, an infrared imaging device includes a substrate, a detecting section, an interconnection, a contact plug and a support beam. The detecting section is provided above the substrate and includes an infrared absorbing section and a thermoelectric converting section. The interconnection is provided on an interconnection region of the substrate and is configured to read the electrical signal. The contact plug is extends from the interconnection toward a connecting layer provided in the interconnection region. The contact plug is electrically connected to the interconnection and the connecting layer. The support beam includes a support beam interconnection and supports the detecting section above the substrate. The support beam interconnection transmits the electrical signal from the thermoelectric converting section to the interconnection. | 2012-07-12 |
20120175724 | Trenched Schottky Diode and Method of Forming a Trenched Schottky Diode - A Schottky diode with a small footprint and a high-current carrying ability is fabricated by forming an opening that extends into an n-type semiconductor material. The opening is then lined with a metallic material such as platinum. The metallic material is then heated to form a salicide region where the metallic material touches the n-type semiconductor material. | 2012-07-12 |
20120175725 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to an embodiment includes a memory cell array provided on a semiconductor substrate and comprising a plurality of memory cells configured to store data therein, and a peripheral circuit part provided on the semiconductor substrate and configured to control the memory cell array. An element isolation part is provided between active areas where the memory cells and the peripheral circuit part are formed. A sidewall film is provided on a side surface of the active area in the peripheral circuit part. | 2012-07-12 |
20120175726 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device comprises a circuit portion, wells, and dummy wells. A circuit portion is formed on an upper surface of a semiconductor substrate of a first conductivity type. The wells are of a second conductivity type different from the first conductivity type. Each of wells is formed in the semiconductor substrate on an upper surface side, constitutes the circuit portion, and functions as an element. The dummy wells are of the second conductivity type. Each of the dummy wells is formed in the semiconductor substrate on the upper surface side, does not constitute the circuit portion, and does not function as an element. | 2012-07-12 |
20120175727 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer. | 2012-07-12 |
20120175728 | SEAL RING STRUCTURE FOR INTEGRATED CIRCUIT CHIPS - A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W | 2012-07-12 |
20120175729 | Discrete Semiconductor Device and Method of Forming Sealed Trench Junction Termination - A discrete semiconductor device has a substrate with a first conductivity type of semiconductor material. A first semiconductor layer is formed over the substrate. The first semiconductor layer having the first conductivity type of semiconductor material. A second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second conductivity type of semiconductor material. A trench is formed through the second semiconductor layer and extends into the second semiconductor layer. The trench has a rounded or polygonal shape and vertical sidewalls. The trench is lined with an insulating layer and filled with an insulating material. A boundary between the first and second semiconductor layers forms a p-n junction. The trench surrounds the p-n junction to terminate the electric field of a voltage imposed on the second semiconductor layer. The discrete semiconductor device can also be a transistor, thyristor, triac, or transient voltage suppressor. | 2012-07-12 |
20120175730 | INTEGRATED CIRCUIT AND PRODUCTION METHOD - An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate. | 2012-07-12 |
20120175731 | SEMICONDUCTOR STRUCTURE WITH PASSIVE ELEMENT NETWORK AND MANUFACTURING METHOD THEREOF - The present invention relates to a semiconductor structure having an integrated passive network and a method for making the same. The semiconductor structure includes a substrate which can be an interposer. The substrate can include a plurality of conductive vias. In various embodiments, the substrate includes a dielectric layer disposed thereon, the dielectric layer having an opening forming a straight hole allowing electrical connection between the passive network and the conductive via. The passive network includes a series of patterned dielectric and conductive layers, forming passive electronic components. In an embodiment, the passive device includes a common resistor coupled to a pair of inductors, each of the inductors coupled to a capacitor. In another embodiment, the passive device includes a resistor and an inductor electrically connected to each other, a bottom surface of the inductor coplanar with a bottom surface of the resistor. | 2012-07-12 |
20120175732 | Semiconductor Package with Semiconductor Core Structure and Method of Forming Same - A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure. | 2012-07-12 |
20120175733 | SEMICONDUCTOR DEVICE HAVING CONDUCTORS WITH DIFFERENT DIMENSIONS AND METHOD FOR FORMING - A device structure includes an inter-level dielectric, a via, a first conductive trench, and a second conductive trench. The inter-level dielectric has a top surface and a bottom surface. The via extends from the top surface to the bottom surface. The first conductive trench extends from the top surface to a first depth below the top surface. The second conductive trench extends from the top surface to a second depth below the top surface, wherein the second depth is above the bottom surface and below the first depth. | 2012-07-12 |
20120175734 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics. The semiconductor device includes a first storage node contact plug and a second storage node contact plug formed over a semiconductor substrate, wherein the second storage node contact plug is arranged at a height different from that of the first storage node contact plug, and a lower electrode formed over the first storage node contact plug and the second storage node contact plug. | 2012-07-12 |
20120175735 | Semiconductor Device and Method of Forming IPD on Molded Substrate - A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties. | 2012-07-12 |
20120175736 | SEMICONDUCTOR DEVICE - A substrate is provided with a first wiring layer | 2012-07-12 |
20120175737 | SEMICONDUCTOR DEVICES WITH GATE-SOURCE ESD DIODE AND GATE-DRAIN CLAMP DIODE - A semiconductor power device integrated with a Gate-Source ESD diode for providing an electrostatic discharge (ESD) protection and a Gate-Drain clamp diode for drain-source avalanche protection. The semiconductor power device further includes a Nitride layer underneath the diodes and a thick oxide layer as an etching stopper layer for protecting a thin oxide layer on top surface of body region from over-etching. | 2012-07-12 |
20120175738 | METHODS OF FABRICATING BIPOLAR TRANSISTOR FOR IMPROVED ISOLATION, PASSIVATION AND CRITICAL DIMENSION CONTROL - A first (e.g. replaceable or disposable) dielectric spacer formed on a sidewall of a dummy emitter mandrel is removed after a raised extrinsic base layer and covering dielectric layer are formed. Thereafter, a second dielectric spacer is formed within the opening that results. As a result, the second dielectric spacer, which is not subjected to RIE processing, provides a desired level of isolation and tighter emitter final critical dimension than that which could be achieved through the technique described in the prior art. In a particular embodiment, an additional layer of silicon nitride is disposed over a passivation oxide layer as a sacrificial layer which protects the passivation oxide layer from being reduced in thickness and/or being undercut during the RIE process and one or more cleaning processes conducted after the RIE process. | 2012-07-12 |
20120175739 | PLANAR NONPOLAR GROUP-III NITRIDE FILMS GROWN ON MISCUT SUBSTRATES - A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an α-axis direction comprising a 0.15° or greater miscut angle towards the α-axis direction and a less than 30° miscut angle towards the α-axis direction. | 2012-07-12 |
20120175740 | BASE SUBSTRATE, GROUP 3B NITRIDE CRYSTAL, AND METHOD FOR MANUFACTURING THE SAME - Regarding a base substrate, a plurality of steps are formed stepwise on the principal surface (c-face). Each step has a height difference of 10 to 40 μm, and an edge is formed parallel to an a-face of a hexagonal crystal of GaN. Meanwhile, the terrace width of each step is set at a predetermined width. The predetermined width is set in such a way that after a GaN crystal is grown on the principal surface of the base substrate, the principal surface is covered up with grain boundaries when the grown GaN crystal is observed from the surface side. The plurality of steps can be formed through, for example, dry etching, sand blasting, lasing, and dicing. | 2012-07-12 |
20120175741 | Method for Direct Deposition of a Germanium Layer - The present disclosure is related to a method for the deposition of a continuous layer of germanium on a substrate by chemical vapor deposition. According to the disclosure, a mixture of a non-reactive carrier gas and a higher order germanium precursor gas, i.e. of higher order than germane (GeH | 2012-07-12 |
20120175742 | EPITAXIAL STRUCTURE AND METHOD FOR MAKING THE SAME - An epitaxial structure and a method for making the same are provided. The epitaxial structure includes a substrate, an epitaxial layer and a carbon nanotube layer. The epitaxial layer is located on the substrate. The carbon nanotube layer is located in the epitaxial layer. The method includes following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is suspended above the epitaxial growth surface. An epitaxial layer is epitaxially grown from the epitaxial growth surface to enclose the carbon nanotube layer therein. | 2012-07-12 |
20120175743 | EPITAXIAL STRUCTURE - An epitaxial structure is provided. The epitaxial structure includes a substrate, an first epitaxial layer, a second epitaxial layer, a first carbon nanotube layer and a second carbon nanotube layer. The first epitaxial layer is located on the substrate. The first carbon nanotube layer is located between the substrate and the first epitaxial layer. The second epitaxial layer is located on the first epitaxial layer. The second carbon nanotube layer is located between the first epitaxial layer and the second epitaxial layer. | 2012-07-12 |
20120175744 | COPPER ELECTROPLATING COMPOSITION - The present invention relates to a copper electroplating composition comprising a copper alkanesulfonate salt, a free alkanesulfonic acid, and one or more organic compounds selected from the group consisting of suppressors, accelerators, levelers, and mixtures thereof, in which the concentration of free acid is from 0 M to about 0.25 M and the composition is free of halide ions. The present invention also relates to a process of metalizing micro-sized trenches or vias in a substrate using the composition. | 2012-07-12 |
20120175745 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES USING THE SAME - A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width. | 2012-07-12 |
20120175746 | Selective Deposition in the Fabrication of Electronic Substrates - A semiconductor substrate is coated with a single layer of different materials selected from adhesives, coatings, and encapsulants. | 2012-07-12 |
20120175747 | MEMS DEVICE ASSEMBLY AND METHOD OF PACKAGING SAME - An assembly ( | 2012-07-12 |
20120175748 | SEMICONDUCTOR STRUCTURES INCLUDING DUAL FINS AND METHODS OF FABRICATION - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 2012-07-12 |
20120175749 | Structure and Method to Fabricate Resistor on FinFET Processes - A structure comprises first and at least second fin structures are formed. Each of the first and at least second fin structures has a vertically oriented semiconductor body. The vertically oriented semiconductor body is comprised of vertical surfaces. A doped region in each of the first and at least second fin structures is comprised of a concentration of dopant ions present in the semiconductor body to form a first resistor and at least a second resistor, and a pair of merged fins formed on outer portions of the doped regions of the first and at least second fin structures. The pair of merged fins is electrically connected so that the first and at least second resistors are electrically connected in parallel with each other. | 2012-07-12 |
20120175750 | GEOMETRY OF CONTACT SITES AT BRITTLE INORGANIC LAYERS IN ELECTRONIC DEVICES - An electronic device ( | 2012-07-12 |
20120175751 | DEPOSITION OF GROUP IV METAL-CONTAINING FILMS AT HIGH TEMPERATURE - Disclosed are group IV metal-containing precursors and their use in the deposition of group IV metal-containing films{nitride, oxide and metal) at high process temperature. The use of cyclopentadienyl and imido ligands linked to the metal center secures thermal stability, allowing a large deposition temperature window, and low impurity contamination. The group IV metal (titanium, zirconium, hafnium)-containing fvm depositions may be carried out by thermal and/or plasma-enhanced CVD, ALD, and pulse CVD. | 2012-07-12 |
20120175752 | DEVICES WITH FARADAY CAGES AND INTERNAL FLEXIBILITY SIPES - A computer or microchip comprising an outer chamber and at least one inner chamber inside the outer chamber. The outer chamber and the inner chamber being separated at least in part by an internal sipe, and at least a portion of a surface of the outer chamber forming at least a portion of a surface of the internal sipe. The internal sipe has opposing surfaces that are separate from each other and therefore can move relative to each other, and at least a portion of the opposing surfaces are in contact with each other in a unloaded condition. The outer chamber including a Faraday Cage. A computer, comprising a semiconductor wafer having a multitude of microchips. The multitude of microchips forming a plurality of independently functioning computers, each computer having independent communication capabilities. | 2012-07-12 |
20120175753 | THIN SEMICONDUCTOR DEVICE AND OPERATION METHOD OF THIN SEMICONDUCTOR DEVICE - The present invention provides a thin semiconductor device in which its security such as prevention of counterfeit or information leakage is to be enhanced. One feature of the present invention is a thin semiconductor device in which a plurality of thin film integrated circuits are mounted and in which at least one integrated circuit is different from the other integrated circuits in any one of a specification, layout, frequency for transmission or reception, a memory, a communication means, a communication rule and the like. According to the present invention, a thin semiconductor device tag having the plurality of thin film integrated circuits communicates with a reader/writer and at least one of the thin film integrated circuits receives a signal to write information in a memory, and the information written in the memory determines which of the thin film integrated circuits communicates. | 2012-07-12 |
20120175754 | WIRING BOARD - A wiring board including a core substrate made of an insulative material and having a penetrating portion, a first interlayer insulation layer formed on the surface of the core substrate, a first conductive circuit formed on the surface of the first interlayer insulation layer, a first via conductor formed in the first interlayer insulation layer, and an electronic component accommodated in the penetrating portion of the core substrate and including a semiconductor element, a bump body mounted on the semiconductor element, a conductive circuit connected to the bump body, an interlayer resin insulation layer formed on the conductive circuit, and a via conductor formed in the interlayer resin insulation layer. The first via conductor has a tapering direction which is opposite of a tapering direction of the via conductor in the electronic component. | 2012-07-12 |
20120175755 | SEMICONDUCTOR DEVICE INCLUDING A HEAT SPREADER - A semiconductor device includes a semiconductor chip including back side metal, a substrate, and an electrically conductive heat spreader directly contacting the back side metal. The semiconductor chip includes a sintered joint directly contacting the heat spreader and electrically coupling the heat spreader to the substrate. | 2012-07-12 |
20120175756 | SEMICONDUCTOR PACKAGES HAVING LEAD FRAMES - Semiconductor packages having lead frames include a lead frame, which supports a semiconductor chip and is electrically connected to the semiconductor chip by bonding wires, and a molding layer encapsulating the semiconductor chip. The lead frame includes first lead frames extending in a first direction and second lead frames extending in a second direction. The first lead frames may run across the semiconductor chip and support the semiconductor chip and the second lead frames may run across the bottom surface of the semiconductor chip. | 2012-07-12 |
20120175757 | METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, THE SEMICONDUCTOR APPARATUS, AND IGNITOR USING THE SEMICONDUCTOR APPARATUS - A method of manufacturing a semiconductor apparatus according to aspects of the invention can include the steps of coating solder on an predetermined area in the upper surface of a lead frame, mounting a chip on solder and melting solder with a hot plate for bonding the chip to the lead frame. The method can also include wiring with bonding wires, turning lead frame upside down, placing lead frame turned upside down on heating cradle, coating solder, the melting point of which is lower than the solder melting point and mounting electronic part on solder; and melting solder with heating cradle for bonding electronic part to lead frame. The bonding with solder can be conducted at a high ambient temperature. Aspects of the semiconductor apparatus can facilitate mounting semiconductor devices and electronic parts on both surfaces of a lead frame divided to form wiring circuits without through complicated manufacturing steps. | 2012-07-12 |
20120175758 | LEAD FRAME AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A lead frame and a semiconductor package including the lead frame are provided. The lead frame includes: a base material; a first metal layer which is formed on at least one side of the base material, of which a surface is roughly formed, and which includes copper or nickel; a second metal layer which is formed on a surface of the first metal layer, of which a surface is roughly formed, and which includes palladium or a palladium alloy; a third metal layer which is formed on a surface of the second metal layer, of which a surface is roughly formed, and which includes gold or a gold alloy; and a fourth metal layer which is formed on a surface of the third metal layer, of which a surface is roughly formed, and which includes metal that includes silver. | 2012-07-12 |
20120175759 | WIRING DEVICE FOR SEMICONDUCTOR DEVICE, COMPOSITE WIRING DEVICE FOR SEMICONDUCTOR DEVICE, AND RESIN-SEALED SEMICONDUCTOR DEVICE - A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal. | 2012-07-12 |
20120175760 | LEADFRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a die pad, the die pad including a first surface and a second surface, a first chip arranged on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged on the first surface, a plurality of first recesses formed on the first surface, a plurality of second recesses formed on the first surface, the plurality of second recesses being different from the first plurality of recesses in at least one of size and geometry, a wire, a resin, and a lead, one end of the lead being connected to another end of the wire and a part the lead being encapsulated by the resin. The plurality of first recesses includes a third recess and a fourth recess, and the first chip is arranged in a first area. | 2012-07-12 |
20120175761 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device consisting of a lead frame or a circuit board, at least one semiconductor element which is stacked on or mounted in parallel on the lead frame or on the circuit board, a copper wire which electrically connects the lead frame or the circuit board to the semiconductor element, and an encapsulating material which encapsulates the semiconductor element and the copper wire, wherein the wire diameter of the copper wire is equal to or more than 18 μm and equal to or less than 23 μm,
| 2012-07-12 |
20120175762 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other: and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed. | 2012-07-12 |
20120175763 | INTEGRATED CIRCUIT PACKAGING INCLUDING AUXILIARY CIRCUITRY - An integrated circuit package includes a package core and a primary circuitry chip mounted on the package core. The primary circuitry chip has an active surface in which the core circuitry is fabricated. The active surface of the primary circuitry chip faces the package core and includes contacts. The integrated circuit package further includes an auxiliary circuit chip assembled to the package core and having contacts facing and electrically connected to the contacts of the primary circuitry chip. | 2012-07-12 |
20120175764 | METHOD FOR THE PRODUCTION OF AN ELECTRONIC COMPONENT AND ELECTRONIC COMPONENT PRODUCED ACCORDING TO THIS METHOD - The invention relates to an electronic component having a circuit integrated on a semiconductor substrate, and a heat-conducting connection of the substrate by soldering using a carrier serving as a heat sink, wherein the invention proposes depositing a first, thicker Au layer ( | 2012-07-12 |
20120175765 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed that includes an insulation substrate, a metal wiring layer, a semiconductor element, a heat sink, and a stress relaxation member located between the insulation substrate and the heat sink. The heat sink has a plurality of partitioning walls that extend in one direction and are arranged at intervals. The stress relaxation member includes a stress absorbing portion formed by through holes extending through the entire thickness of the stress relaxation member. Each hole is formed such that its dimension along the longitudinal direction of the partitioning walls is greater than its dimension along the arranging direction of the partitioning walls. | 2012-07-12 |
20120175766 | SYSTEM AND METHOD OF ACHIEVING MECHANICAL AND THERMAL STABILITY IN A MULTI-CHIP PACKAGE - A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package. | 2012-07-12 |
20120175767 | SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS AND METHOD FOR MAKING THE SAME - The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage. | 2012-07-12 |
20120175768 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor chip including a main surface electrode; a first mounting lead; a second mounting lead; a connection lead which overlaps with the main surface electrode, the first mounting lead and the second mounting lead when viewed in a thickness direction of the semiconductor chip and makes electrical conduction between the main surface electrode, the first mounting lead and the second mounting lead; and a resin portion which covers the semiconductor chip, the first mounting lead and the second mounting lead, wherein the resin portion has a resin bottom lying on the same plane as a bottom of the first mounting lead and a bottom of the second mounting lead. | 2012-07-12 |
20120175769 | Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate - A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first substrate. A first semiconductor die is mounted to the central region of the first substrate. A second semiconductor die is mounted to the first semiconductor die over the central region of the first substrate. A height of the first and second die is less than or equal to a height of the bumps. A second substrate has a thermal conduction channel. A surface of the second semiconductor die opposite the first die is mounted to the thermal conductive channel of the second substrate. A thermal interface layer is formed over the surface of the second die. The bumps are electrically connected to contact pads on the second substrate. A conductive plane is formed over a surface of the second substrate. | 2012-07-12 |
20120175770 | Semiconductor Device and Method of Forming Conductive Pillars in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices - A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar. | 2012-07-12 |
20120175771 | Semiconductor Device and Method of Forming No-Flow Underfill Material Around Vertical Interconnect Structure - A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump. | 2012-07-12 |
20120175772 | ALTERNATIVE SURFACE FINISHES FOR FLIP-CHIP BALL GRID ARRAYS - A ball grid array package device includes a substrate with a copper ball grid array pad formed on the substrate. A nickel layer may be formed on the copper pad and a tin layer formed on the nickel layer. The nickel layer may be formed using an electroless nickel plating process. The tin layer may be formed using an immersion tin process. In some cases, silver may be used instead of tin and formed using an immersion silver process. | 2012-07-12 |
20120175773 | Thermal Enhanced Package Using Embedded Substrate - An integrated circuit (IC) device is provided. The IC device includes an IC die having opposing first and second surfaces, a carrier coupled to the first surface of the IC die, a laminate coupled to the carrier and the second surface of the IC die, and a trace located on a surface of the laminate and electrically coupled to a bond pad located on the second surface of the IC die. The trace is configured to couple the bond pad to a circuit board. | 2012-07-12 |
20120175774 | WARPAGE CONTROL FEATURES ON THE BOTTOMSIDE OF TSV DIE LATERAL TO PROTRUDING BOTTOMSIDE TIPS - A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap. | 2012-07-12 |
20120175775 | INTEGRATED CIRCUIT LINE WITH ELECTROMIGRATION BARRIERS - An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line. | 2012-07-12 |
20120175776 | ELECTROLESS CU PLATING FOR ENHANCED SELF-FORMING BARRIER LAYERS - Methods and an apparatus are described for an integrated circuit within which an electroless Cu plated layer having an oxygen content is formed on the top of a seed layer comprising Cu and Mn. The integrated circuit is then exposed to a sufficient high temperature to cause the self-formation of a MnSiOx barrier layer. | 2012-07-12 |