28th week of 2013 patent applcation highlights part 13 |
Patent application number | Title | Published |
20130175512 | Organic Light Emitting Display Device - Disclosed is an organic light emitting display device. The organic light emitting display device includes a substrate, a thin film transistor formed on the substrate, a first electrode formed on the thin film transistor, an organic emission layer, and a second electrode formed on the organic emission layer. The organic emission layer includes a first stack that includes a first emission layer formed on the first electrode to emit first color light, a second stack that includes a second emission layer formed on the first electrode to emit second color light, and a charge generation layer formed between the first and second stacks. | 2013-07-11 |
20130175513 | SOLID-STATE ASSEMBLY OF LAYERS AND AN ELECTRIC DEVICE COMPRISING SUCH ASSEMBLY - The present invention relates to a solid-state assembly of layers and to an electric solid-state device comprising such assembly. In one aspect, such electric device is a field effect transistor. In another aspect, such device is a memory device. In yet a further aspect, the device is a sensor device. | 2013-07-11 |
20130175514 | DISPLAY DEVICE - A display device includes a substrate and a pixel formed over the substrate. The pixel includes a red subpixel, a green subpixel, a deep green subpixel, and a blue subpixel. The configuration of the display device increases the luminous efficiency and life-span and realizes the high color purity. | 2013-07-11 |
20130175515 | LIGHT EMITTING APPARATUS - A lighting apparatus comprising a plurality of diodes and an electrical interface configured to receive an electrical signal and transmit the electrical signal to the plurality of diodes is provided. | 2013-07-11 |
20130175516 | LIGHT EMITTING APPARATUS - A lighting apparatus comprising a plurality of diodes and an electrical interface configured to receive an electrical signal and transmit the electrical signal to the plurality of diodes is provided. | 2013-07-11 |
20130175517 | ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE - An organic electroluminescence display device is provided. The organic electroluminescence display device includes plural organic electroluminescence elements. Each organic electroluminescence element includes: a lower electrode; an insulating layer having an opening, in which a lower electrode is exposed at the bottom of the opening; an auxiliary wiring; a stacked structure provided from a portion over the lower electrode exposed at the bottom of the opening to a portion of the insulating layer surrounding the opening, including a light emitting layer made of an organic light-emitting material; and an upper electrode. At least one layer of the stacked structure partially contacts the auxiliary wiring. The insulating layer and the auxiliary wiring are provided in common to the plurality of organic EL elements. The upper electrode covers the whole surface of the stacked structures and the auxiliary wiring. | 2013-07-11 |
20130175518 | ELECTROLUMINESCENT ORGANIC TRANSISTOR - An electroluminescent organic transistor is described. The electroluminescent organic transistor has a semiconductor heterostructure constituted by a plurality of layers of semiconductor materials of p-type and n-type, which act, respectively, for the conduction of holes and electrons within the heterostructure, and at least two layers of emitting materials each of which is interposed between, and in direct contact with, one of the layers of p-type semiconductor material and another one of the layers of n-type semiconductor material. | 2013-07-11 |
20130175519 | NEW CONDENSED POLYCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING ELEMENT USING THE SAME - The present invention provides a stable new condensed polycyclic compound which is not likely to form a molecular association. In addition, the present invention also provides an organic light-emitting element having a high light-emitting efficiency and a low drive voltage. In the condensed polycyclic compound in Claim | 2013-07-11 |
20130175520 | THIN FILM TRANSISTOR - A thin film transistor suitable for being disposed on a substrate is provided. The thin film transistor includes a gate electrode, an organic gate dielectric layer, a metal oxide semiconductor layer, a source electrode and a drain electrode. The gate electrode is disposed on the substrate. The organic gate dielectric layer is disposed on the substrate to cover the gate electrode. The source electrode, the drain electrode and the metal oxide semiconductor layer are disposed above the organic gate dielectric layer, and the metal oxide semiconductor layer contacts with the source electrode and the drain electrode. Because the channel layer of the thin film transistor is a layer of metal oxide semiconductor formed at a lower temperature, thus the thin film transistor can be widely applied into various display applications such as flexible display devices. | 2013-07-11 |
20130175521 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF | 2013-07-11 |
20130175522 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THIN FILM TRANSISTOR, DISPLAY, AND ELECTRONIC APPARATUS - A thin film transistor includes: a gate electrode, a source electrode, and a drain electrode; an oxide semiconductor layer provided on one side of the gate electrode with an insulating film in between, the oxide semiconductor layer being provided in a region not facing the source electrode and the drain electrode and being electrically connected to the source electrode and the drain electrode; and a low resistance oxide layer provided in a region facing the source electrode and in a region facing the drain electrode, the regions being adjacent to the oxide semiconductor layer, and the low resistance oxide layer having an electric resistivity lower than an electric resistivity of the oxide semiconductor layer. | 2013-07-11 |
20130175523 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - One of factors that increase the contact resistance at the interface between a first semiconductor layer where a channel is formed and source and drain electrode layers is a film with high electric resistance formed by dust or impurity contamination of a surface of a metal material serving as the source and drain electrode layers. As a solution, a first protective layer and a second protective layer including a second semiconductor having a conductivity that is less than or equal to that of the first semiconductor layer is stacked successively over source and drain electrode layers without exposed to air, the stack of films is used for the source and drain electrode layers. | 2013-07-11 |
20130175524 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode. | 2013-07-11 |
20130175525 | DISPLAY DEVICE - In order to take advantage of the properties of a display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area are necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer over the gate insulating film; a channel protective layer covering a region which overlaps with a channel formation region of the first oxide semiconductor layer; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and over the first oxide semiconductor layer. The gate electrode is connected to a scan line or a signal line, the first wiring layer or the second wiring layer is directly connected to the gate electrode. | 2013-07-11 |
20130175526 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided. | 2013-07-11 |
20130175527 | SENSOR ARRANGEMENT, A MEASUREMENT CIRCUIT, CHIP-PACKAGES AND A METHOD FOR FORMING A SENSOR ARRANGEMENT - A sensor arrangement is provided, the sensor arrangement including a chip including a sensor circuit configured to detect a bending of the chip; and a package structure configured to protect the chip; wherein the package structure includes a first region and a second region, and wherein the package structure is configured such that it is easier to be deformed in the first region than in the second region. | 2013-07-11 |
20130175528 | CHIP ON FILM PACKAGE INCLUDING TEST PADS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern. | 2013-07-11 |
20130175529 | Semiconductor Diode and Method for Forming a Semiconductor Diode - A semiconductor diode is provided. The semiconductor diode includes a monocrystalline silicon semiconductor body including a first semiconductor region of a first conductivity type extending to a first surface of the semiconductor body and having a first maximum doping concentration, and a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region. The semiconductor diode further includes a polycrystalline silicon semiconductor region of the first conductivity type having a second maximum doping concentration which is higher than the first maximum doping concentration and adjoining the first semiconductor region on the first surface, a first metallization arranged on the polycrystalline silicon semiconductor region and in electric contact with the polycrystalline semiconductor region, and an edge-termination structure arranged next to the first semiconductor region. Further, a method for producing a semiconductor diode is provided. | 2013-07-11 |
20130175530 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a fin-type transistor having an oxide semiconductor in a channel formation region in which the channel formation region comprising an oxide semiconductor is three-dimensionally structured and a gate electrode is arranged to extend over the channel formation region. Specifically, the fin-type transistor comprises: an insulator protruding from a substrate plane; an oxide semiconductor film extending beyond the insulator; a gate insulating film over the oxide semiconductor film; and a gate electrode over and extending beyond the oxide semiconductor film. This structure allows the expansion of the width of the channel formation region, which enables the miniaturization and high integration of a semiconductor device having the transistor. Additionally, the extremely small off-state current of the transistor contributes to the formation of a semiconductor device with significantly reduced power consumption. | 2013-07-11 |
20130175531 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A pixel structure includes a substrate, a gate line, a data line, a semiconductor pattern, a non-metal source electrode pattern, a non-metal drain electrode pattern, and a pixel electrode. The gate line and the data line are disposed on the substrate. The semiconductor pattern is disposed on the gate line, and the semiconductor pattern overlaps two corresponding edges of the gate line along a vertical projective direction. The non-metal source electrode pattern and the non-metal drain electrode pattern are disposed on the semiconductor pattern. The non-metal source electrode pattern and the non-metal drain electrode pattern are respectively disposed on two corresponding edges of the gate line. The non-metal source electrode pattern is partially disposed between the data line and the gate line. The pixel electrode is electrically connected to the non-metal drain electrode pattern. | 2013-07-11 |
20130175532 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a pixel structure is provided. A thin film transistor is formed on a substrate and an insulating layer is formed to cover the substrate and the thin film transistor. The insulating layer is patterned by a half-tone mask to form a protruding pattern, a sunken pattern connecting the protruding pattern, and a contact window inside the sunken pattern. A transparent conductive layer is formed to cover the protruding pattern and the sunken pattern, and filled in the contact window. A passivation layer is formed to cover the transparent conductive layer. A pixel electrode pattern is formed from the transparent conductive layer by removing a part of the passivation layer located on the protruding pattern, a part of the transparent conductive layer on the protruding pattern, and a part of the passivation layer located within the contact window. A pixel structure manufactured by the method is provided. | 2013-07-11 |
20130175533 | Substrate Including Thin Film Transistors and Organic Light Emitting Display Apparatus Including the Substrate - A substrate includes a thin film transistor (TFT) which includes an active layer, a gate electrode, a source electrode, and a drain electrode; a first insulating layer disposed between the active layer and the gate electrode; a second insulating layer disposed between the gate electrode and the source and drain electrodes; a third insulating layer disposed on the second insulating layer, and including a first region for opening the second insulating layer and a second region for opening one of the source and drain electrodes, the first region and the second region being integrally connected; and a first electrode connected to one of the source and drain electrodes, and disposed so as to cover the first region and the second region. | 2013-07-11 |
20130175534 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are disclosed. In one embodiment, the semiconductor device includes a substrate, a first silicon nitride layer formed over the substrate, a first silicon oxide layer formed directly on the first silicon nitride layer and having a thickness of about 1000 Å or less, and a hydrogenated polycrystalline silicon layer formed directly on the first silicon oxide layer. | 2013-07-11 |
20130175535 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - In order to efficiently manufacture a semiconductor device having a plurality of TFTs formed thereon, which can be applied to a variety of uses, a semiconductor device ( | 2013-07-11 |
20130175536 | EL DISPLAY DEVICE, DRIVING METHOD THEREOF, AND ELECTRONIC EQUIPMENT PROVIDED WITH THE EL DISPLAY DEVICE - An EL display device capable of performing clear multi-gradation color display and electronic equipment provided with the EL display device are provided, wherein gradation display is performed according to a time-division driving method in which the luminescence and non-luminescence of an EL element ( | 2013-07-11 |
20130175537 | HIGH ELECTRON MOBILITY GaN-BASED TRANSISTOR STRUCTURE - A high electron mobility GaN-based transistor structure comprises a substrate, an epitaxial GaN layer formed on the substrate, at least one ohmic contact layer formed on the epitaxial GaN layer, a metallic gate layer formed on the epitaxial GaN layer, and a diffusion barrier layer interposed between the metallic gate layer and the epitaxial GaN layer. The diffusion barrier layer hinders metallic atoms of the metallic gate layer from diffusing into the epitaxial GaN layer, whereby are improved the electric characteristics and reliability of the GaN-based transistor. | 2013-07-11 |
20130175538 | SUBSTRATE STRUCTURE, SEMICONDUCTOR DEVICE FABRICATED FROM THE SAME, AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - According to example embodiments, a substrate structure may include a GaN-based third material layer, a GaN-based second material layer, a GaN-based first material layer, and a buffer layer on a non-GaN-based substrate. The GaN-based first material layer may be doped with a first conductive type impurity. The GaN-based second material layer may be doped with a second conductive type impurity at a density that is less than a density of the first conductive type impurity in the first GaN-based material layer. The GaN-based third material layer may be doped with a first conductive type impurity at a density that is less than the density of the first conductive type impurity of the GaN-based first material layer. After a second substrate is attached onto the substrate structure, the non-GaN-based substrate may be removed and a GaN-based vertical type semiconductor device may be fabricated on the second substrate. | 2013-07-11 |
20130175539 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer and a channel layer. The channel layer may include an effective channel region and a high resistivity region. The effective channel region may be between the high resistivity region and the channel supply layer. The high resistivity region may be a region into which impurities are ion-implanted. According to example embodiments, a method of forming a HEMT includes forming a device unit, including a channel layer and a channel supply layer, on a first substrate; adhering a second substrate to the device unit; removing the first substrate; and forming a high resistivity region by ion-implanting impurities into at least a portion of the channel layer. | 2013-07-11 |
20130175540 | DOPED DIAMOND LED DEVICES AND ASSOCIATED METHODS - LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode. | 2013-07-11 |
20130175541 | METHOD OF GROWING NITRIDE SEMICONDUCTOR LAYER - A method of growing a nitride semiconductor layer may include preparing a substrate in a reactor, growing a first nitride semiconductor on the substrate at a first temperature, the first nitride semiconductor having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate, and removing the substrate at a second temperature. | 2013-07-11 |
20130175542 | Group III-V and Group IV Composite Diode - In one implementation, a group III-V and group IV composite diode includes a group IV diode in a lower active die, the group IV diode having an anode situated on a bottom side of the lower active die. The group III-V and group IV composite diode also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a cathode of the group IV diode using a through-semiconductor via (TSV) of the upper active die. | 2013-07-11 |
20130175543 | COMPOSITE GaN SUBSTRATE, METHOD FOR MANUFACTURING COMPOSITE GaN SUBSTRATE, GROUP III NITRIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR DEVICE - A composite GaN substrate of the present invention includes: a conductive GaN substrate having a specific resistance of less than 1 Ωcm; and a semi-insulative GaN layer disposed on the conductive GaN substrate, having a specific resistance of 1×10 | 2013-07-11 |
20130175544 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - It is an object to attain both high gain and a broad band (that is, to attain both reduction in a gate-drain capacitance and reduction in a source-drain capacitance). Provided is a semiconductor device, including: a GaN channel layer ( | 2013-07-11 |
20130175545 | SEMICONDUCTOR DEVICE WITH STRAIN-INDUCING REGIONS AND METHOD THEREOF - Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions. | 2013-07-11 |
20130175546 | Diamond Semiconductor System and Method - Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein at least 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm | 2013-07-11 |
20130175547 | FIELD EFFECT TRANSISTOR DEVICE - A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material. | 2013-07-11 |
20130175548 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A fabrication method for a semiconductor device includes the step of forming a gate insulating film on the side of a trench, the bottom thereof, and the periphery thereof. The step of forming a gate insulating film includes a step of forming a first insulating film on the side of the trench and a step of forming a second insulating film on the bottom and periphery of the trench using a high-density plasma chemical vapor deposition method. The thickness of the portions of the gate insulating film formed on the bottom and periphery of the trench is made larger than that of the portion of the gate insulating film formed on the side of the trench. | 2013-07-11 |
20130175549 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 2013-07-11 |
20130175550 | Donor Film, Method for Manufacturing Organic Light Emitting Diode Display Using the Same, and Organic Light Emitting Diode Display Manufactured by Using the Method - In a donor film, an organic light emitting diode display manufacturing method using the same, and an organic light emitting diode display manufactured by using the method, the donor film includes a donor substrate and a transfer layer formed on the donor substrate. The donor substrate includes a base film, a light-to-heat conversion (LTHC) layer disposed on the base film, and a curved interlayer film provided on the light-to-heat conversion layer and having a wrinkled side. The transfer layer includes an organic emission layer which is formed so as to be curved along a shape of the wrinkled side of the curved interlayer film. | 2013-07-11 |
20130175551 | Packaging Method and System for LEDs - A slim LED package configured to handle large current, having a narrow width, an LED chip mounting area positioned centro-symmetrically within the package, mounting holes positioned equidistantly from the mounting area, wherein multiple packages may be arranged with alternating anode and cathode ends in such a manner that a high-power density radiometric flux line may be created. Some embodiments include current density management areas positioned on one more sides of the LED chip mounting area. | 2013-07-11 |
20130175552 | ARRAY SUBSTRATE AND MANUFACTURING METHOD - Manufacturing an array substrate includes forming data and gate lines which cross and a gate electrode on a substrate. The data line is discontinuously disposed to be separated from the gate line, or the gate line is discontinuously disposed to be separated from the data line. Active and gate insulating layers including bridge and source electrode vias are formed on the substrate. The bridge vias correspond to adjacent discontinuous sections of the data line or the gate line. The source electrode via corresponds to the data line. Pixel, source, and drain electrodes and a bridge line are formed on the substrate. The pixel electrode and the drain electrode are integral. The source electrode is connected to the data line through the source electrode via. The bridge line connects adjacent discontinuous sections of the data line or adjacent discontinuous sections of the gate line through bridge vias. | 2013-07-11 |
20130175553 | LIGHT-EMITTING DIODE DEVICE - The present invention is directed to a light-emitting diode (LED) device, which includes at least one LED unit. Each LED unit includes at least one LED, which includes a first doped layer, a second doped layer and a conductive defect layer. The conductive defect layer is formed on the first or second doped layer. The conductive defect layer may be deposited between two LEDs, or between the first/second doped layer and an electrode. | 2013-07-11 |
20130175554 | LED PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING LED PACKAGE - There is provided a light emitting diode (LED) package substrate including: a substrate including a chip mounting region on which a plurality of LED chips is mountable; a conductive layer including a plurality of electrode patterns disposed on the chip mounting region; and a groove part, forming a dam, wherein the groove part surrounds the chip mounting region and is spaced apart from the chip mounting region by a predetermined interval. | 2013-07-11 |
20130175555 | LIGHT EMITTING DIODE PACKAGE HAVING INTERCONNECTION STRUCTURES - A light emitting diode (LED) package includes a substrate, a first LED chip and a second LED chip. The substrate includes first to fourth electrodes, and an interconnection electrode. A mounting area is defined at center of a top surface of the substrate. The first to fourth electrodes are respectively in four corners of the substrate out of the mounting area. The first interconnection electrode is embedded in the substrate to electrically connect the first and the third electrodes. The first LED chip and the second LED chip are arranged in the mounting area. Each LED chip includes an anode pad and a cathode pad. The first to fourth electrodes are respectively connected to the four pads of the first and the second LED chips via a plurality of metal wires, and no metal wire connection is formed between the first and the second LED chips. | 2013-07-11 |
20130175556 | LIGHT EMITTING APPARATUS - A lighting apparatus comprising a plurality of diodes and an electrical interface configured to receive an electrical signal and transmit the electrical signal to the plurality of diodes is provided. | 2013-07-11 |
20130175557 | LIGHT EMITTING APPARATUS - A lighting apparatus comprising a plurality of diodes and an electrical interface configured to receive an electrical signal and transmit the electrical signal to the plurality of diodes is provided. | 2013-07-11 |
20130175558 | LED LIGHTING DEVICES - Packaged chip-on-board (COB) LED arrays are provided where a color conversion medium is distributed within a glass containment plate, rather than silicone, to reduce the operating temperature of the color conversion medium and avoid damage while increasing light output. In accordance with one embodiment of the present disclosure, a lighting device is provided comprising a chip-on-board (COB) light emitting diode (LED) light source, a light source encapsulant, a distributed color conversion medium, and a glass containment plate. The COB LED light source comprises a thermal heat sink framework and at least one LED and defines a light source encapsulant cavity in which the light source encapsulant is distributed over the LED. The glass containment plate is positioned over the light source encapsulant cavity and contains the distributed color conversion medium. The light source encapsulant is distributed over the LED at a thickness that is sufficient to encapsulate the LED and define encapsulant thermal conduction paths T | 2013-07-11 |
20130175559 | LED MODULE - An LED module | 2013-07-11 |
20130175560 | VERTICAL SOLID-STATE TRANSDUCERS AND SOLID-STATE TRANSDUCER ARRAYS HAVING BACKSIDE TERMINALS AND ASSOCIATED SYSTEMS AND METHODS - Solid-state transducers (“SSTs”) and SST arrays having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a first contact at the first side and electrically coupled to the first semiconductor material, and a second contact extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. A carrier substrate having conductive material can be bonded to the first and second contacts. | 2013-07-11 |
20130175561 | Light-Emitting Device - The invention relates to reducing effect of light that is emitted from a light-emitting element and then enters between a base and a frame member. A light-emitting device ( | 2013-07-11 |
20130175562 | SOLID-STATE RADIATION TRANSDUCER DEVICES HAVING AT LEAST PARTIALLY TRANSPARENT BURIED-CONTACT ELEMENTS, AND ASSOCIATED SYSTEMS AND METHODS - Solid-state radiation transducer (SSRT) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An SSRT device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material. The SSRT device can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. The second contact can include a plurality of buried-contact elements electrically coupled to the second semiconductor material. Individual buried-contact elements can have a transparent portion directly adjacent to the second semiconductor material. The second contact can further include a base portion extending between the buried-contact elements, such as a base portion that is least partially planar and reflective. | 2013-07-11 |
20130175563 | LED CHIP STRUCTURE, PACKAGING SUBSTRATE, PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - An LED package structure includes: a substrate having a die attach pad; a first insulating layer formed on the die attach pad and having a plurality of openings; an LED chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; a second insulating layer formed on the inactive surface and having a plurality of openings, wherein the LED chip is disposed on the substrate with the openings of the second insulating layer corresponding in position to the openings of the first insulating layer; and a plurality of metallic thermal conductive elements formed in the openings of the first insulating layer and the corresponding openings of the second insulating layer, thereby effectively alleviating the conventional problem of thermal stresses induced by a mismatch in CTEs of the LED chip and the substrate. | 2013-07-11 |
20130175564 | Optoelectronic Semiconductor Chip and Method for Producing an Optoelectronic Semiconductor Chip - In at least one embodiment, the optoelectronic semiconductor chip comprises a semiconductor layer sequence for generating an electromagnetic radiation, and also a silver mirror. The silver mirror is arranged at the semiconductor layer sequence. Oxygen is admixed with the silver of the silver mirror. A proportion by weight of the oxygen in the silver mirror is preferably at least 10 | 2013-07-11 |
20130175565 | LIGHT EMITTING DIODES WITH ENHANCED THERMAL SINKING AND ASSOCIATED METHODS OF OPERATION - Solid state lighting devices and associated methods of thermal sinking are described below. In one embodiment, a light emitting diode (LED) device includes a heat sink, an LED die thermally coupled to the heat sink, and a phosphor spaced apart from the LED die. The LED device also includes a heat conduction path in direct contact with both the phosphor and the heat sink. The heat conduction path is configured to conduct heat from the phosphor to the heat sink. | 2013-07-11 |
20130175566 | NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A nitride-based semiconductor light-emitting element includes a substrate and a nitride semiconductor multilayer structure. The nitride semiconductor multilayer structure includes a nitride semiconductor active layer which emits polarized light. Angle θ, which is formed by at least one of the plurality of lateral surfaces of the substrate with respect to the principal surface of the substrate, is greater than 90°. Angle θ | 2013-07-11 |
20130175567 | LIGHT EMITTING DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A light emitting device package and a method of manufacturing the light emitting device package are provided. A base is first provided and a hole is formed on the base. After a light emitting portion is formed on the base, a mold die is placed on the light emitting portion and a molding material is injected through the hole. The mold die is removed to complete the package. | 2013-07-11 |
20130175568 | METHOD FOR MANUFACTURING SEMICONDUCTOR BASE MATERIAL, SEMICONDUCTOR - In forming an etching mask for forming a repetitive concave-convex pattern on a surface of a substrate of a semiconductor base material by exposure development of a resist film, the present invention prevents a development pattern from being deformed due to excessive exposure on a part where exposure regions are adjacent to each other in the resist film by repetitive exposure. In a method for manufacturing a semiconductor base material, when forming an etching mask for forming a concave-convex portion on a surface of the semiconductor base material, by a photolithography process of the resist film, a transfer mask is used, as a transfer mask | 2013-07-11 |
20130175569 | LED Lighting Device - The invention involves a lighting device ( | 2013-07-11 |
20130175570 | LED Lamp - An LED lamp includes a housing, and a base plate combined with the housing. The base plate is integrally combined with the housing by injection molding so that the base plate and the housing are combined closely and solidly and will not detach from each other. | 2013-07-11 |
20130175571 | SEMICONDUCTOR LIGHT EMITTING ELEMENT, METHOD FOR PRODUCING SEMICONDUCTOR LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE - In a semiconductor light emitting element | 2013-07-11 |
20130175572 | LIGHT-EMITTING DIODE CHIP - A light-emitting diode (LED) chip comprising a first semiconductor layer; an active layer disposed on said first semiconductor layer; a second semiconductor layer disposed on said active layer; metal layers which disposed on said second semiconductor layer and overlapped with each other indirectly, comprising a first metal layer which connected to a first electrode deposited on said first semiconductor, and a second metal layer which connected to a transparent conductive layer and a second electrode deposited on said second semiconductor layer; wherein said second metal layer deposited on said first metal layer which further connected to said first semiconductor layer through an indentation. | 2013-07-11 |
20130175573 | LIGHT-EMITTING DIODE CHIP AND METHOD FOR PRODUCING A LIGHT-EMITTING DIODE CHIP - The invention relates to a light-emitting diode chip, comprising an n-type semiconductor layer ( | 2013-07-11 |
20130175574 | IE TYPE TRENCH GATE IGBT - In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween. | 2013-07-11 |
20130175575 | EFFICIENT IGBT SWITCHING - Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed. | 2013-07-11 |
20130175576 | Systems, Devices, and Methods with Integrable FET-Controlled Lateral Thyristors - Methods and systems for lateral switched-emitter thyristors in a single-layer implementation. Lateral operation is advantageously achieved by using an embedded gate. Embedded gate plugs are used to controllably invert a portion of the P-base region, so that the electron population at the portion of the inversion layer which is closest to the anode will provide a virtual emitter, and will provide sufficient gain so that the combination of bipolar devices will go into latchup. | 2013-07-11 |
20130175577 | NFET Device with Tensile Stressed Channel Region and Methods of Forming Same - Disclosed herein is an NFET device with a tensile stressed channel region and various methods of making such an NFET device. In one example, the NFET transistor includes a semiconducting substrate, a first layer of semiconductor material positioned above the substrate, a second capping layer of semiconductor material positioned above the first layer of semiconductor material and a gate electrode structure positioned above the second capping layer of semiconductor material. | 2013-07-11 |
20130175578 | IO ESD Device and Methods for Forming the Same - A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode. | 2013-07-11 |
20130175579 | TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN - A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer. | 2013-07-11 |
20130175580 | GALLIUM NITRIDE POWER DEVICES - Enhancement mode III-nitride devices are described. The | 2013-07-11 |
20130175581 | ZENER DIODE IN A SIGE BICMOS PROCESS AND METHOD OF FABRICATING THE SAME - A zener diode in a SiGe BiCMOS process is disclosed. An N-type region of the zener diode is formed in an active region and surrounded by an N-deep well. A pseudo buried layer is formed under each of the shallow trench field oxide regions on a corresponding side of the active region, and the N-type region is connected to the pseudo buried layers via the N-deep well. The N-type region has its electrode picked up by deep hole contacts. A P-type region of the zener diode is formed of a P-type ion implanted region in the active region. The P-type region is situated above and in contact with the N-type region, and has a doping concentration greater than that of the N-type region. The P-type region has its electrode picked up by metal contact. A method of fabricating zener diode in a SiGe BiCMOS process is also disclosed. | 2013-07-11 |
20130175582 | IMAGE SENSORS INCLUDING COLOR ADJUSTMENT PATH - An image sensor includes a transfer transistor including a vertical gate portion extending in a depth direction of a substrate in an active region of the substrate and photodiode regions located at positions of different depths with respect to a top surface of the substrate in the active region. At least one color adjustment path extends between at least two photodiode regions of the photodiode regions and provides a charge movement path between the at least two photodiode regions. | 2013-07-11 |
20130175583 | SEMICONDUCTOR DEVICES HAVING DIELECTRIC CAPS ON CONTACTS AND RELATED FABRICATION METHODS - Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure involves forming a first layer of a first dielectric material overlying a doped region formed in a semiconductor substrate, forming a first conductive contact electrically connected to the doped region within the first layer, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and a gate structure overlying the semiconductor substrate, and forming a second conductive contact electrically connected to the gate structure within the second layer. | 2013-07-11 |
20130175584 | FinFETs and the Methods for Forming the Same - A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region. | 2013-07-11 |
20130175585 | Methods of Forming Faceted Stress-Inducing Stressors Proximate the Gate Structure of a Transistor - Disclosed herein are various methods of forming faceted stress-inducing stressors proximate the gate structure of a transistor. In one example, a method includes forming a first recess in an active region of a semiconducting substrate, forming a first semiconductor material in the first recess and forming a gate structure above the first semiconductor material. In this example, the method includes the additional steps of performing a crystalline orientation-dependent etching process on the first semiconductor material to define a plurality of second recesses proximate the gate structure, wherein each of the second recesses has a faceted edge, and forming a first region of stress-inducing semiconductor material in each of the second recesses, wherein each of the first regions of stress-inducing semiconductor material has a faceted edge that engages a corresponding faceted edge in one of the second recesses. | 2013-07-11 |
20130175586 | SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a fin-type semiconductor region on a substrate; and introducing an n-type impurity into at least a side of the fin-type semiconductor region by a plasma doping process, thereby forming an n-type impurity region in the side of the fin-type semiconductor region. In the introducing the n-type impurity, when a source power in the plasma doping process is denoted by a character Y [W], the supply of a gas containing the n-type impurity per unit time and per unit volume is set greater than or equal to 5.1×10 | 2013-07-11 |
20130175587 | SELF-ALIGNED CONTACT FOR REPLACEMENT GATE DEVICES - A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure. | 2013-07-11 |
20130175588 | COHERENT SPIN FIELD EFFECT TRANSISTOR - A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° K to provide a few monolayer thick layer. Where the gate is cobalt, the resulting magnetic oxide is Co | 2013-07-11 |
20130175589 | DECOUPLING CAPACITOR AND METHOD OF MAKING SAME - A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns. | 2013-07-11 |
20130175590 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM, AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: an element isolation region formed in a substrate that defines an active region, a conductive layer formed on the active region, a first insulating film formed between the active region and the conductive layer and having a first thickness, and a second insulating film formed between the active region and the conductive layer and spans at least part of a boundary between the active region and the element isolation region and having a second thickness which is greater than the first thickness. | 2013-07-11 |
20130175591 | CAPACITIVE DEVICE, SEMICONDUCTOR UNIT, AND ELECTRONIC APPARATUS - A capacitive device includes: a first capacitive element including a first well region having a first conduction type, a first gate electrode, and first semiconductor layers each formed of an impurity layer having a second conduction type opposite to a conduction type of the first well region; and a second capacitive element electrically connected in parallel to the first capacitive element, the second capacitive element including a second well region having the first conduction type, a second gate electrode, and second semiconductor layers each formed of an impurity layer having the same first conductive type as a conduction type of the second well region. | 2013-07-11 |
20130175592 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes, a semiconductor substrate, a plurality of memory cells being provided on the semiconductor substrate in a memory cell region. Each of the plurality of memory cells having a first gate electrode disposed on the semiconductor substrate with a first gate insulating film, and the first gate electrode having a first charge storage layer, a first inter-electrode insulating film and a first control gate electrode film, and a cavity is interposed between an upper surface of the charge storage layer and the inter-electrode insulating film. | 2013-07-11 |
20130175593 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL - An electronic device can include a nonvolatile memory cell that includes a capacitor, a tunnel structure, a state transistor, and an access transistor. In an embodiment, the capacitor and tunnel structure can include upper electrodes, wherein the upper electrode of the capacitor has a first conductivity type, and the upper electrode of the tunnel structure includes at least a portion that has a second conductivity type opposite the first conductivity type. In another embodiment, a process of forming the nonvolatile memory is performed using a single poly process. In a further embodiment, charge carriers can tunnel through a gate dielectric layer of the state transistor during programming and tunnel through a tunnel dielectric of the tunnel transistor during erasing. | 2013-07-11 |
20130175594 | INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC - An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region. | 2013-07-11 |
20130175595 | INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC - An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed. | 2013-07-11 |
20130175596 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer. | 2013-07-11 |
20130175597 | NANOWIRE FLOATING GATE TRANSISTOR - A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer. | 2013-07-11 |
20130175598 | Damascene Word Line - The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches. | 2013-07-11 |
20130175599 | INLINE METHOD TO MONITOR ONO STACK QUALITY - Embodiments of structures and methods for determining operating characteristics of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer are described. In one embodiment, the method comprises: forming on a substrate a structure including a nitrided tunneling-layer and a charge-storage-layer overlying the tunneling-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a anti-tunneling layer comprising an oxide; depositing a positive charge on the charge-storage-layer and determining a first voltage to establish a first leakage current through the charge-storage-layer and the tunneling-layer; depositing a negative charge on the charge-storage-layer and determining a second voltage to establish a second leakage current through the charge-storage-layer and the tunneling-layer; and determining a differential voltage by calculating a difference between the first and second voltages. | 2013-07-11 |
20130175600 | SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER - Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed. | 2013-07-11 |
20130175601 | FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS - A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer. | 2013-07-11 |
20130175602 | Non-Volatile Memory Device Having Three Dimensional, Vertical Channel, Alternately Stacked Gate Electrode Structure - A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel. | 2013-07-11 |
20130175603 | VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels. | 2013-07-11 |
20130175604 | NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION - An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer. | 2013-07-11 |
20130175605 | FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT - A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials. | 2013-07-11 |
20130175606 | INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 2013-07-11 |
20130175607 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device is provided. The semiconductor device includes a substrate having a first doping region and an overlying second doping region, wherein the first and second doping regions have a first conductivity type and wherein the second doping region has at least one first trench and at least one second trench adjacent thereto. A first epitaxial layer is disposed in the first trench and has a second conductivity type. A second epitaxial layer is disposed in the second trench and has the first conductivity type, wherein the second epitaxial layer has a doping concentration greater than that of the second doping region and less than that of the first doping region. A gate structure is disposed on the second trench. A method of fabricating a semiconductor device is also disclosed. | 2013-07-11 |
20130175608 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device is provided. The semiconductor device includes a plurality of first epitaxial layers, a second epitaxial layer and a gate structure. The plurality of first epitaxial layers is stacked on a substrate and has a first conductivity type. Each first epitaxial layer includes at least one first doping region and at least one second doping region adjacent thereto. The first doping region has a second conductivity and the second doping region has the first conductivity type. The second epitaxial layer is disposed on the plurality of first epitaxial layers, having the first conductivity type. The second epitaxial layer has a trench therein and a third doping region having the second conductivity type is adjacent to a sidewall of the trench. The gate structure is disposed on the second epitaxial layer above the second doping region. A method of fabricating a semiconductor device is also disclosed. | 2013-07-11 |
20130175609 | Semiconductor Device with a Low Ohmic Current Path - A semiconductor device includes a semiconductor substrate having a main horizontal surface, a back surface arranged opposite the main horizontal surface, a vertical transistor structure including a doped region and a control electrode arranged next to the main horizontal surface, an insulating region arranged at or close to the back surface, a deep vertical trench extending from the main horizontal surface through the semiconductor substrate and to the insulating region, an insulating layer arranged on a side wall of the deep vertical trench, and a low ohmic current path extending at least partially along the insulating layer and between the main horizontal surface and the back surface. A first metallization is in ohmic contact with the doped region and arranged on the main horizontal surface. A control metallization is arranged on the back surface and in ohmic contact with the control electrode via the low ohmic current path. | 2013-07-11 |
20130175610 | TRANSISTOR WITH STRESS ENHANCED CHANNEL AND METHODS FOR FABRICATION - A transistor device and methods for its fabrication are provided. In an embodiment, the transistor is fabricated within and on a surface of a semiconductor substrate. The method includes forming a gate structure with a dummy gate electrode material overlying the semiconductor substrate. Recesses are etched into the semiconductor substrate adjacent the gate structure to define a narrow region between the recesses at a selected depth under the surface. The recesses are filled with a stress-inducing material and the dummy gate electrode material is removed to expose the semiconductor substrate. The method further provides for etching the exposed semiconductor substrate to form a recessed gate surface and defining a channel under the recessed gate surface in the narrow region. | 2013-07-11 |
20130175611 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate. | 2013-07-11 |