27th week of 2010 patent applcation highlights part 12 |
Patent application number | Title | Published |
20100171123 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus includes a gate electrode, a first insulating layer pattern formed over the gate electrode, a second insulating layer pattern formed over the first insulating layer pattern, exposing a portion of the first insulating layer, a semiconductor film pattern formed over the second insulating layer pattern and over the first insulating layer pattern, an impurity-doped semiconductor film pattern formed on the semiconductor film pattern, wherein the impurity-doped semiconductor film pattern contacts the top surface of the semiconductor film pattern and exposes a portion of the semiconductor film pattern formed over the gate electrode, a source electrode and a drain electrode each formed over a portion of the impurity doped semiconductor film pattern, a protection film pattern formed over the source electrode and the drain electrode in a TFT area, the protection film pattern having a contact hole over the drain electrode, a pixel electrode pattern formed on the protection film pattern and_electrically connected to the drain electrode. | 2010-07-08 |
20100171124 | Low-defect density gallium nitride semiconductor structures and fabrication methods - A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer. | 2010-07-08 |
20100171125 | Thin film light emitting diode - Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition. | 2010-07-08 |
20100171126 | In situ dopant implantation and growth of a Ill-nitride semiconductor body - In one embodiment a method enabling in situ dopant implantation during growth of a III-nitride semiconductor body, comprises establishing a growth environment for the III-nitride semiconductor body in a composite III-nitride chamber having a dopant implanter and a growth chamber, growing the III-nitride semiconductor body in the growth chamber, and implanting the III-nitride semiconductor body in situ in the growth chamber using the dopant implanter. A semiconductor device produced using the disclosed method comprises a III-nitride semiconductor body having a first conductivity type formed over a support substrate, and at least one doped region produced by in situ dopant implantation of the III-nitride semiconductor body during its growth, that at least one doped region having a second conductivity type. | 2010-07-08 |
20100171127 | OPTICALLY COUPLED DEVICE AND METHOD OF MANUFACTURING THE SAME - An optically coupled device includes a light emitting element and a light receiving element which are electrically isolated from each other, and an optical waveguide allowing therethrough transmission of light from the light emitting element to the light receiving element, wherein the optical waveguide is covered with an encapsulation resin containing a light reflective inorganic particle which is typically composed of titanium oxide, the light emitting element and the light receiving element are respectively provided on a base (for example, package terminals), and the entire portion of the outer surface of the optical waveguide, brought into contact with none of the light emitting element, the light receiving element and the base, is covered with the encapsulation resin. | 2010-07-08 |
20100171128 | PHOTODETECTOR AND DISPLAY DEVICE PROVIDED WITH THE SAME - Provided are a photodetector capable of suppressing variations in the output characteristics among photodiodes, and a display device provided with the photodetector. A display device in use has an active matrix substrate ( | 2010-07-08 |
20100171129 | ACTIVE MATRIX SUBSTRATE, ELECTROPHORETIC DISPLAY APPARATUS, AND ELECTRONIC DEVICE - An active matrix substrate includes a substrate; a plurality of data lines provided on the substrate; a plurality of scanning lines provided to cross the data lines on the substrate when seen in a plan view; a thin film transistor that is electrically connected to one of the plurality of data lines and one of the plurality of scanning lines and has an organic semiconductor layer; a pixel electrode electrically connected to the thin film transistor; and a capacitive element electrically connected in parallel with the thin film transistor between the data line and the pixel electrode. | 2010-07-08 |
20100171130 | Semiconductor device and fabrication method - A semiconductor device comprising a plurality of regions of semiconductor material forming a junction at an interface there-between, the junction including a depletion region having a width which varies spatially in at least one direction along the depletion region. Without limitation, the spatial variation in depletion region width is provided by ionised dopants having a concentration which varies spatially along said at least one direction. Alternatively, or in addition, the spatial variation in depletion region width is achieved by varying the thickness of the region(s) of semiconductor spatially along said at least one direction, for example by creating a plurality of cells within said region(s) devoid of said semiconductor material. A method of fabricating a semiconductor device comprising the step of varying the width of the depletion region spatially there-within in at least one direction along the depletion region. | 2010-07-08 |
20100171131 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - An electro-optical device includes a first light shielding film; a transistor element formed on the first light shielding film to overlap the first light shielding film; a second light shielding film formed on the transistor element to overlap the transistor element and electrically connected to an input terminal of the transistor element; a transparent conductive film extended toward an upper layer side of the second light shielding film in an opening region, through which light penetrates, of the display region; a dielectric film formed on the transparent conductive film in the opening region; and a transparent pixel electrode formed on the dielectric film in the opening region, constituting a storage capacitor together with the transparent conductive film and the dielectric film, and having a transparent pixel electrode which is electrically connected to the transistor element. | 2010-07-08 |
20100171132 | LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A light-emitting device is provided. The light-emitting device comprises a light-emitting layer having a first quaternary clad layer with a first material having a first composition ratio and a second material having a second composition ratio, a second quaternary clad layer with a third material having a third composition ratio and a fourth material having a fourth composition ratio, and an activation layer contacted with first clad layer and the second clad layer between them; a first electrode electrically contacted with the light-emitting layer; and, a second electrode electrically contacted with the light-emitting layer, wherein the first quaternary clad layer and the second quaternary clad layer have a predetermined energy band gap by controlling the first, second, third and fourth composition ratio, for removing the piezoelectric field and spontaneous polarization applied to the activation layer. | 2010-07-08 |
20100171133 | CAPSULAR MICRO LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a capsular micro light-emitting device and a method for manufacturing the same. The capsular micro light-emitting device includes a light emitting part having at least a light emitting layer | 2010-07-08 |
20100171134 | OPTICAL CONVERTER AND MANUFACTURING METHOD THEREOF AND LIGHT EMITTING DIODE - The present invention relates to an optical converter and a manufacturing method thereof and a light emitting diode. An optical converter for a light emitting diode includes two substrates, in which, a annular first cavity wall is arranged between the two substrates, and an airtight space filled with an optical conversion substance is surrounded by the first cavity wall and the two substrates. The invention implements the encapsulation and manufacturing of the optical conversion substance for the LED. The structure and the manufacturing method according to the invention can be utilized to encapsulate an active optical conversion substance in the optical converter while avoiding the active optical conversion substance reacting to other active substance, e.g., oxygen, during manufacturing. Furthermore, the optical conversion substance is encapsulated with wafer level chip size packaging to thereby improve the efficiency of manufacturing the optical converter and reduce the cost. | 2010-07-08 |
20100171135 | Optoelectronic Semiconductor Body and Method for Producing the Same - The invention relates to an opto-electronic semiconductor body having a semiconductor layer sequence ( | 2010-07-08 |
20100171136 | LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - The present invention provides a method of fabricating a light emitting diode, which comprises the steps of forming a compound semiconductor layer on a substrate, the compound semiconductor layer including a lower semiconductor layer, an active layer and an upper semiconductor layer; and scratching a surface of the substrate by rubbing the substrate with an abrasive. According to the present invention, the abrasive is used to rub and scratch the surface of the light emitting diode, thereby making it possible to cause the light emitted from the active layer to effectively exit to the outside. Therefore, the light extraction efficiency of the light emitting diode can be improved. | 2010-07-08 |
20100171137 | LIGHT EMITTING DEVICE AND LAYERED LIGHT EMITTING DEVICE - A light emitting device includes a support part, a first cladding layer formed above the support part, an active layer formed above the first cladding layer, a second cladding layer formed above the active layer, and a reflective part formed above the support part and separated from the active layer. At least a portion of the active layer constitutes a plurality of gain regions. Each of the plurality of gain regions is provided at an angle with respect to a line normal to a first lateral surface of the active layer, from the first lateral surface to a second lateral surface of the active layer that is parallel to the first lateral surface. The plurality of gain regions forms at least one gain region pair. A first gain region that is one of the gain region pair is provided in one direction. A second gain region that is the other of the gain region pair is provided in another direction different from the one direction. At least a portion of an end surface of the first gain region, the end surface being located on the side of the second lateral surface, and at least a portion of an end surface of the second gain region, the end surface being located on the side of the second lateral surface, overlap with each other. Light emitted from the end surface of the first gain region, the end surface being located on the side of the first lateral surface, is reflected by the reflective part, and propagates in the same direction or in the focusing direction with light emitted from the end surface of the second gain region, the end surface being located on the side of the first lateral surface. | 2010-07-08 |
20100171138 | Light Emitting Device and Electronic Device - Thinned and highly reliable light emitting elements are provided. Further, light emitting devices in which light emitting elements are formed over flexible substrates are manufactured with high yield. One light emitting device includes a flexible substrate, a light emitting element formed over the flexible substrate, and a resin film covering the light emitting element, and in the light emitting element, an insulating layer serving as a partition has a convex portion and the convex portion is embedded in the resin film, that is, the resin film covers an entire surface of the insulating layer and an entire surface of the second electrode, whereby the light emitting element can be thinned and highly reliable. In addition, a light emitting device can be manufactured with high yield in a manufacturing process thereof. | 2010-07-08 |
20100171139 | LIGHT EMITTING DEVICE - A light emitting device includes: a light emitting element;
| 2010-07-08 |
20100171140 | SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a semiconductor light emitting device that minimizes reflection or absorption of emitted light, maximizes luminous efficiency with the maximum light emitting area, enables uniform current spreading with a small area electrode, and enables mass production with high reliability and high quality. A semiconductor light emitting device according to an aspect of the invention includes first and second conductivity type semiconductor layers, an active layer formed therebetween, first electrode layer, and a second electrode part electrically connecting the semiconductor layers. The second electrode part includes an electrode pad unit, an electrode extending unit, and an electrode connecting unit connecting the electrode pad unit and electrode extending unit. | 2010-07-08 |
20100171141 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a silicon substrate, a p-type semiconductor layer provided on the silicon substrate, a n-type semiconductor layer provided on the silicon substrate, the n-type semiconductor layer adjoining the p-type semiconductor layer, and a light emitting section formed at a p-n homojunction between the p-type semiconductor layer and the n-type semiconductor layer. The p-n homojunction is substantially perpendicular to a major surface of the silicon substrate. The p-n homojunction is corrugated with a period matched with an integer multiple of an emission wavelength at the light emitting section. | 2010-07-08 |
20100171142 | Embedding type solder point-free combination structure of LED beads with substrate or lamp body - This invention relates to an embedding type solder point-free combination structure of LED beads with substrate or lamp body, in which the LED chip is packaged on the embedded heat conductive socket to form embedding type LED beads without soldering for electric conduction, and the embedding type LED beads are fixed in the docking hole of the substrate or the lamp body by a detachable dock-fixing structure. Furthermore, the embedding type LED beads has elastic conductive pieces, while the substrate or lamp body has conductive contacts. The elastic conductive pieces of the embedding type LED beads and the conductive contacts provided on the substrate or lamp body are in close contact to form solder point-free structure when the embedding type LED beads are fixed in the docking hole of the substrate or lamp body by the dock-fixing structure. In this manner, it is convenient to mount or dismount the embedding type LED beads in case of maintenance needed. | 2010-07-08 |
20100171143 | LIGHT EMITTING DIODE PACKAGE - There is provided an LED package having high heat dissipation efficiency. An LED package according to an aspect of the invention may include: a package body including a first groove portion being recessed into the package body and provided as a mounting area on the top of the package body; first and second lead frames arranged on a lower surface of the first groove portion while parts of the first and second lead frames are exposed; an LED chip mounted onto the lower surface of the first groove portion and electrically connected to the first and second lead frames; and a plurality of heat dissipation patterns provided on the bottom of the package body and formed of carbon nanotubes. | 2010-07-08 |
20100171144 | LIGHT EMITTING DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF - Provided is a light emitting device package. The light emitting device package comprises a housing, first and second lead frames, and a light emitting device. The housing comprises a front opening and side openings. The first and second lead frames pass through the housing to extend to an outside. A portion of each lead frame being exposed through the front opening. The light emitting device is in the front opening and electrically connected to the first and second lead frames. A protrusion protruding in a direction of the side opening is formed on an inner surface of the side opening. | 2010-07-08 |
20100171145 | LED PACKAGE METHODS AND SYSTEMS - Methods and systems are provided for LED modules that include an LED die integrated in an LED package with a submount that includes an electronic component for controlling the light emitted by the LED die. The electronic component integrated in the s submount may include drive hardware, a network interface, memory, a processor, a switch-mode power supply, a power facility, or another type of electronic component. | 2010-07-08 |
20100171146 | OPTICAL SEMICONDUCTOR-SEALING COMPOSITION - The present invention provides an optical semiconductor encapsulating composition comprising (A) an epoxy compound, (B) a carboxylic anhydride curing agent, (C) a curing accelerator, and (D) surface-coated silica particles having an average particle diameter of 5 to 50 nm in which 0.2 to 3 mmol of a silane coupling agent (D2) that contains an epoxy group-containing silane coupling agent (d1) is reacted with 1 g of silica particles (D1) to surface-coat the silica particles, the epoxy group being converted into a hydroxyl group through ring opening; and an optical semiconductor device in which an optical semiconductor is encapsulated with the composition. | 2010-07-08 |
20100171147 | Method of Manufacturing Organic Electroluminescent Device and Organic Electroluminescent Device - An organic electroluminescent device, which, on a substrate, has a plurality of first electrodes, and a second electrode opposing the plurality of first electrodes. The organic electroluminescent device also including a light-emitting functional layer between the second electrode and one of the first electrodes and a buffering layer that covers the second electrode. The buffering layer having a side end portion with an angle equal to or less than 30°. The organic electroluminescent device further including a gas barrier layer that covers the buffering layer. | 2010-07-08 |
20100171148 | SEMICONDUCTOR DEVICES - A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N− well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N− well, a P+ diffusion region in contact with the N− well, and shallow trench isolation structures between the N+ and P+ diffusion regions. | 2010-07-08 |
20100171149 | SYMMETRICAL BI-DIRECTIONAL SEMICONDUCTOR ESD PROTECTION DEVICE - A 2-terminal (i.e., anode, cathode) symmetrical bidirectional semiconductor electrostatic discharge (ESD) protection device is disclosed. The symmetrical bidirectional semiconductor ESD protection device design comprises a first and second shallow wells symmetrically spaced apart from a central floating well. Respective shallow wells comprise a first and second highly doped contact implant with opposite doping types (e.g., n-type, p-type). One or more field plates, connected to the central floating well, extend laterally outward from above the central well. The device can be used as an ESD protection device at a bidirectional I/O (e.g., in parallel with a symmetrical MOS to be protected). Upon an ESD event at an input node comprising the first and second shallow wells, a coupled npn-pnp bipolar component comprising the center well, the first and second shallow wells, and the first and second contact implants, is triggered, thereby shunting current from the first to the second shallow well. | 2010-07-08 |
20100171150 | METHODS OF FABRICATING TRANSISTORS INCLUDING DIELECTRICALLY-SUPPORTED GATE ELECTRODES AND RELATED DEVICES - Transistors are fabricated by forming a protective layer having a first opening extending therethrough on a substrate, forming a dielectric layer on the protective layer having a second opening extending therethrough that is wider than the first opening, and forming a gate electrode in the first and second openings. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. Related devices and fabrication methods are also discussed. | 2010-07-08 |
20100171151 | HETEROJUNCTION BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF - An HBT according to this invention includes: a sub-collector layer; a collector layer formed on the sub-collector layer and the base layer including a first collector layer, a second collector layer, a third collector layer, and a fourth collector layer. The first collector layer is formed on the sub-collector layer, and is made of semiconductor different from semiconductor of which the second to the fourth collector layers are made. The fourth collector layer is formed on the first collector layer, and has an impurity concentration lower than an impurity concentration of the second collector layer. The second collector layer is formed on the fourth collector layer, and has an impurity concentration lower than an impurity concentration of the sub-collector layer and higher than an impurity concentration of the third collector layer. The third collector layer is formed between the second collector layer and the base layer. | 2010-07-08 |
20100171152 | INTEGRATED CIRCUIT INCORPORATING DECODERS DISPOSED BENEATH MEMORY ARRAYS - A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate. | 2010-07-08 |
20100171153 | METHOD AND STRUCTURE OF MONOLITHICALLY INTEGRATED PRESSURE SENSOR USING IC FOUNDRY-COMPATIBLE PROCESSES - A monolithically integrated MEMS pressure sensor and CMOS substrate using IC-Foundry compatible processes. The CMOS substrate is completed first using standard IC processes. A diaphragm is then added on top of the CMOS. In one embodiment, the diaphragm is made of deposited thin films with stress relief corrugated structure. In another embodiment, the diaphragm is made of a single crystal silicon material that is layer transferred to the CMOS substrate. In an embodiment, the integrated pressure sensor is encapsulated by a thick insulating layer at the wafer level. The monolithically integrated pressure sensor that adopts IC foundry-compatible processes yields the highest performance, smallest form factor, and lowest cost. | 2010-07-08 |
20100171154 | Silicon-On-Insulator Junction Field-Effect Transistor Having A Fully Depleted Body and Fabrication Method Therefor - Silicon-on-insulator JFET (SOI JFET) having a fully depleted body and fabrication methods therefor. SOI JFETs offer leakage advantages over bulk silicon JFETs. However, some SOI JFETs have poor switching characteristics (e.g., high switch on time). The devices and techniques include a fully-depleted body SOI-JFET, with improved switching characteristic over partially-depleted SOI JFET or bulk silicon devices. In one example, by tuning the thickness of the silicon containing layer of the SOI substrate, the body region of the JFET can be fully depleted during the OFF-state thus offering the performance benefits of suppressed leakage current. Additionally, improved AC performance (e.g., faster switching time) is achieved. | 2010-07-08 |
20100171155 | Body-biased Silicon-On-Insulator Junction Field-Effect Transistor Having A Fully Depleted Body and Fabrication Method Therefor - Silicon-on-insulator JFET having a body bias and a fully depleted body and fabrication methods therefore are disclosed. SOI JFETs offer leakage advantages over bulk silicon JFETs. However, some SOI JFETs have poor switching characteristics (e.g., high switch on time), and have poor leakage performance at high temperatures. The techniques herein introduced include a fully-depleted body SOI-JFET, with a non-zero bias applied to its body. In one example, the body region of the JFET can be fully depleted by tuning the thickness of the silicon containing layer of the SOI substrate. Additionally, the deep depletion can be induced by applying a non-zero bias to the body region, at a range of operating temperatures. Full body depletion and/or the application of body bias offers the benefits of suppressed leakage current at higher operating temperatures (e.g., between or above 25-115 C) and improved AC performance (e.g., faster switching time). | 2010-07-08 |
20100171156 | Method for Forming Semiconductor Contacts - In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension. | 2010-07-08 |
20100171157 | IMAGE SENSOR WITH COMPACT PIXEL LAYOUT - Solid-state image sensors, specifically image sensor pixels, which have three or four transistors, high sensitivity, low noise, and low dark current, are provided. The pixels have separate active regions for active components, row-shared photodiodes and may also contain a capacitor to adjust the sensitivity, signal-to-noise ratio and dynamic range. The low dark current is achieved by using pinned photodiodes. | 2010-07-08 |
20100171158 | METHOD OF FORMING FERROMAGNETIC MATERIAL, TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - The present invention provides a method of forming a ferromagnetic material, characterized by including: forming a magnetic element layer | 2010-07-08 |
20100171159 | LAYOUT OF SEMICONDUCTOR DEVICE - A layout of a semiconductor device is disclosed, which forms one transistor in one active region to reduce the number of occurrences of a bridge encountered between neighboring layers, thereby improving characteristics of the semiconductor device. Specifically, the landing plug connected to the bit line contact is reduced in size, so that a process margin of word lines is increased to increase a channel length, thereby reducing the number of occurrences of a bridge encountered between the landing plug and the word line. | 2010-07-08 |
20100171160 | SEMICONDUCTOR MEMORY - A semiconductor memory includes a DRAM having, as seen in planar view, a first bit line and a second bit line formed on a first active area, a first cell contact formed on the first active area, and a first capacitor contact formed on the first cell contact and which is connected to a capacitor. As seen in planar view, the first cell contact is positioned closer to the second bit line than to the first bit line, and the first capacitor contact is formed offset in a direction approaching the first bit line with respect to the first cell contact. | 2010-07-08 |
20100171161 | DOUBLE-IMPLANT NOR FLASH MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved. | 2010-07-08 |
20100171162 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - Each of memory strings comprising: a first semiconductor layer having a pair of columnar portions extending in a vertical direction to a substrate and a joining portion formed to join lower ends of the pair of columnar portions; an electric charge accumulation layer formed to surround a side surface of the first semiconductor layer; and a first conductive layer formed to surround a side surface of the electric charge accumulation layer. The columnar portions are aligned at a first pitch in a first direction orthogonal to the vertical direction, and arranged in a staggered pattern at a second pitch in a second direction orthogonal to the vertical and first directions. The first conductive layers are configured to be arranged at the first pitch in the first direction, and extend to curve in a wave-like fashion in the second direction along the staggered-pattern arrangement. | 2010-07-08 |
20100171163 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES INCLUDING SELECT GATE PATTERNS HAVING DIFFERENT WORK FUNCTION FROM CELL GATE PATTERNS - A three-dimensional semiconductor device includes a vertical channel pattern on the substrate, a plurality of cell gate patterns and a select gate pattern stacked on the substrate along the sidewall of the vertical channel pattern, a charge storage pattern between the vertical channel pattern and the cell gate pattern and a select gate pattern between the vertical channel pattern and the select gate pattern. The select gate pattern has a different work function from the cell gate pattern | 2010-07-08 |
20100171164 | Nonvolatile semiconductor memory device and method of manufacturing the same - A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material. | 2010-07-08 |
20100171165 | NON-VOLATILE MEMORY - A non-volatile memory including a substrate, two first conductive layers, a second conductive layer, a first dielectric layer, a second dielectric layer and two heavily doped regions is provided. The substrate has at least two isolation structures therein and an active region between the isolation structures. The first conductive layers are respectively disposed on the isolation structures. The second conductive layer is disposed on the substrate and covering a portion of the active region and a portion of each first conductive layer. The first dielectric layer is disposed between each first conductive layer and the second conductive layer. The second dielectric layer is disposed between the second conductive layer in the active region and the substrate. The heavily doped regions are disposed in the substrate beside the second conductive layer in the active region. | 2010-07-08 |
20100171166 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A non-volatile memory device and a method of fabricating the same are provided. The method can include disposing an isolation layer on a semiconductor substrate. The isolation layer may protrude from the main surface of the semiconductor substrate and define an active region. In a recess defined by the protrusion of the isolation layer and the active region, a diffusion-retarding poly pattern and a floating gate may be formed in sequence. A control gate may be disposed on the isolation layer to cover the diffusion-retarding poly pattern and the floating gate. | 2010-07-08 |
20100171167 | Gated Semiconductor Device and Method of Fabricating Same - A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut. | 2010-07-08 |
20100171168 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes an active region in which a channel of a transistor is formed in a substrate, element isolation films defining the active region and formed on the substrate at both sides of the channel at a height lower than an upper surface of the active region, a first dielectric layer, a second dielectric layer, and a control gate electrode formed on the active region in this order, and a floating gate electrode formed between the first dielectric layer and the second dielectric layer so as to intersect the length direction of the channel and extend to the upper surfaces of the element isolation films at both sides of the channel, thereby surrounding the channel. | 2010-07-08 |
20100171169 | Nonvolatile semiconductor memory device, semiconductor device and manufactoring method of nonvolatile semiconductor memory device - A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen. | 2010-07-08 |
20100171170 | SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE - A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor. | 2010-07-08 |
20100171171 | Trench mosfet device with low gate charge and the manfacturing method thereof - A method for manufacturing trench MOSFET device with low gate charge includes the steps of providing a substrate of first conductivity type; forming an epitaxial layer of first conductivity type on the substrate; forming a body region of second conductivity type in the epitaxial layer, the body region extends downwards from the surface of the epitaxial layer; forming a plurality of trenches in the epitaxial layer, the body region having the trenches formed therethrough; forming a first insulating layer on the body region and on an inner surface of each trench; forming a ploy-silicon spacer on the first insulating layer on an inner side-wall of each trench; filling a dielectric structure in the lower portion of each trench; and filling a ploy-silicon structure on top of the dielectric structure in each trench. Through the trench MOSFET device, the gate capacitance and resistance thereof are reduced so the performance is increased. | 2010-07-08 |
20100171172 | Semiconductor device and method for manufacturing the same - A semiconductor device, includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a polysilicon formed in the trench with an insulator intervening, a first oxide film formed on the polysilicon so that the first oxide film is buried in the trench, a second oxide film formed on the first oxide film so that the second oxide film is buried in the trench, and a flowable insulator film formed on the second oxide film so that the flowable insulator film is buried in the trench. | 2010-07-08 |
20100171173 | TRENCH MOSFET WITH IMPROVED SOURCE-BODY CONTACT - A trench MOSFET with improved source-body contact structure is disclosed. The improved contact structure can enlarge the P+ area below to wrap the sidewalls and bottom of source-body contact within P-body region to further enhance the avalanche capability. On the other hand, one of the embodiments disclosed a wider tungsten plug structure to connect source metal, which helps to further reduce the source contact resistance. | 2010-07-08 |
20100171174 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate trench | 2010-07-08 |
20100171175 | Structure For High Voltage/High Current MOS Circuits - A semiconductor structure for high voltage/high current MOS circuits is provided, including a deep N-well (NMD), a P-well (PW) disposed within NWD, a plurality of field oxide regions (FOX), a plurality of doping regions, including both N+ regions and P+ regions, disposed within NWD and PW, a gate (G) connected to a doping region, a bulk pad (B) connected to a doping regions, a source pad (S) connected to a doping regions and a drain pad (D) connected to a doping region. The top view of the present invention shows that the regions are of non-specific shapes and overlaid in a radial manner, with doping region connected to B being encompassed by doping region connected to S, which in turn encompassed by G, encompassed by FOX, encompassed by doping region connected to D. As long as the regions are overlaid in a manner that one region surrounds another region so that the electric current flows from S towards D in a radiating manner, the geometry and the layout of the semiconductor structure of the present invention can be varied. | 2010-07-08 |
20100171176 | Integrated Circuitry And Methods Of Forming A Semiconductor-On-Insulator Substrate - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. | 2010-07-08 |
20100171177 | SEMICONDUCTOR DEVICE - The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer. | 2010-07-08 |
20100171178 | SEMICONDUCTOR DEVICES INCLUDING DUAL GATE STRUCTURES AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES - Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed. | 2010-07-08 |
20100171179 | FULL PERIPHERY MULTI-GATE TRANSISTOR WITH OHMIC STRIP - A full periphery multi-gate transistor with ohmic strip is disclosed. The multi-gate transistor comprises a substrate, a multi-layer structure, a source finger, a drain finger, and a gate. The gate is formed between the source finger and the drain finger, and then a conduction channel is formed between the source finger and the drain finger. The gate also meanderingly wraps around an end of the source finger and an end of the drain finger. Therefore, the end of the source finger and the end of the drain finger are parts of the conduction channel and both provide channel conductance. In addition, an ohmic strip is formed between two gate lines of the gate. | 2010-07-08 |
20100171180 | METHOD FOR PFET ENHANCEMENT - A semiconductor process and apparatus includes forming PMOS transistors ( | 2010-07-08 |
20100171181 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL SOURCE/DRAIN - A method of forming a semiconductor device includes forming a device isolation region in a silicon substrate to define an nMOS region and a pMOS region. A p-well is formed in the nMOS region and an n-well in the pMOS region. Gate structures are formed over the p-well and n-well, each gate structure including a stacked structure comprising a gate insulating layer and a gate electrode. A resist mask covers the nMOS region and exposes the pMOS region. Trenches are formed in the substrate on opposite sides of the gate structures of the pMOS region. SiGe layers are grown in the trenches of the pMOS region. The resist mask is removed from the nMOS region. Carbon is implanted to an implantation depth simultaneously on both the nMOS region and the pMOS region to form SiC on the nMOS region and SiGe on the pMOS region. | 2010-07-08 |
20100171182 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING SELECTIVE STRESS RELAXATION OF ETCH STOP LAYER - A strained semiconductor device includes a first plurality of transistors spaced with a first gate pitch, a second plurality of transistors spaced with a second gate pitch greater than the first gate pitch, and an etch stop layer disposed on the first and second pluralities of transistors. The etch stop layer between each of the second plurality of transistors has a greater proportion of a stress-altering material than the etch stop layer between each of the first plurality of transistors. | 2010-07-08 |
20100171183 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CARRYING OUT ION IMPLANTATION BEFORE SILICIDE PROCESS - An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs. | 2010-07-08 |
20100171184 | Semiconductor device - A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode. | 2010-07-08 |
20100171185 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming a barrier layer. The method of forming the barrier layer includes providing a workpiece, forming a first material layer over the workpiece, the first material layer comprising a nitride-based metal compound. A second material layer is formed over the first material layer. The second material layer comprises Ta or Ti. The barrier layer comprises the first material layer and at least the second material layer. | 2010-07-08 |
20100171186 | SYSTEM AND METHOD FOR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR - System and method for metal-oxide-semiconductor field effect transistor. In a specific embodiment, the invention provides a field effect transistor (FET), which includes a substrate material, the substrate material being characterized by a first conductivity type, the substrate material including a first portion, a second portion, and a third portion, the third portion being positioned between the first portion and the second portion. The FET also includes a source portion positioned within the first portion, the source portion being characterized by a second conductivity type, the second conductivity type being opposite of the first conductivity type. A first drain portion is positioned within second portion and characterized by the second conductivity type and a first doping concentration. A second drain portion is positioned within the second portion and is characterized by the second conductivity type and a second doping concentration, the second doping concentration being different from the first doping concentration. | 2010-07-08 |
20100171187 | FORMATION OF HIGH-K GATE STACKS IN SEMICONDUCTOR DEVICES - A method of forming a high-K gate stack for a MOSFET device to control the threshold voltage for the MOSFET device. A first high-K metallic oxide layer is formed on a semiconductor substrate. At least one composite layer is then formed directly on the first layer. The composite layer is composed of a second high-K metallic oxide layer formed directly on a dipole induction layer. The dipole induction layer includes a high-K metallic oxide having higher oxygen vacancy affinity and lower oxygen vacancy diffusivity than the first and second layers. A metallic gate electrode is then formed on the composite layer. Formation of the various layers is such as to position the dipole induction layer of the composite layer between the gate electrode and substrate so as to shift the threshold voltage to a desired level. A high-K gate stack in a MOSFET device formed by the above method is also provided. | 2010-07-08 |
20100171188 | INTEGRATED CIRCUIT DEVICE WITH SINGLE CRYSTAL SILICON ON SILICIDE AND MANUFACTURING METHOD - A silicide element separates a single crystal silicon node from an underlying silicon substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node can act as one terminal of a diode, and a second semiconductor node on top of it can act as the other terminal of the diode. The single crystal silicon node can act as one of the terminals of the transistor, and second and third semiconductor nodes are formed in series on top of it, providing a vertical transistor structure, which can be configured as a field effect transistor or bipolar junction transistor. The silicide element can be formed by a process that consumes a base of a protruding single crystal element by silicide formation processes, while shielding upper portions of the protruding element from the silicide formation process. | 2010-07-08 |
20100171189 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film. | 2010-07-08 |
20100171190 | Electromagnetic Radiation Sensor and Metod of Manufacture - A method of forming a semiconductor sensor in one embodiment includes providing a substrate, forming a reflective layer on the substrate, forming a sacrificial layer on the reflective layer, forming an absorber layer with a thickness of less than about 50 nm on the sacrificial layer, forming an absorber in the absorber layer integrally with at least one suspension leg, and removing the sacrificial layer. | 2010-07-08 |
20100171191 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - An image sensor includes at least one photoelectric conversion device formed in a silicon substrate, at least one lens formed on one side of the photoelectric conversion device and configured to collect light, a dielectric layer formed on the other side of the photoelectric conversion device and a reflective pattern formed on the dielectric layer. The reflective pattern serves as an electrical circuit interconnection and is configured to reflect the light passing through the dielectric layer such that the light is absorbed to the silicon substrate again. | 2010-07-08 |
20100171192 | Reflowable Camera Module With Improved Reliability Of Solder Connections - A reflowable camera module has a set of solder joints formed on a bottom surface of the camera module that provide electrical signal and power connections between the camera module and a printed circuit substrate. The solder joints are susceptible to failure caused by shear forces, particularly in corner regions. Additional localized mechanical supports are provided to protect those solder joints carrying power and electrical signals for the camera module. The localized mechanical supports are formed outside of a region containing the solder joints carrying power and electrical signals. The localized mechanical supports may include dummy solder joints formed in corner regions and/or dummy leads used to support the camera module. Solder joint reliability is enhanced without requiring the use of an underfill encapsulant. | 2010-07-08 |
20100171193 | SEMICONDUCTOR DEVICE - This invention provides a semiconductor device, which is used to manufacture two lateral high-voltage devices on the same substrate, where the voltages between maximum voltage terminals and minimum voltage terminals of the two devices have not too much difference. Both devices are formed on two different surface regions with a small isolation region in-between the two regions. When the semiconductor region(s) of the isolation region is fully depleted, its effective electric flux density emitted to the substrate is of a value between the values of its adjacent regions of said two semiconductor devices. The figure presented here schematically shows the structure used to form a low-side high-voltage n-MOST and high-voltage n-MOST and M | 2010-07-08 |
20100171194 | Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate - A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer. | 2010-07-08 |
20100171195 | THIN FILM SILICON WAFER AND METHOD FOR MANUFACTURING THE SAME - Provided are a thin film silicon wafer having high gettering capability, a manufacturing method therefor, a multi-layered silicon wafer formed by laminating the thin film silicon wafers, and a manufacturing method therefor. The thin film silicon wafer is manufactured by: forming one or more gettering layers immediately below a device layer which is formed in a vicinity of a front surface of a semiconductor silicon wafer; fabricating a device in the device layer of the semiconductor silicon wafer; and after the device has been fabricated, removing part of the semiconductor silicon wafer from a rear surface thereof to immediately below the gettering layers so as to leave at least one of the gettering layers in place. As a result, the thin film silicon wafer is allowed to have gettering capability even after having been reduced in thickness to be in a thin film form. | 2010-07-08 |
20100171196 | ELECTRICALLY SHIELDED THROUGH-WAFER INTERCONNECT - Through-Wafer Interconnections allow for the usage of cost-effective substrates for detector chips. According to an exemplary embodiment of the present invention, detecting element for application in an examination apparatus may be provided, comprising a wafer with a sensitive region and a coaxial through-wafer interconnect structure. This may reduce the susceptibility of the interconnection by providing an effective shielding. | 2010-07-08 |
20100171197 | Isolation Structure for Stacked Dies - An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon via. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon via. The isolation film is thinned to re-expose the through-silicon via, and conductive elements are formed on the through-silicon via. The conductive element may be, for example, a solder ball or a conductive pad. The conductive pad may be formed by depositing a seed layer and an overlying mask layer. The conductive pad is formed on the exposed seed layer. Thereafter, the mask layer and the unused seed layer may be removed. | 2010-07-08 |
20100171198 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING APPARATUS AND STORAGE MEDIUM - A method for manufacturing a semiconductor device includes steps of:(a) forming a thin film containing a phenyl group and silicon on a substrate while obtaining a plasma by activating an organic silane gas containing a phenyl group and silicon and nitrogen as not original component but unavoidable impurity and exposing the substrate to the plasma, temperature of the substrate being set at 200° C. or lower; and (b) obtaining a low-permittivity film by supplying energy to the substrate to allow moisture to be released from the thin film. With this method for manufacturing the semiconductor device, it is possible to obtain a silicon-oxide based low-permittivity film containing an organic substance which is not significantly damaged by the release of the organic substance when subjected to a plasma treatment such as an etching treatment, an ashing treatment, and/or the like. | 2010-07-08 |
20100171199 | PRODUCTION METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND EXPOSURE APPARATUS - The present invention provides a production method of a semiconductor device, involving formation of a flattening layer and easy process for layers formed on a semiconductor layer, and also provides a semiconductor device preferably produced by such a production method. | 2010-07-08 |
20100171200 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved. | 2010-07-08 |
20100171201 | CHIP ON LEAD WITH SMALL POWER PAD DESIGN - Embodiments of a semiconductor device and method provide a quad flat no-lead semiconductor package which can have an arrangement of both chip-on-lead (COL) style leads and a die pad for supporting a die, and can also provide non-COL leads, both COL leads and a leadframe power pad, COL leads which have varying lengths to reduce stress resulting from thermal mismatch between a semiconductor die and leads, and a die pad with a curved, meandering edge to reduce stress resulting from thermal mismatch between the semiconductor die and the die pad. | 2010-07-08 |
20100171202 | Method of securely data protecting arrangement for electronic device - A method of securely data protection for an electronic device includes the steps of: enclosing a core circuit module of the electronic within a protection element to form a protection circuit surrounding the core circuit module; operatively linking a detective circuit between the protection element and the core circuit module; and activating the detective circuit in case of a hack of the electronic device, such that when the electronic device is broken to access the core circuit module through the protection element, the detective circuit is activated to block data information saved in the core circuit module from being access. | 2010-07-08 |
20100171203 | Robust TSV structure - A die includes a seal-ring structure below a substrate. The seal-ring structure is disposed around at least one substrate region. At least one means for substantially preventing ion diffusion into the substrate region. The at least one means is coupled with the seal-ring structure. | 2010-07-08 |
20100171204 | THREE-DIMENSIONAL PACKAGE - A three-dimensional package includes a carrier, a first die mounted on a first surface of the carrier, and a second die stacked on the first die. The first die includes first bond pads and second bond pads juxtaposed in separate two rows within a central region of the first die. The package further includes first bond fingers disposed on the first surface along a first side of the carrier, and second bond fingers along a second side opposite to the first side. A first bond wire is bonded to one of the first bond pads and extends to one the first bond fingers. The first bond wire overlies the row of the second bond pads. A second bond wire is bonded to one of the second bond pads and extends to one the second bond fingers. The second bond wire overlies the row of the first bond pads. | 2010-07-08 |
20100171205 | Stackable Semiconductor Device Packages - In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width W | 2010-07-08 |
20100171206 | Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same - A semiconductor package includes: (1) a substrate including an upper surface and a lower surface opposite to the upper surface; (2) a chip mounted and electrically connected to the upper surface of the substrate; (3) an interposer mounted on the chip and electrically connected to the upper surface of the substrate, the interposer including an upper surface and a lower surface that is opposite to the upper surface and facing the chip, the interposer including a plurality of electrical contacts located on the upper surface of the interposer; and (4) a molding compound sealing the substrate, the interposer, and the chip, and exposing the lower surface of the substrate, the molding compound defining a plurality of holes that enclose and expose respective ones of the electrical contacts. | 2010-07-08 |
20100171207 | STACKABLE SEMICONDUCTOR DEVICE PACKAGES - In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate. | 2010-07-08 |
20100171208 | SEMICONDUCTOR DEVICE - A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip | 2010-07-08 |
20100171209 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a tapered portion are melt-joined using solder balls each having a core of a material higher in melting point than solder. When melt-joining the semiconductor chips, the temperature is raised while imparting an urging load to stacked semiconductor chips, thereby correcting warpage of the semiconductor chips. In each chip-to-chip connection thus formed, if the connection is to prevent the occurrence of stress around the electrode due to the urging load, a solder ball having a core of a smaller diameter than in the other connections is used in the connection. | 2010-07-08 |
20100171210 | SEMICONDUCTOR DEVICE, STACKED SEMICONDUCTOR DEVICE AND INTERPOSER SUBSTRATE - A semiconductor device has a semiconductor element; an interposer substrate having a wiring pattern electrically connected to the semiconductor element and an insulating substrate formed with the wiring pattern; a connection layer for adhering between the semiconductor element and the interposer substrate; and a solder ball external terminal arranged on the interposer substrate. The insulating substrate is folded in a portion mounted with the external terminal arranged on an outer side to the semiconductor element, and the unfolded and folded portions of the insulating substrate are opposite each other to form a gap therebetween. | 2010-07-08 |
20100171211 | SEMICONDUCTOR DEVICE - A semiconductor device is provided by the present invention. The semiconductor device includes a semiconductor die, and the semiconductor die includes a die core having at least two bond pads with voltage level equivalent to each other and electrically connected to each other via at least a bond wire, and an input/output (I/O) periphery. The semiconductor device of the present invention is capable of solving the IR drop of the semiconductor die with low cost. | 2010-07-08 |
20100171212 | SEMICONDUCTOR PACKAGE STRUCTURE WITH PROTECTION BAR - A semiconductor package structure includes a carrier, a chip or multi-chips mounted on a top surface of the carrier, a molding compound encapsulating the top surface and the chips, a plurality of solder balls distributed on a bottom surface of the carrier, and a protection bar formed of thermosetting plastic material formed on the bottom surface. | 2010-07-08 |
20100171213 | SEMICONDUCTOR DEVICE HAVING A LIQUID COOLING MODULE - A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate. | 2010-07-08 |
20100171214 | MARKING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PROVIDED WITH MARKINGS - A marking method is provided for putting markings on the surface of a packaged semiconductor device. The semiconductor device includes a semiconductor chip and a resin package for covering the semiconductor chip. The method includes the steps of forming a groove in the obverse surface of the resin package, and filling the groove with a resin that is visually distinguishable from the resin package. | 2010-07-08 |
20100171215 | Method of Producing Optoelectronic Components and Optoelectronic Component - A method of producing optoelectronic components is indicated, in which a plurality of semiconductor bodies, each with a semiconductor layer sequence, are provided. In addition, a component carrier assembly with a plurality of connection pads is provided. The semiconductor bodies are positioned relative to the component carrier assembly. An electrically conductive connection is produced between the connection pads and the associated semiconductor bodies and the semiconductor bodies are attached to the component carrier assembly. The optoelectronic components are finished in that one component carrier ( | 2010-07-08 |
20100171216 | ELECTRONIC DEVICE AND ELECTRONIC APPARATUS - An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion. | 2010-07-08 |
20100171217 | THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS - A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. | 2010-07-08 |
20100171218 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first substrate formed with a through silicon via reaching the back surface thereof, and a second substrate electrically connected to the first substrate via the through silicon via, and bonded to the back surface of the first substrate. A taper angle of a sidewall of a tip end portion of the through silicon via connected to the second substrate is larger than a taper angle of a sidewall of the other portion thereof. | 2010-07-08 |
20100171219 | EXTENDED LINER FOR LOCALIZED THICK COPPER INTERCONNECT - A dielectric layer overlies a semiconductor substrate. The substrate has components and appropriate contacts formed therein. The dielectric layer electrically insulates the substrate and components from overlying conductive interconnect layers. A barrier layer is arranged over the dielectric layer to isolate the interconnect layers from other structures. A copper layer is then deposited over the barrier layer and thick interconnect lines having a first width and a first height are realized. Then, the barrier layer is etched using one of many alternative techniques. The barrier layer has a second width and a second height wherein the second width of the barrier liner is selected to be greater than the first width of the thick copper interconnect. | 2010-07-08 |
20100171220 | Reducing Resistivity in Interconnect Structures of Integrated Circuits - An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening. | 2010-07-08 |
20100171221 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention relates to a semiconductor device and its manufacturing method including the steps of: forming a first semiconductor element layer having a first wiring over a substrate; forming a second semiconductor element layer having a second wiring and fixed to a first structure body having a first sheet-like fiber body, a first organic resin, and a first electrode; preparing a second structure body having a second sheet-like fiber body, a second organic resin which is not cured, and a second electrode; disposing the second structure body between the first and second semiconductor element layers so that the first wiring, the second electrode, and the second wiring are overlapped with each other over the substrate; and curing the second organic resin. | 2010-07-08 |
20100171222 | HIGH RELIABILITY Au ALLOY BONDING WIRE AND SEMICONDUCTOR DEVICE OF SAME - [Issues to be Solved] Providing enhanced bonding reliability of Au alloy bonding wire with low electrical resistivity to Al electrode of semiconductor device, and its application of semiconductor device is bonded with Al electrode pad by the same wire. | 2010-07-08 |