27th week of 2011 patent applcation highlights part 13 |
Patent application number | Title | Published |
20110163324 | LIGHT EMITTING DEVICE - A light emitting diode of one embodiment includes a light emitting device having a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on an upper layer of the plurality of N-type semiconductor layers, and a P-type semiconductor layer on the active layer. The first N-type semiconductor layer includes a first Si doped Nitride layer and the second N-type semiconductor layer includes a second Si doped Nitride layer. The first and second N-type semiconductor layers have a Si impurity concentration different from each other. | 2011-07-07 |
20110163325 | METHOD OF MANUFACTURING GaN SUBSTRATE, METHOD OF MANUFACTURING EPITAXIALWAFER, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND EPITAXIALWAFER - Assuming that r (m) represents the radius of a GaN substrate, t | 2011-07-07 |
20110163326 | SUBSTRATE, EPITAXIAL LAYER PROVIDED SUBSTRATE, METHOD FOR PRODUCING SUBSTRATE, AND METHOD FOR PRODUCING EPITAXIAL LAYER PROVIDED SUBSTRATE - The present invention provides a substrate formed at a low cost and having a controlled plate shape, an epitaxial layer provided substrate obtained by forming an epitaxial layer on the substrate, and methods for producing them. The method for producing the substrate according to the present invention includes an ingot growing step serving as a step of preparing an ingot formed of gallium nitride (GaN); and a slicing step serving as a step of obtaining a substrate formed of gallium nitride, by slicing the ingot. In the slicing step, the substrate thus obtained by the slicing has a main surface with an arithmetic mean roughness Ra of not less than 0.05 μm and not more than 1 μm on a line of 10 mm. | 2011-07-07 |
20110163327 | DEVICE COMPRISING POSITIVE HOLE INJECTION TRANSPORT LAYER, METHOD FOR PRODUCING THE SAME AND INK FOR FORMING POSITIVE HOLE INJECTION TRANSPORT LAYER - A device capable of having an easy production process and achieving a long lifetime. The device has a substrate, two or more electrodes facing each other disposed on the substrate and a positive hole injection transport layer disposed between two electrodes among the two or more electrodes. The positive hole injection transport layer has a transition metal-containing nanoparticle containing at least a transition metal compound including a transition metal oxide, a transition metal and a protecting agent, or at least the transition metal compound including the transition metal oxide, and the protecting agent. | 2011-07-07 |
20110163328 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device includes: a package having a bottom portion and a sidewall portion; a semiconductor chip having an optical element formed on one surface thereof and having an opposite surface to the one surface fixed to the bottom portion of the package; a transparent member fixed to the semiconductor chip so as to cover the optical element; and a sealing resin filling a space between the package and the semiconductor chip. The sidewall portion has in an upper part thereof an overhang portion that projects toward inside of the package. The transparent member is exposed from a window portion formed by the overhang portion. | 2011-07-07 |
20110163329 | Organic light emitting display apparatus and method of manufacturing the same - An organic light emitting display apparatus and a method of fabricating the same are provided. The organic light emitting display apparatus includes a pixel unit on which an organic light emitting device is formed, a thin film transistor (TFT) electrically connected to the pixel unit and a data line and a scan line electrically connected to the TFT and disposed crossing each other on a substrate. The data line and the scan line are formed in one layer. A bridge that allows one of the data line and the scan line to bypass the other is on an intersection of the data line and the scan line. | 2011-07-07 |
20110163330 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display is disclosed. In one embodiment, the OLED display includes an organic light emitting element formed over a substrate and an encapsulation portion covering the organic light emitting element. Further, the encapsulation portion may include at least one organic layer and at least one inorganic layer, wherein ends of the inorganic layer and t he organic layer directly contact the substrate, and wherein the organic layer is thicker than the inorganic layer. | 2011-07-07 |
20110163331 | ORGANIC LIGHT-EMITTING DEVICE - The present invention relates to an organic light-emitting device capable of suppressing deterioration of organic EL elements at the corners of an emission region. | 2011-07-07 |
20110163332 | OLEDS AND OTHER ELECTRONIC DEVICES USING DESICCANTS - Electronic devices that use desiccants for protection from moisture. The electronic devices comprise a substrate ( | 2011-07-07 |
20110163333 | Display Device - A display device includes a plurality of pixels placed in a matrix form in which each pixel has a light emitting device. The light emitting device includes a light emissive layer; a reflective electrode disposed on a rear surface side of the light emissive layer; a transparent electrode disposed on a front surface side of the light emissive layer; a dividing wall, disposed between the reflective electrode and the light emissive layer at a periphery part of a region where the reflective electrode is formed; a protective layer on a front surface side of the transparent electrode; and a transparent substrate disposed above the protective layer. The protective layer and the transparent substrate are spaced from one another so as to delimit a space where a gas is sealed. | 2011-07-07 |
20110163334 | COLOUR MIXING METHOD FOR CONSISTENT COLOUR QUALITY - The present invention relates to a light emitting device ( | 2011-07-07 |
20110163335 | SHAPED CONTACT LAYER FOR LIGHT EMITTING HETEROSTRUCTURE - An improved light emitting heterostructure and/or device is provided, which includes a contact layer having a contact shape comprising one of: a clover shape with at least a third order axis of symmetry or an H-shape. The use of these shapes can provide one or more improved operating characteristics for the light emitting devices. The contact shapes can be used, for example, with contact layers on nitride-based devices that emit light having a wavelength in at least one of: the blue spectrum or the deep ultraviolet (UV) spectrum. | 2011-07-07 |
20110163336 | LIGHT EMITTING DIODE DEVICE - A light emitting diode device is described which includes at least one planar non-periodic high-index-contrast grating. The light emitting diode device includes a cavity formed between a reflective optical element and a transmissive optical element. One or both of the optical elements can be a planar non-periodic high-index-contrast grating. The transmissive optical element can be a collimating lens used to collimate incident beams of light while the reflective optical element can be a parabolic reflector used to reflect incident beams of light along a direction opposite to an incidence direction. A light emitter can be disposed within the cavity and can emit beams of light. | 2011-07-07 |
20110163337 | ARCHITECTURE FOR ORGANIC ELECTRONIC DEVICES - Provided are organic device packages configured to limit current flow through shorted sub-elements in the organic device. In some embodiments, the organic device package may include multiple elements, each having multiple sub-elements connected in parallel. Each element may have a first electrode patterned into thin electrode strips connected in parallel, and each of the electrode strips may be an electrode of one of the multiple sub-elements. The electrode strips may have a resistance which may be higher than the overall resistance of other sub-elements in the element, such that a current flowing to the element may be substantially limited from flowing through a shorted sub-element in the element. Each element may also be connected in series to another element in the organic device package, and one or more series-connected elements may also be connected in parallel within the package. | 2011-07-07 |
20110163338 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a light emitting device and a method of manufacturing the same. The light emitting device includes a body, an insulating layer over a surface of the body, at least one electrode over the insulating layer, a light emitting diode connected to the electrode, and a reflective layer over the insulating layer. | 2011-07-07 |
20110163339 | LIGHT-EMITTING ELEMENT AND METHOD FOR PRODUCTION THEREOF - A light-emitting element includes a first electrode, an organic layer with a light-emitting layer made of organic light-emitting material, a half-transmitting/reflecting film, a resistance layer, and a second electrode, which are sequentially laminated on top of the other. The first electrode reflects light from the light-emitting layer, the second electrode transmits light from the light-emitting layer. The half-transmitting/reflecting film includes a first half-transmitting/reflecting film and a second half-transmitting/reflecting film which are laminated in this order from a side of the organic layer. Also, the half-transmitting/reflecting film on the organic layer has an average thickness of 1 nm to 6 nm. | 2011-07-07 |
20110163340 | Organic Electroluminescent Device - An organic electroluminescent device comprising: a substrate; a first electrode disposed over the substrate for injecting charge of a first polarity; a second electrode disposed over the first electrode for injecting charge of a second polarity opposite to said first polarity; an organic light emitting layer disposed between the first and the second electrode, the second electrode being transparent to light emitted by the light emitting layer; a glass or transparent plastic encapsulant disposed over, and spaced apart from, the second electrode, defining a cavity therebetween; and a cavity filling material disposed within the cavity, the cavity filling material extending from a bottom side of the cavity to a top side of the cavity, the cavity filling material having an optical structure disposed therein. | 2011-07-07 |
20110163341 | LIGHT OUTPUT DEVICE AND ASSEMBLY METHOD - The present invention relates to a light output device ( | 2011-07-07 |
20110163342 | LIGHT EMITTING DEVICE - A light emitting device including a second metal layer, a second conduction type semiconductor layer on the second metal layer, an active layer on the second conduction type semiconductor layer, a first conduction type semiconductor layer on the active layer, a first metal layer on the first conduction type semiconductor layer, an insulating layer being disposed on a peripheral portion of an upper surface of the second metal layer and being disposed under a lower surface of the second conduction type semiconductor layer, and a passivation layer on lateral surfaces of the insulating layer, the second conduction type semiconductor layer, the active layer and the first conduction type semiconductor layer, the passivation layer being on an upper surface of the second metal layer, wherein a lateral surface of the insulating layer is adjacent to a lateral surface of the second metal layer. | 2011-07-07 |
20110163343 | TWO DIMENSIONAL LIGHT SOURCE USING LIGHT EMITTING DIODE AND LIQUID CRYSTAL DISPLAY DEVICE USING THE TWO DIMENSIONAL LIGHT SOURCE - A two-dimensional light source includes a base substrate having holes, wires disposed on a lower surface of the base substrate, a light emitting diode (LED) chip disposed on an upper surface of the base substrate, plugs that connect two electrodes of the LED chip to the wires through the holes, a buffer layer covering the LED chip, and an optical layer that is disposed on the buffer layer and has an optical pattern formed at a portion of the optical layer corresponding to the LED chip. | 2011-07-07 |
20110163344 | Production of Nitride-Based Phosphors - This invention relates to a new method for the production of nitride-based phosphors, in particular, of phosphors containing rare earth elements. The phosphors can be used, for example, in light sources, especially in Light Emitting Devices (LEDs). | 2011-07-07 |
20110163345 | LEAD, WIRING MEMBER, PACKAGE COMPONENT, METAL COMPONENT WITH RESIN, RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE, AND METHODS FOR PRODUCING THE SAME - The present invention aims to make possible facile removal of resin burrs without the risk of damaging resin body covering a wiring lead in a semiconductor device. In detail, the semiconductor device | 2011-07-07 |
20110163346 | LIGHT EMITTING DIODE HAVING ELECTRODE PADS - Exemplary embodiments of the present invention relate to a including a substrate, a first conductive type semiconductor layer arranged on the substrate, a second conductive type semiconductor layer arranged on the first conductive type semiconductor layer, an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer, a first electrode pad electrically connected to the first conductive type semiconductor layer, a second electrode pad arranged on the second conductive type semiconductor layer, an insulation layer disposed between the second conductive type semiconductor layer and the second electrode pad, and at least one upper extension electrically connected to the second electrode pad, the at least one upper extension being electrically connected to the second conductive type semiconductor layer. | 2011-07-07 |
20110163347 | Series Connected Segmented LED - A light source and method for making the same are disclosed. The light source includes a substrate, and a light emitting structure that is divided into segments. The light emitting structure includes a first layer of semiconductor material of a first conductivity type deposited on the substrate, an active layer overlying the first layer, and a second layer of semiconductor material of an opposite conductivity type from the first conductivity type overlying the active layer. A barrier divides the light emitting structure into first and second segments that are electrically isolated from one another. A serial connection electrode connects the first layer in the first segment to the second layer in the second segment. A power contact is electrically connected to the second layer in the first segment, and a second power contact electrically connected to the first layer in the second segment. | 2011-07-07 |
20110163348 | SEMICONDUCTOR CHIP ASSEMBLY WITH BUMP/BASE HEAT SPREADER AND INVERTED CAVITY IN BUMP - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a bump and a base. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump opposite a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the bump. The bump extends from the base into an opening in the adhesive and the base extends laterally from the bump. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal. | 2011-07-07 |
20110163349 | METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT, GROUP III NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT AND LAMP - The present invention provides a method for manufacturing a group III nitride semiconductor light emitting element, with which warping can be suppressed upon the formation of respective layers on the substrate, a semiconductor layer including a light emitting layer of excellent crystallinity can be formed, and excellent light emission characteristics can be obtained; such a group III nitride semiconductor light emitting element; and a lamp. Specifically disclosed is a method for manufacturing a group III nitride semiconductor light emitting element, in which an intermediate layer, an underlayer, an n-type contact layer, an n-type cladding layer, a light emitting layer, a p-type cladding layer, and a p-type contact layer are laminated in sequence on a principal plane of a substrate, wherein a substrate having a diameter of 4 inches (100 mm) or larger, with having an amount of warping H within a range from 0.1 to 30 μm and at least a part of the edge of the substrate warping toward the principal plane at room temperature, is prepared as the substrate; the X-ray rocking curve full width at half maximum (FWHM) of the (0002) plane is 100 arcsec or less and the X-ray rocking curve FWHM of the (10-10) plane is 300 arcsec or less, in a state where the intermediate layer has been formed on the substrate and where thereafter the underlayer and the n-type contact layer are formed on the intermediate layer; and furthermore the n-type cladding layer, the light emitting layer, the p-type cladding layer, and the p-type contact layer are formed on the n-type contact layer. | 2011-07-07 |
20110163350 | METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR LAYER, METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - A method for manufacturing a Group III nitride semiconductor layer according to the present invention includes a sputtering step of disposing a substrate and a target containing a Group III element in a chamber, introducing a gas for formation of a plasma in the chamber and forming a Group III nitride semiconductor layer added with Si as a dopant on the substrate by a reactive sputtering method, wherein a Si hydride is added in the gas for formation of a plasma. | 2011-07-07 |
20110163351 | Low Voltage Power Supply - This invention provides a structure for low-voltage power supply in high-voltage devices or IC's made on a semiconductor substrate of a first conductivity type. The structure comprises a heavily doped semiconductor region of the first conductivity type between, but not contacted with, two semiconductor regions of the second conductivity type. When the two semiconductor regions of the second conductivity type have reverse-biased voltage with respect to substrate, the depletion region of substrate reaches the heavily doped semiconductor region of the first conductivity type, the heavily doped semiconductor region of the first conductivity type constructs a terminal of low-voltage power supply and any one of the semiconductor region of the second conductivity type constructs another terminal. The heavily doped semiconductor region is used as one terminal of a primary low-voltage power supply and any other region is used as another terminal of it. Thus, the cost of a low-voltage power supply can be reduced and the electrical performances be improved. | 2011-07-07 |
20110163352 | MONOLITHIC MULTI-CHANNEL ESD PROTECTION DEVICE - A semiconductor device is described that includes one or more electrostatic discharge (ESD) protection circuits. Each circuit comprises reverse-biased steering diodes connected in series between power rail and signal ground, a bypass Zener diode and a substrate Zener diode. The Zener diodes provide ESD protection and the steering diode cooperate with the substrate Zener diode to provide a bypass function that is substantially symmetric about the signal ground. Noise in the circuit can be shunted using internal and/or external capacitances that can be implemented as Zener diodes. | 2011-07-07 |
20110163353 | GAS SENSOR - A gas sensor having at least one gas-sensitive electrically conductive layer having a surface region which can be brought into contact with a target gas and in which the work function depends on the concentration of the target gas in contact therewith. At least one electrical potential sensor is capacitively coupled to the surface region via an air gap. The surface region is structured by at least one recess in which a flat material element which is connected to the gas-sensitive layer in an electrically conductive manner is arranged, the material of the material element differing from that of the gas-sensitive layer and comprising a metal and/or a metal-containing chemical compound. | 2011-07-07 |
20110163354 | EPITAXIAL SILICON GROWTH - Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer. | 2011-07-07 |
20110163355 | Field effect transistor and method for manufacturing the same - A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode. | 2011-07-07 |
20110163356 | HYBRID TRANSISTOR - A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths. | 2011-07-07 |
20110163357 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES USING STRESS ENGINEERING - A method for fabricating a semiconductor device is presented. The method comprises providing a gate stack including a gate dielectric and gate electrode over a substrate. Stressor regions comprising stressor material incorporated into substitutional sites of the substrate are formed within the substrate on opposed sides of the gate stack. A first stressor layer having a first stress value is formed over the semiconductor device after forming the stressor regions followed by an anneal to memorize at least a portion of the first stress value in the semiconductor device, wherein the anneal is conducted at a low temperature. | 2011-07-07 |
20110163358 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate electrode buried over the trench to form a buried gate pattern, etching portions of the substrate on both sides of the buried gate pattern to a certain depth, performing an ion implantation process on the substrate to form source/drain junctions, and forming metal patterns over the source/drain junctions. | 2011-07-07 |
20110163359 | LITHOGRAPHY FOR PRINTING CONSTANT LINE WIDTH FEATURES - An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width. | 2011-07-07 |
20110163360 | METHOD FOR FORMING A TRANSISTOR HAVING GATE DIELECTRIC PROTECTION AND STRUCTURE - A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure. | 2011-07-07 |
20110163361 | SOLID STATE IMAGING DEVICE - A solid state imaging device in which γ characteristic is obtained and enlargement of dynamic range is provided. The solid state imaging device includes a vertical overflow function and has a feature in which potential of a semiconductor substrate is changed from a high potential to a low potential in a stepwise manner during a period from an exposure start to an exposure end. | 2011-07-07 |
20110163362 | Methods of fabricating image sensors and image sensors fabricated thereby - A method of fabricating an image sensor may include providing a substrate including light-receiving and non-light-receiving regions; forming a plurality of gates on the non-light-receiving region; ion-implanting a first-conductivity-type dopant into the light-receiving region to form a first dopant region of a pinned photodiode; primarily ion-implanting a second-conductivity-type dopant, different from the first-conductivity-type dopant, into an entire surface of the substrate, using the gates as a first mask; forming spacers on both side walls of the gates; and secondarily ion-implanting the second-conductivity-type dopant into the entire surface of the substrate, using the plurality of gates including the spacers as a second mask, to complete a second dopant region of the pinned photodiode. An image sensor may include the substrate; a transfer gate formed on the non-light-receiving region; a first dopant region in the light-receiving region; and a second dopant region formed on a surface of the light-receiving region. | 2011-07-07 |
20110163363 | COMS image sensors and methods of manufacturing the same - Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and methods of manufacturing the same are provided, the sensors include an epitaxial layer on a substrate in which a first, second, third and fourth region are defined. A photodiode may be formed at an upper portion of the epitaxial layer in the first region. A plurality of gate structures may be formed on the epitaxial layer in the second, third and fourth regions. A first blocking layer may be formed on the gate structures and the epitaxial layer in the first and second regions. A first impurity layer may be formed at an upper portion of the epitaxial layer adjacent to the gate structures in the second region, and a second impurity layer at upper portions of the epitaxial layer adjacent to the gate structures in the third and fourth regions. A color filter layer may be formed over the photodiode. A microlens may be formed on the color filter layer. | 2011-07-07 |
20110163364 | IMAGE SENSOR, FABRICATING METHOD THEREOF, AND DEVICE COMPRISING THE IMAGE SENSOR - Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer. | 2011-07-07 |
20110163365 | STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS - A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs). | 2011-07-07 |
20110163366 | Semiconductor Component Arrangement Comprising a Trench Transistor - Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps. | 2011-07-07 |
20110163367 | Semiconductor Devices Comprising a Plurality of Gate Structures - Semiconductor devices are provided. The semiconductor devices may include a plurality of gate structures disposed on a semiconductor substrate, each of the gate structures including a floating gate, an inter-gate dielectric layer, and a control gate. The semiconductor devices may also include liners on opposing sidewalls of adjacent ones of the gate structures. The liners may define a gap. A first width of the gap may be less than a second width of the gap. | 2011-07-07 |
20110163368 | Semiconductor Memory Device and Manufacturing Method Thereof - A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2. | 2011-07-07 |
20110163369 | SURROUNDING STACKED GATE MULTI-GATE FET STRUCTURE NONVOLATILE MEMORY DEVICE - Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode. | 2011-07-07 |
20110163370 | SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A semiconductor memory includes memory cell transistors including a tunnel insulating film, a floating gate electrode, a first insulating film, a control gate electrode, and a first metal salicide film; low-voltage transistors having a first p-type source region and a first p-type drain region, a first gate insulating film, and a first gate electrode of an n conductivity type having the same dose of a first p-type impurity as with the first p-type source region; and high-voltage transistors having a second p-type source region and a second p-type drain region, a second gate insulating film thicker than the first gate insulating film, and a second gate electrode of an n conductivity type having the same dose of a second p-type impurity as with the second p-type source region. | 2011-07-07 |
20110163371 | METHODS OF FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICES - A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines. | 2011-07-07 |
20110163372 | SEMICONDUCTOR DEVICE - A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device. | 2011-07-07 |
20110163373 | Semiconductor device including a voltage controlled termination structure and method for fabricating same - According to one embodiment, a semiconductor device including a voltage controlled termination structure comprises an active area including a base region of a first conductivity type formed in a semiconductor body of a second conductivity type formed over a first major surface of a substrate of the second conductivity type, a termination region formed in the semiconductor body adjacent the active area and including the voltage controlled termination structure. The voltage controlled termination structure includes an electrode electrically connected to a terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a gate terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a source terminal of the semiconductor device. | 2011-07-07 |
20110163374 | TRENCH-TYPED POWER MOS TRANSISTOR AND METHOD FOR MAKING THE SAME - A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region. | 2011-07-07 |
20110163375 | High-Voltage MOS Devices Having Gates Extending into Recesses of Substrates - An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region. | 2011-07-07 |
20110163376 | HIGH VOLTAGE DEVICES AND METHODS OF FORMING THE HIGH VOLTAGE DEVICES - A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type. | 2011-07-07 |
20110163377 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer. | 2011-07-07 |
20110163378 | LAYOUT STRUCTURE OF POWER MOS TRANSISTOR - The present invention discloses a layout structure of a transistor unit of a power MOS transistor, wherein the layout structure comprises a drain area, a plurality of body areas, a plurality of source areas and a gate area. The plurality of body areas surround the drain area. The plurality of source areas extend from the perimeters of the plurality of body areas in an anisotropic manner. The gate area is disposed between the drain area and the plurality of source areas. The contacts of the drain area, the plurality of body areas and the plurality of source areas are all disposed on the same side of the layout structure. | 2011-07-07 |
20110163379 | Body-Tied Asymmetric P-Type Field Effect Transistor - In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor. | 2011-07-07 |
20110163380 | Body-Tied Asymmetric N-Type Field Effect Transistor - In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor. | 2011-07-07 |
20110163381 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object to provide a method for manufacturing a semiconductor substrate in which contamination of a semiconductor layer due to an impurity is prevented and the bonding strength between a support substrate and the semiconductor layer can be increased. An oxide film containing first halogen is formed on a surface of a semiconductor substrate, and the semiconductor substrate is irradiated with ions of second halogen, whereby a separation layer is formed and the second halogen is contained in a semiconductor substrate. Then, heat treatment is performed in a state in which the semiconductor substrate and the support substrate are superposed with an insulating surface containing hydrogen interposed therebetween, whereby part of the semiconductor substrate is separated along the separation layer, so that a semiconductor layer containing the second halogen is provided over the support substrate. | 2011-07-07 |
20110163382 | BODY CONTACTED TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE - A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (Å). This results in a lower parasitic capacitance at the body contact region. | 2011-07-07 |
20110163383 | BULK SUBSTRATE FET INTEGRATED ON CMOS SOI - An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET. | 2011-07-07 |
20110163384 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which the drain region of the ESD protection NMOS transistor is electrically connected, through a drain extension region formed by an impurity diffusion region having the same conductivity as that of the drain region and arranged on both side surfaces and a bottom surface of the second trench isolation region which is formed next to the drain region, to the drain contact region formed by an impurity diffusion region having the same conductivity as that of the drain region. | 2011-07-07 |
20110163385 | ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME - A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure. | 2011-07-07 |
20110163386 | Semiconductor Devices Including Dehydrogenated Interlayer Dielectric Layers - Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided. | 2011-07-07 |
20110163387 | METHODS FOR FORMING SELF-ALIGNED DUAL STRESS LINERS FOR CMOS SEMICONDUCTOR DEVICES - CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures. | 2011-07-07 |
20110163388 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall. | 2011-07-07 |
20110163389 | LOW CAPACITANCE PRECISION RESISTOR - A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate. | 2011-07-07 |
20110163390 | MEMORY CELL ARRAY WITH SEMICONDUCTOR SELECTION DEVICE FOR MULTIPLE MEMORY CELLS - A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices via diode devices. The access devices include vertical semiconductor material mesas upstanding from a semiconductor base that form a conductive channel between first and second doped regions, and also planar access devices. | 2011-07-07 |
20110163391 | WAFER LEVEL STACK DIE PACKAGE - This document discusses, among other things, an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components. | 2011-07-07 |
20110163392 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - By increasing the area of a source electrode | 2011-07-07 |
20110163393 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AN INTEGRATED CIRCUIT COMPRISING SUCH A DEVICE - A method of manufacturing a semiconductor device on a substrate ( | 2011-07-07 |
20110163394 | SEMICONDUCTOR CONTACT STRUCTURE AND METHOD OF FABRICATING THE SAME - Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer. | 2011-07-07 |
20110163395 | Pressure Sensor and Method - A method for providing a pressure sensor substrate comprises creating a first cavity that extends inside the substrate in a first direction perpendicular to a main surface of the substrate, and that extends inside the substrate, in a second direction perpendicular to the first direction, into a first venting area of the substrate; creating a second cavity that extends in the first direction inside the substrate, that extends in parallel to the first cavity in the second direction, and that does not extend into the first venting area; and opening the first cavity in the first venting area. | 2011-07-07 |
20110163396 | Manufacturing method for a micromechanical component, corresponding composite component, and corresponding micromechanical component - The present invention relates to a manufacturing method for a micromechanical component, a corresponding composite component, and a corresponding micromechanical component. The method has the following steps: providing a first composite (W | 2011-07-07 |
20110163397 | Composition and Manufacturing Method - A device includes a substrate ( | 2011-07-07 |
20110163398 | METHOD FOR MANUFACTURING SEPARATED MICROMECHANICAL COMPONENTS SITUATED ON A SILICON SUBSTRATE AND COMPONENTS MANUFACTURED THEREFROM - A method for manufacturing separated micromechanical components situated on a silicon substrate includes the following steps of a) providing separation trenches on the substrate via an anisotropic plasma deep etching method, b) irradiating the area of the silicon substrate which forms the base of the separation trenches using laser light, the silicon substrate being converted from a crystalline state into an at least partially amorphous state by the irradiation in this area, and c) inducing mechanical stresses in the substrate. In one specific embodiment, cavities are etched simultaneously with the etching of the separation trenches. The etching depths can be controlled via the RIE lag effect. | 2011-07-07 |
20110163399 | Method for Manufacturing Microelectronic Devices and Devices According to Such Methods - A method is disclosed for manufacturing a sealed cavity in a microelectronic device, comprising forming a sacrificial layer at least at locations where the cavity is to be provided, depositing a membrane layer over the top of the sacrificial layer, patterning the membrane layer in at least two separate membrane layer blocks, removing the sacrificial layer through the membrane layer, and sealing the cavity by sealing the membrane layer, wherein patterning the membrane layer is performed after removal of the sacrificial layer. | 2011-07-07 |
20110163400 | FERROMAGNETIC TUNNEL JUNCTION ELEMENT AND METHOD OF DRIVING FERROMAGNETIC TUNNEL JUNCTION ELEMENT - In a tunnel junction element having a ferromagnetic free layer, an insulating layer and a ferromagnetic fixed layer, in order to reduce the current necessary for spin-transfer magnetization reversal operation in the tunnel junction element, the ferromagnetic free layer comprises first and second ferromagnetic layers, a nonmagnetic metal layer is provided between these ferromagnetic layers, the nonmagnetic metal layer is such that magnetic coupling is preserved between the first and second ferromagnetic layers, also such that there is no influence on the crystal growth of the first and second ferromagnetic layers, the first ferromagnetic layer and the second ferromagnetic layer are placed such that the first ferromagnetic layer is in contact with the insulating layer, and the second ferromagnetic layer has a smaller magnetization than the first ferromagnetic layer. | 2011-07-07 |
20110163401 | SEMICONDUCTOR DEVICE HAVING MEMORY ELEMENT WITH STRESS INSULATING FILM - Provided are a semiconductor device having an MTJ element capable of intentionally shifting the variation, at the time of manufacture, of a switching current of an MRAM memory element in one direction; and a manufacturing method of the device. The semiconductor device has a lower electrode having a horizontally-long rectangular planar shape; an MTJ element having a vertically-long oval planar shape formed on the right side of the lower electrode; and an MTJ's upper insulating film having a horizontally-long rectangular planar shape similar to that of the lower electrode and covering the MTJ element therewith. As the MTJ's upper insulating film, a compressive stress insulating film or a tensile stress insulating film for applying a compressive stress or a tensile stress to the MTJ element is employed. | 2011-07-07 |
20110163402 | MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic memory according to the present invention has: a first underlayer; a second underlayer so formed on the first underlayer as to be in contact with the first underlayer; and a data storage layer so formed on the second underlayer as to be in contact with the second underlayer. The data storage layer is made of a ferromagnetic material having perpendicular magnetic anisotropy. A magnetization state of the data storage layer is changed by current driven domain wall motion. | 2011-07-07 |
20110163403 | NANOSTRUCTURE-BASED TRANSPARENT CONDUCTORS HAVING INCREASED HAZE AND DEVICES COMPRISING THE SAME - The present disclosure relates to modifications to nanostructure based transparent conductors to achieve increased haze/light-scattering with different and tunable degrees of scattering, different materials, and different microstructures and nanostructures. | 2011-07-07 |
20110163404 | Germanium Film Optical Device - A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes. | 2011-07-07 |
20110163405 | Image Sensor with Pixel Wiring to Reflect Light - An image sensor with a plurality of photodiode pixels supported by a substrate. At least one of the photodiode pixels includes a reflective element that prevents light from traveling onto an adjacent photodiode pixel. The reflective element may be a floating contact on a dielectric barrier that insulates the contact from a substrate. The reflective element may be a via that may or may not be an essential part of an electrical connection between two or more integrated devices. The reflective element may be elongated in a horizontal section parallel to the substrate to maximize the reflective surface area and thus longer than standard vias and contacts. The reflective element may be non-rectilinear. The via may be directly above but insulated from a conductor by a dielectric layer thinner than an inter-metal dielectric (IMD) thickness between interconnect layers, and may straddle one or more conductors. | 2011-07-07 |
20110163406 | PHOTODIODE - A photodiode includes a photosensitive element formed in a silicon semiconductor layer on an insulation layer. The photosensitive element includes a low concentration diffusion layer, a P-type high concentration diffusion layer, and an N-type high concentration diffusion layer. A method of producing the photodiode includes the steps of: forming an insulation material layer on the silicon semiconductor layer after the P-type impurity and the N-type impurity are implanted into the low concentration diffusion layer, the P-type high concentration diffusion layer, and the N-type high concentration diffusion layer; forming an opening portion in the insulation material layer in an area for forming the low concentration diffusion layer; and etching the silicon semiconductor layer in the area for forming the low concentration diffusion layer so that a thickness of the silicon semiconductor layer is reduced to a specific level. | 2011-07-07 |
20110163407 | PHOTOELECTRIC CONVERSION DEVICE, METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE, AND IMAGE PICKUP SYSTEM - A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C | 2011-07-07 |
20110163408 | Schottky diode with low reverse leakage current and low forward voltage drop - A Schottky diode structure with low reverse leakage current and low forward voltage drop has a first conductive material semiconductor substrate combined with a metal layer. An oxide layer is formed around the edge of the combined conductive material semiconductor substrate and the metal layer. A plurality of dot-shaped or line-shaped second conductive material regions are formed on the surface of the first conductive material semiconductor substrate connecting to the metal layer. The second conductive material regions form depletion regions in the first conductive material semiconductor substrate. The depletion regions can reduce the leakage current area of the Schottky diode, thereby reducing the reverse leakage current and the forward voltage drop. When the first conductive material is a P-type semiconductor, the second conductive material is an N-type semiconductor. When the first conductive material is an N-type semiconductor, the second conductive material is a P-type semiconductor. | 2011-07-07 |
20110163409 | SEMICONDUCTOR DEVICE - A TMBS diode is disclosed. In an active portion and a voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of an n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device is high in withstand voltage without injection of minority carriers, and electric field intensity of a trench formed in an end portion of an active portion is relaxed. | 2011-07-07 |
20110163410 | METHOD FOR PRODUCING HYBRID COMPONENTS - A method for producing a hybrid substrate, including a support substrate, a continuous buried insulator layer and, on this continuous layer, a hybrid layer including alternating zones of a first material and at least one second material, wherein these two materials are different by their nature and/or their crystallographic characteristics. The method forms a hybrid layer, including alternating zones of first and second materials, on a homogeneous substrate, assembles this hybrid layer, the continuous insulator layer and the support substrate, and eliminates a part at least of the homogeneous substrate, before or after the assembling. | 2011-07-07 |
20110163411 | MULTI-LAYER MEMORY DEVICES - A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions. | 2011-07-07 |
20110163412 | ISOLATOR AND METHOD OF MANUFACTURING THE SAME - The present invention relates to an isolator and a method of manufacturing the same. An isolator according to the present invention includes a silicon wafer, protective devices formed in predetermined regions of the silicon wafer, and a transformer formed in a predetermined region on the silicon wafer, the transformer having at least two coil patterns spaced apart from each other. According to the present invention, an isolator can be protected from impulses generated by ESD and surge, so that its reliability can be improved, and its size can be considerably decreased. Further, the number of wire bonding times is decreased, so that performance of a chip can be enhanced, and packaging efficiency can be improved, thereby increasing productivity. | 2011-07-07 |
20110163413 | RF SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A radio frequency (RF) semiconductor device includes a semiconductor substrate, a resistor film formed at one area of the semiconductor substrate, a first metal layer formed on the semiconductor substrate, a dielectric layer formed at least on the lower electrode film, a second metal layer formed on the dielectric layer, a first insulating layer having a first pad via connected with the first metal layer, a capacitor via connected with the second metal layer, and an inductor via connected with the first or second metal layer. a third metal layer includes filling parts that fill the capacitor via and the inductor via, respectively, and a second circuit line. A second insulating layer is formed on the first insulating layer to have a second pad via connected with the first pad via. A bonding pad is formed at the first and second pad vias. | 2011-07-07 |
20110163414 | Semiconductor Device Having Embedded Integrated Passive Devices Electrically Interconnected Using Conductive Pillars - A semiconductor device includes a first conductive layer and conductive pillars disposed over the first conductive layer and directly contacting the first conductive layer. The semiconductor device includes an Integrated Passive Device (IPD) mounted to the first conductive layer such that the IPD is disposed between the conductive pillars. The IPD is self-aligned to the first conductive layer, and includes a metal-insulator-metal capacitor disposed over a first substrate and a wound conductive layer forming an inductor disposed over the first substrate. The semiconductor device includes a discrete capacitor mounted over the first conductive layer. The discrete capacitor is electrically connected to one of the conductive pillars. The semiconductor device includes an encapsulant disposed around the IPD, discrete capacitor, and conductive pillars, a first insulation layer disposed over the encapsulant and conductive pillars, and a second conductive layer disposed over the first insulating layer. The second conductive layer is electrically connected to the conductive pillars. | 2011-07-07 |
20110163415 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises depositing an absorption barrier layer of a dielectric film on a semiconductor substrate including a bottom electrode contact plug so as to separate the dielectric films between capacitors without having any influence of a bias of the adjacent capacitor, thereby improving a refresh characteristic of cells. | 2011-07-07 |
20110163416 | METHODS FOR FORMING SMALL-SCALE CAPACITOR STRUCTURES - The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å. | 2011-07-07 |
20110163417 | METHOD TO DYNAMICALLY TUNE PRECISION RESISTANCE - A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging. | 2011-07-07 |
20110163418 | Mounting structures for integrated circuit modules - A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits. | 2011-07-07 |
20110163419 | ALLOTROPIC OR MORPHOLOGIC CHANGE IN SILICON INDUCED BY ELECTROMAGNETIC RADIATION FOR RESISTANCE TURNING OF INTEGRATED CIRCUITS - An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology. | 2011-07-07 |
20110163420 | ASPECT RATIO ADJUSTMENT OF MASK PATTERN USING TRIMMING TO ALTER GEOMETRY OF PHOTORESIST FEATURES - A method for adjusting the geometry of photomask patterns is provided. Such adjusted pattern can be employed to achieve pattern doubling in subsequent layers. A patterned photoresist mask is provided over an underlayer. A polymer layer is placed over the mask. The mask is selectively trimmed to generate individual mask features having an increased aspect ratio. Subsequent pattern layers can be formed on the trimmed mask pattern to generate a hard mask having increased pattern density. The hard mask is selectively etched and the material of the trimmed mask pattern is removed. The underlayer is then etched to achieve pattern transfer from the hard mask to the underlayer to achieve a final double density pattern. | 2011-07-07 |
20110163421 | Method for Fabricating Optical Semiconductor Tubes and Devices Thereof - Semiconductor micro- and nanotubes allow the incorporation of ordered structures such as quantum wells and quantum dots into them providing the potential for ultralow threshold micro- and nanoscale lasers for use in applications such as future ultrahigh-speed photonic systems as well as quantum information processing. According to the invention a means of manufacturing these with high reproducibility, low processing complexity, and at high densities is provided. Also provided is a means of releasing these micro- and nanotubes with low stress and a method of “pick-and-place” allowing micro- and nanotubes to be exploited in devices integrated on substrates that are either incompatible with the manufacturing technique or where the area of substrate required to manufacture them is detrimental to the cost or performance of the circuit. | 2011-07-07 |
20110163422 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF PRINTING ON SEMICONDUCTOR WAFER - A method of printing on a semiconductor wafer, a manufacturing method of a semiconductor device, and a semiconductor device which enable to easily perform positioning in the direction perpendicular to the top of the wafer and to easily identify the type of the wafer. The manufacturing method includes preparing a semiconductor wafer having a structure in which an element forming film is stacked on the top of an insulative transparent substrate, forming a light reflection film to reflect light for positioning on the bottom of the transparent substrate, irradiating a laser from the side at which the element forming film is disposed so as to form printed letters at the light reflection film, forming a semiconductor element at the element forming film, forming an interlayer dielectric film to cover the element forming film and the semiconductor element, forming a contact wire, and forming a metal wire on the interlayer dielectric film. | 2011-07-07 |
20110163423 | METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME - A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked. | 2011-07-07 |