27th week of 2012 patent applcation highlights part 66 |
Patent application number | Title | Published |
20120173784 | INFORMATION PROCESSING SYSTEM AND FUNCTIONALITY EXPANSION APPARATUS - An information processing system is disclosed which includes: an information processing apparatus proper configured to include an optical communication connection portion establishing optical communication connection; a first functionality expansion apparatus configured to have an optical communication connection portion optically communicating with the information processing apparatus proper, and a first processing function portion processing or storing data for use by the information processing apparatus; and a second functionality expansion apparatus configured to have an optical communication connection portion optically communicating with the first functionality expansion apparatus, and a second processing function portion. | 2012-07-05 |
20120173785 | NETWORK INTERFACE CARD, NETWORK SYSTEM, AND METHOD FOR BUILDING NETWORK CONNECTIONS WITH A REMOTE NETWORK APPARATUS VIA HDMI - A network interface card includes a receiving unit and a capturing unit. The receiving unit is used for receiving a first hot-plug signal transmitted from a remote network apparatus via an HDMI. The capturing unit is coupled to the receiving unit, for capturing a physical address of the remote network apparatus via the HDMI. After the physical address of the remote network apparatus is captured by the capturing unit, the network interface card communicates with the remote network apparatus by using the HDMI. | 2012-07-05 |
20120173786 | METHOD AND SYSTEM FOR PERFORMING DMA IN A MULTI-CORE SYSTEM-ON-CHIP USING DEADLINE-BASED SCHEDULING - A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer. | 2012-07-05 |
20120173787 | ANALOG INTERFACE FOR A MICROPROCESSOR-BASED DEVICE - An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit. | 2012-07-05 |
20120173788 | Computing Element Virtualization - System and method for virtualization of computing elements. A hypervisor provides virtualization of one or more peripherals for one or more computing elements. The hypervisor may further allow separate instances of an operating system to be suspended on one computing element to allow another application to be processed by replacing the state information of the computing element. The suspended instance may be resumed on the same or a different computing element. | 2012-07-05 |
20120173789 | ALBUM USB - The Daleth Album USB (Daleth) is an album applied to a USB used for the purpose of listening, storing and distributing music. The functionality is that the Daleth Album USB is to act as an audio record or compact disc (CD) for the music, and the outside is to act as an audio record cover or CD case in which it has the artist(s) image or the image to represent the album along with album title. The Daleth Album USB can be used in computers, exercise machines, vehicles with USB ports, radios with USB ports, and other devices with USB compatibility. | 2012-07-05 |
20120173790 | STORAGE SYSTEM CACHE WITH FLASH MEMORY IN A RAID CONFIGURATION - Embodiments of the invention relate to a storage system cache with flash memory units organized in a RAID configuration. An aspect of the invention includes a storage system comprising a storage system cache with flash memory in a RAID configuration. The storage cache comprises flash memory units organized in an array configuration. Each of the flash memory units comprises flash memory devices and a flash unit controller. Each flash unit controller manages data access and data operations for its corresponding flash memory devices. The storage system further includes an array controller, coupled to the flash memory units, and that manages data access and data operations for the flash memory units and organizes data as full array stripes. The storage system further includes a primary storage device, which is coupled to the array controller, and stores data for the storage system. The storage system further includes a storage cache controller, coupled to the array controller, and comprises a block line manager that buffers write data to be cached for a write operation until the storage cache controller has accumulated an array band, and commits write data to the array controller as full array stripes. The storage cache controller receives storage commands from at least one host system. The storage cache controller determines for a write data storage command, whether to store write data in the storage cache and/or in the primary storage device; and for a read data storage command, whether to access read data from the storage cache or from the primary storage device. | 2012-07-05 |
20120173791 | CONTROL METHOD AND ALLOCATION STRUCTURE FOR FLASH MEMORY DEVICE - A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively. | 2012-07-05 |
20120173792 | Controller and Method for Performing Background Operations - The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed. | 2012-07-05 |
20120173793 | MEMORY DEVICE USING EXTENDED INTERFACE COMMANDS - A memory device includes a serial interface buffer that receives a hardware-decodable command and an extended interface command. The memory device also includes a logic module that directs the hardware-decodable command to a register for execution by a microcontroller. The logic module additionally loads a command received following the extended interface command into a sub-op-code register, wherein the logic module remains passive after loading the command received following the extended interface command into the sub-op-code register. Also included is a microcontroller that interprets the command in the sub-op-code register. | 2012-07-05 |
20120173794 | DRIVE ASSISTED SYSTEM CHECKPOINTING - Systems and methods of managing computing system restore points may include an apparatus having logic to receive a command to start a restore point for a solid state drive (SSD). The logic may also conduct a context drop of an indirection table from a volatile memory of the SSD to a non-volatile memory of the SSD in response to the command to start the restore point. | 2012-07-05 |
20120173795 | SOLID STATE DRIVE WITH LOW WRITE AMPLIFICATION - A solid state drive having a non-volatile memory device and methods of operating the solid state drive to compare existing data stored on the memory device to subsequent data in an incoming data stream received by the solid state drive from a host system. If matching data are found, the solid state drive uses the existing data instead of writing the subsequent data to the memory device. Common data patterns can be shared among different files stored on the memory device. | 2012-07-05 |
20120173796 | METHOD FOR PERFORMING BLOCK MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided, where the method is applied to a controller of a Flash memory that includes a plurality of blocks. The method includes: selecting a target block having a least erase count from at least one portion of blocks in a data region of the Flash memory, and utilizing the target block as a block to be erased, wherein serial numbers of the at least one portion of blocks correspond to order of last update of the at least one portion of blocks, respectively; and determining whether to move/copy valid data of the target block into a heavily worn block or a lightly worn block according to a serial number of the target block, where the degree of wear of the heavily worn block is higher than that of the lightly worn block. An associated memory device and a controller thereof are also provided. | 2012-07-05 |
20120173797 | METHOD FOR PERFORMING BLOCK MANAGEMENT/FLASH MEMORY MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory having multiple channels. The Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: selecting at least one meta block having at least one valid page as at least one candidate meta block for being cleaned, and accumulating respective valid page counts of blocks respectively corresponding to the channels within the at least one candidate meta block, in order to generate a plurality of accumulated values respectively corresponding to the channels; and when it is detected that all of the accumulated values reach a threshold value, triggering a cleaning operation with regard to all candidate meta blocks, in order to simultaneously move/copy valid data respectively corresponding to the channels during the cleaning operation. An associated memory device and a controller thereof are also provided. | 2012-07-05 |
20120173798 | MEMORY CONTROLLER, MEMORY DEVICE AND METHOD FOR DETERMINING TYPE OF MEMORY DEVICE - A memory controller includes a clock detector and a microprocessor. The clock detector is utilized for detecting if a specific pin of the memory controller has a clock signal thereon to generate a detecting result. The microprocessor is coupled to the clock generator, and is utilized for determining which type of memory devices that the memory controller is applied to according to the detecting result. | 2012-07-05 |
20120173799 | DATA STORAGE APPARATUS, INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - An information storage apparatus that includes a memory unit, a first controller that reads data from the memory unit, and a second controller included in the memory unit that reads a first identification and outputs the first identification in response to an external instruction, wherein the first identification may only be read by the second controller. | 2012-07-05 |
20120173800 | SYSTEM INCLUDING DATA STORAGE DEVICE, AND DATA STORAGE DEVICE INCLUDING FIRST AND SECOND MEMORY REGIONS - A data storage device includes a non-volatile memory device including a memory cell array, where the memory cell array includes a first region and a second region, and a memory controller configured to judge whether a size of data externally provided according to a write request exceeds a reference size, and to control the non-volatile memory device according to a judgment result. When the externally provided data exceeds the reference size, the memory controller controls the non-volatile memory device such that a portion of the externally provided data is stored in the second region via a main program operation and such that a remainder of the externally provided data is stored in the first region via a buffer program operation. | 2012-07-05 |
20120173801 | DATA PROCESSING DEVICE, DATA RECORDING METHOD AND DATA RECORDING PROGRAM - A data processing device has plural kinds of recording media and a data block management device. The data block management device classifies data blocks into plural groups and records each group on an appropriate recording medium. The data block management device has a memory unit, a group reconfiguration unit and a medium selection unit. Access trend information representing a trend of combinations of former groups and latter groups is stored in the memory unit. The group reconfiguration unit performs group reconfiguration processing by reference to the access trend information. Specifically, if a sequential access trend between two different groups is increased, they are integrated to generate a new group. If a sequential access trend within a certain group is decreased, the certain group is divided to generate a new group. The medium selection unit records the new group obtained as a result of the group reconfiguration on a corresponding recording medium. | 2012-07-05 |
20120173802 | FLASH MEMORY STORAGE SYSTEM - A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration. | 2012-07-05 |
20120173803 | METHODS AND APPARATUS TO SHARE A THREAD TO RECLAIM MEMORY SPACE IN A NON-VOLATILE MEMORY FILE SYSTEM - A disclosed example method involves associating a shared reclaim thread with an on-board flash memory device to reclaim first memory space in the on-board flash memory device. The shared reclaim thread is associated with a removable flash memory device to reclaim second memory space in the removable flash memory device while the shared reclaim thread is also in association with the on-board flash memory device. Different priorities are assigned to the on-board flash memory device and the removable flash memory device to selectively reclaim the first and second memory spaces based on the different priorities. | 2012-07-05 |
20120173804 | METHODS OF OPERATING A MEMORY SYSTEM - Methods of operating a memory system are useful in facilitating access to data. Where repetitive data patterns are detected among portions of received data, and an indication is provided, a portion of the data may be stored and/or subsequently retrieved without having to store and/or retrieve, respectively, all portions of the data. | 2012-07-05 |
20120173805 | DATA ACCESSING METHOD FOR FLASH MEMORY STORAGE DEVICE HAVING DATA PERTURBATION MODULE, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module. | 2012-07-05 |
20120173806 | SOLID STATE DISK CONTROLLER APPARATUS - A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus. | 2012-07-05 |
20120173807 | Cache Control in a Non-Volatile Memory Device - A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations. | 2012-07-05 |
20120173808 | MEMORY, COMPUTING SYSTEM AND METHOD FOR CHECKPOINTING - Embodiments of the present invention provide local checkpoint memories that are closely coupled to the processor of a computing system used during normal operation. The checkpoint memory may be coupled to the processor through a peripheral bus or a memory bus. The checkpoint memory may be located on a same semiconductor substrate or circuit board as the processor. The checkpoint memory may be located on a same semiconductor substrate as a main memory used by the processor during normal operation. The checkpoint memory may be included in a memory hub configuration, with a checkpoint memory hub provided for access to the checkpoint memory. | 2012-07-05 |
20120173809 | Memory Device Having DRAM Cache and System Including the Memory Device - The present disclosure relates to a memory device and a system including the memory device. The memory device may include a non-volatile memory, a dynamic random access memory (DRAM) cache, a DRAM, and a control circuit. The control circuit may perform interfacing between the DRAM and a host, between the DRAM cache and the host, and between the non-volatile memory and the DRAM cache. The memory device may have a high operating speed and may be incorporated in a simple package, such as a multi-chip package. | 2012-07-05 |
20120173810 | Method and Apparatus for Indicating Mask Information - An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data. | 2012-07-05 |
20120173811 | Method and Apparatus for Delaying Write Operations - An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal. | 2012-07-05 |
20120173812 | METHOD AND SYSTEM FOR DATA DISTRIBUTION ACROSS AN ARRAY OF DRIVES - Methods and systems for data distribution may include, but are not limited to: receiving a request from a client device to store data on a distributed storage system; obtaining a hierarchical cluster map representing the distributed storage system; selecting an object at a hierarchical level of the cluster map; determining if the hierarchical level is a drive level; and adding a drive identifier associated with the object to a drive identifier array if the hierarchical level is the drive level. | 2012-07-05 |
20120173813 | STORAGE CONTROL APPARATUS UNIT AND STORAGE SYSTEM COMPRISING MULTIPLE STORAGE CONTROL APPARATUS UNITS - A first storage control apparatus unit has a first logical volume. A second storage control apparatus unit has a second logical volume, which is a virtual logical volume and is mapped to the first logical volume, and a third logical volume that is associated with the first logical volume. The second storage control apparatus unit receives, from a host, an I/O command which has information including, as information denoting an I/O-destination area, an ID of the second logical volume and an address of an area of the second logical volume. The second storage control apparatus unit identifies a logical volume having an area that serves as an entity of the I/O-destination area, and a storage control apparatus unit that has this logical volume. | 2012-07-05 |
20120173814 | STORAGE CONTROLLER AND VIRTUAL VOLUME CONTROL METHOD - A storage system includes a virtual volume, a plurality of RAID groups, a pool unit for managing a plurality of first real storage areas and a controller. If a write command related to the virtual volume is issued from a higher-level device, the controller selects a prescribed second real storage area from among respective second real storage areas included in a prescribed first real storage area, and associates this prescribed second real storage area with a prescribed area inside the virtual volume corresponding to the write command, and which associates one virtual volume with one first real storage area. A migration destination determination unit selects a migration-targeted second real storage area from among the respective second real storage areas associated with the virtual volume, and selects a migration-destination first real storage area, which is to become the migration destination of data stored in the migration-targeted second real storage area. | 2012-07-05 |
20120173815 | System For Handling Input/Output Requests Between Storage Arrays With Different Performance Capabilities - An apparatus comprising a remote storage array, a primary storage array and a network. The remote storage array may be configured to (i) define a queue size based on a performance capability of the remote storage array, (ii) generate a multiplier based on resources being used by the remote storage array, and (iii) adjust the queue size by the multiplier. The primary storage array may be configured to execute input/output (IO) requests between the remote storage array and the primary storage array based on the adjusted queue size. The network may be configured to connect the remote storage array to the primary storage array. | 2012-07-05 |
20120173816 | ELECTRONIC DEVICE AND METHOD FOR ASSOCIATING MEMORY CARD WITH ELECTRONIC DEVICE - An electronic device for associating at least one memory card and data therein with itself and a method thereof are provided. The device includes a storage unit storing a relationship between one or more identity codes and corresponding associated information. The association information corresponding to each identity code records relationship between at least one application capable of being run by the device and associated data stored in a memory card having the identity code. A processor determines the identity code of a memory card connected to the electronic device, determines the corresponding association information based on the determined identity code and the stored relationship, and associates the at least one application with the associated data according to the determined association information. | 2012-07-05 |
20120173817 | METHOD FOR PROCESSING PARALLEL DATA STORAGE AND AUTHENTICATION AND A TERMINAL - The present invention discloses a method for processing parallel data storage and authentication and a terminal. In this case, the method comprises: a data processing thread of a terminal storing data into a corresponding cache area according to a type of the data, wherein the type of the data comprises authentication type and storage type, data of the authentication type is stored in a first cache area, and data of the storage type is stored in a second cache area; a scheduling processing thread of the terminal reading data from the first cache area and the second cache area alternately according to a reading rule associated with the data type, and sending the read data to a smart card of the terminal; and the smart card performing storage or authentication according to the type of the received data. By way of the present invention, the problem that data storage operation is failed when there is data authentication operation is solved, thus achieving the effect of improving terminal performance and user experience satisfaction. | 2012-07-05 |
20120173818 | DETECTING ADDRESS CONFLICTS IN A CACHE MEMORY SYSTEM - A cache memory includes a data array that stores memory blocks, a directory of contents of the data array, and a cache controller that controls access to the data array. The cache controller includes an address conflict detection system having a set-associative array configured to store at least tags of memory addresses of in-flight memory access transactions. The address conflict detection system accesses the set-associative array to detect if a target address of an incoming memory access transaction conflicts with that of an in-flight memory access transaction and determines whether to allow the incoming transaction memory access transaction to proceed based upon the detection. | 2012-07-05 |
20120173819 | Accelerating Cache State Transfer on a Directory-Based Multicore Architecture - Technologies are generally described herein for accelerating a cache state transfer in a multicore processor. The multicore processor may include first, second, and third tiles. The multicore processor may initiate migration of a thread executing on the first core at the first tile from the first tile to the second tile. The multicore processor may determine block addresses of blocks to be transferred from a first cache at the first tile to a second cache at the second tile, and identify that a directory at the third tile corresponds to the block addresses. The multicore processor may update the directory to reflect that the second cache shares the blocks. The multicore processor may transfer the blocks from the first cache in the first tile to the second cache in the second tile effective to complete the migration of the thread from the first tile to the second tile. | 2012-07-05 |
20120173820 | Distributed Cache for Graph Data - A distributed caching system for storing and serving information modeled as a graph that includes nodes and edges that define associations or relationships between nodes that the edges connect in the graph. | 2012-07-05 |
20120173821 | Predicting the Instruction Cache Way for High Power Applications - A mechanism for accessing a cache memory is provided. With the mechanism of the illustrative embodiments, a processor of the data processing system performs a first execution a portion of code. During the first execution of the portion of code, information identifying which cache lines in the cache memory are accessed during the execution of the portion of code is stored in a storage device of the data processing system. Subsequently, during a second execution of the portion of code, power to the cache memory is controlled such that only the cache lines that were accessed during the first execution of the portion of code are powered-up. | 2012-07-05 |
20120173822 | System and method for storing data off site - A system and method for efficiently storing data both on-site and off-site in a cloud storage system. Data read and write requests are received by a cloud data storage system. The cloud storage system has at least three data storage layers. A first high-speed layer, a second efficient storage layer, and a third off-site storage layer. The first high-speed layer stores data in raw data blocks. The second efficient storage layer divides data blocks from the first layer into data slices and eliminates duplicate data slices. The third layer stores data slices at an off-site location. | 2012-07-05 |
20120173823 | APPLICATION CACHE PROFILER - In an embodiment of the invention, a method for data profiling incorporating an enterprise service bus (ESB) coupling the target and source systems following an extraction, transformation, and loading (ETL) process for a target system and a source system is provided. The method includes receiving baseline data profiling results obtained during ETL from a source application to a target application, caching the updates, determining current data profiling results within the ESB for cached updates, and triggering an action if a threshold disparity is detected upon the current data profiling results and the baseline data profiling results. | 2012-07-05 |
20120173824 | MANAGING CACHE DATA AND METADATA - Embodiments of the invention provide techniques for managing cache metadata providing a mapping between addresses on a storage medium (e.g., disk storage) and corresponding addresses on a cache device at which data items are stored. In some embodiments, cache metadata may be stored in a hierarchical data structure comprising a plurality of hierarchy levels. When a reboot of the computer is initiated, only a subset of the plurality of hierarchy levels may be loaded to memory, thereby expediting the process of restoring the cache metadata and thus startup operations. Startup may be further expedited by using cache metadata to perform operations associated with reboot. | 2012-07-05 |
20120173825 | Cache Result Register for Quick Cache Information Lookup - Each level of cache within a memory hierarchy of a device is configured with a cache results register (CRR). The caches are coupled to a debugger interface via a peripheral bus. The device is placed in debug mode, and a debugger forwards a transaction address (TA) of a dummy transaction to the device. On receipt of the TA, the device processor forwards the TA via the system bus to the memory hierarchy to initiate an address lookup operation within each level of cache. For each cache in which the TA hits, the cache controller (debug) logic updates the cache's CRR with Hit, Way, and Index values, identifying the physical storage location within the particular cache at which the corresponding instruction/data is stored. The debugger retrieves information about the hit/miss status, the physical storage location and/or a copy of the data via direct requests over the peripheral bus. | 2012-07-05 |
20120173826 | MEMORY SYSTEM AND METHOD FOR CONTROLLING MEMORY SYSTEM - A memory system connected to another apparatus via a data crossbar, has a first memory, a second memory that forms a dual configuration together with the first memory, a first memory controller that transmits or receives data to be written into the first memory or data read out from the first memory to or from the other apparatus, a second memory controller that transmits or receives data to be written into the second memory or data read out from the second memory to or from the other apparatus, and a system controller that instructs the first memory controller and the second memory controller to read out, from the first memory and the second memory, data requested to be read out by the other apparatus if the system controller detects that any one of the first data crossbar and the second data crossbar being not capable of transmitting or receiving data. | 2012-07-05 |
20120173827 | APPARATUS, SYSTEM, AND METHOD FOR USING MULTI-LEVEL CELL STORAGE IN A SINGLE-LEVEL CELL MODE - A controller is used for an electronic memory device which has multi-level cell (MLC) memory elements. Each MLC memory element is capable of storing at least two bits. The controller includes a physical interface to couple the controller to the electronic memory device. The controller also includes a processing unit coupled to the physical interface. The processing unit operates the electronic memory device in a single-level cell (SLC) mode using a restricted number of programming states for a single data bit. The restricted number of programming states includes a first state which is an erase state. The restricted number of programming states also includes a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements. | 2012-07-05 |
20120173828 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER READABLE MEDIUM STORING PROGRAM - An information processing apparatus includes an operation detector that detects an operation performed on information, a history memory controller that controls a history memory such that the history memory stores as history information an operator and information, serving as an operation target, in a mapped state if the operation detector has detected the operation, an extractor that extracts from the history memory an operator having performed the operation if the operation detector has detected the operation, and a notifier that notifies the operator extracted by the extractor that the operation has been performed on the information. | 2012-07-05 |
20120173829 | INTERLEAVER AND INTERLEAVING METHOD - An interleaving method includes: generating multiple read-addresses for respective bits of multiple write-words; queuing the read-addresses in parallel in multiple address queues; selecting an address queue among the address queues that is not empty based on status of each address queue; decoding the address from the selected address queue to a read-address and a bit-address; extracting a read-word from data to be interleaved based on the read-address; selecting a write-bit from the read-word based on the bit-address; arbitrating an individual write-bit to one of the write-words based on an address queue ID of the selected address queue; and generating write-addresses for respective write-words. | 2012-07-05 |
20120173830 | SYNCHRONIZATION OF LOGICAL COPY RELATIONSHIPS - An approach to synchronization of logical copy relationships on a local site with those on a remote site that is a mirror. A withdraw command is received on the local site for logical copy relationships between local source tracks and local target tracks. The withdraw command is executed and sent to a remote site buffer, from which it will be transferred to the remote site. Change indicators are set for the at least one local track in the affected logical copy relationships. If the withdraw command is lost from the remote site buffer, the remote site buffer will be rebuilt using the change indicators. By setting change indicators for local tracks in a withdrawn logical copy relationship (even if the data in local tracks hasn't changed), the remote counterparts to these tracks on the remote site will be rewritten, resulting in withdrawal of the logical copy relationship there even if the withdrawal command was never sent to the remote site. | 2012-07-05 |
20120173831 | DATA AWARE STORAGE SYSTEM OPERATIONS - Apparatus, systems, and methods may operate to classify storage locations in a storage medium according to at least three response time grades, to classify data to be stored in the storage locations according to at least three access frequency grades, and to migrate the data between the storage locations according to a predicted access frequency assigned to preemptive allocations of some of the storage locations, based on the response time grade and the access frequency grade associated with the data prior to migration. Other apparatus, systems, and methods are disclosed. | 2012-07-05 |
20120173832 | HANDLING DYNAMIC AND STATIC DATA FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for handling dynamic and static data for a system having non-volatile memory (“NVM”). By determining whether data being written to the NVM is dynamic or not, a NVM interface of a system can determine where to initially place the data on the NVM (e.g., place the data on either a dynamic stream block or a static stream block). Moreover, this information can allow the NVM interface to improve the efficiencies of both garbage collection (“GC”) and wear leveling. | 2012-07-05 |
20120173833 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR AVOIDING RECALL OPERATIONS IN A TIERED DATA STORAGE SYSTEM - According to one embodiment, a system includes logic adapted to: receive a request to open an existing data set indicating a write operation, receive new data to write to the existing data set, determine that the existing data set is stored on a lower tier of a tiered data storage system, determine that the existing data set is capable of being updated by appending the new data to an end of the existing data set, create a temporary data set on a higher tier of the tiered data storage system comprising the new data, associate the temporary data set on the higher tier of the tiered data storage system with the existing data set on the lower tier of the tiered data storage system, and create a write indicator associated with the new data set indicating that the new data set belongs at the end of the existing data set. | 2012-07-05 |
20120173834 | MANAGING DATA ACROSS A PLURALITY OF DATA STORAGE DEVICES BASED UPON COLLABORATION RELEVANCE - A computer-implemented method of managing data storage according to collaborative activity can include determining collaborative activity for each of a plurality of data items associated with a first user and stored within a first data storage device. The method can include calculating a measure of relevancy for each of the plurality of data items according to the collaborative activity and comparing the measure of relevancy of each of the plurality of data items to at least one relevancy threshold. Different ones of the plurality of data items can be selectively migrated from the first data storage device to a second data storage device according to the comparison of the measure of relevancy of each of the plurality of data items. | 2012-07-05 |
20120173835 | SELECTIVE REGISTER RESET - The present disclosure includes methods, devices, modules, and systems for storing selective register reset. One method embodiment includes receiving an indication of a die and a plane associated with at least one address cycle. Such a method can also include selectively resetting a particular register of a number of registers, the particular register corresponding to the plane and the die. | 2012-07-05 |
20120173836 | Dynamic Frequency Memory Control - A memory controller ( | 2012-07-05 |
20120173837 | MEMORY SYSTEM - A memory system is described having a memory, at least one memory area of the memory being able to be configured as data memory or as buffer store as a function of a required memory processing rate. | 2012-07-05 |
20120173838 | DATA STORAGE SYSTEM AND METHOD - Various embodiments storing volumes of data in a data storage system, including one or more data storage containers, the data storage containers being thin-provisioned to provide virtual data storage capacity which is greater than a real data storage capacity of the data storage hardware are provided. In one embodiment, by way of example only, a real data storage capacity of the data storage system for accommodating new volumes is determined. Over-allocation information relating to one or more data storage containers is determined. Extrapolated future anticipated use of one or more containers of the data storage system from historical data storage use information is determined. One or more candidate data storage containers on the basis of information from the determining the real data storage capacity, over-allocation information, and the extrapolated future anticipated use is selected. Additional system and computer program product embodiments are disclosed and provide related advantages. | 2012-07-05 |
20120173839 | STORAGE AREA DYNAMIC ASSIGNMENT METHOD - A storage system allocates a data storage area in response to an access request from a first computer if the capacity of a first physical storage device configuring a first logical storage area, provided to the first computer, is equal to or lower than a predetermined threshold. The storage system associates the first logical storage area with another physical storage device, which is different from the first physical storage device associated with a second logical storage area provided to the first computer and a second computer, and allocates a data storage area from the another physical storage device if the capacity of the first physical storage device associated with the first logical storage area exceeds the predetermined threshold. | 2012-07-05 |
20120173840 | SAS EXPANDER CONNECTION ROUTING TECHNIQUES - Disclosed are techniques for allowing an increase in topology size of a serial attached SCSI expander network, as well as limiting entries in content addressable memory that are used to store address locations relating to the system topology. In accordance with one method, addresses are provided in the OAF request to reduce lookup table entries. In accordance with another embodiment, address ranges are provided in the lookup table. In addition, virtual memory techniques are used, so that either a software lookup process can be used, or a hardware process can be used, so that only the most recently used addresses are stored in the lookup table. | 2012-07-05 |
20120173841 | Explicitly Regioned Memory Organization in a Network Element - A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory. The physical memory address includes a network routing information portion that includes information to route the physical memory address to the target instance, and includes an address payload portion that includes information to identify the physical address space identified by the subtarget and the physical memory address offset. | 2012-07-05 |
20120173842 | Operating System Management of Address-Translation-Related Data Structures and Hardware Lookasides - An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled. | 2012-07-05 |
20120173843 | TRANSLATION LOOK-ASIDE BUFFER INCLUDING HAZARD STATE - A system may include a storage medium with multiple entries, each entry of the configured to store a respective address of a memory write request that has not yet been committed to memory. The system may further include a translation lookaside buffer (TLB) including a multiple TLB entries, each TLB entry having an associated address field and associated one or more hazard status fields. The address field may store a translated physical memory address. Each hazard status field may correspond to a respective storage entry of the storage medium, and contain respective information indicating whether the translated physical memory address matches the respective address in the respective storage entry. The system may also include hazard detection logic to receive the respective information from the TLB, and use the respective information to prevent a hazard from occurring when the translated physical memory address is associated with a memory write request that has not yet been committed to memory. | 2012-07-05 |
20120173844 | APPARATUS AND METHOD FOR DETERMINING A CACHE LINE IN AN N-WAY SET ASSOCIATIVE CACHE - A method and apparatus for determining a cache line in an N-way set associative cache are disclosed. In one example embodiment, a key associated with a cache line is obtained. A main hash is generated using a main hash function on the key. An auxiliary hash is generated using an auxiliary hash function on the key. A bucket in a main hash table residing in an external memory is determined using the main hash. An entry in a bucket in an auxiliary hash table residing in an internal memory is determined using the determined bucket and the auxiliary hash. The cache line in the main hash table is determined using the determined entry in the auxiliary hash table. | 2012-07-05 |
20120173845 | Distributed Cache for Graph Data - A distributed caching system for storing and serving information modeled as a graph that includes nodes and edges that define associations or relationships between nodes that the edges connect in the graph. | 2012-07-05 |
20120173846 | METHOD TO REDUCE THE ENERGY COST OF NETWORK-ON-CHIP SYSTEMS - In a network-on-chip (NoC) system, multiple data messages may be transferred among modules of the system. Power consumption due to the transfer of the messages may affect a cost and overall performance of the system. A described technique provides a way to reduce a volume of data transferred in the NoC system by exploiting redundancy of data messages. Thus, if a data message to be sent from a source in the NoC includes so-called “zero” bytes that are bytes including only bits set to “0,” such zero bytes may not be transmitted in the NoC. Information on whether each byte of the data message is a zero byte may be recorded in a storage such as a data structure. This information, together with non-zero bytes of the data message, may form a compressed version of the data message. The information may then be used to uncompress the compressed data message at a destination. | 2012-07-05 |
20120173847 | PARALLEL PROCESSOR AND METHOD FOR THREAD PROCESSING THEREOF - A parallel processor and a method for concurrently processing threads in the parallel processor are disclosed. The parallel processor comprises: a plurality of thread processing engines for processing threads distributed to the thread processing engines, and the plurality of thread processing engines being connected in parallel; a thread management unit for obtaining, judging the statuses of the plurality of thread processing engines, and distributing the threads in a waiting queue among the plurality of thread processing engines. | 2012-07-05 |
20120173848 | PIPELINE FLUSH FOR PROCESSOR THAT MAY EXECUTE INSTRUCTIONS OUT OF ORDER - An embodiment of an instruction pipeline includes first and second sections. The first section is operable to provide first and second ordered instructions, and the second section is operable, in response to the second instruction, to read first data from a data-storage location, is operable, in response to the first instruction, to write second data to the data-storage location after reading the first data, and is operable, in response to the writing the second data after reading the first data, to cause the flushing of a some, but not all, of the pipeline. Such an instruction pipeline may reduce the processing time lost and the energy expended due to a pipeline flush by flushing only a portion of the pipeline instead of flushing the entire pipeline. | 2012-07-05 |
20120173849 | Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response - Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is to required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism. | 2012-07-05 |
20120173850 | INFORMATION PROCESSING APPARATUS - A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer. | 2012-07-05 |
20120173851 | MECHANISM FOR MAINTAINING DYNAMIC REGISTER-LEVEL MEMORY-MODE FLAGS IN A VIRTUAL MACHINE SYSTEM - A method for maintaining dynamic register-level memory-mode flags in a virtual machine includes parsing a machine instruction of a live memory analysis command in a virtual machine (VM). The machine instruction can include an instruction opcode, a source address referring to a first type of memory and a destination address referring to a second type of memory. A register bitmap can be stored as a register-level memory-mode flag array. Thereafter, it can be determined whether or not the instruction opcode maps to an inheritance class. Finally, in response to a bit in the register-level memory mode flag array referencing virtual memory and the instruction opcode being mapped to an inheritance class, the register bitmap can be replaced with new bit values that represent redefined memory types for each register represented in the register bitmap. Subsequently, the new register bitmap can be used in simulation of a next machine instruction of a live memory analysis command executing in the virtual machine. | 2012-07-05 |
20120173852 | INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE - A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode. | 2012-07-05 |
20120173853 | Processing apparatus and method for performing computation - A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction. | 2012-07-05 |
20120173854 | PROCESSOR HAVING INCREASED EFFECTIVE PHYSICAL FILE SIZE VIA REGISTER MAPPING - Methods and apparatuses are provided for an efficient technique for processing registers having a known value while improving processor performance. The apparatus comprises a processor having a plurality of physical registers available for use in computations and a decoder for determining that a logical register contains a known value. A renaming unit maps the logical register containing the known value to an address outside an address range for the plurality of physical registers once the known value is determined. Thereafter, scheduling and execution units perform computations using the known value without storing the known value in one of the plurality of physical registers. The method comprises determining that a logical register of a processor has a known value and then mapping that logical register to a physical register address outside an expected range of physical register addresses; which indicates that the logical register represents the known value. Thereafter the processor processes any instruction using the known value without storing the known value in a physical register. | 2012-07-05 |
20120173855 | Exception Transporting and Handling of Concurrent Exceptions - Methods and systems for handling exceptions, including being provided with a catch list, the catch list being a flattened inheritance tree for exception types in ascending inheritance order, receiving an exception from a thread, searching the catch list in ascending inheritance order to find a matching exception type to received exception. | 2012-07-05 |
20120173856 | Determining Logical Configuration Commands to Create a Logical Object - An approach to generating logical configuration commands for logical objects in a system. A method may involve receiving a command requesting the logical configuration commands to configure the specified logical object (subject logical object) and the logical objects that support the logical object (the support logical objects). The method may also involve determining what logical objects in the system support the subject logical object. This may require determining the support logical objects that directly support the subject logical object, and then recursively examining each support logical objects to find the logical objects on which they depend. For each logical object (whether the subject logical object or one of the support logical objects), the method may involve determining the logical configuration commands to appropriately create and modify the logical object. The logical configuration commands may then be presented to the user. | 2012-07-05 |
20120173857 | OVER THE AIR APPLIANCE FIRMWARE UPDATE - An appliance is placed in a bootload mode and other operations of the appliance are powered down. Data is gathered through an appliance control module which activates the bootloader mode, and then receives the data and overwrites the remainder of the appliance controller memory. In this manner, software for an appliance is updated without having to enter the home. | 2012-07-05 |
20120173858 | METHOD AND APPARATUS TO CREATE SINGLE FIRMWARE IMAGE FOR MULTIPLE SERVER PLATFORMS - According to one aspect, a computer-implemented method for managing a computer system is disclosed. In one embodiment, the computer system includes a processor that is programmed to cause the computer system to perform specific functions. The functions include: initializing a management controller operating on a management platform; detecting preloaded identification data containing a predetermined manufacturer-specific platform identifier; if no preloaded identification data is detected, determining the platform identifier based on GPIO settings, firmware data, EEPROM data, and/or sensor detection; detecting preloaded hardware data containing operating parameters for hardware components operating on the management platform and operatively coupled to the management controller; if no preloaded hardware data is detected, determining the operating parameters according to the platform identifier; causing the management controller to initialize the hardware components according to the platform identifier and operating parameters; and, flashing initialization data containing the platform identifier and operating parameters to a system memory. | 2012-07-05 |
20120173859 | TECHNIQUES FOR STOPPING ROLLING REBOOTS - Techniques for detecting rolling reboots and for taking responsive actions to stop rolling reboots. | 2012-07-05 |
20120173860 | COMPUTING DEVICE AND METHOD FOR REGISTERING IDENTIFICATION INFORMATION OF NETWORK INTERFACE CARD IN OPERATING SYSTEM - In a method for registering identification information of network interface cards (NICs) in an operating system of a computing device, each of the NICs is respectively and uniquely labeled with a number. A peripheral component interconnect (PCI) device identification (ID) of each of the NICs is allocated according to the labeled number of each NIC using a basic input output system (BIOS) of the computing device when the BIOS is booted up. Then identification information of each of the NICs is registered in the operating system according to the PCI device ID of each NIC using a NIC driver of the computing device, when the NIC driver is driven by the operating system during the booting up process of the operating system. | 2012-07-05 |
20120173861 | DATA CARD AND A BOOTING METHOD FOR THE DATA CARD - The present invention discloses a method for a data card to report a port, including: initializing a power-on startup module and a compact disk (CD) reporting and processing module in the boot phase, where the CD reporting and processing module is configured to report a data card as a CD, interact with a terminal, and realize CD reading; and reporting a data card as a CD to a terminal in the boot phase. The data card is reported as a CD after initialization of the power-on startup module and the CD reporting and processing module, rather than after the initialization of the power-on startup module in the boot phase and the user application modules in the network access phase. In this way, the terminal user can quickly find that the data card is reported as a CD after the data card is inserted, which improves the user experience. | 2012-07-05 |
20120173862 | System and Method of Delaying Power-Up of an Information Handling System - A system and method of delaying power-up of an information handling system is disclosed. According to an aspect, a method of powering an information handling system can include detecting a delay power-up setting within a basic input output system (BIOS) of a particular information handling system using a management controller. The management controller can be configured to delay power-up of the particular information handling system. The method can further include enabling a power-up of the particular information handling system in response to the delay power-up setting using the management controller. | 2012-07-05 |
20120173863 | ELECTRONIC DEVICE - An electronic device includes a power source, a processor, a switching module, and an interface module. The power source provides operating voltage. The processor can switch between a first mode and a second mode. The switching module connects between the processor and the interface module. The interface module is used for exchanging data with an external device. When the processor is in the first mode, the switching module turns off. The power source stops providing operating voltage to the interface module. | 2012-07-05 |
20120173864 | FLEXIBLE MULTI-PROCESSING SYSTEM - A processor includes a scalar computation unit; a vector co-processor coupled to the scalar computation unit; and one or more function-specific engines coupled to the scalar computation unit, the engines adapted to minimize data exchange penalties by processing small in-out bit slices. | 2012-07-05 |
20120173865 | System And Method For Generating Multiple Protected Content Formats Without Redundant Encryption Of Content - Embodiments may include generating a first protected version of content, which may include packetizing the content into multiple packets that each includes content information and non-content information and using initialization vectors to perform chained encryption on multiple blocks of the packetized content. At least some of the initialization vectors are generated dependent upon the non-content information. Embodiments may also include using the encrypted blocks to generate a second protected version of the content without re-encrypting the content. The second protected version of the content may include multiple encrypted content samples each including multiple encrypted blocks from the first protected version of the content. For a given encrypted content sample, different sets of encrypted blocks in that sample may form different encryption chains. The second protected version of the content may include decryption information for decrypting the encrypted content samples including initialization vectors used to create the first protected version. | 2012-07-05 |
20120173866 | SYSTEM FOR SECURING VIRTUAL MACHINE DISKS ON A REMOTE SHARED STORAGE SUBSYSTEM - Embodiments of the present invention provide a method, data processing system and computer program product for secure distribution of virtualized storage. In an embodiment of the invention, a method for secure distribution of virtualized storage in a host in a cloud computing can include composing at least one virtual machine (VM) disk in a secure container and configured to deploy VM images into a cloud computing environment, encrypting the composed at least one VM disk, transmitting the encrypted VM disk to a hypervisor in the cloud computing environment receiving a request to activate a VM instance and generating a bootloader in the secure container, transmitting the bootloader to the hypervisor in the cloud computing environment and providing a key to the bootloader to unlock the at least one VM disk. | 2012-07-05 |
20120173867 | METHOD OF AUTHENTICATION AT TIME OF UPDATE OF SOFTWARE EMBEDDED IN INFORMATION TERMINAL, SYSTEM FOR SAME AND PROGRAM FOR SAME - A load on a server or a network is suppressed at a minimum, the authentication server is not necessary, and download of falsified software is prevented. A server creates a time-limited authentication key, computes a hash value of a file included in update software for each file to create a hash table in which hash values of a file are listed, and encrypts the hash table using the authentication key. A unit obtains the encrypted hash table and the authentication key from a server. An information terminal obtains the encrypted hash table from the unit, obtains the authentication key from the unit, determines whether or not a time limit of the authentication key is valid, obtains the encrypted hash table from the server if the time limit is determined to be valid as a result of the determination, decrypts the tables using the authentication key, compares the tables after decryption, and initiates download of the update software if both the tables are identical to each other. | 2012-07-05 |
20120173868 | Communication Across Domains - Communication across domains is described. In at least one implementation, a determination is made that an amount of data to be communicated via an Iframe exceeds a threshold amount. The data is divided into a plurality of portions that do not exceed the threshold amount. A plurality of messages is formed to communicate the divided data across domains. | 2012-07-05 |
20120173869 | SERVICE LOCATION BASED AUTHENTICATION - A computer is configured to receive a request to access an application, the request having a header. The header includes a source address and an encrypted address generated based on the source address. The computer is further configured to generate a decrypted address from the encrypted address. The computer is further configured to determine whether the source address and the decrypted address match, transmit the source address to a data store, and determine whether a customer profile corresponding to the source address is found within the data store. | 2012-07-05 |
20120173870 | Systems and Methods for Multi-Level Tagging of Encrypted Items for Additional Security and Efficient Encrypted Item Determination - The present disclosure is directed towards systems and methods for performing multi-level tagging of encrypted items for additional security and efficient encrypted item determination. A device intercepts a message from a server to a client, parses the message and identifies a cookie. The device processes and encrypts the cookie. The device adds a flag to the cookie indicating the device encrypted the cookie. The device re-inserts the modified cookie into the message and transmits the message. The device intercepts a message from a client and determines whether the cookie in the message was encrypted by the device. If the message was not encrypted by the device, the device transmits the message to its destination. If the message was encrypted by the device, the device removes the flag, decrypts the cookie, removes the tag from the cookie, re-inserts the cookie into the message and transmits the message to its final destination. | 2012-07-05 |
20120173871 | SYSTEM FOR SECURING VIRTUAL MACHINE DISKS ON A REMOTE SHARED STORAGE SUBSYSTEM - Embodiments of the present invention provide a method, data processing system and computer program product for secure distribution of virtualized storage. In an embodiment of the invention, a method for secure distribution of virtualized storage in a host in a cloud computing can include composing at least one virtual machine (VM) disk in a secure container and configured to deploy VM images into a cloud computing environment, encrypting the composed at least one VM disk, transmitting the encrypted VM disk to a hypervisor in the cloud computing environment receiving a request to activate a VM instance and generating a bootloader in the secure container, transmitting the bootloader to the hypervisor in the cloud computing environment and providing a key to the bootloader to unlock the at least one VM disk. | 2012-07-05 |
20120173872 | Secure Access to a Virtual Machine - A method for providing secure access to a virtual machine includes dispensing an image corresponding to a virtual machine from a management appliance to a distributed computing system such that the virtual machine is implemented by at least one of a plurality of interconnected physical computing devices in the distributed computing system; establishing a trusted relationship between the management appliance and the virtual machine; and providing a user with access to the virtual machine from the management appliance without further authentication credentials from the user. | 2012-07-05 |
20120173873 | SMART GRID DEVICE AUTHENTICITY VERIFICATION - Methods and articles of manufacture are provided. Some embodiments are directed to smart grid device authenticity verification. In an exemplary embodiment a method is provided that generates a firmware package image for a device. The method goes on to manufacture a microcontroller using the image. A ship file is then generated with unique data associated to the device. A board is then manufactured and a board ship file generated. The device is then authenticated on a network using the two ship files and the firmware image. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims. | 2012-07-05 |
20120173874 | Method And Apparatus For Protecting Against A Rogue Certificate - Disclosed is a method for protecting against a rogue certificate. In the method, a web client receives a first certificate from a server during an initial session. The first certificate has a first certificate chain to an authority certificate signed by a certificate authority. The web client receives a second certificate during a subsequent session. The second certificate has a second certificate chain to a signed authority certificate. The web client assigns a signature security rating to each chain certificate in the first and second certificate chains. The web client compares the signature security rating of each corresponding chain certificate in the first and second certificate chains. The web client treats the second certificate as insecure if the signature security rating of a chain certificate in the second certificate chain is lowered from that of a corresponding chain certificate in the first certificate chain. | 2012-07-05 |
20120173875 | METHOD AND APPARATUS FOR PROVIDING SECURE COMMUNICATION IN A SELF-ORGANIZING NETWORK - A communication system provides secure communication between two nodes in a self-organizing network without the need for a centralized security or control device. A first node of the two nodes is provisioned with one or more security profiles, auto-discovers a second node of the two nodes, authenticates the second node based on a security profile of the one or more security profiles, selects a security profile of the one or more security profiles to encrypt a communication session between the two nodes, and encrypts the communication session between the two nodes based on the selected security profile. The second node also is provisioned with the same one or more security profiles, authenticates the first node based on a same security profile as is used to authenticate the second node, and encrypts the communication session based on the same security profile as is used for encryption by the first node. | 2012-07-05 |
20120173876 | KEYLESS CHALLENGE AND RESPONSE SYSTEM - A confidential information exchange between a sender and a receiver may be conducted without the use of encryption keys. The information is coded with a Challenge-Response Table that is shared between the sender and the receiver. Rather than sending a challenge and then waiting for a response, the challenge and response are both sent by the sender of the information. The information sent comprises an index with a challenge and a response from the Challenge-Response Table. Upon receiving the coded information, the receiver uses the Challenge-Response Table to decode the information by using the index to locate the challenge and its valid response. Upon determining that the challenge and the response are correct, a first decoded answer is determined. Upon determining that either the challenge or the response, or both, are incorrect, a second decoded answer is determined. | 2012-07-05 |
20120173877 | METHOD AND APPARATUS FOR BUILDING A HARDWARE ROOT OF TRUST AND PROVIDING PROTECTED CONTENT PROCESSING WITHIN AN OPEN COMPUTING PLATFORM - A system architecture provides a hardware-based root of trust solution for supporting distribution and playback of premium digital content. In an embodiment, hardware root of trust for digital content and services is a solution where the basis of trust for security purposes is rooted in hardware and firmware mechanisms in a client computing system, rather than in software. From this root of trust, the client computing system constructs an entire media processing pipeline that is protected for content authorization and playback. In embodiments of the present invention, the security of the client computing system for content processing is not dependent on the operating system (OS), basic input/output system (BIOS), media player application, or other host software. | 2012-07-05 |
20120173878 | DEVICE AND METHOD FOR FORMING A SIGNATURE - A device is described for forming a signature from an input signal (input). According to the present invention, a plurality of transformation elements is provided, each having a finite-state machine, to which, on the input end, in each case the input signal (input) and/or a signal (input′), that is a function of the input signal, is able to be fed, all the finite-state machines are similar and are configured in such a way, particularly able to be initialized, that each finite-state machine always respectively has a different state than do all the other finite-state machines, and the signature is formable as a function of state data of at least one finite-state machine. | 2012-07-05 |
20120173879 | SECURE TRANSFER OF DATA USING A FILE TRANSFER APPLICATION OVER A USB TRANSPORT LAYER - A media device includes a memory for storing a file transfer application and a storage device for storing content. The device also includes at least one processor and an input-output (I/O) interface over which the file transfer application transfers content. The device also includes a protocol stack that is executable by the processor. The protocol stack includes a file transfer application layer, a transport protocol layer that does not include native support for security, and a security emulation layer located between the file transfer application layer and the transport protocol layer. The security emulation layer is executed in the transport protocol layer. | 2012-07-05 |
20120173880 | System And Method For Decrypting Content Samples Including Distinct Encryption Chains - Embodiments may be configured to receive a protected version of content that includes multiple encrypted content samples. In various embodiments, each encrypted content sample includes multiple encrypted blocks. For a given encrypted content sample, different sets of encrypted blocks in that sample may form different encryption chains. The protected version of the content may further include decryption information for decrypting the encrypted content samples. The decryption information may include at least some initialization vectors generated dependent upon non-content information that is not included in the protected version of the content. The non-content information may be from a different protected version of the content. Embodiments may be configured to use the decryption information to decrypt one or more of the encrypted content samples. | 2012-07-05 |
20120173881 | Method & Apparatus for Remote Information Capture, Storage, and Retrieval - The present disclosure relates to methods and systems that restrict access to stored sensitive information. Specifically, the methods and systems of the present disclosure separate the management of access to data from the encryption and storage of the data itself. The present disclosure allows for retrieval of the access without providing such access to the data host. Further, the present disclosure provides for data ownership privileges that can grant or revoke access. The present disclosure further provides for audio-access of stored data. | 2012-07-05 |
20120173882 | SYSTEM AND METHOD FOR IN-PLACE ENCRYPTION - Disclosed herein are systems, methods, and non-transitory computer-readable storage media for performing in-place encryption. A system configured to practice the method receives a request from a user to encrypt an unencrypted volume of a computing device and identifies, generates, and/or randomly selects a volume key. Then the system converts the unencrypted volume to an encryptable format divided into portions. The system then encrypts, based on the volume key, the encryptable volume, portion by portion, to enable the user to use the computing device while encrypting. The system can maintain an encryption progress status and display the encryption progress status. The system can monitor disk accesses to the encryptable volume, and, when the disk accesses exceed a first threshold, apply a back-off algorithm to stop encrypting until the disk accesses fall below a second threshold. Thus, the computing device can be used while the encryption occurs in the background. | 2012-07-05 |
20120173883 | SECURE DATA PARSER METHOD AND SYSTEM - A secure data parser is provided that may be integrated into any suitable system for securely storing and communicating data. The secure data parser parses data and then splits the data into multiple portions that are stored or communicated distinctly. Encryption of the original data, the portions of data, or both may be employed for additional security. The secure data parser may be used to protect data in motion by splitting original data into portions of data, that may be communicated using multiple communications paths. | 2012-07-05 |