26th week of 2011 patent applcation highlights part 16 |
Patent application number | Title | Published |
20110156052 | Semiconductor device having JFET and method for manufacturing the same - A semiconductor device having a JFET includes: a substrate made of semi-insulating semiconductor material; a gate region in a surface portion of the substrate; a channel region disposed on and contacting the gate region; a source region and a drain region disposed on both sides of the gate region so as to sandwich the channel region, respectively; a source electrode electrically coupled with the source region; a drain electrode electrically coupled with the drain region; and a gate electrode electrically coupled with the gate region. An impurity concentration of each of the source region and the drain region is higher than an impurity concentration of the channel region. | 2011-06-30 |
20110156053 | SEMICONDUCTOR DEVICE HAVING D MODE JFET AND E MODE JFET AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity. | 2011-06-30 |
20110156054 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction. | 2011-06-30 |
20110156055 | INTEGRATED DIAMOND TRANSDUCTION PIXELIZED IMAGER DEVICE AND MANUFACTURING PROCESS - Imaging device including several pixels, each pixel including at least: | 2011-06-30 |
20110156056 | WAVELENGTH-CONVERTED SEMICONDUCTOR LIGHT EMITTING DEVICE - A material such as a phosphor is optically coupled to a semiconductor structure including a light emitting region disposed between an n-type region and a p-type region, in order to efficiently extract light from the light emitting region into the phosphor. The phosphor may be phosphor grains in direct contact with a surface of the semiconductor structure, or a ceramic phosphor bonded to the semiconductor structure, or to a thin nucleation structure on which the semiconductor structure may be grown. The phosphor is preferably highly absorbent and highly efficient. When the semiconductor structure emits light into such a highly efficient, highly absorbent phosphor, the phosphor may efficiently extract light from the structure, reducing the optical losses present in prior art devices. | 2011-06-30 |
20110156057 | SUBSTRATE OF THE SEMICONDUCTOR ON INSULATOR TYPE WITH INTRINSIC AND DOPED DIAMOND LAYERS - A semiconductor substrate including at least a layer based on doped diamond with a thickness greater than or equal to approximately 10 μm, a layer based on at least one semiconductor or a stack of layers including the semiconductor-based layer, and a layer based on intrinsic diamond disposed against the layer based on doped diamond, between the layer based on doped diamond and the semiconductor-based layer. | 2011-06-30 |
20110156058 | SILICON CARBIDE MONOCRYSTAL SUBSTRATE AND MANUFACTURING METHOD THEREFOR - A method for producing a silicon carbide single crystal substrate according to the present invention includes steps of: (A) preparing a silicon carbide single crystal substrate having a mechanically polished main face; (B) performing chemical mechanical polishing on the main face of the silicon carbide single crystal substrate using a polishing slurry containing abrasive grains dispersed therein to finish the main face as a mirror surface; (C′1) oxidizing at least a part of the main face finished as a mirror surface by a gas phase to form an oxide; and (C′2) removing the oxide. | 2011-06-30 |
20110156059 | Light-Emitting Component and Method for The Production Thereof - The invention relates to a light-emitting component, in particular an organic luminescent diode, having an electrode and a counter electrode and an organic region arranged between the electrode and the counter electrode and having an organic light-emitting region. Furthermore, the invention relates to methods for the production of such a component. | 2011-06-30 |
20110156060 | Light emission module with high-efficiency light emission and high-efficiency heat dissipation and applications thereof - A light emission module is provided. The light emission module includes a substrate, a plurality of LED chips disposed on the substrate, a fluorescent colloid and a package colloid surrounding the plurality of LED chips. The substrate includes a substrate body and a plurality of chip pads disposed thereon for carrying the LED chips. A plurality of via holes is formed passing through the chip pads and the substrate body to enhance the heat dissipation of the LED chips. The fluorescent colloid and the package colloid both have light guide structures to improve the color stability and the capacity to process the light shape of the light emission module. | 2011-06-30 |
20110156061 | Light emission module with high-efficiency light emission and high-efficiency heat dissipation and applications thereof - A light emission module is provided. The light emission module includes a substrate, a plurality of LED chips disposed on the substrate, a fluorescent colloid and a package colloid surrounding the plurality of LED chips. The substrate includes a substrate body and a plurality of chip pads disposed thereon for carrying the LED chips. A plurality of via holes is formed passing through the chip pads and the substrate body to enhance the heat dissipation of the LED chips. The fluorescent colloid and the package colloid both have light guide structures to improve the color stability and the capacity to process the light shape of the light emission module. | 2011-06-30 |
20110156062 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display device and a method of manufacturing the same. The organic light-emitting display device includes a first film formed of an inorganic material, a second film that is formed of an organic material and formed on the first film, and includes a first surface and a second surface facing each other and lateral surfaces at boundaries of the first surface and the second surface, with the first surface contacting the first film, a third film that is formed of an inorganic material and covers the second surface and lateral surfaces of the second film, with a first sealing region contacting the first film being formed at a boundary between the second film and the third film, an organic light-emitting unit that is disposed on the third film to overlap with the second film, and a fourth film that covers the organic light-emitting unit, with a second sealing region contacting the third film being formed at a boundary of the fourth film. Accordingly, the organic light-emitting display device is protected from water penetration, thereby providing a long life span to the organic light-emitting display device. | 2011-06-30 |
20110156063 | ORGANIC LIGHT EMITTING DIODE (OLED) DISPLAY DEVICE - An exemplary OLED display device includes a substrate, a colored photo-resist layer and a white OLED arranged in that order. The white OLED includes a reflecting electrode, a transmitting electrode, and an organic white light emitting layer arranged between the reflecting electrode and the transmitting electrode for emitting a white light. The colored photo-resist layer at least includes first through third photo-resist regions, the first through third photo-resist regions contain red pigment particles, green pigment particles and blue pigment particles respectively for extracting red, green and blue light components from the white light. Moreover, the colored photo-resist layer has an expected haze value e.g., greater than 30 by at least utilizing the scattering of the red, green and blue pigment particles and/or mixing of scattering particles that are different from the red, green and blue pigment particles into the first through third photo-resist regions. | 2011-06-30 |
20110156064 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are a light emitting device and a method of fabricating the same. The light emitting device includes a substrate; first and second light emitting cells, each including a first semiconductor layer, an active layer, and a second semiconductor layer; and a connector located between the first and second light emitting cells and the substrate, to electrically connect the first and second light emitting cells to each other. The connector extends from the second semiconductor layer of the first light emitting cell, across the substrate, and through central regions of the second semiconductor layer and active layer of the second light emitting cells, to contact the first semiconductor layer of the second light emitting cell. | 2011-06-30 |
20110156065 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND SEMICONDUCTOR LIGHT EMITTING DEVICE - Provided is a semiconductor light emitting element wherein generation of an open failure of the light emitting device can be eliminated by ensuring a current pathway when disconnection is generated in a transparent electrode layer. A semiconductor light emitting element ( | 2011-06-30 |
20110156066 | SEMICONDUCTOR LIGHT-EMITTING DEVICE WITH A PROTECTION LAYER - The present application discloses a semiconductor light-emitting device with a protection layer. The structure includes a heat dispersion substrate, a first connecting layer on the heat dispersion substrate, a protection layer on the first connecting layer, a second connecting layer on the protection layer, and a light-emitting unit on the second connecting layer. The protection layer is highly insulative and can avoid the current leakage forming between the light-emitting unit and the heat dispersion substrate. | 2011-06-30 |
20110156067 | LIGHT EMITTING MODULE AND ILLUMINATION DEVICE WITH THE SAME - A light emitting module includes a substrate, a conductive layer, a first light emitter, a second light emitter and a protection layer. The substrate has a first surface and a second surface on opposite sides of the substrate. The conductive layer is configured in the substrate. The first light emitter is disposed on the first surface and connected with the conductive layer. The second light emitter is disposed on the second surface and connected with the conductive layer. The protection layer covers the first light emitter and the second light emitter. | 2011-06-30 |
20110156068 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND ILLUMINATION SYSTEM - A light emitting device is provided. The light emitting device includes a first conductive type semiconductor layer, an active layer including a plurality of well layers and a plurality of barrier layers on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the active layer. An upper surface of at least first barrier layer among the barrier layers includes an uneven surface. The first barrier layer is disposed more closely to the second conductive type semiconductor layer than to the first conductive type semiconductor layer. | 2011-06-30 |
20110156069 | Optoelectronic Semiconductor Chip and Method for the Production Thereof - A method for producing an optoelectronic semiconductor chip based on a nitride semiconductor system is specified. The method comprises the steps of: forming a semiconductor section with at least one p-doped region; and forming a covering layer disposed downstream of the semiconductor section in a growth direction of the semiconductor chip, said covering layer having at least one n-doped semiconductor layer. An activation step suitable for electrically activating the p-doped region is effected before or during the formation of the covering layer. An optoelectronic semiconductor chip which can be produced by the method is additionally specified. | 2011-06-30 |
20110156070 | LIGHT EMITTING DIODE - The present invention provides a light emitting diode including a lower semiconductor layer formed on a substrate; an upper semiconductor layer disposed above the lower semiconductor layer, exposing an edge region of the lower semiconductor layer; a first electrode formed on the upper semiconductor layer; an insulation layer interposed between the first electrode and the upper semiconductor layer, to supply electric current to the lower semiconductor layer; a second electrode formed on another region of the upper semiconductor layer, to supply electric current to the upper semiconductor layer. The first electrode includes an electrode pad disposed on the upper semiconductor layer and an extension extending from the electrode pad to the exposed lower semiconductor layer. The insulation layer may have a distributed Bragg reflector structure. | 2011-06-30 |
20110156071 | MULTI-STACK PACKAGE LED - A multi-stack package light emitting diode (LED) includes an LED chip, a first fluorescent powder layer, a first optical bandpass filter layer and a second fluorescent powder layer. The LED chip generates an LED light. The first fluorescent powder layer and the second fluorescent powder layer respectively have a first fluorescent powder and a second fluorescent powder. The first fluorescent powder and the second fluorescent powder are excited by the LED light to respectively generate a first excitation light and a second excitation light. The first optical bandpass filter layer allows the LED light and the first excitation light to pass and reflects the second excitation light. A wavelength of the LED light is shorter than a wavelength of the second excitation light. The wavelength of the second excitation light is shorter than a wavelength of the first excitation light. Therefore, the multi-stack package LED improves a light emission efficiency. | 2011-06-30 |
20110156072 | METHODS FOR PACKAGING LIGHT EMITTING DEVICES AND RELATED MICROELECTRONIC DEVICES - A method for forming a light emitting device includes providing a light emitting diode (LED) configured to emit light of a first color and providing a plurality of semi-spherical lenses made of a silicone material that contains no phosphor material. Each of the lenses has a layer of phosphor material attached thereto. The method also includes testing the plurality of lenses to select a subset of lenses that converts light of the first color to light of a second color. The method further includes forming the light emitting device using the LED, one of the selected subset of lenses, and a heat conductive substrate. In an embodiment, after the testing of the plurality of lenses, one of the selected subset of lenses is disposed overlying the LED. In another embodiment, the testing of the plurality of lenses is conducted with a light source other than the LED. | 2011-06-30 |
20110156073 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE - Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a light emitting structure, a buffer layer on the light emitting structure, and a filter layer on the buffer layer. | 2011-06-30 |
20110156074 | CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME - The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided. | 2011-06-30 |
20110156075 | SEMICONDUCTOR ELEMENT - A semiconductor element according to an embodiment of present application includes a first voltage drop portion providing a first voltage drop, a second voltage drop portion providing a second voltage drop, and a connecting material between the first voltage drop portion and the second voltage drop portion and having a physical dimension smaller than that of at least one of the first voltage drop portion and the second voltage drop portion. The semiconductor element can operate under a total bias voltage. The total bias voltage is greater than the second voltage drop, while the second voltage drop is greater than or equal to the first voltage drop. | 2011-06-30 |
20110156076 | OPTOELECTRONIC COMPONENT AND A METHOD FOR PRODUCING IT - An optoelectronic component, includes a carrier, a metallic mirror layer arranged on the carrier, a first passivation layer arranged on a region of the metallic mirror layer, a semiconductor layer that generates an active region during electrical operation arranged on the first passivation layer, a second passivation layer including two regions, wherein the first region is arranged on a top face of the semiconductor layer, and the second region which is free of the semiconductor layer is arranged on the metallic mirror layer, and wherein the first and second regions are separated from one another by a region which surrounds the first passivation layer and which is free of the second passivation layer. | 2011-06-30 |
20110156077 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - A light emitting device is provided. The light emitting device comprises: a conductive support substrate; a bonding layer on the conductive support substrate; a reflective layer on the bonding layer; and a light emitting structure layer on the reflective layer. The bonding layer comprises a solder bonding layer on the conductive support substrate and at least one of a diffusion barrier layer and an adhesion layer on the solder bonding layer, the solder bonding layer, the diffusion barrier layer, and the adhesion layer being formed of a metal or an alloy of which the Young's Modulus is 9 GPa to 200 GPa. | 2011-06-30 |
20110156078 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor light-emitting device includes a light-impervious substrate, a bonding structure, a semiconductor light-emitting stack, and a fluorescent material structure overlaying the semiconductor light-emitting stack. The semiconductor light-emitting stack is separated from a growth substrate and bonded to the light-impervious substrate via the bonding structure. A method for producing the semiconductor light-emitting device includes separating a semiconductor light-emitting stack from a growth substrate, bonding the semiconductor light-emitting stack to a light-impervious substrate, and forming a fluorescent material structure over the semiconductor light-emitting stack. | 2011-06-30 |
20110156079 | ORGANIC EL DEVICE AND METHOD FOR MANUFACTURING SAME - A manufacturing method of an organic EL device, comprising: providing a substrate on which a pixel electrode is arranged, forming a liquid repellent organic film on the substrate and the pixel electrode, radiating a light selectively to an area of the pixel electrode to be coated with an organic functional layer, to oxidize a surface of the pixel electrode, and to change the liquid repellent organic film on the area to a lyophilic organic film or to remove the liquid repellent organic film on the area, applying an ink containing an organic functional material on the area defined by the liquid repellent organic film to form the organic functional layer on the pixel electrode. | 2011-06-30 |
20110156080 | LIGHT EMITTING DEVICE - A light emitting device is provided with: a pair of an anode and a cathode that are opposed to each other; and a phosphor layer, composed of a plurality of phosphor particles, that is sandwiched between the paired anode and cathode, from direction that is perpendicular to main surfaces of the anode and the cathode, and in this structure, each phosphor particle is a nitride semiconductor phosphor particle having a wurtzite crystal structure that contains an n-type nitride semiconductor portion and a p-type nitride semiconductor portion, with the n-type nitride semiconductor portion being made in contact with the cathode and the p-type nitride semiconductor portion being made in contact with the anode, and the n-type nitride semiconductor portion and the p-type nitride semiconductor portion have the common c-axe in the respective crystal structures thereof made in parallel with each other, with the n-type nitride semiconductor portion and the p-type nitride semiconductor portion being made in contact with each other on a plane in parallel with the c-axe. | 2011-06-30 |
20110156081 | POLYMERIC WAVELENGTH CONVERTING ELEMENTS - A wavelength converting element ( | 2011-06-30 |
20110156082 | LED MODULE - An exemplary LED module includes a ceramic substrate, a heat spreader, a heat sink, an LED die, and a packaging layer. The substrate defines a hole extending therethrough from a top side to a bottom side thereof. The heat spreader is disposed in the hole with a top side thereof substantially coplanar with the top side of the substrate. An outer circumferential surface of the heat spreader contacts an inner circumferential surface of the substrate around the hole. The heat sink is attached to the top sides of the substrate and the heat spreader. The LED die is attached to a bottom side of the heat spreader, and the packaging layer encapsulates the LED die. | 2011-06-30 |
20110156083 | Light emission module with high-efficiency light emission and high-efficiency heat dissipation and applications thereof - A light emission module is provided. The light emission module includes a substrate, a plurality of LED chips disposed on the substrate, a fluorescent colloid and a package colloid surrounding the plurality of LED chips. The substrate includes a substrate body and a plurality of chip pads disposed thereon for carrying the LED chips. A plurality of via holes is formed passing through the chip pads and the substrate body to enhance the heat dissipation of the LED chips. The fluorescent colloid and the package colloid both have light guide structures to improve the color stability and the capacity to process the light shape of the light emission module. | 2011-06-30 |
20110156084 | ORGANIC LIGHT EMITTING DIODE LIGHTING APPARATUS - An organic light emitting diode lighting apparatus is disclosed. In one embodiment, the apparatus includes: i) a substrate main body including a light emitting region and a sealing region surrounding the light emitting region, ii) an organic light emitting diode formed over the substrate main body and iii) a sealant formed over the sealing region of the substrate main body, wherein the sealant includes a conductive member electrically connected to the organic light emitting diode. The apparatus may further include a printed circuit board bonded to the substrate main body by the sealant to seal and cover the organic light emitting diode, wherein the printed circuit board includes external input terminals which directly contact the conductive member. | 2011-06-30 |
20110156085 | SEMICONDUCTOR PACKAGE - A semiconductor package includes at least four lead frames each having an extending portion and a connecting portion, a heat dissipation plate having a top surface and a bottom surface, at least one semiconductor chip positioned on the top surface of the heat dissipation plate. At least one conductive wire electrically connects the chip to the lead frames. An encapsulation covers the lead frames, the heat dissipation plate, the semiconductor chip, and the conductive wires, while the bottom surface of the heat dissipation plate and the extending portions of the lead frames are exposed. | 2011-06-30 |
20110156086 | LIGHT EMITTING DIODE HAVING ELECTRODE EXTENSIONS - An exemplary embodiment of the present invention discloses a light emitting diode including a lower contact layer having a first edge, a second edge opposite to the first edge, a third edge connecting the first edge to the second edge, and a fourth edge opposite to the third edge, a mesa structure arranged on the lower contact layer, the mesa structure including an active layer and an upper contact layer, a first electrode pad arranged on the lower contact layer, a second electrode pad arranged on the mesa structure, a first lower extension and a second lower extension extending from the first electrode pad towards the second edge, distal ends of the first lower extension and the second lower extension being farther away from each other than front ends thereof contacting the first electrode pad, and a first upper extension, a second upper extension, and a third upper extension extending from the second electrode pad. In addition, the first upper extension and the second upper extension extend from the second electrode pad to enclose the first lower extension and the second lower extension, and the third upper extension extends to a region between the first lower extension and the second lower extension. | 2011-06-30 |
20110156087 | FACE-UP OPTICAL SEMICONDUCTOR DEVICE AND METHOD - A face-up optical semiconductor device can be prepared by forming an n-type GaN layer, an active layer, and a p-type GaN layer on a C-plane sapphire substrate. Parts of the p-type GaN layer and the active layer can be removed, and a transparent electrode can be formed over all or most of the remaining p-type GaN layer. A p-side electrode including a pad portion and auxiliary electrode portions can be formed on the transparent electrode layer. An n-side electrode can be formed on the exposed n-type GaN layer. On regions of the transparent electrode layer where weak light emission regions may be formed, outside independent electrodes can be provided. They can be disposed on concentric circles with the n-side electrode as a center or tangent lines thereof so as to be along the circles or the tangent lines. The outside independent electrodes can diffuse current from the p-side electrode to the n-side electrode flowing through the transparent electrode layer into the short side end portions of the transparent electrode layer, thereby decreasing the weak light emission regions. | 2011-06-30 |
20110156088 | LIGHT EMITTING DEVICE - A light emitting device includes at least one particle over the light emitter. Light at a first wavelength travels from the emitter along a first path adjacent to the particle and at a second wavelength along a second path that passes through the particle. The particle converts the light on the second path from the first wavelength into a second wavelength. The light at the first wavelength mixes with the light at the second wavelength to form light of a third wavelength, which may be white light or another color. | 2011-06-30 |
20110156089 | Light Emitting Device, Light Emitting Device Package And Lighting System - Embodiments relate to a light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises: a substrate; a light emitting structure over the substrate, the light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer, wherein the first conductive type semiconductor layer is partially exposed; a first region having a first concentration and provided at a region of the second conductive type semiconductor layer; a second region having a second concentration and provided at another region of the second conductive type semiconductor layer; and a second electrode over the second conductive type semiconductor layer. | 2011-06-30 |
20110156090 | SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE/POST HEAT SPREADER AND ASYMMETRIC POSTS - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and first and second adhesives. The heat spreader includes a first post, a second post and a base. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The first post extends from the base in a first vertical direction into a first opening in the first adhesive and is located within a periphery of the second post, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts. The conductive trace provides signal routing between the pad and the terminal. | 2011-06-30 |
20110156091 | CONTACTING A DEVICE WITH A CONDUCTOR - The invention relates to a method for contacting a device with a conductor | 2011-06-30 |
20110156092 | SMT ENCAPSULATION BODY OF A LIGHT-EMITTING DIODE WITH A WIDE-ANGLE ILLUMINATION LIGHT SHAPE - An SMT encapsulation body of a light-emitting diode with a wide-angle illumination light shape, comprising: a) a substrate; b) an LED die mounted on the substrate by use of SMT; and c) an encapsulation body positioned around the LED die in the shape of a double dome at the top thereof with the center at a lower position such that the illumination light shape of the light-emitting diode becomes to be a wide-angle and elongated body. The encapsulation body may be formed either in the shape of a batwing or in the shape of a double batwing symmetrically positioned in a cross way. In this way, the light-emitting diode achieves a wide-angle illumination light shape fulfilling the requirements of a certain purpose without the use of the double optical effect of the lens. Meanwhile, the drawbacks of the conventional structure are resolved. Moreover, an increased efficiency in using the light source is ensured. | 2011-06-30 |
20110156093 | HIGH-VOLTAGE POWER TRANSISTOR USING SOI TECHNOLOGY - The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 μm. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT. | 2011-06-30 |
20110156094 | ELECTRICAL MODULE - A method for fabricating an electrical module comprising a first substrate plate ( | 2011-06-30 |
20110156095 | Semiconductor Component with an Emitter Control Electrode - A semiconductor component includes a first emitter zone of a first conductivity type, a second emitter zone of a second conductivity type, a first base zone arranged between the first and second emitter zones and a first control structure. The first control structure includes a control electrode arranged adjacent the first emitter zone, the control electrode being insulated from the first emitter zone by a first dielectric layer and extending in a current flow direction of the semiconductor component. The first control structure includes a first control connection and at least one first connection zone arranged between the first control connection and the control electrode and comprising a semiconductor material. | 2011-06-30 |
20110156096 | Lateral Insulated Gate Bipolar Transistor (LIGBT) - This invention generally relates to LIGBTs, ICs comprising an LIGBT and methods of forming an LIGBT, and more particularly to an LIGBT comprising a substrate region of first conductivity type and peak dopant concentration less than about 1×10 | 2011-06-30 |
20110156097 | REDUCED DARK CURRENT PHOTODETECTOR - A photo-detector comprising: a photo absorbing layer comprising an n-doped semiconductor exhibiting a valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers from the photo absorbing layer to the contact area and block the flow of thermalized majority carriers from the photo absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, and conductance band energy levels of the barrier and photo absorbing layers are equalized. | 2011-06-30 |
20110156098 | BUFFER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION - Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers. | 2011-06-30 |
20110156099 | ENHANCED CONFINEMENT OF SENSITIVE MATERIALS OF A HIGH-K METAL GATE ELECTRODE STRUCTURE - When forming sophisticated high-k metal gate electrode structures, the removal of a dielectric cap material may be accomplished with superior process uniformity by using a silicon dioxide material. In other illustrative embodiments, an enhanced spacer regime may be applied, thereby also providing superior implantation conditions for forming drain and source extension regions and drain and source regions. | 2011-06-30 |
20110156100 | High Electron Mobility Transistor and Method for Fabricating the Same - A high electron mobility transistor includes a substrate, a buffer layer, a channel layer, a spacer layer, a schottky layer and a cap layer. The buffer layer is formed on the substrate. The channel layer is formed on the buffer layer, in which the channel layer comprises a superlattice structure formed with a plurality of indium gallium arsenide thin films alternately stacked with a plurality of indium arsenide thin films. The spacer layer is formed on the channel layer. The schottky layer is formed on the spacer layer. The cap layer is formed on the schottky layer. | 2011-06-30 |
20110156101 | SEMICONDUCTOR DEVICE AND LAYOUT DESIGN APPARATUS OF SEMICONDUCTOR DEVICE - A semiconductor device may include a plurality of logic circuits connected to each other through input and output terminals thereof. The plurality of logic circuits comprising a first sub-plurality of logic circuits coupled to a first one of different power systems. The first sub-plurality of logic circuits is laid out and adjacent to each other in a first direction. The first sub-plurality of logic circuits includes a first logic circuit and a second logic circuit. The second logic circuit is adjacent to the first logic circuit. The first logic circuit includes a first element comprising a first diffusion layer. The second logic circuit includes a second element comprising the first diffusion layer. | 2011-06-30 |
20110156102 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line. | 2011-06-30 |
20110156103 | Method and System to Reduce Area of Standard Cells - A signal routing grid. A first metal layer has wires running in a first direction. A second metal layer, spaced from and substantially parallel to the first metal layer, has wires running in a second direction different to the first direction, such that the wires of the first and second metal layers appear from above or below to form virtual intersections. Vias or contacts are coupled between the first and second metal layers and configured to route signals between the first and second metal layers. Pins are coupled to the first metal layer and configured to provide input signals or receive output signals from a standard cell, the pins being positioned along the wires in the first metal layer so as to be spaced from the virtual intersections. | 2011-06-30 |
20110156104 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A solid-state imaging device including a semiconductor substrate, a photoelectric conversion portion interposed between a lower electrode and an upper electrode, a contact plug formed so as to connect the lower electrode and the semiconductor substrate in order to read signal charges generated in the photoelectric conversion portion to the semiconductor substrate side, a vertical type transmitting path configured by sequentially laminating a connection portion for electrically connecting the contact plug to the semiconductor substrate, a charge accumulation layer for accumulating the signal charges read to the connection portion, and a potential barrier layer configuring a potential barrier between the connection portion and the charge accumulation layer in a vertical direction of the semiconductor substrate, and a charge reading portion configured to read the signal charges accumulated in the charge accumulation layer to the circuit forming surface side of the semiconductor substrate. | 2011-06-30 |
20110156105 | PHOTOSENSORS INCLUDING PHOTODIODE CONTROL ELECTRODES AND METHODS OF OPERATING SAME - A sensor includes a substrate, a floating diffusion node in the substrate, a photodiode in the substrate laterally spaced apart from the floating diffusion region and a transfer transistor coupling the photodiode and the floating diffusion region. The sensor further includes a photodiode control electrode disposed on the photodiode and configured to control a carrier distribution of the photodiode responsive to a control signal applied thereto. The floating diffusion region may have a first conductivity type, the photodiode may include a first semiconductor region of a second conductivity type disposed on a second semiconductor region of the first conductivity type, and the photodiode control electrode may be disposed on the first semiconductor region. The photodiode may be configured to receive incident light from a side of the substrate opposite the photodiode control electrode. The transfer transistor may include a gate electrode on a channel region in the substrate and the photodiode control electrode and the transfer transistor gate electrode may be separately controllable. In further embodiments, the photodiode control electrode comprises an extension of the transfer transistor gate electrode. | 2011-06-30 |
20110156106 | HERMETIC MEMS DEVICE AND METHOD FOR FABRICATING HERMETIC MEMS DEVICE AND PACKAGE STRUCTURE OF MEMS DEVICE - A hermetic microelectromechanical system (MEMS) package includes a CMOS MEMS chip and a second substrate. The CMOS MEMS Chip has a first substrate, a structural dielectric layer, a CMOS circuit and a MEMS structure. The structural dielectric layer is disposed on a first side of the first structural substrate. The structural dielectric layer has an interconnect structure for electrical interconnection and also has a protection structure layer. The first structural substrate has at least a hole. The hole is under the protection structure layer to form at least a chamber. The chamber is exposed to the environment in the second side of the first structural substrate. The chamber also comprises a MEMS structure. The second substrate is adhered to a second side of the first substrate over the chamber to form a hermetic space and the MEMS structure is within the space. | 2011-06-30 |
20110156107 | Self-aligned contacts - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 2011-06-30 |
20110156108 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An insulating cover film is formed over at least a portion of a gate electrode in the direction of the channel width. A diffusion layer is formed to a portion of a substrate situating at a device forming region, thereby forming a source and a drain of a transistor. An insulating layer is formed over the device forming region, over the gate electrode, and over the insulating cover film. A contact is formed to the insulating layer and connected to the diffusion layer. A silicide layer is formed over the gate electrode. A side wall is formed higher than the gate electrode in a region in which the insulating cover film is formed. Then, the contact faces a region of the gate electrode in which the insulating cover film is formed. | 2011-06-30 |
20110156109 | METHOD AND SYSTEM FOR MANIPULATING ORGANIC NANOSTRUCTURES - A method of manipulating an organic nanostructure is disclosed. The method comprises: contacting a liquid sample having the organic nanostructure therein with an arrangement of electrodes, and applying voltage to the arrangement of electrodes to manipulate and immobilize the organic nanostructure over the electrodes by electrokinetics. | 2011-06-30 |
20110156110 | Field Effect Transistors Having Gate Electrode Silicide Layers with Reduced Surface Damage - Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode. | 2011-06-30 |
20110156111 | Solid-state image pickup device, electronic apparatus using such solid-state image pickup device and method of manufacturing solid-state image pickup device - A back-illuminated type solid-state image pickup device ( | 2011-06-30 |
20110156112 | IMAGE SENSOR WITH DOPED TRANSFER GATE - An image sensor includes an array of pixels, with at least one pixel including a photodetector formed in a substrate layer and a transfer gate disposed adjacent to the photodetector. The substrate layer further includes multiple charge-to-voltage conversion regions. A single photodetector can transfer collected charge to a single charge-to-voltage conversion region, or alternatively multiple photodetectors can transfer collected charge to a common charge-to-voltage conversion region shared by the photodetectors. An implant region formed when dopants are implanted into the substrate layer to form source/drain implant regions is disposed in only a portion of each transfer gate while each charge-to-voltage conversion region is substantially devoid of the implant region. | 2011-06-30 |
20110156113 | BACK SIDE ILLUMINATION IMAGE SENSOR REDUCED IN SIZE AND METHOD FOR MANUFACTURING THE SAME - A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size. | 2011-06-30 |
20110156114 | Image sensor using light-sensitive transparent oxide semiconductor material - An image sensor according to example embodiments may include a plurality of light-sensitive transparent oxide semiconductor layers as light-sensing layers. The light-sensing layers may be stacked in one unit pixel region. | 2011-06-30 |
20110156115 | APPARATUS FOR VARIABLE RESISTIVE MEMORY PUNCHTHROUGH ACCESS METHOD - Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode. | 2011-06-30 |
20110156116 | RELAXED-PITCH METHOD OF ALIGNING ACTIVE AREA TO DIGIT LINE - According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at least two drains defining a first axis. The memory device further comprises at least two substantially parallel word lines, at least a portion of a first word line located between a first drain and the source, and at least a portion of a second word line located between a second drain and the source, which word lines define a second axis. The memory device further comprises a digit line coupled to the source, wherein the digit line forms a substantially zig-zag pattern. | 2011-06-30 |
20110156117 | SEMICONDUCTOR DEVICE - An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other. | 2011-06-30 |
20110156118 | SEMICONDUCTOR DEVICE WITH VERTICAL CELLS AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor substrate includes defining an active region by forming a device isolation layer over the substrate, forming a first trench dividing the active region into a first active region and a second active region, forming a buried bit line filling a portion of the first trench, forming a gap-filling layer gap-filling an upper portion of the first trench over the buried bit line, forming second trenches by etching the gap-filling layer and the device isolation layer in a direction crossing the buried bit line, and forming a first buried word line and a second buried word line filling the second trenches, wherein the first buried word line and the second buried word line are shaped around sidewalls of the first active region and the second active region, respectively. | 2011-06-30 |
20110156119 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME - Semiconductor memory devices and methods of forming the same are provided, the semiconductor memory devices include a first and a second buried gate respectively disposed on both inner sidewalls of a groove formed in an active portion and a device isolation pattern. The first and second buried gates are controlled independently from each other. | 2011-06-30 |
20110156120 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - There are provided: a silicon pillar that is formed almost perpendicularly to a main surface of a substrate; first and second impurity diffused layers that are arranged in a lower part and an upper part of the silicon pillar, respectively; a gate electrode that is arranged horizontally through the silicon pillar; and a gate insulating film that is arranged between the gate electrode and the silicon pillar. The silicon pillar consequently has a small volume, which makes it possible to reduce the leak current of the transistor or thyristor formed in the silicon pillar. | 2011-06-30 |
20110156121 | MEMORY CELL WITH IMPROVED RETENTION - A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals. | 2011-06-30 |
20110156122 | High Density NOR Flash Array Architecture - In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and consequently isolate and self-align the contact in the horizontal and vertical directions. | 2011-06-30 |
20110156123 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH HAFNIUM OXIDE LAYER - A method for manufacturing a twin bit cell structure of with a hafnium oxide material includes providing a semiconductor substrate having a surface region and forming a gate dielectric layer overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer and subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure. The method forms an undercut region underneath the polysilicon gate structure and subjects the polysilicon gate structure to an oxidization environment. Thereafter, the method forms a hafnium oxide material overlying the polysilicon gate structure including the undercut region and exposed portions of the gate dielectric layer. The hafnium oxide material is then selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed hafnium oxide material. | 2011-06-30 |
20110156124 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention enhances program performance by increasing a coupling ratio between an N+ type source layer and a floating gate and reduces a memory cell area. Trenches are formed on the both sides of an N+ type source layer. The sidewalls of the trench includes first and second trench sidewalls that are parallel to end surfaces of two element isolation layers, a third trench sidewall that is perpendicular to the STIs, and a fourth trench sidewall that is not parallel to the third trench sidewall. The N+ type source layer is formed so as to extend from the bottom surface of the trench to the fourth trench sidewall, largely overlapping a floating gate, by performing ion-implantation of arsenic ion or the like in a parallel direction to the third trench sidewall and in a perpendicular direction or at an angle to a P type well layer from above the trench having this structure. | 2011-06-30 |
20110156125 | NONVOLATILE SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE AND ASSOCIATED SYSTEMS - A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes. | 2011-06-30 |
20110156126 | SEMICONDUCTOR DEVICE HAVING AN OXIDE FILM FORMED ON A SEMICONDUCTOR SUBSTRATE SIDEWALL OF AN ELEMENT REGION AND ON A SIDEWALL OF A GATE ELECTRODE - A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film. | 2011-06-30 |
20110156127 | FLASH MEMORY DEVICE WITH WORD LINES OF UNIFORM WIDTH AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated. | 2011-06-30 |
20110156128 | DIELECTRIC FILM MANUFACTURING METHOD - The present invention provides a manufacturing method of a dielectric film which reduces a leak current value while suppressing the reduction of a relative permittivity, suppresses the reduction of a deposition rate caused by the reduction of a sputtering rate, and also provides excellent planar uniformity. A dielectric film manufacturing method according to an embodiment of the present invention is forms a dielectric film of a metal oxide mainly containing Al, Si, and O on a substrate, and comprises steps of forming the metal oxide having an amorphous structure in which a molar fraction between an Al element and a Si element, Si/(Si+Al), is 02011-06-30 | |
20110156129 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH HAFNIUM OXIDE AND NANO-CRYSTALLINE SILICON LAYER - A method and system for forming a non-volatile memory structure. The method provides a semiconductor substrate and forms a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of a second silicon oxide layer overlying a surface region of the substrate. A hafnium oxide material is formed overlying the first and second silicon oxide layers and filling the undercut region. The hafnium oxide material has a nanocrystalline silicon material sandwiched between a first hafnium oxide layer and a second hafnium oxide layer. The hafnium oxide material is selectively etched while a portion of it is maintained in an insert region in a portion of the undercut region. | 2011-06-30 |
20110156130 | METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE - A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures. | 2011-06-30 |
20110156131 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere. | 2011-06-30 |
20110156132 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes memory strings which have a plurality of transistors including gate electrode films formed over sides of columnar semiconductor films on gate dielectric films in a height direction of the semiconductor films, and which are arranged in a matrix shape substantially perpendicularly above a substrate. The gate electrode films of the transistors at same height of the memory strings arranged in a first direction are connected to one another. A distance between the semiconductor films at least in a forming position of the transistor at an uppermost layer of the memory strings adjacent to each other in the first direction is smaller than double of thickness of the gate dielectric films. | 2011-06-30 |
20110156133 | SEMICONDUCTOR NANOSTRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME - A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm. | 2011-06-30 |
20110156134 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATED THEREBY - The present invention is for weakening an electric field between a gate and a drain and preventing an electronic short between them. An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising forming a highly doped region in a semiconductor substrate through a first ion implantation process, forming a lightly doped region over the highly doped region through a second ion implantation process, forming a vertical transistor including the lightly doped region and a channel region having a pillar shape over the lightly doped region. | 2011-06-30 |
20110156135 | BURIED GATE IN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A buried gate in a semiconductor device and a method for fabricating the same are presented. The method includes: forming a gate trench in an active region of a semiconductor substrate; filling the gate trench with a barrier metal film and a metal film; recessing the metal film and the barrier metal film to form buried gate electrodes that partially fill the gate trench; recessing the barrier metal film of the buried gate electrode below the surface of the metal film; and filling an exposed part of the buried gate electrode and the gate trench with a capping film. | 2011-06-30 |
20110156136 | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOF - A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film. | 2011-06-30 |
20110156137 | TRENCH GATE SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A trench gate semiconductor device is disclosed which has a trench gate structure including an insulator in the upper portion of a first trench, the insulator being on a gate electrode; a source region having a lower end surface positioned lower than the upper surface of the gate electrode; a second trench in the surface portion of a semiconductor substrate between the first trenches, the second trench having a slanted inner surface providing the second trench with the widest trench width at its opening and a bottom plane positioned lower than the lower end surface of the source region, the slanted inner surface being in contact with the source region; and a p-type body-contact region in contact with the slanted inner surface of the second trench. The trench gate semiconductor device and its manufacturing method facilitate increasing the channel density and lowering the body resistance of the parasitic BJT. | 2011-06-30 |
20110156138 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance. | 2011-06-30 |
20110156139 | Super-Junction trench mosfet with resurf step oxide and the method to make the same - A super-junction trench MOSFET with Resurf Stepped Oxide is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . . Furthermore, the fabrication method can be implemented more reliably with lower cost. | 2011-06-30 |
20110156140 | METHOD FOR MANUFACTURING A POWER DEVICE BEING INTEGRATED ON A SEMICONDUCTOR SUBSTRATE, IN PARTICULAR HAVING A FIELD PLATE VERTICAL STRUCTURE AND CORRESPONDING DEVICE - An embodiment of a method for manufacturing a power device integrated on a semiconductor substrate comprising the steps of: growth on said substrate of an epitaxial layer; photo-lithography and etching of said epitaxial layer for the formation of at least one deep trench; deposition of a dielectric layer with partial filling of the at least one trench; complete filling of the at least one trench with a layer of sacrificial material; selective etching of the dielectric layer with consequent retrocession below the layer of sacrificial material; selective etching of the layer of sacrificial material with consequent formation of an empty region within the at least one trench; growth of a layer of gate oxide; formation of at least one gate region, of at least one buried source region, of at least one body region and of at least one source region; deposition of a dielectric layer; simultaneous formation of at least one gate contact, at least one body/source contact and at least one buried source contact; formation of a source contact region and of a gate contact region through deposition, masking and etching of a metallisation layer. An embodiment of the method also comprises the step of formation of the at least one gate region and of the at least one buried source region, electrically insulated, through a single deposition of a conductive filling material on the epitaxial layer, on the vertical walls of the trench and within the empty region; and through etching of the conductive filling material forming a first spacer and a second spacer, suitable for serving as a gate electrode and forming a buried source electrode within the empty region. | 2011-06-30 |
20110156141 | TRANSISTOR AND METHOD THEREOF - An electronic device can include a first well region of a first conductivity-type and a second well region of a second conductivity-type and abutting the first well region. The first conductivity-type and the second conductivity type can be opposite conductivity types. In an embodiment, an insulator region can extend into the first well region, wherein the insulator region and the first well region abut and define an interface, and, from a top view, the insulator region can include a first feature extending toward the first interface, and the insulator region can define a first space bounded by the first feature, wherein a dimension from a portion of the first feature closest to the first interface is at least zero. A gate structure can overlie an interface between the first and second well regions. | 2011-06-30 |
20110156142 | HIGH VOLTAGE DEVICE WITH PARTIAL SILICON GERMANIUM EPI SOURCE/DRAIN - A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity. | 2011-06-30 |
20110156143 | Parasitic Vertical PNP Bipolar Transistor And Its Fabrication Method In Bicmos Process - This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process. And this PNP bipolar transistor can be used as the IO (Input/Output) device in high speed, high current and power gain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuits. It also provides a device option with low cost. | 2011-06-30 |
20110156144 | Compensated Isolated P-WELL DENMOS Devices - An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. | 2011-06-30 |
20110156145 | FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR - A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region. | 2011-06-30 |
20110156146 | eFUSE ENABLEMENT WITH THIN POLYSILICON OR AMORPHOUS-SILICON GATE-STACK FOR HKMG CMOS - An eFUSE is formed with a gate stack including a layer of embedded silicon germanium (eSiGe) on the polysilicon. An embodiment includes forming a shallow trench isolation (STI) region in a substrate, forming a first gate stack on the substrate for a PMOS device, forming a second gate stack on an STI region for an eFUSE, forming first embedded silicon germanium (eSiGe) on the substrate on first and second sides of the first gate stack, and forming second eSiGe on the second gate stack. The addition of eSiGe to the eFUSE gate stack increases the distance between the eFUSE debris zone and an underlying metal gate, thereby preventing potential shorting. | 2011-06-30 |
20110156147 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device includes first and second wells of a first conductivity type, the first and second wells having different impurity doping concentrations, respectively, a gate formed on the first well, a source region of a second conductivity type formed at one side of the gate in the first well, a drift region of the second conductivity type formed at the other side of gate and over both of the first well and the second well, and a drain region of the second conductivity type formed in the drift region of the second well. | 2011-06-30 |
20110156148 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME USING SEMICONDUCTOR FIN DENSITY DESIGN RULES - A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion. | 2011-06-30 |
20110156149 | Dummy Pattern Design for Thermal Annealing - The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region. | 2011-06-30 |
20110156150 | SEMICONDUCTOR DEVICE AND DESIGN METHOD THEREOF - A semiconductor device includes a plurality of first cells having a first cell height, and a plurality of second cells having a second cell height. Each of the first cells has a first MIS transistor of a first conductivity type, and a substrate contact region of a second conductivity type. Each of the second cells has a second MIS transistor of the first conductivity type, a power supply region of the first conductivity type, and a first extended region of the first conductivity type that is silicidated at a surface thereof. The first cell height is greater than the second cell height. | 2011-06-30 |
20110156151 | Electrode Pick Up Structure In Shallow Trench Isolation Process - This invention disclosed a kind of electrode pick up structure in shallow trench isolation process. The active region is isolated by shallow trench. A pseudo-buried layer under the bottom of shallow trench is formed. The pseudo-buried layer extends into active region and connects to doping region one which needs to be picked up by an electrode. The pick up is realized by deep trench contacts which etch through STI and get in touch with pseudo buried layer. This invention can reduce the device size, pick up electrode resistance, collector parasitic capacitance, and increase device cut off frequency. | 2011-06-30 |