26th week of 2012 patent applcation highlights part 52 |
Patent application number | Title | Published |
20120164788 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING PLURAL SEMICONDUCTOR CHIPS STACKED TOGETHER - Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode. | 2012-06-28 |
20120164789 | Three-Dimensional Semiconductor Device - A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device. | 2012-06-28 |
20120164790 | DOUBLE-FACED ELECTRODE PACKAGE, AND ITS MANUFACTURING METHOD - A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like. | 2012-06-28 |
20120164791 | Substrate for semiconductor package and method for manufacturing the same - Disclosed herein are a substrate for a semiconductor package and a method for manufacturing the same. The substrate for the semiconductor package includes: a semiconductor chip forming region; and a hydrophobic film for controlling the flow of an adhesive for bonding a semiconductor chip in a portion of a solder resist layer. According to the present invention, a molecular film type of chemically treated hydrophobic film is formed to effectively control the flow of epoxy resin as an adhesive for bonding a semiconductor chip at a location where the epoxy resin meets the hydrophobic film. Also, a part to be controlled is bonded to a substrate through chemical bonding, thereby maintaining a very stable form. | 2012-06-28 |
20120164792 | MODULAR LOW STRESS PACKAGE TECHNOLOGY - A method of manufacturing a modular semiconductor subassembly: providing at least one semiconductor subassembly having a modular sidewall element of modular dimensions and a semiconductor substrate base element coupled to the modular sidewall element that has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element. If a modular package protective cover is to be used: providing the modular package protective cover configured to accommodate the semiconductor subassembly in accordance with a modular design; securing the semiconductor subassembly in the modular package protective cover to create a modular package assembly; and mounting the modular package assembly to a core, with a base side of the semiconductor substrate base element in contact with the core; otherwise: mounting the at semiconductor subassembly to the core, with the base side of the semiconductor substrate base element in contact with the core. | 2012-06-28 |
20120164793 | Power Semiconductor Device Package Method - Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected. | 2012-06-28 |
20120164794 | METHOD OF MAKING A COPPER WIRE BOND PACKAGE - A method for making a wire bond package comprising the step of providing a lead frame array comprising a plurality of lead frame units therein, each lead frame unit comprises a first die pad and a second die pad each having a plurality of tie bars connected to the lead frame array, a plurality of reinforced bars interconnecting the first and second die pads; the reinforced bars are removed after molding compound encapsulation. | 2012-06-28 |
20120164795 | Ultrasonic Wire Bonding Method for a Semiconductor Device - A risk of an electrical short between electrode pads of a semiconductor device can be reduced to thereby improve quality of the semiconductor device. During ball bonding in wire bonding, in each of the electrode pads of a semiconductor chip which are arrayed along an ultrasonic wave application direction (ultrasonic vibration direction), a ball at the tip of a copper wire and the electrode pad are coupled to each other while being rubbed against each other in a direction intersecting the ultrasonic wave application direction. Thus, the amount of AL splash formed on the electrode pad can be minimized to make the AL splash smaller. As a result, the quality of the semiconductor device assembled by the above-mentioned ball bonding can be improved. | 2012-06-28 |
20120164796 | Method of Manufacturing a Printable Composition of a Liquid or Gel Suspension of Diodes - An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary method of making a liquid or gel suspension of diodes comprises: adding a viscosity modifier to a plurality of diodes in a first solvent; and mixing the plurality of diodes, the first solvent and the viscosity modifier to form the liquid or gel suspension of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns. | 2012-06-28 |
20120164797 | Method of Manufacturing a Light Emitting, Power Generating or Other Electronic Apparatus - An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary method of fabricating an electronic device comprises: depositing one or more first conductors; and depositing a plurality of diodes suspended in a mixture of a first solvent and a viscosity modifier. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns. | 2012-06-28 |
20120164798 | METHODS OF FORMING A NONVOLATILE MEMORY CELL AND METHODS OF FORMING AN ARRAY OF NONVOLATILE MEMORY CELLS - A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material. | 2012-06-28 |
20120164799 | Method of Forming a Semiconductor Device Comprising eFuses of Increased Programming Window - In a sophisticated semiconductor device, a semiconductor-based electronic fuse may be formed in a bulk configuration, wherein the design and thus the configuration of the contact areas and the fuse region provide a wide programming window in terms of programming voltages and duration of the corresponding programming pulses. | 2012-06-28 |
20120164800 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device which includes a MISFET, includes: forming a gate insulating film on a semiconductor substrate; forming a gate electrode on the gate insulating film; implanting nitrogen equal to or more than 5.0e14 atoms/cm | 2012-06-28 |
20120164801 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a CMOS structure, wherein, in manufacturing a CMOS circuit, an impurity element which imparts p-type conductivity to the active layer of the p-channel type semiconductor device is added before forming the gate insulating film. Then, by applying thermal oxidation treatment to the active layer, the impurity element is subjected to redistribution, and the concentration of the impurity element in the principal surface of the active layer is minimized. The precise control of threshold voltage is enabled by the impurity element that is present in a trace quantity. | 2012-06-28 |
20120164802 | ADVANCED CMOS USING SUPER STEEP RETROGRADE WELLS - The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer ( | 2012-06-28 |
20120164803 | STRAINED-INDUCED MOBILITY ENHANCEMENT NANO-DEVICE STRUCTURE AND INTEGRATED PROCESS ARCHITECTURE FOR CMOS TECHNOLOGIES - A CMOS semiconductor integrated circuit device includes an NMOS device comprising a gate region, a source region, and a drain region and an NMOS channel region formed between the source region and drain region. A silicon carbide material is formed within the source region and formed within the drain region. The silicon carbide material causes the channel region to be in a tensile mode. The CMOS device also has a PMOS device comprising a gate region, a source region, and a drain region. The PMOS device has a PMOS channel region formed between the source region and the drain region. A silicon germanium material is formed within the source region and formed with in the drain region. The silicon germanium material causes the channel region to be in a compressive mode. | 2012-06-28 |
20120164804 | METHODS OF FORMING REVERSE MODE NON-VOLATILE MEMORY CELL STRUCTURES - Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system. | 2012-06-28 |
20120164805 | FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A HARD MASK LAYER STACK AND APPLYING A PLASMA-BASED MASK PATTERNING PROCESS - When forming sophisticated high-k metal gate electrode structures, a threshold adjusting semiconductor alloy may be formed on the basis of selective epitaxial growth techniques and a hard mask comprising at least two hard mask layers. The hard mask may be patterned on the basis of a plasma-based etch process, thereby providing superior uniformity during the further processing upon depositing the threshold adjusting semiconductor material. In some illustrative embodiments, one hard mask layer is removed prior to actually selectively depositing the threshold adjusting semiconductor material. | 2012-06-28 |
20120164806 | SEMICONDUCTOR DEVICE - A semiconductor device includes, a gate insulating film, a gate electrode, a source/drain region, and a Si mixed crystal layer in the source/drain region. The Si mixed crystal layer includes a first Si mixed crystal layer that includes impurities with a first concentration, a second Si mixed crystal layer formed over the first Si mixed crystal layer and that includes the impurities with a second concentration higher than the first concentration, and a third Si mixed crystal layer formed over the second Si mixed crystal layer and that includes the impurities with a third concentration lower than the second concentration. | 2012-06-28 |
20120164807 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region. | 2012-06-28 |
20120164808 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening. | 2012-06-28 |
20120164809 | SEMICONDUCTOR DEVICES INCLUDING STRAINED SEMICONDUCTOR REGIONS, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEMS INCLUDING THE DEVICES - A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, forming an amorphous silicon (a-Si) region adjacent to the gate pattern by implanting a dopant containing a Group IV or VIII element into portions of the semiconductor substrate, forming gate spacers on sidewalls of the gate pattern, forming a first cavity by etching the a-Si region and the substrate using a first etching process, forming a second cavity by etching the substrate, such that the second cavity expands a profile of the first cavity in lateral and vertical directions, and forming a strained semiconductor region in the second cavity. | 2012-06-28 |
20120164810 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A first impurity region is formed by ion implantation through a first opening formed in a mask layer. By depositing a spacer layer on an etching stop layer on which the mask layer has been provided, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. An angle of the second sidewall with respect to a surface is 90°±10° across a height as great as a second depth. Thus, accuracy in extension of an impurity region can be enhanced. | 2012-06-28 |
20120164811 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, WIRING AND SEMICONDUCTOR DEVICE - In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film. | 2012-06-28 |
20120164812 | Methods of Manufacturing Semiconductor Devices - In a method of manufacturing a semiconductor device, a mask is formed on a substrate. The substrate is divided into a first region and a second region. An upper portion of the substrate in the first region is partially removed using the mask as an etching mask to form a recess. A first gate structure is formed in the recess. A portion of the mask in the first region is removed. A blocking layer pattern is formed on the substrate in the first region over the first gate structure. | 2012-06-28 |
20120164813 | RESISTOR WITH IMPROVED SWITCHABLE RESISTANCE AND NON-VOLATILE MEMORY DEVICE - A resistor with improved switchable resistance includes a first electrode, a second electrode, and an insulating dielectric structure between the first and second electrodes. The insulating dielectric structure includes a confined conductive region providing a first resistance state and a second resistance state; the resistance state of the confined conductive region being switchable between the first and second resistance states by a control signal. | 2012-06-28 |
20120164814 | HIGH VOLTAGE DIODE WITH REDUCED SUBSTRATE INJECTION - A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps. | 2012-06-28 |
20120164815 | METHOD OF FORMING ELEMENT ISOLATION LAYER - There is provided a method of forming an element isolation layer, the method including: forming a pad oxide layer and a nitride layer in succession on a front face of a semiconductor substrate; forming a trench so as to penetrate through the pad oxide layer and the nitride layer and into the semiconductor substrate; forming an in-fill oxide layer so as to fill the trench and cover the nitride layer; polishing the in-fill oxide layer using a first polishing agent so as to leave in-fill oxide layer remaining over the nitride layer; and polishing the in-fill oxide layer using a second polishing agent having a polishing selectivity ratio of the in-fill oxide layer to the nitride layer greater than that of the first polishing agent, so as to expose the nitride layer and flatten the exposed faces of the nitride layer and the in-fill oxide layer. | 2012-06-28 |
20120164816 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes groove-like regions that are formed between two adjacent bit lines among a plurality of bit lines each having upper and side surfaces covered with a cap insulating film and a side-wall insulating film, respectively, a SiON film that contains more O (oxygen) than N (nitrogen) and continuously covers inner surfaces of the groove-like regions, and a silicon dioxide film formed by reforming polysilazane and filled in the groove-like regions with the SiON film interposed therebetween. | 2012-06-28 |
20120164817 | METHOD FOR MANUFACTURING SOI SUBSTRATE - The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween. | 2012-06-28 |
20120164818 | Process for Cleaning Wafers - Disclosed is a process for cleaning a wafer having an uneven pattern at its surface. The process includes at least: a step of cleaning the wafer; a step of substituting a cleaning liquid retained in recessed portions of the wafer with a water-repellent liquid chemical after cleaning; and a step of drying the wafer. The process is characterized in that the cleaning liquid has a boiling point of 55 to 200° C., and characterized in that the water-repellent liquid chemical used for the substitution has a temperature of not lower than 40° C. and lower than a boiling point of the water-repellent liquid chemical thereby imparting water repellency at least to surfaces of the recessed portions. With this process, it is possible to provide a cleaning process for improving the cleaning step that tends to induce a pattern collapse. | 2012-06-28 |
20120164819 | APPARATUS AND METHOD FOR MANUFACTURING POLY-SI THIN FILM - An apparatus and method for fabricating a polycrystalline silicon (poly-Si) thin film are provided. The apparatus includes a chamber, a substrate stage installed at a lower portion in the chamber and on which a substrate including a conductive layer is located, a power application unit installed at an upper portion in the chamber and including an electrode terminal applying power to the conductive layer, and a conductive pad interposed between the electrode terminal and the conductive layer. Thus, it is possible to form a uniform electric field on the conductive layer, and to form a good quality of poly-Si thin film. | 2012-06-28 |
20120164820 | SEMICONDUCTOR DEVICE FABRICATED USING A METAL MICROSTRUCTURE CONTROL PROCESS - The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal. | 2012-06-28 |
20120164821 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device may include: alternatively stacking dielectric layers and conductive layers on a substrate to form a stack structure, forming a first photoresist pattern on the stack structure, forming a second photoresist pattern whose thickness is reduced as the second photoresist pattern extends from the center of the stack structure towards a periphery of the stacked structure by performing a heat treatment on the first photoresist pattern, etching the stack structure through the second photoresist pattern to form a slope profile on the stack structure whose thickness is reduced as the slope profile extends from the center of the stack structure towards a periphery of the stacked structure, and forming a step-type profile on the end part of the stack structure by selectively etching the dielectric layer. | 2012-06-28 |
20120164822 | METHODS OF FABRICATING HIGH-K METAL GATE DEVICES - Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate. | 2012-06-28 |
20120164823 | SPLIT GATE TYPE NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A split gate-type non-volatile semiconductor memory device includes a floating gate having an acute-angled portion between a side surface and an upper surface above a semiconductor substrate; a control gate provided apart from the floating gate to oppose to the acute-angled portion; and an insulating portion provided on the floating gate. A side surface of the insulating portion on a side of the control gate is inclined to a direction apart from the control gate with respect to a vertical line to the semiconductor substrate. | 2012-06-28 |
20120164824 | METHOD FOR FABRICATING A HIGH-K METAL GATE MOS - A method is provided for fabricating a high-K metal gate MOS device. The method includes providing a semiconductor substrate having a surface region, a gate oxide layer on the surface region, a sacrificial gate electrode on the gate oxide layer, and a covering layer on the sacrificial gate electrode, an inter-layer dielectric layer on the semiconductor substrate and the sacrificial gate electrode. The method also includes planarizing the inter-layer dielectric layer to expose a portion of the covering layer atop the sacrificial gate electrode, implanting nitrogen ions into the inter-layer dielectric layer until a depth of implantation is deeper than a thickness of the portion of the covering layer atop the sacrificial gate electrode and polishing the inter-layer dielectric layer to expose a surface of the sacrificial gate electrode, removing the sacrificial gate electrode, and depositing a metal gate. | 2012-06-28 |
20120164825 | SEMICONDUCTOR PACKAGE WITH A METAL POST AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an insulating layer, being formed on one surface of the semiconductor substrate; a metal post, penetrating through the conductive pad, the semiconductor substrate, and the insulating layer; and an outer-layer circuit, being electrically connected to the metal post. With the present invention, it can become unnecessary to form an additional via for electrically connecting both surfaces of the semiconductor substrate, thereby simplifying the manufacturing process, reducing the manufacturing cost, and improving the coupling reliability. | 2012-06-28 |
20120164826 | Methods of Forming Metal Patterns in Openings in Semiconductor Devices - A method of forming a semiconductor device is disclosed. A dielectric layer having a opening therein is formed on a semiconductor substrate. An inner surface of the opening is treated by plasma. A barrier metal layer is formed on the plasma-treated inner surface of the opening. A seed layer is formed on the barrier metal layer. A metal bulk layer is formed on the seed layer. High quality semiconductor devices can be fabricated by using these methods, which may stably fill the opening formed in the dielectric layer. | 2012-06-28 |
20120164827 | FABRICATION OF THROUGH-SILICON VIAS ON SILICON WAFERS - A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias. | 2012-06-28 |
20120164828 | HIDDEN PLATING TRACES - A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided. | 2012-06-28 |
20120164829 | FABRICATION OF THROUGH-SILICON VIAS ON SILICON WAFERS - A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. | 2012-06-28 |
20120164830 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES - Provided is a method of fabricating a semiconductor device. The method includes: preparing a substrate with an etching target, and etching the etching target through a plasma-free etching process that uses an etching gas including one of interhalogen compound, F | 2012-06-28 |
20120164831 | Methods Of Forming Semiconductor Devices - Methods of forming a semiconductor device are provided. The methods may include forming a second insulation pattern on a first insulation pattern. The first insulation pattern may cover a plurality of conductive structures, and may include a hole therein. The second insulation pattern may include a trench therein that is connected with the hole. The methods may also include forming a spacer on sidewalls of the hole and the trench. The methods may further include forming a wiring structure in the hole and the trench. | 2012-06-28 |
20120164832 | METHOD FOR DEPOSITING TUNGSTEN FILM HAVING LOW RESISTIVITY, LOW ROUGHNESS AND HIGH REFLECTIVITY - Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines. | 2012-06-28 |
20120164833 | Polishing Agent, Compound Semiconductor Manufacturing Method, and Semiconductor Device Manufacturing Method - Afforded are a polishing agent, and a compound semiconductor manufacturing method and semiconductor device manufacturing method utilizing the agent, whereby the surface quality of compound semiconductor substrates can be favorably maintained, and high polishing rates can be sustained as well. The polishing agent is a polishing agent for Ga | 2012-06-28 |
20120164834 | Variable-Density Plasma Processing of Semiconductor Substrates - Methods and hardware for generating variable-density plasmas are described. For example, in one embodiment, a process station comprises a showerhead including a showerhead electrode and a substrate holder including a mesa configured to support a substrate, wherein the substrate holder is disposed beneath the showerhead. The substrate holder includes an inner electrode disposed in an inner region of the substrate holder and an outer electrode being disposed in an outer region of the substrate holder. The process station further comprises a plasma generator configured to generate a plasma in a plasma region disposed between the showerhead and the substrate holder, and a controller configured to control the plasma generator, the inner electrode, the outer electrode, and the showerhead electrode to effect a greater plasma density in an outer portion of the plasma region than in an inner portion of the plasma region. | 2012-06-28 |
20120164835 | Method of Forming Via Hole - The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned photoresist layer is formed on the blocking layer. The patterned photoresist layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned photoresist layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area. | 2012-06-28 |
20120164836 | INTEGRATED CIRCUIT FABRICATION METHODS UTILIZING EMBEDDED HARDMASK LAYERS FOR HIGH RESOLUTION PATTERNING - Embodiments of a method for fabricating integrated circuits are provided. In one embodiment, the method includes the steps of depositing a dielectric layer over a semiconductor device, forming a plurality of trimmed hardmask structures at predetermined locations over the dielectric layer, embedding the plurality of trimmed hardmask structures in a surrounding hardmask layer, removing the plurality of trimmed hardmask structures to create a plurality of openings through the surrounding hardmask layer, and etching the dielectric layer through the plurality of openings to form a plurality of etch features therein. | 2012-06-28 |
20120164837 | FEATURE SIZE REDUCTION - Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited. | 2012-06-28 |
20120164838 | METHOD FOR PLANARIZING INTERLAYER DIELECTRIC LAYER - The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer. | 2012-06-28 |
20120164839 | SUBSTRATE PROCESSING METHOD - There is provided a substrate processing method capable of increasing an etching rate of a copper member without using a halogen gas. A Cu layer | 2012-06-28 |
20120164840 | Substrate Processing Method and Substrate Processing Apparatus - A substrate processing method includes a liquid processing process that supplies a processing liquid onto a substrate to process the substrate; a heating process that heats the substrate on which a liquid film of the processing liquid is formed; a supplying process that supplies a volatile processing liquid to the substrate on which the liquid film of the processing liquid is formed; a stopping process that stops the supply of the volatile processing liquid to the substrate; and a drying process that dries the substrate by removing the volatile processing liquid, in which the heating process starts before the supplying process that supplies the volatile processing liquid and the substrate is heated so that the surface temperature of the substrate is higher than a dew point before the surface of the substrate is exposed from the volatile processing liquid. | 2012-06-28 |
20120164841 | COMBINATORIAL NON-CONTACT WET PROCESSING - An apparatus and method for combinatorial non-contact wet processing of a liquid material may include a source of a liquid material, a first reaction cell, a second reaction cell, a first plurality of gas jets disposed within an interior of the first reaction cell, the first plurality of gas jets configured to atomize the liquid material transferred to the interior of the first reaction cell, a second plurality of gas jets disposed within an interior of the second reaction cell, the second plurality of gas jets configured to atomize the liquid material transferred to the interior of the second reaction cell, a first vacuum element disposed along a periphery of the first reaction cell, and a second vacuum element disposed along a periphery of the at least a second reaction cell. | 2012-06-28 |
20120164842 | TRENCH EMBEDDING METHOD AND FILM-FORMING APPARATUS - A trench embedding method includes forming an oxidization barrier film on a trench; forming an expandable film on the oxidization barrier film; embedding an embedding material that contracts by being fired on the trench; and firing the embedding material, wherein the forming of the oxidization barrier film includes: forming a first seed layer on the trench by supplying an aminosilane-based gas; and forming a silicon nitride film on the first seed layer, wherein the forming of the expandable film includes: forming a second seed layer on the silicon nitride film by supplying an aminosilane-based gas; and forming a silicon film on the second seed layer. | 2012-06-28 |
20120164843 | TRANSFER OF HIGH TEMPERATURE WAFERS - This invention provides methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a method for moving wafers or substrates that can bathe a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency. | 2012-06-28 |
20120164844 | METHOD AND APPARATUS FOR FORMING OXIDE FILM ON CARBON FILM - A method for forming an oxide film on a carbon film includes the steps of forming a carbon film on an object to be processed; forming an object-to-be-oxidized layer on the carbon film; and forming an oxide film on the object-to-be-oxidized layer while oxidizing the object-to-be-oxidized layer. | 2012-06-28 |
20120164845 | DUAL ZONE GAS INJECTION NOZZLE - The present invention generally provides apparatus and method for processing a substrate. Particularly, the present invention provides apparatus and methods to obtain a desired distribution of a process gas. One embodiment of the present invention provides an apparatus for processing a substrate comprising an injection nozzle having a first fluid path including a first inlet configured to receive a fluid input, and a plurality of first injection ports connected with the first inlet, wherein the plurality of first injection ports are configured to direct a fluid from the first inlet towards a first region of a process volume, and a second fluid path including a second inlet configured to receive a fluid input, and a plurality of second injection ports connected with the second inlet, wherein the second injection ports are configured to direct a fluid from the second inlet towards a second region of the process volume. | 2012-06-28 |
20120164846 | Method of Forming Metal Oxide Hardmask - A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula Si | 2012-06-28 |
20120164847 | THIN FILM FORMING METHOD, THIN FILM FORMING APPARATUS, AND PROGRAM - A control unit heats a reaction pipe to a load temperature by controlling a temperature-raising heater | 2012-06-28 |
20120164848 | METHOD FOR FORMING NITRIDE FILM - A plasma-assisted ALD method using a vertical furnace and being performed by repeating a cycle until a desired film thickness is obtained is disclosed. The cycle comprises introducing a source gas containing a source to be nitrided, adsorbing, purging, introducing a nitriding gas and nitriding the source, and then, purging. A flow rate of a second carrier gas during introduction of the nitriding gas is reduced relative to that of a first carrier gas during introduction of the source gas. Particularly, a flow ratio of NH | 2012-06-28 |
20120164849 | SELF-ORIENTING ELECTRICAL CONNECTOR - An electrical connector and electronic device for connecting to a complementary electrical connector are provided. The electrical connector comprises a main body containing one or more electrically conducting mediums. The electrical connector also comprises an end piece rotatably connected to the main body at one end of the main body. The end piece has a connecting side for engaging the complementary electrical connector. The end piece is rotatable about an axis of rotation. The connecting side comprises one or more electrical contacts for engaging complementary electrical contacts on the complementary electrical connector. Each electrical contact of the electrical connector is electrically connected to one of the electrically conducting mediums of the main body. The connecting side also comprises a magnet disposed on the connecting side of the end piece for engaging a complementary magnet on the complementary electrical connector. | 2012-06-28 |
20120164850 | SENSOR APPARATUS - A sensor apparatus ( | 2012-06-28 |
20120164851 | Circuit Board Assembly, Board Device, And Method For Assembling Circuit Board Assembly - The invention has an object to provide a circuit board assembly for a circuit board, the circuit board assembly having a contact and a housing. The housing includes a contact holding plate having a receiving passageway located n a surface of the contact holding plate disposed perpendicular to a surface of a circuit board, and a contact securing portion. The contact includes a press-fit into and held by the contact securing portion of the receiving passageway, and having a board insertion portion positioned perpendicular to the surface of the circuit board inserted into the receiving passageway from a side of the board insertion portion with respect to the contact holding plate, and a housing insertion section extending in parallel to the surface of the circuit board inserted into the receiving passageway from a side of the board insertion portion with respect to the contact holding plate. | 2012-06-28 |
20120164852 | ADAPTER APPARATUS - An adapter apparatus for connecting two connectors of the same type includes a receiving rack used to fasten two connectors, and a connection board attached to the receiving rack. A number of first gold fingers and a number of second gold fingers are formed on opposite ends of the connection board, to be electrically connected to the connectors, respectively. | 2012-06-28 |
20120164853 | BOARD-TO-BOARD CONNECTOR - A board-to-board connector includes a double plastic pin header connector and a supporting plate. The double plastic pin header connector includes two opposite positioning plates, and a number of pin headers arranged in two rows and extending through the positioning plates. The supporting plate is placed between the two rows of pin headers, with opposite ends of the supporting plate resisting against the corresponding positioning plates. | 2012-06-28 |
20120164854 | PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME - A packaging substrate is proposed, which includes: a circuit layer formed on a substrate and having conductive pads, an insulating protective layer formed on the substrate for covering the circuit layer and having openings for correspondingly exposing the conductive pads; copper bumps each having a connection portion formed in a corresponding one of the openings and electrically connected to a corresponding one of the conductive pads, and a protruding portion integrally connected to the connection portion and extending to a portion of the insulating protective layer surrounding the corresponding one of the openings, allowing the protruding portion to be greater in diameter than the connection portion, and a surface treatment layer having an electroplated nickel material formed on top surfaces of the protruding portions of the copper bumps, and an electroplated gold material formed on the electroplated nickel material. The surface treatment layer is not formed on side surfaces of the protruding portions, such that the thickness of the surface treatment layer is irrelevant to the diameter of the protruding portion. | 2012-06-28 |
20120164855 | CONNECTOR TERMINAL - A connector terminal curved from a strip-shaped metal plate has a soldering plate of which a substantial middle of one end edge extends upward to form a bracket plate, an arched connecting portion bent upward from the other end of the soldering plate and apart facing the bracket plate, and a flexible arm extending from a free end of the connecting portion towards the bracket plate and parallel to the soldering plate. Two opposite side edges of a top end of the bracket plate oppositely protrude to form a pair of blocking ears. A free end of the flexible arm is arched upward to form an inverted-V shaped contacting portion adjacent to the bracket plate. Two ends of a distal edge of the contacting portion further extend beyond the two opposite side edges of the bracket plate to form a pair of resisting tails respectively restrained under the blocking ears. | 2012-06-28 |
20120164856 | CONNECTOR AND SOLDER SHEET - A connector includes a lead part configured to be connected to a board; and a solder sheet having a plate shape. The solder sheet is engaged with and fixed to the lead part with the lead part passing through a hole in the solder sheet. At least one of the lead part and the solder sheet has a structure configured to prevent the solder sheet from coming off the lead part. | 2012-06-28 |
20120164857 | Cable Adapter and Adapted System - An electrical adapter enables the conductors of a flexible cable to be extended into an armored conduit with electrical ground continuity and a rigid structural attachment. The adapter is cylindrical and has removable cover over an oblique aperture providing a highly rigid and strengthened fixture, which has a ground wire clamp for securement of the wires of the cable. An adapter collar is secured rotationally to one end of the adapter body for connecting the adapter to a nipple of an armored conduit mounted to a wall structure. The ground wire is secured to the ground wire fixture, and with the adapter collar secured to the armored conduit, electrical ground continuity is extended from the flexible cable to the armored conduit. With the removable cover secured over the access aperture, exposure of the ground wire clamp and the conductors of the flexible cable is eliminated. | 2012-06-28 |
20120164858 | COVER FOR A CONNECTION TERMINAL OF A PORTABLE TERMINAL - A connection terminal opening and closing device for a portable terminal is provided, in which a connection terminal cover is disposed movably at an inlet of the connection terminal for automatically closing, when a predetermined area of the external cover is pressed which in turn triggers an elastic member engaged with the connection terminal cover between the body and the external cover to provide an automatic closing force to the connection terminal cover. | 2012-06-28 |
20120164859 | CARD EDGE CONNECTOR - A card edge connector includes an elongated housing extending along a lengthwise direction thereof and having a pair of opposed side walls, and a central slot between the side walls. A plurality of contacts are retained in the housing and exposed to the central slot. A pair of ejector mechanisms are rotatable retained on two opposite ends of the housing. A pair of auxiliary insulators are attached to the ejector mechanisms, respectively. A tie wrap is located on the auxiliary insulators to urge the auxiliary insulators to prevent the ejector mechanisms from rotating. | 2012-06-28 |
20120164860 | PLUG CONNECTOR HAVING A RELEASING MECHANISM AND A CONNECTOR ASSEMBLY HAVING THE SAME - A connector assembly includes a receptacle ( | 2012-06-28 |
20120164861 | SAFETY SOCKET - A safety socket includes a first conductive clamp seat and a second conductive clamp seat in alignment with a first insertion hole and a second insertion hole. In normal state, the first and second conductive clamp seats are spaced from a first power terminal and a second power terminal in an open state. When a plug is plugged into the safety socket, the prongs of the plug outward bias spring limbs of the first and second conductive clamp seats into contact with the corresponding first and second power terminals respectively. Only under such circumstance, the first and second conductive clamp seats electrically contact the first and second power terminals to close the circuit and provide power for an electric appliance. If a child inserts a conductive article into the first or second insertion hole, the danger of electrical shock can be avoided to ensure safety in use of electricity. | 2012-06-28 |
20120164862 | ELECTRICAL CONNECTOR HAVING IMPROVED CONTACT MEMBER - An electrical connector ( | 2012-06-28 |
20120164863 | CARD EDGE CONNECTOR - A card edge connector comprises an insulating body and a plurality of terminals. The insulating body comprises a base defining a forward mating slot and a plurality of passageways communicating with the mating slot, and two flexible arms respectively extending forward and upward from two ends of the base. Each flexible arm is provided with a locking member, a pressing member near the locking member, and a stopping member near the locking member and lower than the pressing member. The plurality of terminals are correspondingly fixed in the plurality of passageways. Each terminal includes a fixing portion positioned in the base, a soldering portion extending out from the base, and a contact portion extending into the mating slot. | 2012-06-28 |
20120164864 | CARD EDGE CONNECTOR - A card edge connector is connectable to a card having a side edge. The card edge connector has a holding member extending in a first direction and a pair of arms each extending in a second direction perpendicular to the first direction from the holding member. Each of the arms includes an abutment portion and a spring portion. The spring portion is bendable elastically outward in the first direction. The spring portion has a latch and an abutting portion. The latch is engaged with the side edge of the card when the card edge connector is connected to the card. When the connected card presses the latch along a third direction perpendicular to both the first direction and the second direction, the abutting portion is brought into contact with the abutment portion so that the abutting portion regulates a movement of the latch in the third direction. | 2012-06-28 |
20120164865 | CONNECTING SYSTEM FOR ELECTRICALLY CONNECTING ELECTRONIC DEVICES AND METHOD FOR CONNECTING AN ELECTRICALLY CONDUCTIVE FIRST CONNECTOR AND AN ELECTRICALLY CONDUCTIVE SECOND CONNECTOR - A connecting system for electrically connecting electronic devices includes an electrically conductive first connector, an electrically conductive second connector and a clip element. The first connector is insertable in the second connector. The first connector or the second connector has a first opening into which the clip element can be inserted. In the inserted state, the clip element generates a contact pressure due to which the first connector and the second connector are pressed against one another so that an electrical contact between the first connector and the second connector is safeguarded. | 2012-06-28 |
20120164866 | Connector Member - A connector member that is improved in durability and reliability by preventing fracture of hinges of a retainer and can be smoothly mated with a mating connector. The connector member having a lance housing. a connector housing, and the retainer. The lance housing includes a plurality of terminal receiving slots, a recess disposed at a rear of the plurality of terminal receiving slots and in a portion of the lance housing near a rear surface thereof, and a pair of guide walls positioned opposite each other along a top surface of the lance housing. The connector housing includes a housing recess opening at one side for housing the lance housing. The retainer is fitted into the recess of the lance housing and swingably connected to the lance housing by a hinge. | 2012-06-28 |
20120164867 | DIRECT MOUNT CONNECTOR TERMINAL AND DIRECT MOUNT CONNECTOR - The present invention is to provide a direct mount connector terminal and a direct mount connector for improving reliability of connection thereof. The direct mount connector terminal is locked to a connector housing with a lance of the connector housing. The direct mount connector terminal includes an electrical connection portion extending toward a connection direction of a mating terminal, a bent portion connected to and bent with respect to the electrical connection portion, a parallel portion connected to the bent portion and parallel to the electrical connection portion, and a locking portion disposed on the parallel portion and to be locked to the lance of the connector housing. | 2012-06-28 |
20120164868 | RJ-45 CONNECTOR ASSEMBLY AND ASSISTING APPARATUS FOR UNPLUGGING RJ-45 CONNECTOR - A Registered Jack-45 (RJ-45) connector assembly includes an RJ-45 connector, and an assisting apparatus for unplugging the RJ-45 connector. The RJ-45 connector includes a slanted resilient latch. The assisting apparatus includes a latching portion and a pressable portion. A receiving slot is defined in the front end of the latching portion, to engage with the resilient latch of the RJ-45 connector. When the pressable portion is pressed, the assisting apparatus drives the resilient latch of the RJ-45 connector to deform and disengage from a connector of an electronic device. | 2012-06-28 |
20120164869 | CONNECTOR FOR CONNECTING ELECTRONIC DEVICE - A connector includes a connector main body that connects with another connector, a lanyard part and a latch part provided at least on one of the side planes of the connector main body, and a hook provided on the latch part and protruding outward from the connector main body. The lanyard part includes a first lanyard bent part, a straight lanyard part, and a second lanyard bent part that are sequentially arranged in a connecting direction with respect to the another connector. The latch part includes a first latch bent part, a first latch straight part, and a second latch bent part that are sequentially arranged in the connecting direction. The first lanyard bent part includes a first lanyard opening into which the first latch bent part is inserted. The second lanyard bent part includes a second lanyard opening into which the second latch bent part is inserted. | 2012-06-28 |
20120164870 | HIGH STRENGTH ELECTRICAL CONNECTOR - A high strength electrical connector includes an outer cylindrical, rigid support cover open at both ends and preferably comprised of a high strength metal. A first electrical lead extends through a tension bushing attached to one end of the support cover. A mating receptacle through which a second electrical lead passes is securely attached to a second opposed end of the support cover. Electrical connection between the ends of the first and second electrical leads is established within the support cover. Securely attaching the ends of the first and second electrical leads together within the support cover, which is preferably comprised of a high strength metal, directs axial and transverse forces exerted on the first electrical lead through the support cover, thus bypassing the electrical connection. | 2012-06-28 |
20120164871 | CHARGER CONNECTOR - An electrical connector ( | 2012-06-28 |
20120164872 | CONNECTOR - A connector which makes it less difficult to insert two types of card-type electronic components, even when it is used over a long term. A first recess in which a first memory card is inserted has a bottom surface formed with a second recess in which a second memory card is inserted, whereby guiding surfaces are formed for guiding a second memory card in a card-inserting direction. | 2012-06-28 |
20120164873 | Junction Box, Particularly for Lighting Lines for Tunnels - A junction box particularly for lighting lines for tunnels includes a casing body provided with a cover; the casing body includes an electrical socket; a junction device inside the casing body connects the electrical socket to a pair of power supply wires of a power supply line that is affected by the junction box; the junction device includes one or more insulation displacement contacts; each insulation displacement contact engages a respective power supply wire without cutting it. | 2012-06-28 |
20120164874 | CARD-EDGE CONNECTOR AND CARD-EDGE CONNECTOR ASSEMBLY HAVING HEAT-RADIATING STRUCTURES - A card-edge connector includes an insulative housing and a number of conductive contacts. The insulative housing defines a mating direction along a front-to-back direction and opposite front face and rear face. The insulative housing includes a pair of lengthwise walls, a central slot recessed from the front face along the front-to-back direction and at least one heat-radiating slot recessed from the front face along the front-to-back direction, and a number of contact-receiving passages in the lengthwise walls and communicating with the central slot. The heat-radiating slot is recessed from at least one of the pair of lengthwise walls and communicates with the contact-receiving passages along the mating direction. The conductive contacts are received in the contact-receiving passages. | 2012-06-28 |
20120164875 | CABLE CONNECTOR ASSEMBLY WITH AN IMPROVED LIGHT PIPE - A cable connector assembly ( | 2012-06-28 |
20120164876 | RESILIENT PLUG CONNECTOR - An improved plug connector ( | 2012-06-28 |
20120164877 | METHOD AND APPARATUS FOR INSTALLING AN ACCESS POINT OVER AN ELECTRONIC WALL BOX - An access point which is installed over the standard electronic wall box and provides access to different types of existing cables in a standard electronic wall box is disclosed. The access point includes at least one pass-through slot which houses a pass-through port. The pass-through port supports different types of connectors for different types of cables installed in the standard electronic wall box. The pass-through slot is used to expose the different types of connectors on the access point. The access point also includes a connection port to connect the access point to a wall cable which is a network uplink cable for connecting the access point to a network. The access point further includes an expansion slot to connect an expansion module to the access point. When the access point is installed on the standard electronic wall box, the pass-through slot is used to expose a cable that is different from the wall cable. | 2012-06-28 |
20120164878 | RF MODULE - An RF module configured to be coupled to a backplane module includes a front housing that has walls that define connector cavities. The walls include a rear wall that has a plurality of openings therethrough. The connector cavities are open opposite the rear wall to receive electrical connectors. The RF module also includes RF cable assemblies having front end connectors and rear end connectors that are connected by corresponding cables. The front and rear end connectors are coaxial connectors. The front end connectors are received in corresponding connector cavities through corresponding openings. The RF module includes a connector holder extending from the front housing rearward of the rear wall. The connector holder holds the rear end connectors such that the rear end connectors are simultaneously pluggable into corresponding board connectors of the backplane module. | 2012-06-28 |
20120164879 | COAXIAL CONNECTOR - A coaxial connector includes a terminal, an insulating housing for receiving the terminal therein, and a shell for receiving the insulating housing therein. The terminal includes a carrier plate; two contacts correspondingly provided at their facing sides with two concaved areas for electrically connecting with an external round-shaped conductor; and a first and a second fastening plate for fastening to a core wire of a cable. The two contacts and the first and second fastening tabs are oriented toward the same direction. With the above arrangements, the coaxial connector can be easily assembled and have reduced assembly height, the first and second fastening plates are in direct contact with the core wire to securely fasten the same to the terminal, and the contact area between the contacts and the external round-shaped conductor is increased, ensuring good electrical signal transmission via the coaxial connector. | 2012-06-28 |
20120164880 | TERMINAL FOR COAXIAL CONNECTOR - A terminal for coaxial connector includes a carrier plate; two contacts provided on two opposite lateral edges of the carrier plate; and a first and a second fastening tab separately provided on an end of the carrier plate. The two contacts and the first and second fastening tabs are oriented toward the same direction, the first and second fastening tabs are directly fastened to a core wire of a cable, and the contacts are correspondingly provided on their facing sides with two concaved areas for electrically connecting to an external round-shaped conductor. With these arrangements, the terminal for coaxial connector can be easily assembled to a cable and has reduced assembly height, the first and second fastening plates are in direct and firm contact with the core wire, and the contact area between the contacts and the external round-shaped conductor is increased to thereby ensure good electrical signal transmission. | 2012-06-28 |
20120164881 | SHIELDED CONNECTOR - A shielded connector includes: a seat, including an insulating body having a plurality of receiving slots, in which an intermediate layer is disposed on at least a part of an inner surface of the receiving slot, a shield is disposed outside the intermediate layer, and an isolator is disposed outside the shield, at least one conductive body disposed outside the receiving slots and connected to the shields, and at least one lead-out portion electrically connected to the conductive body; and a plurality of conductive terminals, correspondingly accommodated in the receiving slot, each including a contact portion exposed at one side of the seat, a body portion extending from the other end of the contact portion into the receiving slot, and a connecting section extending from the body portion and exposed at the other side of the seat. | 2012-06-28 |
20120164882 | ELECTRICAL CONNECTOR - An electrical connector including a housing having an opening through which an FPC is inserted into the housing, conductive contacts arranged on the housing for contacting with signal connecting terminals on the FPC, and a conductive shell member mounted on the housing and provided therein with a holding portion for holding the FPC inserted in the housing and a releasing portion for releasing the FPC from holding by the holding portion, wherein the holding portion extends into the housing from an end wall portion of the conductive shell member covering a side end portion of the housing to engage with the FPC and the releasing portion is movable in an operating direction intersecting a direction of arrangement of the conductive contacts and provided thereon with an engaging projection for engaging with the holding portion to release the same from the engagement with the FPC. | 2012-06-28 |
20120164883 | DEVICE FOR SECURING A POST IN A TERMINAL CLAMP - A device is proposed for fastening a post in a terminal clamp, having at least one terminal clamp for connection to a battery terminal, at least one electronics unit or measuring element capable of being connected to the terminal clamp, at least one post for connecting a battery cable, the post being mechanically fastened to the terminal clamp via a connection, and having at least one insulating element between the post and the terminal clamp, means being provided for the rotational securing of the post. | 2012-06-28 |
20120164884 | Plug-in Connector - The invention relates to a plug-in connector ( | 2012-06-28 |
20120164885 | APPARATUS AND SYSTEM FOR ELECTRONIC DEVICE INTERROGATION AND DATA EXTRACTION - An apparatus for connecting a computing device to different types of mobile devices that includes an enclosure that encloses a USB hub, mobile device cables connectable to different mobile devices, and a USB cable connectable to a computing device to extract data from connected mobile devices. The mobile device cables are coupled to the USB cable through the USB hub. The apparatus can include multimedia card readers within the enclosure that are coupled to the USB hub and connectable to different types of multimedia cards to extract data from connected multimedia cards. The multimedia card readers can be write-protected to only read information from connected multimedia cards. The apparatus can include biometric data gathering tools, camera or light within the enclosure. The enclosure can be tube, notebook or flask shaped. The apparatus can also include a wiring harness that seals one end of the enclosure from the other end. | 2012-06-28 |
20120164886 | LOWER PROFILE ELECTRICAL CONNECTOR ASSEMBLY - An electrical connector assembly comprises: a housing, a plurality of conductive terminals received in the housing and arranged in two rows, each conductive terminal defining a front mating portion, a retaining portion retained in the housing, and an exposing portion located behind the housing, a PCB electrically connected to the conductive terminals, and having a number of through holes through an upper and a lower surfaces thereof; a metal shell enclosing the housing and the PCB; and a cable electrically connected to the PCB. At least a row of conductive terminals are bent and pass through the through holes, and two rows of exposing portions of the conductive terminals are soldered on a surface of the PCB. | 2012-06-28 |
20120164887 | ELECTRICAL CONNECTOR WITH A COVER TRANSITIONALLY ASSEMBLED ON AN INCLINED SLIDING SLOT - An electrical connector includes an insulative housing defining a mounting face, a pair of pivotal grooves on opposite sides of a rear end of the housing and a pair of locking recesses in front of the pivotal grooves respectively; a plurality of contacts arranged in the housing and a metal shell defining a pair of pivotal posts assembled in the pivotal grooves and a pair locking tabs to couple with the pair of locking recesses in a condition that the metal shell rotates to cover on the insulating housing and move forwards. The pair of pivotal posts therebetween defines an axis paralleling to the mounting face and the axis of the pair of pivotal posts is closer gradually to the mounting face during forward movement of the metal shell. | 2012-06-28 |