| 26th week of 2013 patent applcation highlights part 68 |
| Patent application number | Title | Published |
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| 20130166875 | WRITE DATA MASK METHOD AND SYSTEM - In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface. | 2013-06-27 |
| 20130166876 | METHOD AND APPARATUS FOR USING A PREVIOUS COLUMN POINTER TO READ ENTRIES IN AN ARRAY OF A PROCESSOR - A method and apparatus are described for using a previous column pointer to read a subset of entries of an array in a processor. The array may have a plurality of rows and columns of entries, and each entry in the subset may reside on a different row of the array. A previous column pointer may be generated for each of the rows of the array based on a plurality of bits indicating the number of valid entries in the subset to be read, the previous column pointer indicating whether each entry is in a current column or a previous column. The entries in the subset may be read and re-ordered, and invalid entries in the subset may be replaced with nulls. The valid entries and nulls may then be outputted. | 2013-06-27 |
| 20130166877 | SHAPED REGISTER FILE READS - One embodiment of the present invention sets forth a technique for performing a shaped access of a register file that includes a set of N registers, wherein N is greater than or equal to two. The technique involves, for at least one thread included in a group of threads, receiving a request to access a first amount of data from each register in the set of N registers, and configuring a crossbar to allow the at least one thread to access the first amount of data from each register in the set of N registers. | 2013-06-27 |
| 20130166878 | VECTOR SIMD PROCESSOR - Operation parallelism of a data processor is enhanced by floating-point inner product execution units compatible with single instruction multiple data (SIMD). An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining efficiency of floating-point length-4 vector inner product execution units is implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle. | 2013-06-27 |
| 20130166879 | MULTIPROCESSOR SYSTEM AND SYNCHRONOUS ENGINE DEVICE THEREOF - The invention discloses a multiprocessor System and synchronous engine device thereof. the synchronous engine includes: a plurality of storage queues, wherein one of the queues stores all synchronization primitives from one of the processors; a plurality of scheduling modules, selecting the synchronization primitives for execution from the plurality of storage queues and then according to the type of the synchronization primitive transmitting the selected synchronization primitives to corresponding processing modules for processing, scheduling modules corresponding in a one-to-one relationship with the storage queues; a plurality of processing modules, receiving the transmitted synchronization primitives to execute different functions; a virtual synchronous memory structure module, using small memory space and mapping main memory spaces of all processors into a synchronization memory structure to realize the function of all synchronization primitives through a control logic; a main memory port, communicating with virtual synchronous memory structure module to read and write the main memory of all processors, and initiate an interrupt request to processors; a configuration register, storing various configuration information required by processing modules. | 2013-06-27 |
| 20130166880 | PROCESSING DEVICE AND METHOD FOR CONTROLLING PROCESSING DEVICE - A processing device has an instruction buffer retaining one or more instructions obtained by an instruction fetch request, an instruction execution control unit decoding and executing an instruction, a branch prediction mechanism retaining one or more branch histories including a distance flag indicating a difference between a branch instruction address and a branch destination instruction address and performing a branch prediction of an instruction, and an instruction fetch control unit issuing the instruction fetch request. When a branch prediction result is a branch taken and it is judged based on the distance flag that the instruction fetch request for the branch destination instruction address is included in the instruction fetch requests in a sequential direction which are issued until the branch prediction result is outputted, the control unit causes to output an instruction retained in the instruction buffer without issuing an instruction fetch request for the branch destination instruction address. | 2013-06-27 |
| 20130166881 | METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS USING PRE-DECODE DATA - Systems and methods for scheduling instructions using pre-decode data corresponding to each instruction. In one embodiment, a multi-core processor includes a scheduling unit in each core for selecting instructions from two or more threads each scheduling cycle for execution on that particular core. As threads are scheduled for execution on the core, instructions from the threads are fetched into a buffer without being decoded. The pre-decode data is determined by a compiler and is extracted by the scheduling unit during runtime and used to control selection of threads for execution. The pre-decode data may specify a number of scheduling cycles to wait before scheduling the instruction. The pre-decode data may also specify a scheduling priority for the instruction. Once the scheduling unit selects an instruction to issue for execution, a decode unit fully decodes the instruction. | 2013-06-27 |
| 20130166882 | METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS WITHOUT INSTRUCTION DECODE - Systems and methods for scheduling instructions without instruction decode. In one embodiment, a multi-core processor includes a scheduling unit in each core for scheduling instructions from two or more threads scheduled for execution on that particular core. As threads are scheduled for execution on the core, instructions from the threads are fetched into a buffer without being decoded. The scheduling unit includes a macro-scheduler unit for performing a priority sort of the two or more threads and a micro-scheduler arbiter for determining the highest order thread that is ready to execute. The macro-scheduler unit and the micro-scheduler arbiter use pre-decode data to implement the scheduling algorithm. The pre-decode data may be generated by decoding only a small portion of the instruction or received along with the instruction. Once the micro-scheduler arbiter has selected an instruction to dispatch to the execution unit, a decode unit fully decodes the instruction. | 2013-06-27 |
| 20130166883 | METHOD AND APPARATUS FOR PERFORMING LOGICAL COMPARE OPERATIONS - A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location. | 2013-06-27 |
| 20130166884 | METHOD AND APPARATUS FOR PERFORMING LOGICAL COMPARE OPERATIONS - A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location. | 2013-06-27 |
| 20130166885 | METHOD AND APPARATUS FOR ON-CHIP TEMPERATURE - When an instruction is executed on an integrated circuit (IC), an activity level and temperature are measured. A relationship between the activity level and temperature is determined, to estimate the temperature from the activity level. The activity level is monitored and is input to a scheduler, which estimates the IC temperature based on the activity level. The scheduler distributes work taking into account the temperature of various IC regions and may include distributing work to the IC region that has a lowest estimated temperature or relatively lower estimated temperature (e.g., lower than the average IC or IC region temperature). When the utilization level of one or more IC regions is high, the scheduler is configured to reduce the clock speed or the voltage of the one or more IC regions, or flag the regions as being unavailable for additional workload. | 2013-06-27 |
| 20130166886 | SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS - Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks. | 2013-06-27 |
| 20130166887 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - According to one embodiment, a data processing apparatus includes a processor and a memory. The processor includes core blocks. The memory stores a command queue and task management structure data. The command queue stores a series of kernel functions. The task management structure data defines an order of execution of kernel functions by associating a return value of a previous kernel function with an argument of a subsequent kernel function. Core blocks of the processor are capable of executing different kernel functions. | 2013-06-27 |
| 20130166888 | PREDICTIVE OPERATOR GRAPH ELEMENT PROCESSING - Techniques are described for predictively starting a processing element. Embodiments receive streaming data to be processed by a plurality of processing elements. An operator graph of the plurality of processing elements that defines at least one execution path is established. Embodiments determine a historical startup time for a first processing element in the operator graph, where, once started, the first processing element begins normal operations once the first processing element has received a requisite amount of data from one or more upstream processing elements. Additionally, embodiments determine an amount of time the first processing element takes to receive the requisite amount of data from the one or more upstream processing elements. The first processing element is then predictively started at a first startup time based on the determined historical startup time and the determined amount of time historically taken to receive the requisite amount of data. | 2013-06-27 |
| 20130166889 | METHOD AND APPARATUS FOR GENERATING FLAGS FOR A PROCESSOR - A method and apparatus are described for generating flags in response to processing data during an execution pipeline cycle of a processor. The processor may include a multiplexer configured generate valid bits for received data according to a designated data size, and a logic unit configured to control the generation of flags based on a shift or rotate operation command, the designated data size and information indicating how many bytes and bits to rotate or shift the data by. A carry flag may be used to extend the amount of bits supported by shift and rotate operations. A sign flag may be used to indicate whether a result is a positive or negative number. An overflow flag may be used to indicate that a data overflow exists, whereby there are not a sufficient number of bits to store the data. | 2013-06-27 |
| 20130166890 | APPARATUS COMPRISING A PLURALITY OF ARITHMETIC LOGIC UNITS - An arrangement of at least two arithmetic logic units carries out an operation defined by a decoded instruction including at least one operand and more than one operation code. The operation codes and at least one operand are received and corresponding executions are performed by the arithmetic logic units on a single clock cycle. The result of the execution from one arithmetic logic unit is used as an operand by a further arithmetic logic unit. The decoding of the instruction is performed in an immediately preceding single clock cycle. | 2013-06-27 |
| 20130166891 | HANDLING INSTRUCTION RECEIVED FROM A SANDBOXED THREAD OF EXECUTION - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for enveloping a thread of execution within an IDT-based secure sandbox. In one aspect, embodiments of the invention provide a method performed in a computer system, the method receiving an instruction from an execution thread where the computer system can be configured for redirection of instructions from the execution thread. The method can determine whether the instruction includes at least one of an interrupt instruction, a system call instruction and a system enter instruction. In response to determining that the instruction includes at least one of the interrupt instruction, the system call instruction and the system enter instruction, the method can further: (i) eliminate the redirection, (ii) modify a stack to specify return of control, and (iii) thereafter, pass the control to an operating system kernel. | 2013-06-27 |
| 20130166892 | GENERATING A RUNTIME FRAMEWORK - In an embodiment, the runtime framework is responsible for executing multidimensional analytical metadata in a runtime environment that is determined by the runtime framework. To generate such a runtime framework, the received multidimensional analytical metadata is analyzed to determine a type of an associated calculation pattern. Based upon the type, subsets of the multidimensional analytical metadata and corresponding runtime decision rules are determined. To execute the subsets, executable conditions corresponding to the multidimensional analytical metadata are identified. Based upon the executable conditions, the calculation pattern associated with the multidimensional analytical metadata is executed by executing the associated subsets, and the runtime framework is generated. The runtime framework determines calculation scenario executable subsets and calculation scenario inexecutable subsets that are associated with the multidimensional analytical metadata, and executes the subsets in their respective engines. | 2013-06-27 |
| 20130166893 | AUXILIARY CARD INITIALIZATION ROUTINE - A memory system or flash card may be initialized from a protected block of flash memory as a backup process. If there is an error during regular card initialization and the firmware for the card cannot be loaded, the card may be inaccessible to a user. Booting with a protected block of memory may be used to load a different version of the firmware that can still initialize the card despite the error from loading the other firmware. | 2013-06-27 |
| 20130166894 | COMPUTER SYSTEM AND DETECTING-ALARMING METHOD THEREOF - A computer system and a detecting-alarming method thereof are provided. The computer system includes a device and a basic input/output system (BIOS) unit. The BIOS unit has a current device table. The BIOS unit detects the device of the computer system to obtain a detecting result in a start procedure, and compares the detecting result with the current device table. If the detecting result does not match the current device table, the BIOS unit gives an alarm. | 2013-06-27 |
| 20130166895 | ELECTRONIC DEVICE AND METHOD FOR SETTING BOOT PARAMETERS - A method for setting boot parameters includes: controlling a display to display an input box when detecting a boot setting signal in response to user operation; receiving boot parameters input by the user from the input box; converting the boot parameters input by the user to corresponding ASCII codes, combining the ASCII codes with an identifier identifying the boot parameter to form a data segment, and storing the data segment into the CMOS RAM; reading the ASCII codes from the CMOS RAM when detecting the identifier; setting the boot parameters according to the ASCII codes, and storing the set boot parameters into the BIOS memory. | 2013-06-27 |
| 20130166896 | MANAGEMENT SYSTEM FOR NETWORK CARD - A management system for controlling a communication between a baseboard management controller (BMC) and a basic input/output system (BIOS) coupled to a platform controller hub (PCH), includes a network chip coupled to the BMC, a switch unit configured to control connection between the BIOS and the BMC, and a control unit to output a first control signal or a second control signal to the switch unit. When the control unit outputs the first control signal to the switch unit, the switch unit enables the communication between the BIOS and the network chip. When the control unit outputs the second control signal to the switch unit, the switch unit disables the communication between the BIOS and the network chip. | 2013-06-27 |
| 20130166897 | ELECTRONIC DEVICE SYSTEM AND ELECTRONIC DEVICE - An electronic device system includes a connection device configured to store a plurality of types of boot data and an electronic device, wherein the electronic device includes a connection unit to which the connection device is connected, a selection unit configured to select boot data to be obtained from the connection device connected to the connection unit, an obtaining unit configured to obtain the boot data selected by the selection unit from the connection device, a storage unit configured to store the boot data obtained by the obtaining unit; and a boot processing unit configured to perform processing in relation to booting of the electronic device by using the boot data stored in the storage unit. | 2013-06-27 |
| 20130166898 | System and Method for User Driven Configuration Sets for Energy Efficient Networks - A system and method for user driven configuration sets for energy efficient networks. A customization module can be used to generate energy efficiency control policy customizations based on indications of user preference received through a graphical user interface. These customizations enable abstraction of the energy efficiency control policy customization process from low-level details. | 2013-06-27 |
| 20130166899 | METHOD AND SYSTEM FOR CONTROLLING SYSTEM SETTINGS OF A COMPUTING DEVICE - Methods and devices for controlling system settings of a computing device are described herein. One example embodiment comprises: determining configuration data associated with a software application, wherein the configuration data identifies one or more new system settings to be temporarily enforced on the computing device during an execution of the software application, and wherein the configuration data is digitally signed; and in response to an initiation of the execution of the software application, reconfiguring system settings on the computing device; wherein the reconfiguring comprises verifying at least one digital signature associated with the digitally signed configuration data; wherein if the at least one digital signature associated with the digitally signed configuration data successfully verifies, then the reconfiguring further comprises temporarily enforcing new system settings for the duration of the execution of the software application. | 2013-06-27 |
| 20130166900 | MEDIUM, CONTROL METHOD AND INFORMATION PROCESSING APPARATUS - A computer-readable storage medium stores a control program for an information processing apparatus that includes a process unit capable of executing an application program. The control program causes the information processing apparatus to execute a process. The process includes acquiring control information included in the application program, generating association information associating the application program with response performance information in accordance with the control information acquired in the acquiring, type information associating a combination of control information with a type of the application program, and response performance information associated with a type of the application program, and controlling operating frequency of the process unit in accordance with the response performance information corresponding to the application program when the application program described in the association information is operating. | 2013-06-27 |
| 20130166901 | DISPLAY APPARATUS AND CONTROL METHOD THEREOF - A display apparatus and a control method thereof are provided. The display apparatus includes a connection unit which is connected to an upgrade apparatus; an image processing unit which processes an image signal; a display unit which displays an image based on the processed image signal; a storage unit which stores setting information on a plurality of items related to the display apparatus; and a controller which changes the setting information stored in the storage unit according to the connected upgrade apparatus and which displays the image based on the changed setting information when the upgrade apparatus is connected to the display apparatus. | 2013-06-27 |
| 20130166902 | SIMPLIFIED SMARTCARD PERSONALIZATION METHOD, AND CORRESPONDING DEVICE - The invention relates to a method for personalizing an electronic device using an encryption device adaptable to standard certified apparatuses. The encryption device makes it possible to ensure the confidentiality of the transfer of a secret code from the user to a possible personalization server. | 2013-06-27 |
| 20130166903 | Communication of Information between a Plurality of Network Elements - A communications protocol interface may be configured as being divisible into a core portion and an extensible portion. The extensible portion of the communications protocol interface may be further configured so that each network element can communicate a unique and optimally small subset of actual interoperable data that corresponds to at least a portion of a larger defined data set. A software generator program may be configured to generate a set of extensible source code that operates upon the subset of actual data and that directs the execution of the extensible portion of the communications protocol interface for a particular network element. | 2013-06-27 |
| 20130166904 | MULTIMEDIA PRIVACY ENHANCER - The disclosure relates to a method and a system for protecting private multimedia content which comprises a central server in communication with a client application, characterized in that a user uploads a private multimedia content to the central server and a reference file is generated including a pointer to the private multimedia content and access requirements associated. The reference file is uploaded to multimedia servers and other users of the network download it through a web browser. The client application extracts the pointer from the reference file and sends a request to the central server, where it is checked if the request fulfils the access requirements associated for the private multimedia content requested. | 2013-06-27 |
| 20130166905 | METHODS AND ARRANGEMENTS FOR SECURE COMMUNICATION OVER AN IP NETWORK - The embodiments of the present invention relate to a method in a transmitting node; a method in a receiving node; a transmitting node and a receiving node in an IP network employing Internet security. The receiving node comprises a Receiving Unit, a Processing Unit and a Transmitting Unit. When an IP packet is received, the Processing Unit is adapted to derive a Security Association and a Traffic Class associated with the IP packet. The Processing unit is also adapted to maintain one anti-replay window for each Traffic Class within the Security Association and to determine if a sequence number of the IP packet is within the anti-replay window of the Traffic Class and is not a duplicate of an earlier received packet. If said sequence number is not within the anti-replay window or is a duplicate of an earlier received packet, the packet is dropped. | 2013-06-27 |
| 20130166906 | Methods and Apparatus for Integrating Digital Rights Management (DRM) Systems with Native HTTP Live Streaming - Methods and apparatus for integrating digital rights management (DRM) systems with native HTTP live streaming. Several methods for integrating a DRM system with HTTP live streaming on an operating system (OS) platform are described. In each of these methods, a manifest is delivered to an application on a device; the application then accesses a remote DRM server to obtain a license and one or more keys for the content. The DRM server enforces the rights of the client in regard to the indicated content. The application may modify the manifest to indicate a method for obtaining the key. The application delivers the manifest to the OS, which uses the indicated method (e.g., a URL) to obtain the key. While similar, the methods primarily differ in the manner in which the OS is directed to obtain the key. | 2013-06-27 |
| 20130166907 | Trusted Certificate Authority to Create Certificates Based on Capabilities of Processes - A device certificate binds an identity of a first device to a public key of the first device. The first device comprises a certificate authority service that creates for a process on the first device a process certificate certifying one or more capabilities of the process on the first device. The process certificate is presented to the second device. Upon validating the process certificate using the device certificate, the second device permits the process on the first device to have on the second device one or more of the verified certified capabilities. | 2013-06-27 |
| 20130166908 | SYSTEM AND METHOD OF PROTECTING DATA ON A COMMUNICATION DEVICE - A system and method of protecting data on a communication device are provided. Data received when the communication device is in a first operational state is encrypted using a first cryptographic key and algorithm. When the communication device is in a second operational state, received data is encrypted using a second cryptographic key and algorithm. Received data is stored on the communication device in encrypted form. | 2013-06-27 |
| 20130166909 | Client-Side Player File and Content License Verification - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for verifying a message based on application of a hashing algorithm. In one aspect, a method includes obtaining a license, from a remote server, for a content item to be presented using a player file executed by a multimedia player on a computing device. The license includes an encryption key and an authorization to present the content item using one or more authorized player files. A particular player file is received for use in presenting the content item, and a determination is made whether the particular player file is authorized for use in presenting the content item based on the authorization. The content item is decrypted using the encryption key, and the content item is presented using the particular player file in accordance with the determination. | 2013-06-27 |
| 20130166910 | Revocable Security System and Method for Wireless Access Points - Disclosed are various embodiments of a wireless access point. Embodiments can include establishing a master pre-shared key associated with a wireless network, obtaining a request to establish a connection to the wireless network with a client device and generating a revocable key for the client device that is different from the pre-shared key. | 2013-06-27 |
| 20130166911 | IMPLEMENTATION PROCESS FOR THE USE OF CRYPTOGRAPHIC DATA OF A USER STORED IN A DATA BASE - A security module (“SM”) implements user cryptographic data by means of a user terminal. The cryptographic data is encrypted by a first encryption key established from a secret key from the terminal and the user's authentication element and by a second encryption key specific to the SM. An authentication is performed between the SM and the terminal, based on an asymmetric cryptographic protocol, and, in the event of a positive authentication of the SM and the terminal, an authentication of the SM and the user is performed. In the event of positive authentication between the SM and the terminal and between the SM and the user, the SM obtains the user's cryptographic data, and the terminal calculates the first encryption key and sends the first encryption key to the SM. The user's cryptographic data is decrypted by the SM using the second encryption key and then the first encryption key. | 2013-06-27 |
| 20130166912 | INFORMATION PROCESSING APPARATUS AND METHOD - In order to limit use of content, when a source receives a request for transmitting content from a sink, the source performs an authentication process. When the authentication is successful, the source transmits to the sink key information necessary for decrypting the encryption applied to the content. The sink can receive the content by receiving the key information and by decrypting the encryption applied to the content by using the key information. | 2013-06-27 |
| 20130166913 | Encryption Device and Method - A method is disclosed of encrypting a value input into a user device storing an authentication key, a code generation algorithm, and a value verification code generation algorithm. The method includes the user device processing the authentication key using the code generation algorithm to generate an authentication code; and the user device processing the value using the value verification code generation algorithm to generate a value verification code. The method further includes the user device using the authentication code, the value and the value verification code to construct a message encrypting the value, the message for communicating to an authentication system via a communications network for processing by the authentication system to determine and verify the value, and authenticate the user device and/or the user. A method of communicating a value input into a user device to an authentication system and of verifying the value so communicated as well as an associated user device and authentication system are also disclosed. | 2013-06-27 |
| 20130166914 | METHODS AND SYSTEMS FOR AUTHENTICATING ELECTRONIC MESSAGES USING CLIENT-GENERATED ENCRYPTION KEYS - Systems and methods for authenticating electronic messages using client-generated encryption keys provide for a sender transmitting an original message to a recipient device that includes a digital signature of the original message content and the key used to generate the digital signature. The sender may store an association between the digital signature, the key, and the recipient's address. The recipient may verify the integrity of the original message using the received digital signature and may further verify the authenticity of the message by transmitting a confirmation request message back to the sender that includes the original digital signature and a second digital signature of the confirmation request message using the received key. The sender may either confirm or deny that it sent the original message by determining whether a record exists that associates the digital signature and the key received from the recipient as well as the recipient's address. | 2013-06-27 |
| 20130166915 | SECURE TEXT-TO-SPEECH SYNTHESIS IN PORTABLE ELECTRONIC DEVICES - A method for secure text-to-speech conversion of text using speech or voice synthesis that prevents the originator's voice from being used or distributed inappropriately or in an unauthorized manner is described. Security controls authenticate the sender of the message, and optionally the recipient, and ensure that the message is read in the originator's voice, not the voice of another person. Such controls permit an originator's voiceprint file to be publicly accessible, but limit its use for voice synthesis to text-based content created by the sender, or sent to a trusted recipient. In this way a person can be assured that their voice cannot be used for content they did not write. | 2013-06-27 |
| 20130166916 | DUAL-CHANNEL ELECTRONIC SIGNATURE SYSTEM USING IMAGE CODES AND RELATED COMPUTER PROGRAM PRODUCT - A dual-channel electronic signature system is disclosed, having a signature verification server, a signature requester device, and a hand-held device. The signature requester device calculates a characteristic value related to content of a target document, encodes the characteristic value and a destination message to generate a first graph, and outputs the first graph The hand-held device captures and decodes an image of the first graph to obtain the characteristic value, performs an electronic signature operation on the characteristic value to generate a signature data, encodes the signature data to generate a second graph, and transmits the second graph to a destination network address. If the signature data contained in the second graph passes a verification procedure of the signature verification server, the signature verification server transmits a verification graph corresponding to the second graph to the signature requester device. | 2013-06-27 |
| 20130166917 | AUTHENTICATED CHECKIN VIA PASSIVE NFC - The present disclosure involves a method of verifying user check-ins to a venue. The method includes initializing a digital check-in chain for a venue. The method includes expanding, electronically by a processor, the check-in chain with a plurality of check-in entries that each correspond to a visit to the venue by a respective user. Each check-in entry on the check-in chain is generated in response to one or more preceding check-in entries on the check-in chain. The method includes detecting fraudulent check-in entries in response to a split in the check-in chain. The method includes removing the fraudulent check-in entries from the check-in chain. | 2013-06-27 |
| 20130166918 | Methods for Single Signon (SSO) Using Decentralized Password and Credential Management - A method for single sign-on (SSO) that provides decentralized credential management using end-to-end security. Credential (and other personal user information) management is decentralized in that encryption is performed locally on the user's computer. The user's encrypted credentials may be stored by the login server and/or a plurality of distributed servers/databases (such as a cloud). The login server never has access to the user's credentials or other personal information. When the user wants to use single sign-on, he enters his password into his browser and the browser submits the encrypted/hashed password to the login server for validation. Upon validation, the browser receives the user's encrypted credentials. The credentials are decrypted by the browser and provided to relevant websites to automatically log the user in. | 2013-06-27 |
| 20130166919 | SECURE DATA DELETION IN A DATABASE - A data storage application encrypts one or more data pages using a first initialization vector and one or more encryption keys. In addition, the data storage application encrypts one or more converter pages using a second initialization vector and the encryption key(s). The first initialization vector uses the converter page(s) to encrypt the data page(s). The encrypted data page(s) and the converter page(s) are stored to physical storage. Related apparatus, systems, techniques and articles are also described. | 2013-06-27 |
| 20130166920 | MOBILE DATA VAULT - A portable electronic device is provided. The portable electronic device includes a data interface module that processes files associated with a user, the data interface module receives and validates a password from a user of the portable electronic device before the user is allowed access to files processed by the data interface module, an encryption key formed by the data interface module upon validation of the password, the encryption key further comprising the password, a hard coded private string and a serial number of the portable electronic device and a data storage area that stores files received from the data interface module the stored files are encrypted using the encryption key and where neither the encryption key or the password are stored in an unencrypted format anyplace within the portable electronic device. | 2013-06-27 |
| 20130166921 | PORTING DIGITAL RIGHTS MANAGEMENT SERVICE TO MULTIPLE COMPUTING PLATFORMS - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for porting digital rights management services. In one aspect, a system includes: a hardware processor; one or more memory devices coupled with the hardware processor and effecting an operating system for the hardware processor; and a digital rights management (DRM) component having a DRM adaptor configured to check whether the hardware processor has a hardware-based encryption element, use the hardware-based encryption element if available, and use a software-based encryption element if the hardware-based encryption element is not available, wherein the software-based encryption element includes code compiled from source code for the hardware processor, the source code prepared for different computer platforms. | 2013-06-27 |
| 20130166922 | METHOD AND SYSTEM FOR FRAME BUFFER PROTECTION - When content, such as premium video or audio, is decoded, the content is stored in protected memory segments. Read access to the protected memory segments from a component not in a frame buffer protected (FBP) mode is blocked by a memory controller. The memory controller also blocks components in the FBP mode from writing to unprotected memory segments. The content may be processed by a processing engine operating in the FBP mode and may only be written back to protected memory segments. The memory segment may later be marked as unprotected if the memory segment is no longer needed. If the content is encrypted in protected memory, the encrypting key associated with the memory segment may be removed. If the content is stored in the clear, the protected memory segments are scrubbed before releasing the segments for use as unprotected memory segments. | 2013-06-27 |
| 20130166923 | AUTOMATIC VIRTUALIZATION MEDIUM, AUTOMATIC VIRTUALIZATION METHOD, AND INFORMATION PROCESSING APPARATUS - A computer-readable recording medium having stored therein a program for causing a computer to execute an automatic virtualization process includes creating a copy of information stored in a storage unit in a migration source, storing the created copy in a migration destination apparatus; and encrypting the storage unit in the migration source after storing the copy in the migration destination apparatus. | 2013-06-27 |
| 20130166924 | METHOD FOR PERFORMING SCENARIO DRIVEN VOLTAGE SCALING, AND ASSOCIATED APPARATUS - A method for performing scenario driven voltage scaling of a system includes: monitoring at least one condition of the system, wherein the at least one condition includes user scenario switching of the system; and based upon at least one predetermined table, determining at least one level of at least one voltage for driving the system according to the at least one condition, where the predetermined table includes a plurality of sets of frequency/voltage information respectively corresponding to a plurality of scenarios. An associated apparatus for performing scenario driven voltage scaling of the system is also provided. The apparatus includes at least one tracking module capable of monitoring the at least one condition of the system, and further includes at least one voltage control module capable of determining the at least one level of the at least one voltage. | 2013-06-27 |
| 20130166925 | DEVICE FOR ADJUSTING POWER CONSUMPTION AND METHOD THEREOF - A device and a method for adjusting power consumption are provided. The method is adapted for adjusting power consumption of an external graphic processing unit (GPU) according to different voltage sources and includes following steps: determining whether power to the external GPU is supplied by a first voltage source or a second voltage source according to a comparison result of an input voltage of the external GPU and a default reference voltage. If the input voltage is higher than or equal to the default reference voltage, power to the external GPU is supplied by the first voltage source, and the external GPU is controlled to remain in a normal speed operation status. If the input voltage is lower than the default reference voltage, power to the external GPU is supplied by the second voltage source, and the external GPU is controlled to remain in a low speed operation status. | 2013-06-27 |
| 20130166926 | INFORMATION PROCESSING APPARATUS THAT OFFERS CHANCE OF ELIMINATING HANG-UP STATE, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM - An information processing apparatus which is capable of, when hang-up occurs, eliminating the hang-up state and restoring to a normal state without bothering a user. A first power supply unit supplies power to predetermined devices among a plurality of devices, and a second power supply unit supplies power to the plurality of devices. When startup is done with power being supplied to the predetermined devices, software is started by supplying power to all of the plurality of devices. When the second power supply unit is turned on during the startup, whether or not the software has been normally started is determined. When the software has not been normally started, the software is restarted by carrying out an off-on process in which the plurality of devices are reset, the second power supply unit is turned off, and then the second power supply unit is turned on again. | 2013-06-27 |
| 20130166927 | POWER CONTROL SYSTEM AND METHOD - The power control system controls a first power unit of an environmental control unit of a server and a second power unit of the server, and includes a receiving unit, a control unit, a warning unit, a determination unit, and a timing unit. When a first operating state of the first power unit is a power-off state and a second operating state of the second power unit is a power-on state, the control unit controls the warning unit to provide a warning signal and controls the timing unit to start a timer. When an elapsed time of the timer reaches a predetermined time, the control unit turns off the server. The disclosure further provides a power control method. | 2013-06-27 |
| 20130166928 | UNIVERSAL SERIAL BUS HOST AND POWER MANAGEMENT METHOD THEREOF - A universal serial bus (USB) host includes a power unit and a USB interface unit. The power unit includes a battery and a charging module configured to control the battery. The USB interface unit is configured to interface with a first USB device, and is configured to be controlled based on a remaining amount of power of the battery. The USB interface unit is further configured to maintain a data connection between the USB interface unit and the first USB device when a power supply connection between the USB interface unit and the first USB device is disconnected. | 2013-06-27 |
| 20130166929 | POWER SUPPLY SYSTEM FOR MEMORY MODULES - A power supply system includes a state detection unit, a control unit, a first voltage regulator, a second voltage regulator, a first group of memory slots, and a second group of memory slots. The first voltage regulator supplies power to memory modules connected to the first group of memory slots. The second voltage regulator supplies power to memory modules connected to the second group of memory slots. The state detection unit detects operation states of the memory modules connected to the first and second groups of memory slots. When the state detection unit detects one of the memory modules connected to the first group of memory slots is damaged, the state detection unit outputs a control signal to the control unit. The control unit controls the first voltage regulator not to supply power to the memory modules connected to the first group of memory slots, after receiving the control signal. | 2013-06-27 |
| 20130166930 | REDUCING POWER CONSUMPTION OF MEMORY - Described embodiments provide for a memory system adapted to enable power-gating in one or more memories. Each memory has a corresponding timing characteristic. A monitor in the memory system determines a timing threshold and determines whether the timing characteristic of a memory is at least equal to the timing threshold. If the corresponding timing characteristic is at least equal to the timing threshold, power-gating is applied to the memory. | 2013-06-27 |
| 20130166931 | REDUCING POWER CONSUMPTION OF MEMORY - Described embodiments provide for a memory system which power-gates a memory operating at a first clock. Control logic in the memory system activates, during a rising edge of a second clock, the memory from a sleep mode. The memory is accessed. After a cycle of the first clock, the control logic asserts a power-gating signal, thereby returning the memory to the sleep mode. The frequency of the second clock is less than a frequency of the first clock. | 2013-06-27 |
| 20130166932 | SYSTEMS AND METHODS OF EXITING HIBERNATION IN RESPONSE TO A TRIGGERING EVENT - A method may be performed by an electronic device coupled to a volatile system memory. The method includes entering a hibernation mode of the electronic device, where in the hibernation mode, the volatile system memory is powered off. The method further includes detecting a triggering event and, in response to detecting the triggering event, exiting the hibernation mode. While exiting the hibernation mode, the volatile system memory is powered and a pre-hibernation state of the volatile system memory is restored. | 2013-06-27 |
| 20130166933 | METHOD FOR WAKING UP A PLURALITY OF HIBERNATED MASS STORAGE DEVICES - A method for waking up a plurality of hibernated mass storage devices is disclosed. The method includes receiving a first command from a control circuit for accessing data stored in a plurality of hibernated mass storage devices; dividing the plurality of hibernated mass storage devices into a plurality of mass storage groups; waking up a first mass storage group of the plurality of mass storage groups; and notifying the control circuit to stop sending commands to the remaining hibernated mass storage devices in a period of time. | 2013-06-27 |
| 20130166934 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER AND CONTROLLING METHOD - A controlling method for a memory storage device is provided. The method includes: disposing a rewriteable non-volatile memory module which is operated at a first working voltage in the memory storage device; and detecting whether the first working voltage is lower than a first voltage threshold. The method also includes: detecting whether a circuit component working voltage is lower than a circuit component voltage threshold; when the first working voltage is lower than the first voltage threshold, setting the memory storage device to stop executing commands from a host system and to stop giving commands to the rewriteable non-volatile memory module; and, when the circuit component working voltage is lower than the circuit component voltage threshold, enabling a reset signal to stop receiving and executing commands from the host system. Therefore, the method can effectively improve the stability of the memory storage device. | 2013-06-27 |
| 20130166935 | CONTROL DEVICE AND COMPUTER PROGRAM PRODUCT FOR CONTROLLING METHOD - In an embodiment, provided is a control device that operates: in a second mode where electric power to each of a processing unit and a second storage unit is stopped and is supplied to a first storage unit; and in a first mode where first control information controlling a state of the processing unit is stored in the second storage unit and electric power to each of the processing unit, and the first and second storage unit is stopped. When shifted from the first to second mode, the power supply control unit starts supply of electric power to each of the processing unit and the first storage unit. If the processing unit has been made to be in an operable first state, the processing unit creates and stores second control information in the first storage unit. Then, the power supply control unit stops electric power to the processing unit. | 2013-06-27 |
| 20130166936 | ROBUST MICROPROCESSOR RESET LATCH - A microprocessor reset control operates in one of two reset states and transitions from the first state to the second state when a first signal falls below a first threshold and from the second state to the first state when a second signal exceeds a second threshold. | 2013-06-27 |
| 20130166937 | UNIVERSAL SERIAL BUS HUB - A Universal Serial Bus (USB) hub includes a USB input, a number of USB outputs, a USB controller, a power processing module, and an alarm. The USB controller controls data transmission between a connected USB device connected to the USB output and a computer. The power processing module obtains a power of each USB output and sums the power of all the USB outputs. The power processing module further compares a preset power value with the sum of the power. When the sum of the power is greater than the preset power value, the power processing module outputs a control signal to activate the alarm. | 2013-06-27 |
| 20130166938 | ARBITRATION CIRCUITRY FOR ASYNCHRONOUS MEMORY ACCESSES - A data processing system comprises a processor operating according to a first clock signal and a memory operating according to a second clock signal. The data processing system causes the processor to read data from the memory at least in part in response to a signal from first synchronizing circuitry and a signal from second synchronizing circuitry. The first synchronizing circuitry comprises a first storage element that samples a signal synchronized to the second clock signal in combination with a second storage element that samples an output of the first storage element. The first and second storage elements are triggered by inverse transitions in the first clock signal. The second synchronizing circuitry comprises third and fourth storage elements configured in a similar manner, except that they sample a signal synchronized to the first clock signal and are triggered by inverse transitions in the second clock signal. | 2013-06-27 |
| 20130166939 | APPARATUS, SYSTEM, AND METHOD FOR PROVIDING CLOCK SIGNAL ON DEMAND - Described herein are apparatus, system, and method for providing clock signal on demand. The method comprises determining an indication of clock signal usage in multiple hardware logic units; generating an enable signal according to the indication; and gating or un-gating the clock signal for clock islands of at least a hardware logic unit, of the multiple hardware logic units, in response to a logic level of the enable signal, wherein the clock islands are part of a global clock distribution network and are operable to be enabled or disabled independently. | 2013-06-27 |
| 20130166940 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes an initialization information generation unit configured to operate in response to a first clock and generate first initialization information having a value that is adjusted according to a value of an address signal that corresponds to output data, a domain crossing unit configured to receive the first initialization information in response to the first clock and output the first initialization information as second initialization information by outputting the second initialization information in response to a second clock, and a pulse generation unit configured to operate in response to the second clock and adjust a toggling point in time of a control pulse in response to the second initialization information. | 2013-06-27 |
| 20130166941 | CALCULATION APPARATUS, CALCULATION METHOD, AND RECORDING MEDIUM FOR CALCULATION PROGRAM - A calculation method includes calculating, by a processor, a difference between a first value and a second value, the first value being read from a clock counter that counts pulses of a clock signal having a plurality of types of frequencies, supplied to the processor in response to control command to start processing for an unit to be allocated to the processor, the second value being read from the clock counter in response to control command to stop processing. | 2013-06-27 |
| 20130166942 | UNFUSING A FAILING PART OF AN OPERATOR GRAPH - Techniques for managing a fused processing element are described. Embodiments receive streaming data to be processed by a plurality of processing elements. Additionally, an operator graph of the plurality of processing elements is established. The operator graph defines at least one execution path and wherein at least one of the processing elements of the operator graph is configured to receive data from at least one upstream processing element and transmit data to at least one downstream processing element. Embodiments detect an error condition has been satisfied at a first one of the plurality of processing elements, wherein the first processing element contains a plurality of fused operators. At least one of the plurality of fused operators is selected for removal from the first processing element. Embodiments then remove the selected at least one fused operator from the first processing element. | 2013-06-27 |
| 20130166943 | Method And Apparatus For Energy Efficient Distributed And Elastic Load Balancing - Various embodiments provide a method and apparatus of providing a load balancing configuration that adapts to the overall load and scales the power consumption with the load to improve energy efficiency and scalability. The energy efficient distributed and elastic load balancing architecture includes a collection of multi-tiered servers organized as a tree structure. The handling of incoming service requests is distributed amongst a number of the servers. Each server in the virtual load distribution tree accepts handles incoming service requests based on its own load. Once a predetermined loading on the receiving server has been reached, the receiving server passes the incoming requests to one or more of its children servers. | 2013-06-27 |
| 20130166944 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a memory cell array comprising a normal memory cell and a redundancy memory cell and configured to store data, a data compression unit configured to compress data stored in the memory cell array and generate compression information, and a repair control unit configured to control a repair operation for accessing the redundancy memory cell in response to the compression information. | 2013-06-27 |
| 20130166945 | STORAGE DEVICE - A storage device according to the present invention constructs a RAID structure using a plurality of detachable recording mediums. When a first drive device fails to reproduce data from a recording medium, a transport device transports the recording medium to a second drive device different from the first drive device which failed to reproduce the data, and the second drive device attempts to reproduce the data from the recording medium, the data reproduction from which failed. Owing to this, even when faults of a number exceeding the number of faults correctable by the RAID structure occur, the probability that the data is recovered can be improved. | 2013-06-27 |
| 20130166946 | DISASTER RECOVERY PRODUCTION TAKEOVER - Various embodiments for disaster recovery (DR) production takeover in a computing environment by a processor device are provided. If, for a designated storage system operable in the computing environment, a takeover operation may be executed, and a DR storage system has validly replaced the designated storage system using a replacement process, a withdrawal of a DR mode of operation is performed, and ownership of at least one storage device operable in the computing environment is transferred to the DR storage system. The replacement process authorizes the DR storage system to transfer the ownership while withdrawn from the DR mode of operation. | 2013-06-27 |
| 20130166947 | POWER SYSTEM WITH HOT-SWAP AND THE METHOD THEREOF - The present disclosure discloses a power system with hot-swap with a buck converter. The power system comprises a front stage, a hot-swap stage and a load stage; wherein the hot-swap stage comprises: a buck converter having a switch operate at ON/OFF state to provide a desired output voltage to the load stage with low power loss and optimized thermal design. | 2013-06-27 |
| 20130166948 | UNFUSING A FAILING PART OF AN OPERATOR GRAPH - Techniques for managing a fused processing element are described. Embodiments receive streaming data to be processed by a plurality of processing elements. Additionally, an operator graph of the plurality of processing elements is established. The operator graph defines at least one execution path and wherein at least one of the processing elements of the operator graph is configured to receive data from at least one upstream processing element and transmit data to at least one downstream processing element. Embodiments detect an error condition has been satisfied at a first one of the plurality of processing elements, wherein the first processing element contains a plurality of fused operators. At least one of the plurality of fused operators is selected for removal from the first processing element. Embodiments then remove the selected at least one fused operator from the first processing element. | 2013-06-27 |
| 20130166949 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes, a memory cell array configured to include a plurality of memory cells each having a plurality of logic pages, an error detector configured to detect a recovery target data among the data stored in the memory cell array, and output a logic page information of the recovery target data, a data recoverer configured to recover the recovery target data by using adjustment of a read reference voltage in response to the logic page information of the recovery target data, and a page buffer configured to read the recovery target data output from the memory cell array and write a recovered data output from the data recoverer in the memory cell array. | 2013-06-27 |
| 20130166950 | DATA PROCESSING DEVICE - A data processing device | 2013-06-27 |
| 20130166951 | SYSTEM-DIRECTED CHECKPOINTING IMPLEMENTATION USING A HYPERVISOR LAYER - While system-directed checkpointing can be implemented in various ways, for example by adding checkpointing support in the memory controller or in the operating system in otherwise standard computers, implementation at the hypervisor level enables the necessary state information to be captured efficiently while providing a number of ancillary advantages over those prior-art methods. This disclosure details procedures for realizing those advantages through relatively minor modifications to normal hypervisor operations. Specifically, by capturing state information in a guest-operating-system-specific manner, any guest operating system can be rolled back independently and resumed without losing either program or input/output (I/O) continuity and without affecting the operation of the other operating systems or their associated applications supported by the same hypervisor. Similarly, by managing I/O queues as described herein, rollback can be accomplished without requiring I/O operations to be repeated and I/O device failures can be circumvented without losing any I/O data in the process. | 2013-06-27 |
| 20130166952 | DATA PROCESSING APPARATUS WITH AN EXECUTION PIPELINE AND ERROR RECOVERY UNIT AND METHOD OF OPERATING THE DATA PROCESSING APPARATUS - A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state. | 2013-06-27 |
| 20130166953 | SYSTEM AND METHOD OF PROCESSING FAILURE - A system includes a first obtaining unit that, when a failure occurs in the system, obtains via a first route failure information held by devices connected with a first processing unit and a second processing unit, respectively through a first route and a second route, a second obtaining unit that obtains the failure information through the second route when the failure information is not able to be obtained by the first obtaining unit, a second failure location estimation unit that estimates a failure causing location based on the failure information obtained by the second obtaining unit, an identification unit that identifies a subject using the failure location estimated by the second failure location estimation unit, and a termination unit that terminates the subject identified by the identification unit. | 2013-06-27 |
| 20130166954 | TEST APPARATUS FOR TESTING SIGNAL TRANSMISSION OF MOTHERBOARD - A test apparatus for testing peripheral component interconnect express (PCIe) signals transmission of a motherboard includes a printed circuit board including an edge connector, a number of first switches having a same number with the type of the PCIe signals to be test, an encoder, and a microprocessor. The first switches are used to select a type selection signal. The encoder converts signals outputted from the first switches to binary data. The microprocessor outputs clock signals to a PCIe controller according to the binary data to make the PCIe controller transmit the PCIe signal to the PCIe slot. | 2013-06-27 |
| 20130166955 | KEYBOARD AUTOMATIC TEST METHOD AND SYSTEM USING THE SAME - A keyboard automatic test method is provided. A keyboard test unit first outputs a key test command to a keyboard controller. The key test command represents a trigger element of a keyboard is triggered. The keyboard controller generates a corresponding code corresponding to the trigger element. The keyboard test unit then determines whether a relationship between the corresponding code and the trigger element is correct. | 2013-06-27 |
| 20130166956 | DIAGNOSTIC CARD FOR RECORDING REBOOT TIMES OF SERVERS - A diagnostic card includes a circuit board, a connector, a controller, and a first display. The connector is coupled to a low pin count (LPC) to receive a reset signal outputted by a basic input output system as a server reboots. The controller is configured to record the total number of reboot times of the server and displays the total number of reboot times on the first display area. | 2013-06-27 |
| 20130166957 | SYSTEM ERROR ANALYSIS METHOD AND THE DEVICE USING THE SAME - A system error analysis device which includes a top unit and a storage unit coupled to the top module is mentioned. The storage unit is configured to store each of the input data, each of the output data and each of the bus data transmitted by the top unit. When receiving an interrupting signal, the system error analysis device outputs the input data, the output data and the bus data stored as soon as the interrupting signal is received and the input data, the output data and the bus data stored before the receiving of the interrupting signal. Accordingly, by comparing and analyzing the data output by system error analysis device, the system employing the system error analysis device is able to obtain the reason of the generation of the interrupting signal. | 2013-06-27 |
| 20130166958 | SOFTWARE BURNING SYSTEM AND BURNING CONTROL METHOD - A burning control method for burning software to at least one chip is provided, the method includes: controlling the at least one chip to enter a download mode when the at least one chip is startup; initializing the at least one chip when the chip enters the download mode; executing a burning process to burn software into the at least one chip when the chip is initialized; controlling the at least one chip to enter the test mode when the burning process is completed; testing whether the software has been burned into the at least one chip successfully when the at least one chip is in the test mode. | 2013-06-27 |
| 20130166959 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD OF THE SAME - A semiconductor memory device includes a normal data storage block configured to store a normal data, a setup data storage block for storing a setup data including at least two duplicate data, an access unit configured to access the normal data of the normal data storage block or the setup data of the setup data storage block, a first transfer unit configured to transfer the setup data accessed by the access unit, a data decision unit configured to determine a correct data based on the setup data transferred by the first transfer unit, a second transfer unit configured to transfer the normal data accessed by the access unit, and a data output unit configured to output the setup data transferred by the first transfer unit or the normal data transferred by the second transfer unit to the outside of the semiconductor memory device in response to a control signal. | 2013-06-27 |
| 20130166960 | Byte By Byte Received Data Integrity Check - A method and an apparatus for testing a network. A source port unit may generate a packet including a payload, the payload comprising a content identifier and content data in accordance with the content identifier, and transmit the packet via the network. A destination port unit may receive the packet and extract the content identifier and received content data from the received packet. The destination port unit may obtain expected content data in accordance with the extracted content identifier and compare the expected content data and the received content data. | 2013-06-27 |
| 20130166961 | DETECTING AND RESOLVING ERRORS WITHIN AN APPLICATION - Techniques for managing errors within an application are provided. Embodiments monitor errors occurring in each of a plurality of portions of the application while the application is executing. An error occurring in a first one of the plurality of portions of the application is detected. Additionally, upon detecting the error occurring in the first portion, embodiments determine whether to prevent subsequent executions of the first portion of the application. | 2013-06-27 |
| 20130166962 | DETECTING AND RESOLVING ERRORS WITHIN AN APPLICATION - Techniques for managing errors within an application are provided. Embodiments monitor errors occurring in each of a plurality of portions of the application while the application is executing. An error occurring in a first one of the plurality of portions of the application is detected. Additionally, upon detecting the error occurring in the first portion, embodiments determine whether to prevent subsequent executions of the first portion of the application. | 2013-06-27 |
| 20130166963 | PROCESS INTEGRATION ALERTING FOR BUSINESS PROCESS MANAGEMENT - A computer implemented method may include identifying one or more business process runtime events received at an events queue of a process integration runtime component. One or more errors associated with the business process runtime events may be identified. The one or more errors may be evaluated based, at least in part, on one or more rules associated with the business process runtime event and configuration information associated with the process integration runtime component. The one or more rules may be associated with the business process runtime event and configuration information associated with the process integration runtime component having the same format. An alert for the one or more errors associated with the business process runtime event can be stored. | 2013-06-27 |
| 20130166964 | GROUPING RELATED ERRORS IN A DISTRIBUTED COMPUTING ENVIRONMENT - Techniques are described for detecting the occurrence of error scenarios occurring across a plurality of nodes. Embodiments retrieve a plurality of error scenario profiles. Each of the error scenario profiles specifies prerequisite criteria, the prerequisite criteria including at least one of (i) one or more errors and (ii) one or more conditions. The plurality of nodes is monitored to detect errors occurring on nodes within the plurality of nodes. Embodiments then detect the occurrence of an error scenario, when at least a portion the monitored errors match the prerequisite criteria specified in a first one of the error profiles and when the one or more conditions specified in the first error profile are satisfied. | 2013-06-27 |
| 20130166965 | METHOD AND SYSTEM FOR PROVIDING REMOTE MONITORING AND CONTROL OF A BATHING SYSTEM - A network-enabled controller for a bathing unit is provided. The controller includes a network interface and a memory storing operational setting information associated with the bathing unit. Through the network interface, the controller connects to a home network and registers and maintains an active communication link with a gateway accessed over a network external to the home network. In response to receipt of a status request originating from a remote client, the controller processes the status request and selectively transmits operational setting information stored in the memory to the remote client. A system for facilitating remote control and monitoring of network-enabled controllers for bathing units is also provided. The system comprises a remote control client executed on a personal computing device, an Internet-based server implementing a gateway and a plurality of controllers, wherein respective active communication links are maintained between the server and the plurality of registered controllers. | 2013-06-27 |
| 20130166966 | APPARATUS AND METHOD FOR TESTING CONFORMANCE OF SERVICE CHOREOGRAPHY - An apparatus and method for testing conformance of service choreography are provided. The apparatus for testing conformance of service choreography analyzes an architecture and an operation between web services cooperating on a distributed network to test conformance of a choreography application into which the web services are combined, on the basis of a service choreography specification. | 2013-06-27 |
| 20130166967 | GROUPING RELATED ERRORS IN A DISTRIBUTED COMPUTING ENVIRONMENT - Techniques are described for detecting the occurrence of error scenarios occurring across a plurality of nodes. Embodiments retrieve a plurality of error scenario profiles. Each of the error scenario profiles specifies prerequisite criteria, the prerequisite criteria including at least one of (i) one or more errors and (ii) one or more conditions. The plurality of nodes is monitored to detect errors occurring on nodes within the plurality of nodes. Embodiments then detect the occurrence of an error scenario, when at least a portion the monitored errors match the prerequisite criteria specified in a first one of the error profiles and when the one or more conditions specified in the first error profile are satisfied. | 2013-06-27 |
| 20130166968 | REDUCED FOOTPRINT CORE FILES IN STORAGE CONSTRAINED ENVIRONMENTS - A method for creating diagnostic files that includes receiving an error notification indicating that an error has occurred in a particular system section of a system that has a plurality of system sections. The error notification includes information about the error. A diagnostic file that includes a summarized error report of the particular system section is created based on the information included in the error notification. The diagnostic file is saved. | 2013-06-27 |
| 20130166969 | METHOD AND SYSTEM FOR ENHANCED HELP INSTRUCTIONS - A computerized method and system for providing enhanced help messages for equipment operation is described herein. A device having a processor automatically detects an error condition in the device, and determines that the error condition requires operator action. An appropriate message is selected that indicates a required operator action corresponding to the error condition. The message is configured to include a scannable barcode. The scannable barcode includes a website link to a website having more detailed information to assist an operator in performing the operator action. The message is displayed on a screen so that the operator can scan the barcode with his mobile device, and see the more detailed information on how to perform the required operator action. Alternatively, the message is configured as radio frequency data to be transmitted by the equipment using near field communication (NFC) technology to a mobile device having an NFC receiver. | 2013-06-27 |
| 20130166970 | BROADCASTING RECEPTION APPARATUS AND METHOD OF CONTROLLING CABLE CARD - A broadcasting reception apparatus and method of controlling a cable card are provided. The broadcasting reception apparatus includes an interface unit configured to mount a cable card, a cable card configured to be mounted in the interface unit and to process broadcasting service information, and a control unit configured to periodically receive a protocol message according to a preset specification from the cable card when the cable card is mounted in the interface unit. The control unit may transmit to the cable card a request signal requesting transmission of the protocol message if the protocol message is not received at a preset first critical time, and initialize the cable card if the protocol message is not received at a second critical time after the request signal is transmitted to the cable card. Therefore, recovery from a failure of the cable card is rapidly performed. | 2013-06-27 |
| 20130166971 | Method And Apparatus For Encoding Channel Quality Indicator And Precoding Control Information Bits - A method and apparatus for encoding channel quality indicator (CQI) and precoding control information (PCI) bits are disclosed. Each of the input bits, such as CQI bits and/or PCI bits, has a particular significance. The input bits are encoded with a linear block coding. The input bits are provided with an unequal error protection based on the significance of each input bit. The input bits may be duplicated based on the significance of each input bit and equal protection coding may be performed. A generator matrix for the encoding may be generated by elementary operation of conventional basis sequences to provide more protection to a most significant bit (MSB). | 2013-06-27 |
| 20130166972 | Apparatus and Methods of Programming Memory Cells using Adjustable Charge State Level(s) - Apparatus and methods are disclosed, including a method of programming involving determining an error rate for the memory cells, and programming the memory cells using a charge state level for a charge state that is based at least in part on the determined error rate. | 2013-06-27 |
| 20130166973 | STORAGE-MEDIUM DIAGNOSIS DEVICE, STORAGE-MEDIUM DIAGNOSIS METHOD - A storage-medium diagnosis includes a storage unit that stores therein respective diagnosis results of subregions of a storage region of a storage medium; a higher-access executing unit that accesses a region corresponding to access request from a higher-level device, and stores a result of the access as a diagnosis result in the storage unit; a diagnosis-region identifying unit that identifies a diagnosis region to be diagnosed next on the basis of the respective diagnosis results of the subregions stored in the storage unit; and a diagnosis executing unit that accesses and diagnoses the diagnosis region identified by the diagnosis-region identifying unit, and stores a result of the diagnosis in the storage unit. The storage-medium diagnosis can reduce the time used for diagnosis of the storage medium and suppress degradation in performance even during operation. | 2013-06-27 |
| 20130166974 | METHODS AND SYSTEMS FOR LOGIC DEVICE DEFECT TOLERANT REDUNDANCY - Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the logic devices is defective based upon its respective defect indicator. The scheduler intentionally omits sending workloads to the disabled logic units, and thus enables the device to be functional albeit at a lower performance or in a differently performing product. | 2013-06-27 |
