| 26th week of 2013 patent applcation highlights part 48 |
| Patent application number | Title | Published |
|---|
| 20130164875 | BUFFER LAYERS FOR ORGANIC ELECTROLUMINESCENT DEVICES AND METHODS OF MANUFACTURE AND USE - Organic electroluminescent device can be formed with multiple layers including an electrode, an emission layer, and a buffer layer. The emission layer includes a light emitting material. The buffer layer is disposed between and in electrical communication with the electrode and the emission layer and includes a triarylamine hole transport material and an electron acceptor material. The buffer layer optionally includes one or more of a) a polymeric binder, b) a color converting material, and c) light scattering particles. The buffer layer can also be formed using a polymeric hole transport material having a plurality of triarylamine moieties. | 2013-06-27 |
| 20130164876 | METHOD OF MANUFACTURING SOLAR CELL MODULE - A method includes a first bonding step of bonding a first main surface of a first solar cell and one side portion of a first wiring member to each other in such a way that the first main surface of the first solar cell and the one side portion are heated and pressed against each other by heated first and second tools in a state where the first main surface of the first solar cell and the one side portion face each other with the resin adhesive interposed therebetween. The first bonding step is performed with the first tool disposed in such a way that, in an extending direction of the first wiring member, both end portions of the first tool are located outside both ends of a portion of the first wiring member, the portion facing the first solar cell with the resin adhesive interposed therebetween. | 2013-06-27 |
| 20130164877 | ISOLATION STRUCTURES FOR GLOBAL SHUTTER IMAGER PIXEL, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region adjacent to the gate. The pixel sensor cell further includes an isolation region located below a channel region of the gate and about the photosensitive region, which prevents electrons collected in the photosensitive region to drift to the diffusion region. | 2013-06-27 |
| 20130164878 | HYBRID POLYSILICON HETEROJUNCTION BACK CONTACT CELL - A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells. | 2013-06-27 |
| 20130164879 | HYBRID POLYSILICON HETEROJUNCTION BACK CONTACT CELL - A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells. | 2013-06-27 |
| 20130164880 | METHOD FOR PRODUCING PHOTOVOLTAIC DEVICE AND PHOTOVOLTAIC DEVICE - A method for producing a photovoltaic device that includes spherical photovoltaic elements and a support with a large number of recesses for receiving the elements one by one and to the photovoltaic device. Each of the spherical photovoltaic elements includes a spherical first semiconductor and a second semiconductor layer covering the first semiconductor. A conductive adhesive is applied to the bottoms of the recesses of the support serving as a second conductor layer. The elements are disposed in the bottoms of the recesses with the conductive adhesive applied thereto, to fix the elements to the support and electrically connect their second semiconductor layers to the support. An electrical insulator layer, which has through-holes serving as conductive paths, is bonded to the backside of the support, and a first conductor layer, which interconnects the electrodes of the first semiconductors of the respective elements, is formed thereon. | 2013-06-27 |
| 20130164881 | METHOD FOR PRODUCING FULLY AQUEOUS PHASE-SYNTHESIZED NANOCRYSTALS/CONDUCTING POLYMER HYRID SOLAR CELL - Provided is a method for producing a highly efficient organic/inorganic hybrid solar cell using fully aqueous phase-synthesized semiconductor nanocrystals and conducting polymer. The method mainly includes three steps: synthesizing nanocrystals in an aqueous phase, synthesizing a conjugated polymer precursor in an aqueous phase, and producing a device of solar cell. The nanocrystal material required for producing a solar cell by the method is widely available, diversified and size-controlled, and the used conjugated polymer has regulated molecular structure and molecular weight, which contributes to increase the absorption of sunlight. The processing of cell device can be performed at room temperature in air, and has advantages of no pollution, short processing period, and low cost. A method for producing an organic/inorganic hybrid solar cell is developed, which succeeds in introducing the high quality nanocrystals synthesized in an aqueous phase and is an eco-friendly and pollution-free technology for producing a solar cell. | 2013-06-27 |
| 20130164882 | TRANSPARENT CONDUCTING LAYER FOR SOLAR CELL APPLICATIONS - Disclosed is a method which includes forming a bottom metallic electrode on an insulating substrate; forming a semiconductor junction on the metallic electrode; forming a transparent conducting overlayer in contact with the semiconductor junction; and forming a metallic layer in contact with the transparent conducting overlayer, wherein the metallic layer is formed by a plating process. The plating process may be an electroplating process or an electroless plating process. The transparent conducting overlayer may be carbon nanotubes or graphene. The semiconductor junction may be a p-i-n semiconductor junction, a p-n semiconductor junction, an n-p semiconductor junction or an n-i-p semiconductor junction. | 2013-06-27 |
| 20130164883 | LASER ANNEALING APPLICATIONS IN HIGH-EFFICIENCY SOLAR CELLS - Various laser processing schemes are disclosed for producing various types of hetero-junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero-junction solar cells. Laser ablation techniques are disclosed that leave the underlying silicon substantially undamaged. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, or other cleavage techniques such as ion implantation and heating, that are either planar or textured/three-dimensional. These techniques are highly suited to thin crystalline semiconductor, including thin crystalline silicon films. | 2013-06-27 |
| 20130164884 | ASSEMBLY OF QUASICRYSTALLINE PHOTONIC HETEROSTRUCTURES - A method and system for assembling a quasicrystalline heterostructure. A plurality of particles is provided with desirable predetermined character. The particles are suspended in a medium, and holographic optical traps are used to position the particles in a way to achieve an arrangement which provides a desired property. | 2013-06-27 |
| 20130164885 | Absorbers For High-Efficiency Thin-Film PV - Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for depositing a Cu-rich precursor layer followed by a Cu-poor precursor layer. Methods are described for depositing a Cu-poor precursor layer followed by a Cu-rich precursor layer. Methods are described for depositing a Cu-poor precursor layer followed by a Cu-poor precursor layer. Methods are described for depositing a Cu-rich precursor layer followed by removing excess Cu-chalcogenide using a wet etch, followed by a Cu-poor precursor layer. Methods are described for utilizing Ag to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer. | 2013-06-27 |
| 20130164886 | Absorbers For High-Efficiency Thin-Film PV - Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer. Methods are described for forming a Cu—In—Ga layer followed by partial or full selenization. This results in a higher Ga concentration at the back interface. The substrate is then exposed to an aluminum CVD precursor while the substrate is still in the selenization equipment to deposit a thin Al layer. The substrate is then exposed to a Se source to fully convert the absorber layer. This results in a higher Al concentration at the front of the absorber. | 2013-06-27 |
| 20130164887 | METHOD FOR MANUFACTURING A SOLAR CELL - In a method for manufacturing a solar cell where the solar cell includes a dopant layer having a first portion of a first resistance and a second portion of a second resistance lower than the first resistance, the method includes ion-implanting a dopant into the semiconductor substrate to form the dopant layer; firstly activating by heating the second portion and activating the dopant at the second portion; and secondly activating by heating the first portion and the second portion and activating the dopant at the first portion and the second portion. | 2013-06-27 |
| 20130164888 | Graphene Solar Cell - A solar cell includes a semiconductor portion, a graphene layer disposed on a first surface of the semiconductor portion, and a first conductive layer patterned on the graphene layer, the first conductive layer including at least one bus bar portion and a plurality of fingers extending from the at least one bus bar portion. | 2013-06-27 |
| 20130164889 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device, a first semiconductor element having a first terminal is embedded in a resin layer such that terminals thereof are exposed through a first surface of the resin layer. A wiring layer is formed in the first surface of the resin layer. A second semiconductor element includes second and third terminals. Regardless of the relationship between the plane size of the first semiconductor element and that of the second semiconductor element, the second terminal of the second semiconductor element is connected to the first terminal of the first semiconductor element exposed through the first surface of the resin layer, and the third terminal of the second semiconductor element is connected to the wiring layer formed in the resin layer. | 2013-06-27 |
| 20130164890 | METHOD FOR FABRICATING FINFET WITH MERGED FINS AND VERTICAL SILICIDE - A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region. | 2013-06-27 |
| 20130164891 | HIGH DENSITY BUTTED JUNCTION CMOS INVERTER, AND MAKING AND LAYOUT OF SAME - A method of manufacturing a butted junction CMOS inverter with asymmetric complementary FETS on an SOI substrate may include: forming a butted junction that physically contacts a first drain region of a first FET and a second drain region of a second complementary FET on the SOI substrate, where the butted junction is disposed medially to a first channel region of the first FET and a second channel region of the second complementary FET; implanting a first halo implant on only a source side of the first channel region, to form a first asymmetric FET; and forming a second halo implant on only a source side of the second channel region of the second complementary FET, to form a second asymmetric complementary FET. | 2013-06-27 |
| 20130164892 | THIN-FILM TRANSISTOR DEVICE MANUFACTURING METHOD, THIN-FILM TRANSISTOR DEVICE, AND DISPLAY DEVICE - A thin-film transistor device manufacturing method and others according to the present disclosure includes: forming a plurality of gate electrodes above a substrate; forming a gate insulating layer on the plurality of gate electrodes; forming an amorphous silicon layer on the gate insulating layer; forming a buffer layer and a light absorbing layer above the amorphous silicon layer; forming a crystalline silicon layer by crystallizing the amorphous silicon layer with heat generated by heating the light absorbing layer using a red or near infrared laser beam; and forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes, and film thicknesses of the gate insulating layer, the amorphous silicon layer, the buffer layer, and the light absorbing layer satisfy predetermined expressions. | 2013-06-27 |
| 20130164893 | FABRICATION OF FLOATING GUARD RINGS USING SELECTIVE REGROWTH - A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing a n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming a growth mask coupled to the n-type GaN epitaxial layer. The method further includes patterning the growth mask to expose at least a portion of the n-type GaN epitaxial layer, and forming at least one p-type GaN epitaxial structure coupled to the at least a portion of the n-type GaN epitaxial layer. The at least one p-type GaN epitaxial structure comprises at least one portion of an edge termination structure. The method additionally includes forming a first metal structure electrically coupled to the second surface of the n-type GaN substrate. | 2013-06-27 |
| 20130164894 | METHOD OF FABRICATING A THREE-DIMENTIONAL SEMICONDUCTOR MEMORY DEVICE - A method of fabricating a semiconductor memory device includes alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate, forming an active pattern penetrating the sacrificial layers and the insulating layers, continuously patterning the insulating layers and the sacrificial layers to form a trench, removing the sacrificial layers exposed in the trench to form recess regions exposing a sidewall of the active pattern, forming an information storage layer on the substrate, forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer, and performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other. | 2013-06-27 |
| 20130164895 | Trench-Gated Power Devices with Two Types of Trenches and Reliable Polycidation - Methods and systems for power semiconductor devices and structures with silicide cladding on both gates and field plates. Sidewall spacers, e.g. of silicon nitride, avoid lateral shorts or leakage between the gate silicide and the source region. A source metallization makes lateral contact to the shallow n++ source, and also makes contact to the field plate silicide and the p+ body contact region. | 2013-06-27 |
| 20130164896 | VOLTAGE CONVERTER AND SYSTEMS INCLUDING SAME - A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. | 2013-06-27 |
| 20130164897 | TRANSISTORS HAVING ARGON GATE IMPLANTS AND METHODS OF FORMING THE SAME - Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided. | 2013-06-27 |
| 20130164898 | CARRIER MOBILITY IN SURFACE-CHANNEL TRANSISTORS, APPARATUS MADE THEREWITH, AND SYSTEM CONTAINING SAME - A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers. | 2013-06-27 |
| 20130164899 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly reliable semiconductor device in which a transistor including an oxide semiconductor film has stable electric characteristics is manufactured. In the semiconductor device which includes an inverted-staggered transistor having a bottom-gate structure and being provided over a substrate having an insulating surface, at least a first gate insulating film and a second gate insulating film are provided between a gate electrode layer and an oxide semiconductor film, and heat treatment is performed at a temperature of 450° C. or higher, preferably 650° C. or higher, and then the oxide semiconductor film is formed. By the heat treatment at a temperature of 450° C. or higher before the formation of the oxide semiconductor film, diffusion of hydrogen elements into the oxide semiconductor film, which causes degradation or variations in electric characteristics of the transistor, can be reduced, so that the transistor can have stable electric characteristics. | 2013-06-27 |
| 20130164900 | GATED CO-PLANAR POLY-SILICON THIN FILM DIODE - A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel region remaining undoped, depositing a layer of gate dielectric on the layer of material, arranging a gate adjacent the channel region on the gate dielectric, and electrically connecting a voltage source to the gate. | 2013-06-27 |
| 20130164901 | Method of Making Capacitor With a Sealing Liner and Semiconductor Device Comprising Same - Generally, the subject matter disclosed herein relates to various methods of making a capacitor with a sealing liner and a semiconductor device including such a capacitor. In one example, the method includes forming a layer of insulating material, forming a capacitor opening in the layer of insulating material, forming a sealing liner on the sidewalls of the capacitor opening and forming a first metal layer in the capacitor opening and on the sealing liner by performing a process using a precursor having a minimum particle size, wherein the sealing liner is made of a material having an opening size that is less than the minimum particle size of the precursor. | 2013-06-27 |
| 20130164902 | Methods Of Forming Capacitors - A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric. | 2013-06-27 |
| 20130164903 | METHOD FOR FABRICATING CAPACITOR OF SEMICONDUCTOR DEVICE - A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer. | 2013-06-27 |
| 20130164904 | INDUCTOR STRUCTURES FOR INTEGRATED CIRCUIT DEVICES - An IC device ( | 2013-06-27 |
| 20130164905 | 3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY - The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided. | 2013-06-27 |
| 20130164906 | FULL WAFER PROCESSING BY MULTIPLE PASSES THROUGH A COMBINATORIAL REACTOR - Overlapping combinatorial processing can offer more processed regions, better particle performance and simpler process equipment. In overlapping combinatorial processing, one or more regions are processed in series with some degrees of overlapping between regions. In some embodiments, overlapping combinatorial processing can be used in conjunction with non-overlapping combinatorial processing and non-combinatorial processing to develop and investigate materials and processes for device processing and manufacturing. | 2013-06-27 |
| 20130164907 | METHODS OF FORMING A THIN FILM AND METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING USING THE SAME - Provided are methods of forming a thin film and methods of fabricating a semiconductor device including the same. The thin film forming methods may include supplying an organic silicon source to form a silicon seed layer on a lower layer, the silicon seed layer including silicon seed particles adsorbed on the lower layer, and supplying an inorganic silicon source to deposit a silicon film on the lower layer adsorbed with the silicon atoms. | 2013-06-27 |
| 20130164908 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE - A manufacturing method for a TFT array substrate includes providing a substrate; defining a plurality of normal alignment regions and a plurality of abnormal alignment regions on the substrate; forming an insulating layer and a transparent conductive layer on the substrate; performing a patterning process to at least one of the insulating layer and the transparent conductive layer to form a plurality of alignment structures in each abnormal alignment region; forming an alignment material layer on the substrate, the alignment material layer having a plurality of first alignment slits formed along the alignment structures in each of the abnormal alignment regions; and performing a rubbing alignment process to form a plurality of second alignment slits on the alignment material layer in each of the normal alignment regions along a alignment direction. | 2013-06-27 |
| 20130164909 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an insulating isolation portion in a groove of a substrate, forming a projection portion in which an upper portion of the insulating isolation portion projects from a principal surface of the substrate, forming a sidewall spacer covering a side surface of the projection portion and part of the principal surface of the substrate along the side surface of the projection portion, and forming a first trench in the substrate by etching the substrate using the sidewall spacer as a mask. | 2013-06-27 |
| 20130164910 | DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE - Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes. | 2013-06-27 |
| 20130164911 | PLASMA PROCESSING METHOD - The present invention provides a plasma processing method in which sideetching and microloading can be suppressed in a plasma processing method of forming trenches with a mask having a minimum opening width of 20 nm or less. The plasma processing method of the present invention is characterized by including the steps of forming trenches by plasma etching, forming a nitride film on sidewalls of trenches using plasma, and forming an oxide film on sidewalls and bottom surfaces of the trenches using plasma. | 2013-06-27 |
| 20130164912 | REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING - Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier. | 2013-06-27 |
| 20130164913 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method, an insulating layer is formed on a front surface of a semiconductor substrate. Trenches are formed in the substrate by using the insulating layer as a mask so that a first portion of the insulating layer is located on the front surface between the trenches and that a second portion of the insulating layer is located on the front surface at a position other than between the trenches. The entire first portion is removed, and the second portion around an opening of each trench is removed. The trenches are filled with an epitaxial layer by epitaxially growing the epitaxial layer over the front surface side. The front surface side is polished by using the remaining second portion as a polishing stopper. | 2013-06-27 |
| 20130164914 | LASER PROCESSING METHOD FOR WAFER - A wafer has a device area where a plurality of devices are formed, and a peripheral marginal area surrounding the device area. These devices are formed on the front side of the wafer so as to be partitioned by a plurality of division lines. A modified layer is formed by applying a laser beam along the division lines with the focal point of the laser beam set inside the wafer, thereby forming a modified layer as a division start point inside the wafer along each division line. The wafer is transported to a position where the next step is to be performed. In the modified layer forming step, the modified layer is not formed in the peripheral marginal area of the wafer to thereby form a reinforcing portion in the peripheral marginal area. Accordingly, breakage of the wafer from the modified layer in the transporting step can be prevented. | 2013-06-27 |
| 20130164915 | METHOD FOR FABRICATING POWER SEMICONDUCTOR DEVICE WITH SUPER JUNCTION STRUCTURE - A method for fabricating a power semiconductor device is provided. A substrate with a first conductivity type is prepared. A semiconductor layer with a second conductivity type is formed on the substrate. A hard mask pattern having at least an opening is formed on the semiconductor layer. A first trench etching is performed to form a first recess in the semiconductor layer via the opening. A first ion implantation is performed to vertically implant dopants into the bottom of the first recess via the opening, thereby forming a first doping region. A second trench etching is performed to etch through the first doping region, thereby forming a second recess. | 2013-06-27 |
| 20130164916 | ABSORBERS FOR HIGH EFFICIENCY THIN-FILM PV - Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for utilizing Ag to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing at least one of Na, Mg, K, or Ca to increase the band gap at the front surface of the absorber layer. | 2013-06-27 |
| 20130164917 | Absorbers For High-Efficiency Thin-Film PV - Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for utilizing Ag to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing metal chalcogenide layers to impact the band gap and the morphology of the absorber layer. | 2013-06-27 |
| 20130164918 | Absorbers For High-Efficiency Thin-Film PV - Methods are described for forming CZTS absorber layers in TFPV devices with graded compositions and graded bandgaps. Methods are described for utilizing at least one of Zn, Ge, or Ag to alter the bandgap within the absorber layer. Methods are described for utilizing Te, S, Se, O, Cd, Hg, or Sn to alter the bandgap within the absorber layer. Methods are described for utilizing either a 2-step process or a 4-step process to alter the bandgap within the absorber layer. | 2013-06-27 |
| 20130164919 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING GATE INSULATING LAYERS - A method of fabricating a semiconductor device may include forming active and field regions in a substrate; forming a gate trench in which the active and field regions are exposed; forming a gate insulating layer on a surface of the exposed active region, wherein forming the gate insulating layer includes forming a first gate oxide layer by primarily oxidizing the surface of the active region, and forming a second gate oxide layer between the surface of the active region and the first gate oxide layer by secondarily oxidizing the surface of the active region; conformally forming a gate barrier layer on the gate insulating layer and the exposed field region; forming a gate electrode layer on the gate barrier layer; and forming a gate capping layer in contact with the gate insulating layer, the gate barrier layer, and the gate electrode layer in the gate trench. | 2013-06-27 |
| 20130164920 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film are reduced and electric characteristics of a transistor including the oxide semiconductor film are improved. Further, a highly reliable semiconductor device including the transistor including the oxide semiconductor film is provided. In the transistor including the oxide semiconductor film, at least one insulating film in contact with the oxide semiconductor film contains excess oxygen. By the excess oxygen included in the insulating film in contact with the oxide semiconductor film, oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced. Note that the insulating film including the excess oxygen has a profile of the excess oxygen concentration having two or more local maximum values in the depth direction. | 2013-06-27 |
| 20130164921 | HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided. | 2013-06-27 |
| 20130164922 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - Methods of manufacturing a semiconductor device are provided. The method may include forming an etch target layer on a substrate, forming a carbon layer doped with boron on the etch target layer, a top end portion of the carbon layer having a different boron concentration from a bottom end portion of the carbon layer, patterning the carbon layer to form at least one opening exposing the etch target layer, and etching the exposed etch target layer using the carbon layer as an etch mask. | 2013-06-27 |
| 20130164923 | LOW VOLTAGE PNPN PROTECTION DEVICE - A low voltage protection device that includes a silicon substrate comprises an inner layer of a first dopant type. The device also includes a first outer layer of a second dopant type disposed adjacent a first surface of the inner layer and a second outer layer of the second dopant type disposed adjacent a second surface of the inner layer opposite the first surface. The device further includes a first mesa region disposed in a peripheral region of a first side of the low voltage protection device. The first mesa region includes a first area that includes a peripheral portion of a cathode of the low voltage protection device, the cathode formed by diffusing a high concentration of dopant species of the first type on a first surface of the silicon substrate, and a second area comprising a high concentration of diffused dopant species of the second type. | 2013-06-27 |
| 20130164924 | Structure and Method for Fabricating Fin Devices - A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes. | 2013-06-27 |
| 20130164925 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory device comprises forming a plurality of gate lines on a semiconductor substrate, forming an insulating layer on the gate lines, and performing a cleaning process using a surfactant-free cleaning solution having a viscosity of lower than 2 cP and an acidity of lower than 3 pH to remove residue from the surface of the insulating layer. | 2013-06-27 |
| 20130164926 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming first and second gate lines over a semiconductor substrate, wherein each second gate line has a greater width than each of the first gate lines, forming a first insulating layer surrounding the top and side walls of the first and the second gate lines so that first air gaps are formed between the first and second gate lines and between the first gate lines, forming a first reaction region in the first insulating layer by diffusing an etchant to a depth less than a target depth from a surface of the first insulating layer, removing the first reaction region, forming second reaction regions in the first insulating layer by diffusing the etchant to the target depth from the surface of the first insulating layer, and removing the second reaction regions exposing a portion of each first and second gate lines. | 2013-06-27 |
| 20130164927 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded. | 2013-06-27 |
| 20130164928 | Semiconductor Device and Method for Forming the Same - Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed. | 2013-06-27 |
| 20130164929 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction. | 2013-06-27 |
| 20130164930 | GATE HEIGHT LOSS IMPROVEMENT FOR A TRANSISTOR - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures. | 2013-06-27 |
| 20130164931 | Metal Structure for Memory Device - A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate, the first metal layer providing local interconnection to the SRAM unit cell, a second metal layer formed over the first metal layer, the second metal layer including: a bit line and a complementary bit line each having a first thickness and a Vcc line disposed between the bit line and the complementary bit line, and a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness. | 2013-06-27 |
| 20130164932 | METHODS OF FORMING WIRINGS IN ELECTRONIC DEVICES - A method of forming a wiring may include forming a first wire on a substrate; forming a material layer on the substrate, except on the first wire; forming a surface treatment film on the material layer; and forming a second wire on the first wire. The surface treatment film has physical properties opposite to the first wire. A method of forming a wiring may include forming a first wire on a substrate; forming a material layer on the substrate and the first wire; removing a portion of the material layer from the first wire; forming a surface treatment film on the material layer and the first wire; removing a portion of the surface treatment film from the first wire; and forming a second wire on the first wire. A thickness of the material layer on the substrate is greater than a thickness of the first wire on the substrate. | 2013-06-27 |
| 20130164933 | HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS - An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate. | 2013-06-27 |
| 20130164934 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF - A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity. | 2013-06-27 |
| 20130164935 | LOW RESISTANCE THROUGH-WAFER VIA - The present invention provides a wafer ( | 2013-06-27 |
| 20130164936 | FILM DEPOSITION METHOD - A film deposition method includes a film depositing step of depositing titanium nitride on a substrate mounted on a substrate mounting portion of a turntable, which is rotatably provided in a vacuum chamber, by alternately exposing the substrate to a titanium containing gas and a nitrogen containing gas which is capable of reacting with the titanium containing gas while rotating the turntable; and an exposing step of exposing the substrate on which the titanium nitride is deposited to the nitrogen containing gas, the film depositing step and the exposing step being continuously repeated to deposit the titanium nitride of a desired thickness. | 2013-06-27 |
| 20130164937 | CHEMICAL MECHANICAL PLANARIZATION SITE ISOLATION REACTOR - The embodiments describe systems and methods for combinatorial processing of a substrate. In some embodiments, chemical mechanical polishing (CMP) techniques are combinatorially processed and evaluated. The CMP system is capable of providing a localized planarization surface to at least a region of a substrate being combinatorially processed. In some embodiments, the CMP system comprises a reactor assembly having plurality of reaction chambers, with at least a reaction chamber comprising a rotatable polishing head, slurry and chemical distribution, chemical and water rinse, and slurry and fluid removal. Accordingly, from a single substrate, a variety of materials, process conditions, and process sequences may be evaluated for desired planarization results. | 2013-06-27 |
| 20130164938 | Selective Bias Compensation for Patterning Steps in CMOS Processes - A method includes forming a photo resist pattern, and performing a light-exposure on a first portion of the photo resist pattern, wherein a second portion of the photo resist pattern is not exposed to light. A photo-acid reactive material is coated on the first portion and the second portion of the photo resist pattern. The photo-acid reactive material reacts with the photo resist pattern to form a film. Portions of the photo-acid reactive material that do not react with the photo resist pattern are then removed, and the film is left on the photo resist pattern. | 2013-06-27 |
| 20130164939 | METHOD, APPARATUS FOR HOLDING AND TREATMENT OF A SUBSTRATE - Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area. | 2013-06-27 |
| 20130164940 | HIGHLY SELECTIVE SPACER ETCH PROCESS WITH REDUCED SIDEWALL SPACER SLIMMING - A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure. | 2013-06-27 |
| 20130164941 | PLASMA REACTOR WITH ADJUSTABLE PLASMA ELECTRODES AND ASSOCIATED METHODS - Plasma reactors with adjustable plasma electrodes and associated methods of operation are disclosed herein. The plasma reactors can include a chamber, a workpiece support for holding a microfeature workpiece, and a plasma electrode in the chamber and spaced apart from the workpiece support. The plasma electrode has a first portion and a second portion configured to move relative to the first portion. The first and second portions are configured to electrically generate a plasma between the workpiece support and the plasma electrode. | 2013-06-27 |
| 20130164942 | FILM DEPOSITION METHOD - A film deposition method, in which a film of a reaction product of a first reaction gas, which tends to be adsorbed onto hydroxyl radicals, and a second reaction gas capable of reacting with the first reaction gas is formed on a substrate provided with a concave portion, includes a step of controlling an adsorption distribution of the hydroxyl radicals in a depth direction in the concave portion of the substrate; a step of supplying the first reaction gas on the substrate onto which the hydroxyl radicals are adsorbed; and a step of supplying the second reaction gas on the substrate onto which the first reaction gas is adsorbed. | 2013-06-27 |
| 20130164943 | Substrate Processing Apparatus and Method of Manufacturing Semiconductor Device - The substrate processing apparatus includes a reaction chamber configured to accommodate a substrate; a first gas supply unit configured to supply a first process gas containing a silicon element to the substrate; a second gas supply unit configured to supply a second process gas containing a silicon element and a chlorine element to the substrate; an exhaust unit configured to exhaust the first process gas and the second process gas; a cleaning gas bypass supply unit configured to supply a cleaning gas to the exhaust unit; a cleaning monitoring unit installed in the exhaust unit; a gas flow rate control unit configured to adjust an amount of the cleaning gas supplied; and a main control unit configured to control the gas flow rate control unit in response to a signal received from the cleaning gas monitoring unit. | 2013-06-27 |
| 20130164944 | Methods Of Forming Openings And Methods Of Patterning A Material - Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines. | 2013-06-27 |
| 20130164945 | FILM DEPOSITION METHOD - A film deposition method includes an adsorption step of adsorbing a first reaction gas onto a substrate by supplying the first reaction gas from a first gas supplying portion for a predetermined period without supplying a reaction gas from a second gas supplying portion while separating a first process area and a second process area by supplying a separation gas from a separation gas supplying portion and rotating a turntable; and a reaction step of having the first reaction gas adsorbed onto the substrate react with a second reaction gas by supplying the second reaction gas from the second gas supplying portion for a predetermined period without supplying a reaction gas from the first gas supplying portion while separating the first process area and the second process area by supplying the separation gas from the separation gas supplying portion and rotating the turntable. | 2013-06-27 |
| 20130164946 | METHOD OF FORMING SILICON OXYCARBONITRIDE FILM - The method of forming a silicon oxycarbonitride film on a base includes stacking a silicon carbonitride film and a silicon oxynitride film on the base to form the silicon oxycarbonitride film. | 2013-06-27 |
| 20130164947 | TITANIUM-CONTAINING PRECURSORS FOR VAPOR DEPOSITION - Disclosed are titanium-containing precursors and methods of synthesizing the same. The compounds may be used to deposit titanium, titanium oxide, strontium-titanium oxide, and barium strontium titanate containing layers using vapor deposition methods such as chemical vapor deposition or atomic layer deposition. | 2013-06-27 |
| 20130164948 | METHODS FOR IMPROVING WAFER TEMPERATURE UNIFORMITY - A method of improving temperature uniformity across a wafer or substrate is provided. The inventors have discovered that thermal radiation reflected from the showerhead injector affects the temperature uniformity across the wafer. Temperature uniformity across the wafer, particularly from the center to edge of the wafer, is improved by controlling the reflected energy from the showerhead. Control of the reflected energy from the showerhead is achieved by a variety of means, including changing the emissivity of the showerhead, creating different zones of emissivity of the showerhead, selectively heating the showerhead, varying the distance between the showerhead and the wafer, and increasing reflectivity of the showerhead in selected regions by employing an ring configured to emit thermal radiation to the showerhead which is then reflected back to the wafer. | 2013-06-27 |
| 20130164949 | Magnetic Docking Base for Handset - Novel tools and techniques are described for coupling electronic devices with docking stations. In one aspect, a coupling system comprises a first material in the docking station and a second material in the electronic device. The first material and the second material may each comprise at least one magnet and/or at least one ferromagnetic material that interact magnetically to align the electronic device in an appropriate position with respect to the docking station. The docking station comprises a first set of electrical contacts and the electronic device comprises a second set of electrical contacts. When in the appropriate position, the first set of electrical contacts electrically couples with the second set of electrical contacts. The shapes of the first and second electrical contacts, and the polarities of the magnets/ferromagnetic materials, may be configured to facilitate electrical coupling while avoiding mismatching of the positive/negative terminals of the electrical contacts. | 2013-06-27 |
| 20130164950 | ATTACHMENT MECHANISM FOR ELECTRONIC COMPONENT - An attachment mechanism for an electronic component includes a circuit board and a fastener. The circuit board includes a first connector connected to a second connector of the electronic component. The fastener includes two operation portions and a connection portion connected between the operation portions. The operation portions clamp the first connector. A hook extends from a top of the connection portion to engage with a first end of the electronic component. | 2013-06-27 |
| 20130164951 | MOUNTING APPARATUS FOR MEMORY CARD - A mounting apparatus for mounting a memory card to a printed circuit board (PCB) includes a connector mounted on the PCB and a fixing member. The connector defines a slot in a top surface for electrically receiving the memory card. An ear protrudes from each of opposite end surfaces of the connector and defines a through hole. The fixing member includes a bar abutted against a top of the memory, two legs respectively extending down from opposite ends of the bar to abut against opposite ends of the memory card, and two deformable latches respectively extending from distal ends of the legs and engaged in the corresponding through holes. | 2013-06-27 |
| 20130164952 | DISPLAY CARD ASSEMBLY - A display card assembly includes a display card with a first circuit board, a straight through connector, and an expansion card with a second circuit board. A first edge connector is arranged on a bottom edge of the first circuit board and includes first power pins connected to a control chip and first storage chips, first ground pins, and first signal pins. A second edge connector connected to the straight through connector is arranged on an end edge of the first circuit board adjoining the bottom edge and includes second power pins connected to the first power pins, second ground pins, and second signal pins connected to the control chip. A third edge connector engaged in the straight through connector is arranged on an end edge of the second circuit board and includes third power pins and third signal pins connected to the second storage chips, and third ground pins. | 2013-06-27 |
| 20130164953 | ATTACHMENT MECHANISM FOR ELECTRONIC COMPONENT - An attachment mechanism for fastening an electronic component includes a circuit board and a fastener. The circuit board includes a first connector to be connected to a second connector of the electronic component. The first connector defines a groove in a first end of the first connector and a hooking slot below the groove. The fastener includes a main body and an operation portion extending up from the main body. The main body includes a block engaging in the groove and a latch engaging in the hooking slot. An engaging bar protrudes from the operation portion to abut against a top of the electronic component. | 2013-06-27 |
| 20130164954 | ATTACHMENT MECHANISM FOR ELECTRONIC COMPONENT - An attachment mechanism for an electronic component includes a circuit board, an engaging member, and a pivoting member. The circuit board comprises a first connector to be connected to a second connector of the electronic component. The pivoting member is rotatably connected to the engaging member. The first connector is sandwiched by the pivoting member and the engaging member. The pivoting member includes a resilient bar to abut against a first end of a top surface of the electronic component. | 2013-06-27 |
| 20130164955 | CONNECTION BLADE, INTERMEDIATE CONNECTION ELECTRICAL CONNECTOR HAVING CONNECTION BLADE, AND CONNECTION BLADE ASSEMBLY - A connection blade, an intermediate connection electrical connector and a connection blade assembly including the connection blade are provided. The connection blade includes an insulation board. The insulation board includes differential pair circuits thereon. The differential pair circuits include a straight pair and a cross pair. Both of the straight pair and the cross pair includes a parallel section where wire paths of the pair extend in parallel. In a region other than the parallel section, the cross pair includes a crossing section where wire paths thereof intersect with each other. In a region other than the parallel section, the straight pair includes a quasi-crossing section where wire paths thereof approach each other in non-contact manner so that the wire paths thereof have the same length and the same shape with that of the cross pair, thereby reducing difference of impedance and manufacturing cost. | 2013-06-27 |
| 20130164956 | ELECTRONIC COMPONENT AND ELECTRONIC DEVICE - A surface of a connection terminal of an electronic component is covered with a protection layer made of a AgSn alloy. The electronic component is soldered to a connection terminal of a circuit board. | 2013-06-27 |
| 20130164957 | POWER SOCKET AND ELECTRONIC DEVICE HAVING THE SAME - A power socket disposed on a power supply casing of the electronic device to provide power for the electronic device through a power cord is disclosed. The power socket includes an insulating body, three input end contacts disposed at first side of the insulating body, three output end contacts including a grounding contact disposed at second side of the insulating body, and a rigid connector connected between the grounding contact and a protective grounding pin of the power supply casing. The invention simplifies the connection between the power socket and the power supply casing, thereby simplifies the manufacturing process of the power socket and eliminating the potential safety hazard. | 2013-06-27 |
| 20130164958 | PORTABLE ELECTRONIC DEVICE WITH CHIP CARD EJECTING MECHANISM - A chip card ejecting mechanism includes a main body, a tray slidably fixed to the main body, a latching element, a first elastic member and a second elastic member. The tray defines a latching groove. The latching element includes latching board, a latching block protruding from the latching board, and a triggering member rotatably fixed to the main body. The first elastic member is resisted between the latching board and the main body, to make the latching block latch with the latching groove. The second elastic member is fixed to the main body and is compressed by the tray. After the triggering member rotates relative to the main body to release the latching block from the latching groove, the second elastic member decompresses to drive the tray out of the main body. | 2013-06-27 |
| 20130164959 | LEVER-ENGAGING CONNECTOR AND CONNECTOR UNIT HAVING THE CONNECTOR - A connector for determining whether or not to having been disengaged from the mating connector | 2013-06-27 |
| 20130164960 | UNIVERSAL ADAPTER FOR CONSUMABLE ASSEMBLY USED WITH ADDITIVE MANUFACTURING SYSTEM - A universal adapter for use with a consumable assembly that is configured for use with an additive manufacturing system, the universal adapter comprising an inlet opening configured to receive a guide tube of the consumable assembly, and a connection member at the outlet end, which is configured interface with a mating panel of the additive manufacturing system. | 2013-06-27 |
| 20130164961 | PANELBOARD PLUG-ON NEUTRAL BUS AND METHOD OF MAKING SAME - A loadcenter is equipped with a unitary neutral bus bar capable of receiving AFI and GFI circuit breakers having either a plug-on-neutral connection or a wire-neutral connection. The neutral bus bar is connected to line neutral and has a rolled rail that is formed by rolling an end of a conductive plate and bending the plate at a transition portion to position the rolled rail above and at an angle of a major flat surface of an extension of the neutral bus bar. Wire-capture apparatuses secured along an edge of an extension of the neutral bus bar can capture wires from circuit breakers that lack an internal connection to a neutral plug-on mounting jaw or that lack a neutral plug-on mounting jaw altogether. | 2013-06-27 |
| 20130164962 | Socketed Nut Coaxial Connectors with Radial Grounding Systems for Enhanced Continuity - Axially compressible F-connectors for conventional installation tools for interconnection with coaxial cable include radially compressed grounding inserts seated within a body fitted to a nut socket. Each connector has a rigid nut, a post penetrating the nut, a tubular, metallic body, and an end cap. The conductive post coaxially extends through the connectors, linking the nut and body. A post end penetrates the coaxial cable. The nut has an integral, tubular socket at its rear that is engaged by a tubular, metallic connector body. The body front has at least one groove for receiving a peripheral grounding insert, preferably in the form of a coiled spring wrapped around the body, that is radially sandwiched within the nut socket to insure grounding. An end cap press fitted to the assembly coaxially engaging the body, closing the fitting. Internal O-rings may be combined for sealing the connector. | 2013-06-27 |
| 20130164963 | SOCKET FOR ELECTRIC PARTS - A socket for electric part which suppresses a warp of a floating plate caused by the bias power of the spring even if a bending stiffness of the floating plate is low. The socket for electrical part according to a preferred embodiment of the present invention comprises a unit body being located on a interconnection substrate and having through holes into which the contact terminals are inserted, a floating plate holding an IC package and vertically movably supported at the upper part of the socket body, a rivet put in the floating plate to guide a vertical movement of the floating plate, and a spring located between a part of the socket body and the rivet to biases the floating plate upward via the rivet. | 2013-06-27 |
| 20130164964 | CLAMP MECHANISM - A clamp mechanism for clamping a cable on a circuit board is disclosed in the present invention. The clamp mechanism includes a base disposed on the circuit board. The cable can be accommodated inside the base. The clamp mechanism further includes a clamping portion disposed on the base in a resiliently deformable manner. The clamping portion moves away from the circuit board when the cable is accommodated inside the base, and a resilient recovering force generated by the resilient deformation simultaneously drives the clamping portion to press the cable, so as to constrain a movement of the cable relative to the base. | 2013-06-27 |
| 20130164965 | CONNECTOR WITH ROTATABLE LATCHING ELEMENT - A connector includes a connector body, a connector head and a latching element. The connector head is integrally formed at one end of the connector body, and the connector body and the connector heat define a slot. The latching element includes a plate body, a latching protrusion, and an elastic branching plate. The elastic branching plate branches from the plate body. The latching element is rotatably received in the slot, and the protrusion is releasably latched with a port of an electronic apparatus. | 2013-06-27 |
| 20130164966 | Telecommunications Jack Having Offset Stop Latches and Panel Including the Same - A telecommunications jack and associated panel and method of construction are disclosed. The telecommunications jack is configured for use in a twisted pair system and includes a housing defining a port for receiving a plug, and a latching mechanism positioned to retain the housing in an opening of a face of a telecommunications panel. The telecommunications jack also includes a first stop latch positioned along the left side of the housing and a second stop latch positioned along the right side of the housing, the first and second stop latches vertically offset from each other and extending from the sides of the housing by a width, wherein the telecommunications jack is installable in an array of telecommunications jacks at a distance from a neighboring telecommunications jack of less than twice the width. | 2013-06-27 |
| 20130164967 | INSULATION DISPLACEMENT TERMINAL BLOCK, ELECTRICAL JACK, JACK MODULE AND MODULAR PATCH PANEL - An insulation displacement contact terminal block for providing electrical contact with a bundle of twisted pair wires having at least two differentially driven wire-pairs, a first wire-pair diverging from a second wire-pair at a diverging point of the bundle, and a first wire of each wire-pair untwisting from a second wire of that wire-pair at an untwisting point, the terminal block comprising a first contact-pair and a second contact-pair. The first contact-pair comprising first and second insulation displacement contacts for electrical connection with respective first and second wires of the first wire-pair. The second contact-pair comprising first and second insulation displacement contacts for electrical connection with respective first and second wires of the second wire-pair. The first and second insulation displacement contacts of each contact-pair are substantially equidistant from the untwisting point and are proximate to the untwisting point. | 2013-06-27 |
| 20130164968 | Insulation Displacement Connector (IDC) - An electrical insulation displacement connector includes a bare single-wire contact element having a first end defined by opposed blades that define a receipt aperture for an insulated wire, and a second end configured for direct electrical contact at a contact position on a printed circuit board. Retaining structure is defined on the blades. A cap is configured for fitting over the exposed bare blades. The cap includes side walls and end walls with a slot defined in each of he end walls that align with the blade aperture. The side walls are engaged by the retaining structure upon pressing the cap onto the blades. The slots in the end walls of the cap have a width and height such that upon fully pressing the cap onto the blades, the slots engage and longitudinally align the insulated wire into the blade aperture so that the blades pierce and make electrical contact with a core in the insulated wire. | 2013-06-27 |
| 20130164969 | CABLE ASSEMBLY HAVING IMPROVED STRAIN RELIEF - A cable assembly includes a connector, a cover enclosing the connector, a strain relief located on the rear end of the cover, a spring, and a cable. The cover includes a blocking. The strain relief is fixed by the blocking. The strain relief defines a through hole and a receiving cavity communicated with the through hole. The through hole has an inner diameter smaller than an inner diameter of the receiving cavity. A shoulder is formed between the through hole and the receiving cavity. The spring is received in the cavity, and has one end restricted by the shoulder and an opposite end restricted by the blocking. The cable is connected to the connector and runs through the spring and the through hole. | 2013-06-27 |
| 20130164970 | CONNECTOR WITH INTEGRATED HEAT SINK - A receptacle connector defines a port. The port is provided with spring fingers that are configured to engage a mating module. The spring fingers are thermally coupled to a heat transfer plate that can be configured to provide part of a cage that defines the port. Fins can be mounted on or integrated into the heat transfer plate. In operation, thermal energy from an inserted module is transferred from the module to spring fingers and then to the heat transfer plate and then to a thermal dissipation system. | 2013-06-27 |
| 20130164971 | SMART PLUGS, SMART SOCKETS AND SMART ADAPTORS - A smart socket is provided. The smart socket has a set of power sockets, configured for a set of power pins of a smart plug to plug into, a driving pin and a set of detection pins, configured for forming a circuit with a set of feedback pins of a smart plug when the set of power pins is plugged into the power sockets, and an identification code module, configured for obtaining an identification code of an electric appliance, from the circuit, to which the smart plug belongs. | 2013-06-27 |
| 20130164972 | MOUNTING APPARATUS FOR FLASH DRIVE - A mounting apparatus is used to fix a flash drive mounted on a circuit board with a connector. The mounting apparatus is mounted on the circuit board and receives the flash drive and connector. The mounting apparatus includes a base board, and a first sidewall and a second sidewall opposite to each other. The second sidewall defines a receiving space. The first sidewall is pivotably connected to the first sidewall, and includes a deformable engaging portion, away from the first sidewall, to be engaged in the receiving space. | 2013-06-27 |
| 20130164973 | PANEL MOUNT ELECTRICAL CONNECTOR - In accordance with one embodiment, a panel mount electrical connector can include a connector housing configured to be inserted into an opening in a panel. The electrical connector can include at least one first retention member in the form of a spacer member supported by the connector housing and configured to be removably coupled to the connector housing. The at least one spacer member can have a spacer thickness that at least partially defines a gap between the spacer member and at least one second retention member, the gap sized to receive a panel of a predetermined thickness. The panel mount electrical connector can further include a locking member supported by the connector housing, the locking member configured to prevent removal of the panel mount electrical connector from a panel when the locking member is in the locked position. | 2013-06-27 |
| 20130164974 | TELESCOPIC DEVICE FOR SECURING LAMP TO SOCKET - A conductive telescopic device is provided with a conductive member releasably connected to an electrical socket in a fixture body; a hollow member having one end secured to the conductive member; a sleeve comprising a shell, a shaft member slidably disposed in a lower portion of the shell and including a recess on a surface, a sleeving member secured onto a lower portion of the shaft member, and an eccentric spiral member disposed on the shaft member and including a latch end complimentary to the recess; a socket member for releasably holding at least one lamp; a hollow connecting member having one end secured to the sleeving member and the other end secured to the socket member; and an electrical wire electrically connected to the conductive member and the socket member. A rotation of the shaft member about the shell can lengthen or shorten the telescopic device. | 2013-06-27 |
