| 26th week of 2013 patent applcation highlights part 32 |
| Patent application number | Title | Published |
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| 20130163275 | ELECTRONIC INCENSE AND ELECTRONIC BURNING USING SAME - An electronic burner includes a burner base and an electronic incense. The burner base includes a burner body and a light emitting source mounted in the burner body. Then electronic incense includes a light guiding body and an incense head. The light guiding body is detachably mounted with the burner body. The incense head includes a first chamber, a second chamber, first reaction solution, and second solution. The first chamber is connected with the light guiding body away from the burner body. The second chamber is received in the first chamber. The first reaction solution received in the first chamber, and the second solution is received in the second chamber. When the second chamber is cracked, the first reaction solution and the second reaction solution would be mixed together in the first chamber to make a chemistry reaction happen, and at the same time, produce light. | 2013-06-27 |
| 20130163276 | Providing consistent output from an endoilluminator system - In certain embodiments, determining an endoilluminator output includes calculating an illuminator contribution of an endoilluminator system and a fiber contribution of one or more optical fibers of the endoilluminator system. The endoilluminator output is determined from the illuminator contribution and the fiber contribution. The illuminator contribution may be established using calibrated or empirically determined factors, such as an illuminator leg efficiency, an attenuator factor, an initial lamp performance, and/or a lamp performance degradation factor of the lamp. The fiber contribution may be established using calibrated or empirically determined factors, such as a fiber coupling factor and/or fiber transmission ratio of the optical fibers. | 2013-06-27 |
| 20130163277 | DISPLAY MODULE AND APPARATUS HAVING THE SAME - A display module includes a display panel including a display area and a non-display area, an upper prism layer including a plurality of parallel upper prisms at a lower surface thereof, wherein the plurality of the upper prisms are parallel to one another, a lower prism layer including a plurality of lower prisms at a lower surface thereof, wherein the plurality of the lower prisms are parallel to one another and extend in a substantially perpendicular direction to the upper prisms, and an adhesive part which is at a side of the upper prism layer and is adhered to the lower prism layer and the non-display area of the display panel, wherein the adhesive part fixes the upper prism layer and the lower prism layer to each other. | 2013-06-27 |
| 20130163278 | ELECTRONIC DEVICE HAVING A FLEXIBLE SCREEN, A BACKLIGHT MODULE AND A LIGHT GUIDE PLATE - An electronic device includes a base having two opposite sidewalls, two carriers connected pivotally and respectively to the sidewalls, and two light guide plates respectively disposed on the carriers. The carriers are rotatable relative to the base between a first position, where the carriers cooperatively define a carrier surface, and a second position, where the carriers are parallel to each other. A flexible screen is superposed on the light guide plates, is expanded to a planar state when move along with the carriers to the first position, and is folded when move along with the carriers to the second position. | 2013-06-27 |
| 20130163279 | BACKLIGHT MODULE - A backlight module including a light guide plate and a light source is provided. The light guide plate has a light incident surface, a light reflection surface, a first side surface and a second side surface. The light incident surface is connected to the second side surface. The reflection surface is connected between the first side surface and the light incident surface. The first and the second side surfaces are two planes with their extending planes intersected. The light incident surface is a chamfering plane connected between the first and the second side surfaces. The light reflection surface is a cambered surface connected between the first side surface and the light incident surface. The light source is disposed next to the light incident surface, so as to transmit light into the light guide plate through the light incident surface. | 2013-06-27 |
| 20130163280 | LIGHT GUIDE DEVICE AND ILLUMINATION MODULE USING THE SAME THEREOF - An illumination device comprising a light guide bar, a light source and a reflective sleeve is provided. The light guide bar comprises a first end surface, a second end surface, and a cylindrical surface. The cylindrical surface is disposed between the first end surface and the second end surface and has a light-emitting surface and a reflective surface. The light source is disposed at the outside of the first end surface of the light guide bar. The reflective sleeve covers the second end surface of the light guide bar and has a reflective cavity, which tapers inward to form a vertex angle. A part of the incident light of the light source is reflected to the light-emitting surface via the reflective surface by the reflective cavity or directly reflected to the light-emitting surface by the reflective cavity. | 2013-06-27 |
| 20130163281 | LIGHT GUIDE PLATE AND BACKLIGHT MODULE USING SAME - A light guide plate includes an incident surface, an emitting surface, and a reflecting surface opposite to the emitting surface. The incident surface connects the emitting surface to the reflecting surface. A plurality of microstructures is defined in the reflecting surface. Each microstructure is a slot. A cross-section across each microstructure and parallel to a light emitting direction is substantially V-shaped. Each microstructure is formed with two sidewalls. Each sidewall includes a plurality of stepped portions connected in order. | 2013-06-27 |
| 20130163282 | SPREAD ILLUMINATING APPARATUS - A spread illuminating apparatus includes a point light source with a light-emitting surface, a circuit board with a mounting surface on which the point light source is mounted, and a light guide plate with an incident light surface and an emitting surface. The circuit board is arranged as that at least a partial portion of the circuit board extends beyond an area where the point light source is mounted so as to be superposed on the light guide plate, a light-reflecting member is arranged on the mounting surface, and a region of the mounting surface in which the light-reflecting member is arranged includes a first region that extends forward from a position corresponding to the center of the light-emitting surface of the point light source. | 2013-06-27 |
| 20130163283 | LIGHT GUIDE, LIGHT SOURCE UNIT, ILLUMINATING DEVICE, AND DISPLAY DEVICE - A light guide ( | 2013-06-27 |
| 20130163284 | LATERAL PLANAR LIGHT EMITTING MODULE - A lateral planar light emitting module has a rectangular base plate and a plurality of light emitting diodes, and the light emitting diodes are designed with an array arrangement and installed on both opposite sides of the rectangular base plate respectively, so that a light exit surface opposite to a light projection area with a different intensity produced by the same light emitting diode has an optical path with a different distance after a light source emitted from the light emitting diodes is projected directly or reflected from a reflective micro-structure of the rectangular base plate, and a light emitting effect with a uniform light intensity distribution is achieved on the light exit surface to lower the manufacturing cost and improve the light emitting efficiency effectively. | 2013-06-27 |
| 20130163285 | COOLING STRUCTURE FOR LIGHT EMITTING ELEMENTS FOR LIQUID CRYSTAL PANEL - A cooling structure for light emitting elements for a liquid crystal panel according to the present invention includes: a long-shaped substrate that is disposed so as to extend along an edge of a light guide plate provided on a rear surface of a liquid crystal panel, and in which a plurality of through-holes are formed; a plurality of light emitting elements that are disposed on a front surface of the substrate so as to face the light guide plate; and a chassis that is provided at a rear surface side of the substrate, and the through-holes are arranged at a higher density at a center portion of the substrate in a long direction than at end portions of the substrate in the long direction. | 2013-06-27 |
| 20130163286 | BACKLIGHT MODULE - A backlight module includes a housing, a light emitting unit, plural supporters and a light guiding plate. The housing includes a base and a first frame and a second frame arranged on two opposite sides of the base. Each supporter includes two supporting portions placed on two opposite sides of the light emitting unit. Each supporting portion includes a supporting surface facing the light emitting unit, wherein the supporting surface is slant. A distance between two opposite supporting portions is increased along a direction from the base to a top surface of the supporter. The light guiding plate is arranged on the supporting surfaces of the supporters. The light guiding plate includes a light input surface facing to the light emitting unit and a light output surface facing the first frame. | 2013-06-27 |
| 20130163287 | Regulated Controller with Self-Adjusting Output Set-Point Control - A power conversion system includes a power converter that converts an input voltage into a DC output voltage. Additionally, the power conversion system also includes a controller that provides a self-adjusting set-point control scheme for the power converter. A method of power conversion system operation is also provided. | 2013-06-27 |
| 20130163288 | POWER MODULE AND DISTRIBUTED POWER SUPPLY APPARATUS HAVING THE SAME - There are a power module and a distributed power supply apparatus having the same. The power module includes: a power factor correction stage switching input power to correct a power factor thereof; a DC/DC conversion stage switching the power of which the power factor has been corrected by the power factor correction stage to convert the power into preset DC power; a control unit controlling the power factor correction stage and the DC/DC conversion stage to perform a power conversion operation in a preset powered mode and stopping the power conversion operation of the DC/DC conversion stage in a preset idle mode; and a reference voltage supply unit supplying a preset reference voltage to the DC/DC conversion stage in the idle mode. | 2013-06-27 |
| 20130163289 | POWER SWITCHING DRIVING APPARATUS, AND POWER FACTOR CORRECTION DEVICE AND POWER SUPPLY DEVICE HAVING THE SAME - There are provided a power switching driving apparatus able to reduce a circuit area and increase a driving speed, and a power factor correction device and a power supply device having the same. The power switching driving apparatus includes: a first driving unit providing a switching signal in response to a control signal from the outside; a second driving unit including first and second NMOS FETs cascode-connected between an operational power source terminal supplying pre-set operation power and a ground, and performing switching complimentarily in response to the switching signal to provide a switching control signal controlling power switching; a current supply unit supplying a current for driving the second driving unit; and a voltage maintaining unit maintaining a voltage for driving the second driving unit. | 2013-06-27 |
| 20130163290 | POWER SUPPLY APPARATUS - There is provided an LLC type power supply apparatus for controlling switching of a secondary side rectifier based on primary side current, particularly, controlling switching of the secondary-side rectifier based on primary side resonance current and magnetizing current. The power supply apparatus includes: a switching unit switching input power; a transformer unit transforming the switched power from the switching unit; a rectifying unit including a rectifier turned on and turned off in response to a control signal to rectify the transformed power; a controlling unit controlling the switching of the switching unit, based on an output power of the rectifying unit; and a switching controlling unit controlling turning-on and turning-off of the rectifier of the rectifying unit, based on current flowing in the transformer unit. | 2013-06-27 |
| 20130163291 | SWITCH CIRCUIT, POWER SUPPLY DEVICE INCLUDING THE SAME, AND DRIVING METHOD THEREOF - The present invention relates to a switch circuit, a power supply including the same, and a method for driving the power supply. When a load of the power supply represents an overload state, a sense resistor for controlling a drain current flowing through a power switch is controlled. In this instance, the sense resistor is controlled according to an on-time of the power switch. | 2013-06-27 |
| 20130163292 | MID-POINT VOLTAGE CONTROL - A midpoint voltage control system includes a power source, a generator coupled to the power source, a midpoint voltage controller coupled to the back-to-back converter configuration, a generator converter controller coupled to the midpoint power controller, a grid converter controller coupled to midpoint power controller, a first voltage converter coupled to the generator converter controller, the midpoint power controller and the generator, a second voltage converter coupled to the grid converter controller the midpoint power controller, the second voltage converter having a capacitor bank direct current (DC) bus midpoint and a transformer coupled to the second voltage converter and having a grid neutral midpoint, wherein the capacitor midpoint is interconnected to the grid neutral midpoint. | 2013-06-27 |
| 20130163293 | BUCK CIRCUIT - A buck circuit of a computer includes a voltage input terminal, a voltage output terminal, first and second electronic switches, and first to third field effect transistors (FETs). When the computer is powered on, the signal control terminal of the computer outputs a first control signal to control the first FET to be turned on through the first and second electronic switches, and simultaneously controls the first and third FETs with a pulse width modulation (PWM) control chip. After the computer is powered off, the signal control terminal of the computer outputs a second control signal to control the first FET to be turned off through the first and second electronic switches, and to control the third FET through the PWM control chip. | 2013-06-27 |
| 20130163294 | INVERTER APPARATUS HAVING POWER SUPPLY CIRCUIT - An inverter apparatus having a power supply circuit includes a converter circuit for rectifying AC power into DC power, a smoothening circuit for smoothening the rectified DC power, an inverter circuit for converting the smoothened DC into AC at a variable frequency through a plurality of switches to control a load, and a current detection circuit for detecting overcurrent from the smoothened DC supplied from the inverter circuit, wherein the inverter circuit applies bootstrap power for driving the switches to the current detection circuit to use the bootstrap power as power of the current detection circuit. When bootstrap power for driving switch gates is used, it is possible to use the bootstrap power as the power of the current detection circuit by adding the auxiliary circuit composed of a small number of passive elements. | 2013-06-27 |
| 20130163295 | POWER SUPPLY CONVERTER WITH A PRE-REGULATOR - A power supply converter with a pre-regulator is provided. In one embodiment, the power supply converter comprises a rectifier that receives an AC input voltage and provides a rectified AC input voltage, a filter that receives the rectified AC input voltage and provides a filtered DC input voltage and a pre-regulator that connects the rectified AC input voltage for allowing for providing current and voltage to the filter from the rectified AC input voltage upon a measurement that indicates that the AC input voltage or the rectified AC input voltage crosses a predetermined turn on threshold. | 2013-06-27 |
| 20130163296 | POWER CIRCUIT - A power circuit includes an input terminal receiving alternating current, a first AC filtering circuit connected to the input terminal, a bridge rectifier circuit, a DC filtering circuit, a DPDT switch, and an output terminal. Two input ends of the bridge rectifier circuit are connected to the first AC filtering circuit. The DPDT switch includes a first pair of pins, a second pair of pins, and a pair of output pins. The first pair of pins is connected to the DC filtering circuit. The second pair of pins is connected to the input terminal. The DC filtering circuit is connected to the pair of output pins of the DPDT switch. The first pair of pins is switched on to enable the output terminal to output direct current, and the second pair of pins is switched on to enable the output terminal to output alternating current. | 2013-06-27 |
| 20130163297 | SINGLE PHASE REDUNDANT POWER SUPPLY SYSTEMS FOR REDUCING PHASE CURRENT IMBALANCES - A single phase redundant power supply system may include a first power supply having an input coupled to a first phase voltage in a polyphase power distribution system and an output coupled to a load for supplying an amount of DC power to the load, and a second power supply having an input for coupling to a second phase voltage in the polyphase power distribution system and an output coupled to the load for supplying an amount of DC power to the load. At least the first power supply is configured to reduce phase current imbalances in the polyphase power distribution system by adjusting the amount of DC power supplied to the load by the first power supply and the amount of DC power supplied to the load by the second power supply. | 2013-06-27 |
| 20130163298 | ELECTROMAGNETIC DEVICE FOR GENERATING ELECTRICAL CURRENT AND METHODS THEREOF - An energy harvesting device (EHD) and method including a hollow outer envelope ( | 2013-06-27 |
| 20130163299 | POWER SUPPLY DEVICE SYSTEM, SWITCHING POWER SUPPLY DEVICE, CONTROL PARAMETER GENERATION DEVICE, AND PROGRAM - A power supply device system | 2013-06-27 |
| 20130163300 | BOOST POWER FACTOR CORRECTION CONTROLLER - The present invention relates to a power factor correction (PFC) controller. In one embodiment, a boost PFC controller configured in an AC/DC converter can include: (i) a conductive signal generator configured to receive a first sampling signal, and to generate a conductive signal according to the first sampling signal and a first control signal; (ii) a shutdown signal generator configured to compare a second control signal against a third control signal, and to generate a shutdown signal when the second control signal reaches a level of the third control signal; and (iii) a logic controller coupled to the conductive signal generator and the shutdown signal generator to control a switching state of a power switch in AC/DC converter. | 2013-06-27 |
| 20130163301 | POWER CONVERSION APPARATUS - A power conversion apparatus includes a comparison circuit which compares a determination element related to a loss in the power converter with a switching reference value and outputs a determination instruction when a difference has occurred between them, a determination circuit which outputs a two-level operation switching instruction when the determination element is greater than or equal to the switching reference value, and a switching circuit which, when having received a two-level operation switching instruction, turns off the alternating-current switch and turns on the valve devices in the arm sequentially, thereby bringing the power converter into a two-level operation state. | 2013-06-27 |
| 20130163302 | DC-DC CONVERTER SYSTEMS - DC-DC converter systems are disclosed. DC-DC converter systems may include an input, an output, a resonant switched-capacitor DC-DC converter, and a second DC-DC converter. The resonant switched-capacitor DC-DC converter may include a first input side and a first output side. The second DC-DC converter may include a second input side and a second output side. The first input side may be connected to the input, the second input side may be connected to an input voltage, and the first and second output sides may be connected in series to the output. In some examples, the second DC-DC converter may be a buck-boost DC-DC converter. | 2013-06-27 |
| 20130163303 | SEMICONDUCTOR DEVICE HAVING MULTI-LEVEL WIRING STRUCTURE - Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer. | 2013-06-27 |
| 20130163304 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - Provide are a three-dimensional semiconductor device and a method of operating the same. the device may include a substrate, left, center, and right blocks provided on the substrate, and at least one decoding block provided between the left and center blocks and/or between the right and center blocks. The center block comprises first lines arranged to form a plurality of columns and a plurality of layers, and the at least one decoding block comprises a plurality of decoding groups, each of which is configured to selectively connect a corresponding one of the columns of the first lines to one of the left and right blocks. | 2013-06-27 |
| 20130163305 | APPARATUSES AND METHODS INCLUDING MEMORY WITH TOP AND BOTTOM DATA LINES - Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described. | 2013-06-27 |
| 20130163306 | One-Time Programmable Memory Cell, Memory and Manufacturing Method Thereof - The present invention pertains to the technical field of one-time programmable memory (OTP), and in particular to a one-time programmable memory unit, OTP, and method of fabricating the same. The OTP unit comprises a lower electrode, an upper electrode and a storage medium layer placed between the upper electrode and the lower electrode, the storage medium layer comprises a first metal oxide layer and a second metal oxide layer, wherein an adjoining area for programming is formed between the first metal oxide layer and the second metal oxide layer. The OTP comprises a plurality of the above-described one-time programmable memory units arranged in rows and columns. The OTP unit and the OTP have such characteristics as low programming voltage, small unit area, being able to integrate into a back-end structure of integrated circuit, great process flexibility, and the method of fabricating the OTP unit and the OTP is relatively simple and low in cost. | 2013-06-27 |
| 20130163307 | Memory Device Correcting the Effect of Collisions of High-Energy Particles - A memory device automatically correcting the effect of collisions of high-energy particles, comprising at least one memory cell, and further comprising: retention means for retaining, for a determined period, a single copy of the stored value stored in said memory cell; detection means for detecting a change of state of said memory cell, by comparing the stored value stored in said memory cell with the value in retention in said retention means; and management means suitable for determining whether a detected change of state of said memory cell is due to a high-energy particle and, in which case, to automatically command a reloading of the stored value stored in said retention means into said memory cell. | 2013-06-27 |
| 20130163308 | METHOD OF PROGRAMMING VARIABLE RESISTANCE ELEMENT, METHOD OF INITIALIZING VARIABLE RESISTANCE ELEMENT, AND NONVOLATILE STORAGE DEVICE - Programming a variable resistance element includes: a writing step of applying a writing voltage pulse to transition metal oxide comprising two stacked metal oxide layers to decrease resistance of the metal oxide, each metal oxide layer having different oxygen deficiency; and an erasing step of applying an erasing voltage pulse, of different polarity than the writing pulse, to the metal oxide to increase resistance of the metal oxide. |Vw | 2013-06-27 |
| 20130163309 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array configured of at least a first portion and a second portion each including a plurality of memory cells each with a variable resistor which stores an electrically rewritable resistance value as a data, and a control circuit which controls a first operation including selected one of operations to erase, write and read the data in the first portion and a second operation including selected one of operations to erase, write and read the data in the second portion, the first operation and the second operation being performed in temporally overlapped relation with each other. | 2013-06-27 |
| 20130163310 | RESISTIVE MEMORY - A memory device includes an upper conductive layer, a lower conductive layer, and a resistive, optical or magnetic matrix positioned between the upper and lower conductive layers. | 2013-06-27 |
| 20130163311 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises a memory cell array having memory cells each configured to hold data, a plurality of N ports, a port selection circuit that selects M (M| 2013-06-27 | |
| 20130163312 | SRAM TIMING TRACKING CIRCUIT - A static random access memory (SRAM) test apparatus includes an array of SRAM test cells. The test cells are configured according to a layout with NMOS and PMOS transistors coupleable as inverters and responsive to a first passing gate transistor. At least one of the NMOS and PMOS transistors of a test cell at a predetermined location in the array is coupled to a fixed voltage to force a logic state of an associated inverter. A switching signal coupled to the associated inverter through a second passing gate transistor produces a detectable test current through one of the NMOS and PMOS transistors of the associated inverter of said test cell and through one of the NMOS and PMOS transistors of an associated inverter of an adjacent series-connected test cell. | 2013-06-27 |
| 20130163313 | MAGNETOELECTRIC MEMORY - Magnetoelectric memory element comprising: a magnetic element (ELM) that has two equilibrium directions (P | 2013-06-27 |
| 20130163314 | MEMORY ELEMENT AND MEMORY APPARATUS - A memory element includes a layered structure. The layered structure includes a memory layer, a magnetization-fixed layer, and an intermediate layer. The memory layer has magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on information, and the direction of the magnetization is changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer. The magnetization-fixed layer has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer, has a laminated ferri-pinned structure including at least two ferromagnetic layers and a non-magnetic layer, and includes an anti-ferromagnetic oxide layer formed on any of the at least two ferromagnetic layers. The intermediate layer is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. | 2013-06-27 |
| 20130163315 | MEMORY ELEMENT AND MEMORY APPARATUS - A memory element includes a layered structure. The layered structure includes a memory layer, a magnetization-fixed layer, and an intermediate layer. The memory layer has magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on information, and the direction of the magnetization is changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer. The magnetization-fixed layer has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer, and has a laminated ferri-pinned structure including at least two ferromagnetic layers and a non-magnetic layer. The non-magnetic layer includes Cr. The intermediate layer is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. | 2013-06-27 |
| 20130163316 | MEMORY ELEMENT AND MEMORY APPARATUS - A memory element has a layered configuration, including a memory layer in which a magnetization direction is changed corresponding to information; the magnetization direction being changed by applying a current in a lamination direction of the layered configuration to record the information in the memory layer, a magnetization-fixed layer in which a magnetization direction is fixed, an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer, and a perpendicular magnetic anisotropy inducing layer, the memory layer including a first ferromagnetic layer, a first bonding layer, a second ferromagnetic layer, a second bonding layer and a third ferromagnetic layer laminated in the stated order. | 2013-06-27 |
| 20130163317 | MEMORY ELEMENT AND MEMORY APPARATUS - There is provided a memory element having a layered structure, including a memory layer having magnetization perpendicular to a film face in which a magnetization direction is changed corresponding to information, and including a Co—Fe—B magnetic layer and at least on non-magnetic layer; the magnetization direction being changed by flowing a current in a lamination direction of the layered structure to record the information in the memory layer, a magnetization-fixed layer having magnetization perpendicular to the film face that becomes a base of the information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer, further including a laminated structure where an oxide layer, the Co—Fe—B magnetic layer and the non-magnetic layer are laminated is formed. | 2013-06-27 |
| 20130163318 | Self-Referenced MRAM Cell and Method for Writing the Cell Using a Spin Transfer Torque Write Operation - The present disclosure concerns a method for writing to a self-referenced MRAM cell comprising a magnetic tunnel junction comprising: a storage layer including a first ferromagnetic layer having a first storage magnetization, a second ferromagnetic layer having a second storage magnetization, and a non-magnetic coupling layer separating the first and second ferromagnetic layers; a sense layer having a free sense magnetization; and a tunnel barrier layer included between the sense and storage layers; the first and second ferromagnetic layers being arranged such that a dipolar coupling between the storage) and the sense layers is substantially null; the method comprising: switching the second ferromagnetic magnetization by passing a spin-polarized current in the magnetic tunnel junction; wherein the spin-polarized current is polarized when passing in the sense layer, in accordance with the direction of the sense magnetization. The MRAM cell can be written with low power consumption. | 2013-06-27 |
| 20130163319 | MULTI-PORT NON-VOLATILE MEMORY THAT INCLUDES A RESISTIVE MEMORY ELEMENT - A particular method of accessing a multi-port non-volatile memory device includes executing a first memory operation with respect to a first memory cell while executing a second memory operation with respect to a second memory cell. The first memory operation is via a first port and the second memory operation is via a second port. The first memory cell includes a first non-volatile memory that includes a first resistive memory structure. The second memory cell includes a second non-volatile memory that includes a second resistive memory structure. The first memory cell and the second memory cell are each accessible via the first port and the second port. | 2013-06-27 |
| 20130163320 | ENERGY-EFFICIENT ROW DRIVER FOR PROGRAMMING PHASE CHANGE MEMORY - A drive circuit and method for parallel programming a plurality of phase change memory (PCM) cells includes a first signal generator device for generating a slow ramping signal; an adiabatic computing element receives the slow ramping signal and responsively generates an output slow ramping signal in adiabatic fashion, the output slow ramping signal applied to the single wordline conductor associated with each PCM cell of the plurality of cells being programmed in a time interval. Each PCM cell of the plurality being programmed is connected to a respective bitline conductor. A second signal generator generates, during the time interval, one or more bitline signals for input to a respective bitline conductor of a respective PCM cell. A state of the applied slow ramping output signal and the one or more bitline signals during the time interval governs a programmed state of the PCM cell. | 2013-06-27 |
| 20130163321 | DRIFT MITIGATION FOR MULTI-BITS PHASE CHANGE MEMORY - An RC-based sensing scheme to effectively sense the cell resistance of a programmed Phase Change Material (PCM) memory cell. The sensing scheme ensures the same physical configuration of each cell (after programming): same amorphous volume, same trap density/distribution, etc. The sensing scheme is based on a metric: the RC based sense amplifier implements two trigger points. The measured time interval between these two points is used as the metric to determine whether the programmed cell state, e.g., resistance, is programmed into desired value. The RC-based sensing scheme is embedded into an iterative PCM cell programming technique to ensure a tight distribution of resistance at each level after programming; and ensure the probability of level aliasing is very small, leading to less problematic drift. | 2013-06-27 |
| 20130163322 | PARALLEL PROGRAMMING SCHEME IN MULTI-BIT PHASE CHANGE MEMORY - A system, a method for parallel programming multiple bits of a phase change memory array for high bandwidth. The system and method includes parallel programming scheme wherein a common wordline (WL) is driven with a first pulse of one of: gradually increasing (RESET) or decreasing (SET) amplitudes which control current flow through one or more phase change memory cells associated with the WL. Simultaneously therewith, one or more bitlines (BLs) are driven with one or more second pulses, each second pulse more narrow than that of the first pulse applied to the WL. The starting time of the one or more second pulses may vary with each bitline driven at a time later than, but within the window of the wordline pulse to achieve a programming current suitable for achieving the corresponding memory cell state. | 2013-06-27 |
| 20130163323 | SEMICONDUCTOR MEMORY DEVICE USING VARIABLE RESISTANCE ELEMENT OR PHASE-CHANGE ELEMENT AS MEMORY DEVICE - A semiconductor memory device includes a first conductive line, a second conductive line, a cell unit, a silicon nitride film and a double-sidewall film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The cell unit includes a phase-change film and a rectifier element connected in series with each other between the first conductive line and the second conductive line. The silicon nitride film is formed on a side surface of the phase-change film. The double-sidewall film includes a silicon oxide film and the silicon nitride film formed on a side surface of the rectifier element. | 2013-06-27 |
| 20130163324 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array including first memory cells and second memory cells connected to at least one word line, a circuit group configured to perform a pre-program operation on the first memory cells using a target voltage and a main program operation on the first memory cells and the second memory cells using a final target voltage, and a control circuit configured to set the target voltage depending on variations in threshold voltages of the first memory cells caused by the main program operation of the second memory cells. | 2013-06-27 |
| 20130163325 | NON-VOLATILE MEMORY DEVICE, METHOD FOR FABRICATING THE SAME, AND METHOD FOR OPERATING THE SAME - A non-volatile memory device includes a first string and a second string that each include a first drain selection transistor, a second drain selection transistor, a plurality of memory cells, and a source selection transistor that are coupled in series in that order, respectively, a first bit line coupled with a node between the first and second drain selection transistors of the first string, and a second bit line coupled with an end node of the second string on the side of the first drain selection transistor of the second string, wherein gates of the first drain selection transistors of the first and second strings are coupled with each other, and gates of the second drain selection transistors of the first and second strings are coupled with each other. | 2013-06-27 |
| 20130163326 | Nonvolatile Memory Device and Program Method Thereof - Methods of operating nonvolatile memory devices are described. A bit line program voltage is applied to at least one selected bit line and a bit line program-inhibition voltage is applied to at least one unselected bit line. The methods further include concurrently applying a word line program voltage to a selected word line, a first pass voltage to at least one unselected word line and a second pass voltage less than the first pass voltage to at least one unselected word line immediately adjacent the selected word line on a string selection line side of the selected word line. | 2013-06-27 |
| 20130163327 | WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM - Aspects of the subject technology encompass a method for retrieving information stored in flash memory. In certain implementations, the method can include operations for reading a plurality of memory cells in a word line, generating a plurality of read signals based on the reading of the plurality of memory cells and identifying, from among the plurality of read signals, a first read signal associated with a first memory cell and a second read signal associated with a second memory cell, wherein the first memory cell is adjacent to the second memory cell in the word line. In certain aspects, the method can further include operations for generating an output for the first memory cell, wherein the output is based on the first and second read signals. A data storage system and article of manufacture are also provided. | 2013-06-27 |
| 20130163328 | INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES - Aspects of the subject technology relate to a method for reading information stored in a flash memory device. In some implementations, the method can include steps including, obtaining a first read signal of a first cell, wherein the first cell is located in a first word line and a first bit line in the flash memory device, obtaining a programming level of a second cell, wherein the second cell is located in a second word line and the first bit line, and wherein the second word line is adjacent to the first word line. In certain aspects, the method may further comprise steps for obtaining decoding information for the first cell based on the programming level of the second cell. A data storage system and article of manufacture are also provided. | 2013-06-27 |
| 20130163329 | MEMORY SYSTEM - Provided is a non-volatile semiconductor storage device according to one embodiment including: a memory cell array where memory cells capable of storing data of three or more levels are arrayed; a flag cell which is provided in an access prevention area where external access to the memory cell array is prevented; a flag data generating unit which generates flag data which is to be written in the flag cell based on a written state of the memory cell array; and an access prevention cancelling unit which permits external reading of the flag data based on an externally applied command. | 2013-06-27 |
| 20130163330 | MITIGATING VARIATIONS ARISING FROM SIMULTANEOUS MULTI-STATE SENSING - Methods and devices for mitigating sensing variations that may arise from simultaneous multi-threshold (SMT) sensing are provided. During SMT sensing, two or more different bias conditions may be used to simultaneously sense two different threshold voltages. However, there may be variances in the threshold voltage shift of memory cells when read with a different bias condition than was used to verify. In one embodiment each programmed state is read using both (or all) bias conditions that were used during SMT verify. In other words, two (or more) different sense operations are used to read each memory cell. The data from these different sense operations may be used to compute initialization values (e.g., LLRs, LRs, probabilities) for an ECC decoder. In one embodiment, this technique is only performed when a normal read fails. | 2013-06-27 |
| 20130163331 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device and a method of operating the same results in reduced programming time. The semiconductor memory device includes advanced circuitry that enables reductions in programming and verification times, leading to a substantial reduction in the total time required to program the device. | 2013-06-27 |
| 20130163332 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes memory blocks including pages connected to plural main cells, a spare block, including pages connected to spare cells, configured to store a random seed for randomization to the spare cells connected to each page, page buffers configured to scramble data inputted for program operation by using random seed read from a page of the spare block selected by a control signal to transmit the scrambled data to the bit line, and configured to descramble data read from a main cell selected for read operation and output the descrambled data, and a controller configured to output the control signal to select a page of the spare block corresponding to an address of a page of the memory block selected for the programming or reading, and configured to control a scramble operation and a descramble operation of the page buffers. | 2013-06-27 |
| 20130163333 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - The semiconductor memory device includes a memory cell array configured to include a plurality of blocks, wherein each of the blocks has pages and each of the pages includes memory cells, and a peripheral circuit configured to program the memory cells to target program states. Here, the peripheral circuit programs the memory cells to temporary program states by applying program voltages increasing step-by-step by a first incremental value, and then programs the memory cells to the target program states by applying program voltages increasing step-by-step by a second incremental value. | 2013-06-27 |
| 20130163334 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same include a circuit group configured to apply a program maintaining voltage between the program prohibition voltage and the program permission voltage to bit lines connected to programmed memory cells to prevent a decrease in threshold voltage. | 2013-06-27 |
| 20130163335 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device is operated by, inter alia, sequentially inputting program data to page buffers coupled to selected pages of at least four planes in order to program selected memory cells included in the selected pages; performing a program operation on each of the four planes; performing a program verify operation on each of the four planes; and inputting new program data for next pages to the page buffers coupled to the next pages, after determining the selected pages of at least two of the four planes have passed the program verify operation, while performing the program operations and the program verify operations on the two remaining planes. | 2013-06-27 |
| 20130163336 | Erase Operation With Controlled Select Gate Voltage For 3D Non-Volatile Memory - An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles. | 2013-06-27 |
| 20130163337 | Erase Inhibit For 3D Non-Volatile Memory - An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test, then a one-sided erase of the remaining NAND strings is performed. The two-sided erase charges up the body of a NAND string from the source-side and drain-side ends, while the one-sided erase charges up the body of the NAND string from the drain-side end. The NAND strings associated with one bit line form a set. The switch to the one-sided erase can occur when the set meets a set erase-verify condition, such as one, all, or some specified portion of the NAND strings of the set passing the erase-verify test. The erase operation can end when no more than a specified number of NAND strings have not met the erase-verify test. As a result, erase degradation of the memory cells is reduced. | 2013-06-27 |
| 20130163338 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - Provided is a non-volatile semiconductor storage device including: a memory cell array where memory cells are arranged in a matrix shape; and a control unit which erases the memory cell by applying an erasing voltage to a well side of the memory cell and preliminarily erases the memory cell by applying a preliminary erasing voltage to the well side of the memory cell before the erasing while applying a voltage, which is higher than the voltage during the erasing, to a control gate electrode of the memory cell. | 2013-06-27 |
| 20130163339 | READING METHOD OF NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a first selection transistor, a second selection transistor, and a plurality of memory cells serially coupled between the first selection transistor and the second selection transistor. A reading method of the non-volatile memory device includes applying a read voltage to a gate of a selected memory cell; applying a first pass voltage to a gate of a memory cell adjacent to the selected memory cell, and applying a second pass voltage to gates of the other memory cells, wherein the selected memory cell is in one program state among first to T | 2013-06-27 |
| 20130163340 | NON-VOLATILE STORAGE SYSTEM WITH THREE LAYER FLOATING GATE - A non-volatile storage system includes memory cells with floating gates that comprises three layers separated by two dielectric layers (an upper dielectric layer and lower dielectric layer). The dielectric layers may be an oxide layers, nitride layers, combinations of oxide and nitride, or some other suitable dielectric material. The lower dielectric layer is close to the bottom of the floating gate (near interface between floating gate and tunnel dielectric), while the upper dielectric layer is close to top of the floating gate (near interface between floating gate and inter-gate dielectric). | 2013-06-27 |
| 20130163341 | MULTI-PASS PROGRAMMING IN A MEMORY DEVICE - A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a preprogram level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further. | 2013-06-27 |
| 20130163342 | PROGRAM TEMPERATURE DEPENDENT READ - Methods and non-volatile storage systems are provided for using compensation that depends on the temperature at which the memory cells were programmed. Note that the read level compensation may have a component that is not dependent on the memory cells' Tco. That is, the component is not necessarily based on the temperature dependence of the Vth of the memory cells. The compensation may have a component that is dependent on the difference in width of individual Vth distributions of the different states across different temperatures of program verify. This compensation may be used for both verify and read, although a different amount of compensation may be used during read than during verify. | 2013-06-27 |
| 20130163343 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - The semiconductor memory device includes a memory cell array that includes a plurality of cell strings coupled between a common source line and a plurality of bit lines, a peripheral circuit that reads data stored in a selected memory cell, a bouncing detection circuit that compares a voltage supplied to the common source line and a reference voltage to thereby output a detection signal while performing a reading operation, and a control circuit that controls the peripheral circuit in order to perform the reading operation by adjusting the number of sensing operation times in accordance with the detection signal. | 2013-06-27 |
| 20130163344 | PROGRAMMING TO MITIGATE MEMORY CELL PERFORMANCE DIFFERENCES - Methods for programming and memory devices are disclosed. In one such method for programming, a first programming voltage applied to control gates of a group of memory cells generates a maximum threshold voltage of the group of memory cell threshold voltages. A voltage difference between the maximum threshold voltage and a maximum target voltage is used as a gate step voltage for a second programming voltage. Fast and slow programming memory cells are determined from the distribution resulting from the second programming voltage. An effective gate voltage applied to the control gates of the fast programming memory cells is less than an effective gate voltage applied to the control gates of the slow programming memory cells during the third programming voltage. | 2013-06-27 |
| 20130163345 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device includes an operation of applying a first voltage to selected bit lines, a second voltage to unselected bit lines and a common source line, and turning on drain and source selection transistors, an operation of applying a program voltage to a selected word line and a switch voltage to a switch word line, and applying a first pass voltage to first unselected word lines disposed between the switch word line and a common source line and between the selected word line and a bit line, and elevating the switch voltage to generate hot electrons and inject the hot electrons to a selected memory cell of the selected word line to program the selected cell. | 2013-06-27 |
| 20130163346 | METHODS AND APPARATUSES FOR DETERMINING THRESHOLD VOLTAGE SHIFT - Apparatuses and methods for determining threshold voltage shift are described. A number of methods for determining threshold voltage shift in memory cells include determining changes in threshold voltage for memory cells at each data state of a first number of data states by searching threshold voltage data of memory cells programmed to the first number of data states and determining changes in threshold voltage for memory cells at each data state of a second number of data states by searching threshold voltage data of memory cells programmed to the second number of data states within a range of threshold voltages, wherein the range is shifted from a previous range based on the changes in threshold voltage for memory cells programmed to the first number of data states. | 2013-06-27 |
| 20130163347 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of repair fuse circuits configured to each program a repair target address; and an enable signal generation circuit configured to generate at least one enable signal in response to a source signal and provide the enable signal to each of the repair fuse circuits in common. Since the semiconductor device may iteratively generate a rupture enable signal through a feedback scheme, the area occupied by a circuit, such as a shift register or a D flip-flop may be saved. | 2013-06-27 |
| 20130163348 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device and a method for operating the same are provided relating to a nonvolatile memory device for sensing data using resistance change. The semiconductor device comprises a verification read control unit configured to sequentially output verification read data received from a sense amplifier into a global input/output line in response to a test signal, and a read data latch unit configured to store sequentially the verification read data received from the global input output line in response to a latch enable signal in activation of the test signal. | 2013-06-27 |
| 20130163349 | PROGRAMMING PULSE GENERATION CIRCUIT AND NON-VOLATILE MEMORY APPARATUS HAVING THE SAME - A program pulse generation circuit includes: a set pulse generator configured to apply a set pulse to an output node in response to a driving signal, a set pulse control signal, and a first switching signal, and a current controller configured to control step reductions forming the set pulse in response to the driving signal and a second switching signal. | 2013-06-27 |
| 20130163350 | LEVEL-SHIFT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A level-shift circuit with simpler circuit structure is provided. The level-shift circuit includes a first transistor in which a first power source potential is applied to a source electrode and a first gate electrode and a second power source potential is applied to a second gate electrode, and an inverter circuit to which a first input signal is applied and either a third power source potential or a potential obtained by subtracting an amount of change in the threshold voltage of the first transistor from the first power source potential is supplied as a power source voltage and from which a first output signal is output. A channel formation region of the first transistor is formed in an oxide semiconductor film. | 2013-06-27 |
| 20130163351 | DATA TRANSMISSION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A data transmission circuit includes first to fourth local lines, one or more first bit line sense amplifiers configured to correspond to the first local line, one or more second bit line sense amplifiers configured to correspond to the second local line, one or more third bit line sense amplifiers configured to correspond to the third local line, one or more fourth bit line sense amplifiers configured to correspond to the fourth local line, and a selection unit configured to select some first to fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to a first address in a first mode, and select some first and second bit line sense amplifiers or some third and fourth bit line sense amplifiers among the first to fourth bit line sense amplifiers in response to the first address and a second address in a second mode. | 2013-06-27 |
| 20130163352 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of repair fuse units configured to program repair target addresses respectively for repair target memory cells, wherein at least one of the repair fuse units is programmed with data information used for different purposes from the repair target addresses, a plurality of address comparison units each configured to compare an access target address with a corresponding address of the repair target addresses and determine whether to perform a repair operation or not, and a data transfer unit configured to transfer the data information to a corresponding circuit of the semiconductor memory device. | 2013-06-27 |
| 20130163353 | SEMICONDUCTOR DEVICE HAVING ODT FUNCTION - Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other. | 2013-06-27 |
| 20130163354 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a command delay section configured to delay a command signal applied through a command input pad by a parity delay amount in synchronization with an operating clock and output a parity command signal in a parity operation mode, wherein the command delay section is further configured to be controlled in response to an error determination signal, a command decoder configured to decode the parity command signal and transfer a resultant signal to a plurality of memory banks, and an error determination unit configured to determine whether an error has occurred in the command signal and generate an error determination signal. | 2013-06-27 |
| 20130163355 | MEMORY DEVICE - A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal. | 2013-06-27 |
| 20130163356 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of memory cells, a plurality of receivers, each of the plurality of receivers being provided for a corresponding one of a plurality of units set by dividing the plurality of memory cells in a unit, and each of the plurality of receivers receiving a test result of the corresponding one of the plurality of units, and a controller that reads out a plurality of test results from the plurality of receivers. | 2013-06-27 |
| 20130163357 | Quantifying the Read and Write Margins of Memory Bit Cells - Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells. | 2013-06-27 |
| 20130163358 | SYSTEMS, CIRCUITS, AND METHODS FOR CHARGE SHARING - Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines. | 2013-06-27 |
| 20130163359 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. The method includes performing an overall erase operation such that each threshold voltage of all memory cells connected to even word lines and odd word lines in a selected memory cell block are lower than a first target level, performing an erase operation such that each threshold voltage of the memory cells connected to the even word lines are lower than a second target level which is lower than the first target level, and performing an erase operation such that each threshold voltage of the memory cells connected to the odd word lines are lower than the second target level. | 2013-06-27 |
| 20130163360 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device and an operating method thereof comprise peripheral circuits configured to apply an erase voltage to memory cells when performing an erase operation, and sense a voltage change of bit lines by an erase verification voltage applied to word lines of the memory cells when performing an erase verification operation to thereby detect cells which are not erased, and a control circuit configured to control the peripheral circuits by changing a sensing reference level for determining the voltage change of the bit lines when the cells which are not erased are detected when performing the erase verification operation, so that the erase verification operation is repeatedly performed. | 2013-06-27 |
| 20130163361 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device comprises a first pair of signal lines and a first control circuit. The first control circuit precharges each of the first pair of signal lines to a first voltage in response to a precharge signal, and changes the voltage level of each of the first pair of signal lines to a second voltage different from the first voltage when a deep power down signal is input. | 2013-06-27 |
| 20130163362 | PRECHARGE CIRCUIT AND NON-VOLATILE MEMORY DEVICE - A precharge circuit includes a precharge unit configured to apply a voltage of a precharge voltage terminal to a data line during a precharge operation, and a sensing unit configured to disable the precharge unit by sensing the voltage of the precharge voltage terminal, The precharge circuit may control a precharge operation by sensing a change in the voltage level of the precharge voltage terminal. | 2013-06-27 |
| 20130163363 | SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES - Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them. | 2013-06-27 |
| 20130163364 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes a first semiconductor chip including a first pad group configured to input/output first data and a second pad group configured to input/output second data; and a second semiconductor chip in a stack with the first semiconductor chip and configured to be electrically connected to the first semiconductor chip by at least one chip through via, wherein the second semiconductor chip includes a first unit bank group including at least one first upper bank group and at least one first lower bank group, a second unit bank group including at least one second upper bank group and at least one second lower bank group, and a data path selector configured to electrically connect one among the first and second upper bank groups and the first and second lower bank groups with the chip through via. | 2013-06-27 |
| 20130163365 | SEMICONDUCTOR DEVICE HAVING HIGH-VOLTAGE TRANSISTOR - A semiconductor device includes a memory cell array having a plurality of memory cells respectively coupled to first and second bit lines, page buffers, and a bit line selection circuit including a plurality of selection circuit blocks configured to couple the first or second bit lines to the page buffers. A pair of the first and second bit lines is disposed in each of the plurality of selection circuits so that first bit lines of adjacent selection circuit blocks face each other, or second bit lines of adjacent selection circuit blocks face each other. | 2013-06-27 |
| 20130163366 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a delay locked loop configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generate a feedback clock signal by delaying the DLL clock signal by the second delay time, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal and an output enable control circuit configured to generate an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation. | 2013-06-27 |
| 20130163367 | CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE EMPLOYING THE SAME - A semiconductor memory device includes a first internal clock generation circuit configured to generate a first internal clock by compensating an external clock signal for a transfer delay thereof in the semiconductor memory device, a control voltage generation circuit configured to generate a control voltage in response to a profile selection signal, a second internal clock generation circuit configured to generate a second internal clock signal by delaying the first internal clock signal by a time corresponding to the control voltage, a selection output circuit configured to select one of the first internal clock signal and the second internal clock signal in response to a path selection signal and output a selected signal as a synchronization clock signal, and a data output circuit configured to output a data in synchronization with the synchronization clock signal. | 2013-06-27 |
| 20130163368 | APPARATUS AND PROCESS FOR MIXING RUBBER COMPOUNDS - A mixing apparatus for manufacturing a rubber compound is disclosed. The mixing apparatus comprises a plurality of multiple shaft extruder devices, each comprising at least one inlet for receiving a plurality of materials to be fed into the extruder device and an outlet for discharging a mixed material extruded by the extruder device. The multiple shaft extruder devices are either arranged in such a way that operatively the extrudate of at least one of the plurality of multiple shaft extruder devices can be fed into the inlet of at least one other of plurality of multiple shaft extruder devices, or are arranged to operate in parallel in such a way that operatively the extrudates of the plurality of multiple shaft extruder devices can be fed together into the inlet of at least one further mixing device. | 2013-06-27 |
| 20130163369 | KNEADING APPARATUS AND METHOD FOR PRODUCING THERMOPLASTIC RESIN MOLDED PRODUCT - A kneading apparatus includes a plasticizing cylinder in which a high pressure kneading zone and a pressure reduction zone are formed adjacently in this order from an upstream side so that a molten resin obtained by plasticizing a thermoplastic resin and a pressurized fluid are kneaded with each other in the high pressure kneading zone, and gasified pressurized fluid, which is gasified by reducing a resin internal pressure, is separated in the pressure reduction zone from the molten resin kneaded with the pressurized fluid, a screw which is arranged rotatably and movably back and forth in the plasticizing cylinder; and a downstream side seal mechanism which is provided between the high pressure kneading zone and the pressure reduction zone and which makes communication and disconnection between the high pressure kneading zone and the pressure reduction zone in accordance with a rotation state of the screw. | 2013-06-27 |
| 20130163370 | Mixing Device - A device for mixing liquid preparations. | 2013-06-27 |
| 20130163371 | SYSTEMS AND DEVICES FOR MIXING SUBSTANCES AND METHODS OF MAKING SAME - A mixing apparatus including a kinetic energy source, a mixing tank, a pivot guide, and transfer shaft is used to drive a mixing paddle through a circular path within a tank without substantial shaft rotation. Sleeved and sleeveless mixing paddles are provided in combination with sealable mixing tanks. A volumetric compensation system responsive to tank wall deflection is used to maintain the internal volume of a mixing tank within predetermined limits. One mixing apparatus includes multiple mixing shafts and paddles coupled to at least one kinetic energy source. Methods for fabricating sleeved paddle-containing mixing apparatuses are further provided. | 2013-06-27 |
| 20130163372 | SYSTEMS AND METHODS FOR DIFFUSING GAS INTO A LIQUID - Systems and methods for diffusing gas into a liquid are disclosed. In some cases, the methods include tangentially introducing a liquid into a cylindrical chamber having a cylindrical inner wall such that the liquid develops a spiral flow. In some cases, gas bubbles are orthogonally introduced into the liquid as the liquid flows through the chamber. In some cases, a flow of the liquid and the gas bubbles is controlled such that a ratio of a liquid flow rate to a gas bubble flow rate does not exceed values which convert non-bacteria enriched, clear water into froth. In such cases, a mixture of the liquid and the gas bubbles to exit the chamber near an output end. While the liquid can include clear water, in some instances, the liquid also includes bacteria (e.g., surfactant-producing or non-surfactant-producing bacteria) and/or bacterial nutrients that allow for improved bioremediation. | 2013-06-27 |
| 20130163373 | CONTINUOUS MIXER AND MIXING METHOD - A continuous mixer includes a barrel with a hollow interior, and a pair of mixing rotors housed in the barrel and that rotate in mutually different directions, each mixing rotor including a mixing portion with plural mixing flights formed about an axial center of the mixing rotor and projecting radially outward. The mixing rotors have a center distance therebetween smaller than a rotation outer diameter of each of the respective mixing flights. An inter-rotor clearance, which is the smallest clearance between the mixing portions at each rotation phase of the mixing rotors in a cross section perpendicular to axial directions of the both mixing rotors, has a dimension allowing an extensional flow to be generated in a material passing through the inter-rotor clearance. The continuous mixer can reliably and efficiently mix a material having a large viscosity difference between a dispersed phase and a matrix phase. | 2013-06-27 |
| 20130163374 | WATER-COUPLED UNDERWATER NODE FOR SEISMIC SURVEYS - A marine node for recording seismic waves underwater. The node includes a spherical body made of a material that has a density similar to a density of the water so that the body is buoyant neutral; a first sensor located in the body and configured to record three dimensional movements of the node; a second sensor located in the body and configured to record pressure waves propagating through the water; and one or more cables connected to the first and second sensors and configured to exit the body to be connected to an external device. The body is coupled to the water. | 2013-06-27 |
