26th week of 2013 patent applcation highlights part 22 |
Patent application number | Title | Published |
20130162277 | UNIFORM FIELD AREA TESTING APPARATUS AND TESTING METHOD USING SAME - A uniform field area (UFA) testing apparatus, used for an UFA test, including a testing rack and a plurality of field strength probes. The plurality of field strength probes are mounted on the testing rack. The plurality of field strength probes are positioned on a vertical plane and forms a probe grid array corresponding to the testing points of the UFA test, the grid spacing of the probe grid array corresponds to the distance of the neighboring testing points of the UFA test. | 2013-06-27 |
20130162278 | PROBE PIN, PROBE CARD USING THE PROBE PIN, AND METHOD OF MANUFACTURING THE PROBE CARD - There is provided a probe card, including: a substrate having a plurality of grooves formed in one surface thereof; and at least one probe pin having a plurality of substrate combining protrusions formed on one surface thereof and corresponding to the plurality of grooves, the plurality of substrate combining protrusions having heights corresponding to the plurality of grooves. | 2013-06-27 |
20130162279 | UNIVERSAL TEST SYSTEM FOR TESTING ELECTRICAL AND OPTICAL HOSTS - According to an example implementation, a universal tester includes a host interface slot connected to a first pluggable host card during an electrical test mode of operation to provide a stressed electrical signal to a host under test. The host interface slot is connected to a second pluggable host card during an optical test mode of operation, the second pluggable host card including an electrical-optical conversion block to convert a stressed electrical signal to a stressed optical signal that is provided to a host under test. A stressor generator may operation in pass-through mode or a loop-back mode. | 2013-06-27 |
20130162280 | PROBE CARD AND METHOD OF MANUFACTURING THE SAME - There are provided a probe card and a method of manufacturing the same, in which an electrode pad having a probe pin bonded thereto may be prevented from being delaminated from a substrate. The probe card according to embodiments of the present invention may include a ceramic substrate including at least one pad groove formed in one surface thereof and an electrode pad embedded in the pad groove; and a probe pin bonded to the electrode pad. | 2013-06-27 |
20130162281 | Probe Card and Fabricating Method Thereof - A probe card includes a circuit board and an integrated circuit (IC) test interface. The IC test interface includes a first probe assembly, disposed on a terminal of the circuit board, and a second probe assembly, disposed on another terminal of the circuit board, wherein the first probe assembly and the second probe assembly are separated to allow being independently assembled to, or disassembled from, the circuit board. Each of the first probe assembly and the second probe assembly includes a probe base, disposed on the circuit board; a plurality of needles, which are cantilever needles; and a covering layer, for covering the plurality of needles, and fixed on a surface of the probe base. | 2013-06-27 |
20130162282 | SEMICONDUCTOR DEVICE HAVING POTENTIAL MONITORING TERMINAL TO MONITOR POTENTIAL OF POWER-SUPPLY LINE - Disclosed herein is a device that includes an internal circuit, a first terminal supplied with a first voltage, a first power-supply line coupled between the first terminal and the internal circuit, a potential monitoring terminal, and a first switch coupled between the internal power-supply line and the potential monitoring terminal. | 2013-06-27 |
20130162283 | LUMINANCE TEST SYSTEM FOR LEDS - A test system for Light-emitting diodes (LEDs) includes a microcontroller, a plurality of light sensors, a plurality of shielding members and a display module. Each of the plurality of light sensors is connected to the microcontroller and each of LEDs. Each of the plurality of light sensors is capable of detecting luminance of the plurality of LEDs respectively. Each of the plurality of shielding members is configured to prevent light outside of each of the plurality of shielding members from interfering with light emitted from each of the LEDs inside of each of the plurality of shielding members. The microcontroller is adapted to read light intensities sensed by the plurality of light sensors according to a predetermined sequence and send the light intensities to the display module to display the light intensities in the predetermined sequence. | 2013-06-27 |
20130162284 | METHOD AND APARATUS FOR HIGH SIDE TRANSISTOR PROTECTION - A method and apparatus for detecting a high energy event in a transistor includes performing the steps of: monitoring a gate to source voltage of a transistor during transistor start up, continuously determining a derivative of the monitored gate to source voltage with respect to time, and detecting a high energy event when the derivative of the gate to source voltage exceeds a predetermined threshold. | 2013-06-27 |
20130162285 | Methods and Systems for Performing Scan Testing to Identify Logic Device Defects - Provided is a method of testing a logic device. The method includes comparing a first test pattern provided at an input of a first chain of logic device sub-modules with an output from the first chain to determine first type failures and comparing a second test pattern provided at an input of a second chain of logic device sub-modules with an out from the second chain to determine second type failures. An occurrence of one of the first type failures renders the logic device inoperable. An occurrence of the second type of failures is tolerated. | 2013-06-27 |
20130162286 | IMPEDANCE CODE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - An impedance code generation circuit includes an impedance code generation unit configured to generate an impedance code, a set value generation unit configured to generate a set value by counting an external signal, and an impedance code modification unit configured to generate a modified impedance code by performing a logic operation on the set value and the impedance code. | 2013-06-27 |
20130162287 | SEMICONDUCTOR PACKAGE INCLUDING MULTIPLE CHIPS AND MEMORY SYSTEM HAVING THE SAME - A package includes a master chip including a storage circuit configured to store an impedance setting of the master chip and an impedance setting of a slave chip, and a termination circuit for an impedance matching with an outside of the package, and the slave chip connected to the master chip, wherein if a termination operation for the slave chip is activated, the termination circuit of the master chip performs an impedance matching operation using the impedance setting for the slave chip. | 2013-06-27 |
20130162288 | TERMINATION CIRCUIT - A termination circuit includes: a pull-up termination unit configured to pull-up terminate an interface node in response to a pull-up signal; a pull-down termination unit configured to pull-down terminate the interface node in response to a pull-down signal; one or more pull-up resistors connected to the interface node and enabled to affect termination resistance in response to a pull-up setting value when a termination signal is activated; and one or more pull-down resistors connected to the interface node and enabled to affect termination resistance in response to a pull-down setting value when the termination signal is activated. | 2013-06-27 |
20130162289 | METHOD AND APPARATUS FOR CONFIGURING AN INTEGRATED CIRCUIT - A method and apparatus configures an integrated circuit by determining a multi-bit configuration value on a single node. The multi-bit configuration value is determined by using at least a voltage level at the single node and also by detecting a time to reach a voltage threshold level at the single node, based on a voltage ramp generation circuit. The method and apparatus also includes configuring an operation mode of a circuit in the integrated circuit based on the determined multi-bit configuration value from the single node. Multi-bit configuration values may be obtained on multiple single nodes in an integrated circuit. In one example, a voltage level is employed in addition to a time to reach a voltage threshold level whereas in another example a current level on a single node is utilized in combination with detection of a time to reach a voltage threshold level. | 2013-06-27 |
20130162290 | PARTIAL RECONFIGURATION CIRCUITRY - Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring a portion of a memory array. The PR circuitry may include a host circuit, a control circuit, an address register, and first, second, and third data registers. The host circuit may send a series of PR instructions to the control circuit. The control circuit may include a decompression circuit for decompressing compressed instructions, a decryption circuit for decrypting encrypted instructions, an error checking circuit for detecting errors in the instructions, and a logic circuit. The address register may select a desired frame. The selected frame may be loaded into the third data register. The contents of the third data register may be shifted into the first data register. The contents of the first data register may be modified according to a desired logic function using the logic circuit, shifted into the second data register, and written into the selected frame. | 2013-06-27 |
20130162291 | Configuration Context Switcher with a Latch - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 2013-06-27 |
20130162292 | NON-LUT FIELD-PROGRAMMABLE GATE ARRAYS - New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is an AND-Inverter Cone (AIC), which is a binary tree including one or more AND gates with a programmable conditional inversion and a number of intermediary outputs. Compared to LUTs, AICs are richer in terms of input and output bandwidth, because the area of the AICs grows only linearly with the number of inputs. Also, the delay grows only logarithmically with the input count. The new logic blocks can map circuits more efficiently than LUTs, because the AICs are multi-output blocks and can cover more logic depth due to the higher input bandwidth. | 2013-06-27 |
20130162293 | Soft Error Hard Electronics Layout Arrangement and Logic Cells - A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell. The method further includes connecting the combined logic integrated circuit cells, where the outputs of the combined integrated circuit cells provide the inputs for other combined circuit cells such that, when the output of the original logic integrated circuit from a first combined logic integrated circuit cell is connected as input to a second combined logic integrated circuit cell, then the output of the second circuit in the first combined logic integrated circuit cell is always also connected to the second combined logic integrated circuit cell serving as the inverse of the input signals that come from the original logic integrated circuit cell. | 2013-06-27 |
20130162294 | LEVEL SHIFT CIRCUIT AND DRIVE CIRCUIT OF DISPLAY DEVICE - In a level shift circuit, input signals are input into gates of a first and a second MOS transistors whose sources are coupled to a first supply voltage VSS. Gates of a third and a fourth MOS transistors whose sources are coupled to a second supply voltage are coupled to drains of the second and the first MOS transistors. A first voltage generation circuit is coupled between the drains of the first and the third MOS transistors, and a second voltage generation circuit is coupled between the drains of the second and the fourth MOS transistors. The gate of the fifth MOS transistor is coupled to a connection node NDB, and the source of the fifth MOS transistor is coupled to the second supply voltage. | 2013-06-27 |
20130162295 | CLOCK GENERATOR INTERMITTENTLY GENERATING SYNCHRONOUS CLOCK - A clock generator includes a counter unit receiving a reference clock signal to generate a timing signal, a selector receiving the timing signal to output a clock enable based on bit string data stored in a storage unit and a clock gate cell receiving the reference clock signal based on the clock, thinning some pulses out from the reference clock signal based on the clock enable so that a clock signal is maskable, and outputting an inter intermittent clock signal. | 2013-06-27 |
20130162296 | PEAK VOLTAGE DETECTOR AND RELATED METHOD OF GENERATING AN ENVELOPE VOLTAGE - A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor. | 2013-06-27 |
20130162297 | PEAK VOLTAGE DETECTOR AND RELATED METHOD OF GENERATING AN ENVELOPE VOLTAGE - A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor. | 2013-06-27 |
20130162298 | IDENTIFYING CIRCUIT - An identifying circuit is connected between a Universal Serial Bus (USB) interface and a controller. The identifying circuit includes first and second resistors, and a diode. When a power adapter is connected to the USB interface, a negative data pin of the USB interface is floating, an identify pin of the controller receives a high level signal to determine that the power adapter is connected to the USB interface. When a computer is connected to the USB interface, the negative data pin of the USB interface outputs a low level signal, the identify pin of the controller receives a low level signal to determine that the USB interface is connected to the computer. | 2013-06-27 |
20130162299 | Analog sample circuit with switch circuit - Techniques pertaining to an analog sample circuit are disclosed. One embodiment of the analog sample circuit shows characteristics of low distortion and high linearity, which can be used in many circuits including integrated circuits (IC). | 2013-06-27 |
20130162300 | HIGH SPEED SERIAL INPUT/OUTPUT BUS VOLTAGE MODE DRIVER WITH TUNABLE AMPLITUDE AND RESISTANCE - A device having a voltage mode driver with tunable amplitude and resistance that supports a predetermined output resistance and output amplitude is described herein. The voltage mode driver includes multiple configurable drivers. The voltage mode driver is controlled by a control module. Resistance tuning is controlled by the number of active configurable drivers and amplitude tuning is controlled by setting the high or low drive state of each active configurable driver. The slew rate of the device is controlled by delaying the setting of the high or low drive state of an active configurable driver by a predetermined interval. | 2013-06-27 |
20130162301 | LOW VOLTAGE LINE DRIVER - A line driver includes a transconductance stage that senses a differential voltage present at differential output nodes. The transconductance stage replicates a fraction of the differential voltage and generates a differential output current corresponding to the replicated differential voltage. The differential output current flows through a current mirror stage that mirrors the differential output current to the differential output nodes. The line driver thereby decouples the transconductance stage from the differential output nodes. A lower line driver voltage supply (e.g., 1.8 V) may therefore supply the differential output nodes. A transconductance stage voltage supply separate from the line driver voltage supply may provide the supply voltage for the transconductance stage. | 2013-06-27 |
20130162302 | SEMICONDUCTOR DEVICE HAVING DATA OUTPUT CIRCUIT IN WHICH SLEW RATE THEREOF IS ADJUSTABLE - Disclosed herein is a device that includes: a first circuit configured to operate on a first power voltage to produce a first set of slew rate control signals; a second circuit configured to operate on a second power voltage to produce a second set of slew rate control signals in response to the first set of slew rate control signals; and a third circuit configured to operate on the second power voltage to produce a signal at a rate that is controllable in response to the second set of slew rate control signals. | 2013-06-27 |
20130162303 | PROPORTIONAL BIAS SWITCH DRIVER CIRCUIT WITH CURRENT TRANSFORMER - A switch bias system is provided that includes a bipolar junction transistor (BJT) switch comprising a base, emitter, and collector; an energy storage circuit coupled to the collector of the BJT, the energy storage circuit supplying current flow to the collector of the BJT; a current transformer circuit coupled to the emitter, the current transformer circuit configured to sense current flow through the emitter of the BJT switch; and a proportional bias circuit configured to generate a bias current to the base of the BJT switch, the bias current set to a proportion of the sensed current flow through the emitter of the BJT switch. | 2013-06-27 |
20130162304 | Gate Line Driver Capable Of Controlling Slew Rate Thereof - A gate line driver including an output buffer configured to receive a driving signal and output a driving voltage, and a slew rate controller including at least one capacitor and a switch connected in series to the at least one capacitor, the switch configured to selectively, electrically connect the at least one capacitor between an input terminal and an output terminal of the output buffer according to a slew rate control signal to control a slew rate of the output buffer. | 2013-06-27 |
20130162305 | SEMICONDUCTOR DEVICE, IMAGE DISPLAY DEVICE, STORAGE DEVICE, AND ELECTRONIC DEVICE - To provide a semiconductor device with reduced power consumption that includes a selection transistor. To provide a semiconductor device capable of high-speed operation without increasing a power supply potential. A buffer circuit connected to a gate line has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential in response to a selection signal. Specifically, a bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side in the buffer circuit. Further, the bootstrap circuit boosts the potential when the gate line is selected, and does not boost the potential when the gate line is not selected. | 2013-06-27 |
20130162306 | METHOD FOR DRIVING SEMICONDUCTOR DEVICE - Provided is a method for driving a semiconductor device, which allows a reduction in scale of a circuit, reduce the power consumption, and increase the speed of reading data. An H level (data “1”) potential or an L level (data “0”) potential is written to a node of a memory cell. Potentials of a source line and a bit line are set to the same potential at an M level (L level2013-06-27 | |
20130162307 | HIGH VOLTAGE LINEAR AMPLIFIER DRIVING HEAVY CAPACITIVE LOADS WITH REDUCED POWER DISSIPATION - A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down. | 2013-06-27 |
20130162308 | SEMICONDUCTOR DEVICE THAT CAN ADJUST PROPAGATION TIME OF INTERNAL CLOCK SIGNAL - Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal. | 2013-06-27 |
20130162309 | RECEIVING CIRCUIT - Disclosed is a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a correction circuit correcting the two input data selected by the data selection circuit; a phase detection circuit detecting a phase at which the level of input data changes as a boundary phase in the one unit interval, based on the two input data corrected by the correction circuit; an arithmetic unit calculating the center phase, based on the boundary phase detected by the phase detection circuit; and data decision circuit determining and outputting the level of one of the two input data, based on the center phase and the boundary phase, the correction circuit implements the correction based on a correction value corresponded to the past data level output by the data decision circuit. | 2013-06-27 |
20130162310 | CLOCK GENERATOR WITH INTEGRATED PHASE OFFSET PROGRAMMABILITY - A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit. | 2013-06-27 |
20130162311 | FILTERING CIRCUIT, PHASE IDENTITY DETERMINATION CIRCUIT AND DELAY LOCKED LOOP - A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock. | 2013-06-27 |
20130162312 | DELAY LOCKED LOOP - A delay locked loop in accordance with some embodiments of the inventive concept may include a delay signal generation part generating a first delay signal having a first phase and a second delay signal having a second phase by delaying a reference signal on the basis of a delay control signal; a phase synthesizing part generating at least one third signal having a third phase using the first delay signal and the second delay signal; and a phase detection part generating a control code by comparing the reference signal with each of the first delay signal, the second delay signal and the third signal. | 2013-06-27 |
20130162313 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first structural body including a first temperature voltage generation unit configured to generate first and second temperature voltages which have different voltage level variations according to a temperature variation, in response to a temperature measurement command, and a first temperature information determination unit configured to generate first temperature information depending on a difference between levels of the first and second temperature voltages; and a second structural body including a second temperature voltage generation unit configured to generate a third temperature voltage and a fourth temperature voltage which have different voltage level variations according to a temperature variation, when a predetermined time elapses after the first and second temperature voltages are generated from the first structural body, and a second temperature information determination unit configured to generate second temperature information depending on a difference between levels of the third and fourth temperature voltages. | 2013-06-27 |
20130162314 | SIGNAL OUTPUT CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A signal output circuit includes a signal transfer unit configured to transfer a signal of a first line to a pull-up line during an activation period of a first clock, transfer the signal of the first line to a pull-down line during a deactivation period of a second clock, transfer a signal of a second line to the pull-up line during a deactivation period of the first clock, and transfer the signal of the second line to the pull-down line during an activation period of the second clock; and an output driving unit configured to pull-up drive an output node in response to a signal of the pull-up line and pull-down drive the output node in response to a signal of the pull-down line, wherein the first clock and the second clock have the activation periods longer than the deactivation periods. | 2013-06-27 |
20130162315 | SIGNAL TRANSMISSION/RECEPTION SYSTEM - A signal transmission/reception system includes a transmission line, a signal transmission circuit configured to generate a transfer signal and transfer the transfer signal through the transmission line, wherein a logic value of the transfer signal is changed whenever a pulse signal is input to the signal transmission circuit, and a signal reception circuit configured to receive the transfer signal through the transmission line and generate a restoration signal using the transfer signal and a delayed transfer signal obtained by delaying the transfer signal. | 2013-06-27 |
20130162316 | PULSE GENERATION CIRCUIT, BURST ORDER CONTROL CIRCUIT, AND DATA OUTPUT CIRCUIT - A pulse generation circuit includes a control unit configured to activate one or more of control clocks among a plurality of control clocks, and to activate one or more of select signals among a plurality of select signals, in response to one or more of sequence signals; a plurality of shifting units each configured to generate one or more of output signals, and to sequentially activate the one or more of output signals by shifting an input pulse when a corresponding control clock among the plurality of control clocks is activated; and a signal transfer unit configured to transfer one or more of output signals of a shifting unit corresponding to an activated select signal among the plurality of shifting units, as one or more of pulses. | 2013-06-27 |
20130162317 | SYSTEM AND METHOD FOR PROCESSING SIGNAL - A system for processing signals includes an original wave outputting module, a signal sampling module and a signal processing module. The signal processing module includes an SCM, an FGPA chip and an amplifier electrically connected to the SCM. The original wave outputting module outputs an originating wave. The signal sampling module samples the wave, and outputs a plurality of signals. The signal processing module receives the plurality of signals, and outputs an amplified wave. The SCM has a predetermined wave frequency value and a predetermined wave amplitude value. The FGPA chip generates digital signals according to the predetermined wave frequency value. The amplifier amplifies the digital signals according to the predetermined wave amplitude value. | 2013-06-27 |
20130162318 | DIFFERENTIAL OUTPUT CIRCUIT - A differential output circuit is controlled according to its mode of operation. While in the first mode, the differential output circuit controls a current flow through a variable current source according to an impedance of the variable current source, and while in the second mode, the differential output circuit compares a voltage at a monitored node and a reference voltage and controls the current flow through the variable current source to make the voltage at the monitored node to be equal to the reference voltage. | 2013-06-27 |
20130162319 | Active Hybrids for Antenna System - In various embodiments, a differential phase generating hybrid can comprise a first input port in communication with a first active splitter, a second input port in communication with a second active splitter, a first active combiner that can be configured to receive a first signal from the first active splitter and a second signal from the second active splitter. The differential phase generating hybrid can further comprise a second active combiner that can be configured to receive the first signal from the first active splitter and the second signal from the second active splitter. The differential phase generating hybrid can further comprise a first output port to provide a first composite signal from the first active combiner, and a second output port to provide a second composite signal from the second active combiner. The size of the differential phase generating hybrid can be independent of an operating frequency. | 2013-06-27 |
20130162320 | COUPLING ARRANGEMENT FOR PHANTOM-MODE TRANSMISSION - In accordance with an embodiment, the coupling arrangement includes adders for adding a common-mode signal to a differential-mode signal and amplification units for individually and evenly amplifying input signals present on their input terminals, thereby yielding amplified common-and-differential-mode signals. Coupling units with capacitive coupling are configured to pass the amplified common-and-differential-mode signals towards a wire pair. | 2013-06-27 |
20130162321 | SEMICONDUCTOR DEVICE - A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit. | 2013-06-27 |
20130162322 | HIGH SPEED LOW LOSS GATE DRIVE CIRCUIT - A gate drive circuit includes an insulated gate semiconductor switch. A controlled current source is connected to the semiconductor switch gate terminal to provide a gate drive circuit that is responsive to recycled gate charge corresponding to an internal gate capacitance of the insulated gate semiconductor switch. | 2013-06-27 |
20130162323 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a clear period, transistors NT | 2013-06-27 |
20130162324 | CONTROL CIRCUIT FOR CONNECTOR - A circuit for controlling a connector to transmit data according to Low Pin Count (LPC) protocol or Joint Test Action Group (JTAG) protocol includes a switch unit, first and second electronic switches, and first and second switch chips. When the switch unit outputs a high level signal to the first electronic switch, the connector transmits data according to LPC protocol. When the switch unit outputs a low level signal to the first electronic switch, the connector transmits data according to JTAG protocol. | 2013-06-27 |
20130162325 | SWITCHING CIRCUIT - A switching circuit suitable for a low power oscillator circuit includes control and output circuits, the control circuit arranged to control the output circuit, the control circuit having input and output terminals, the output circuit having input and output terminals and control terminals; wherein the input terminal of the control circuit is connected to the input terminal of the output circuit, and the control terminal of the output circuit is connected to the output terminal of the control circuit, the output circuit first switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time, and the control circuit has second switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time. | 2013-06-27 |
20130162326 | HIGH-VOLTAGE SWITCH USING THREE FETS - Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal. | 2013-06-27 |
20130162327 | METHOD AND SYSTEM FOR REDUCTION OF OFF-CURRENT IN FIELD EFFECT TRANSISTORS - A method for reducing an off-current of a field effect transistor in which two electrodes of the field effect transistor have fixed voltage values and the rest electrode has an alternating voltage value by an AC voltage pulse generator to form an off-stress near source and drain junctions in turn. | 2013-06-27 |
20130162328 | TOUCH PANEL AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a touch panel and a method for manufacturing the same. The touch panel | 2013-06-27 |
20130162329 | ANTI-FUSE CIRCUIT AND FUSE REPTURE METHOD THEREOF - An anti-fuse circuit includes a control block configured to generate a first control signal and a second control signal in response to a first test signal and a second test signal, and a fuse set block configured to perform a primary fuse rupture operation in response to the first control signal and to perform a secondary fuse rupture operation in response to the second control signal, the fuse set block activating a fuse signal if any one of the primary fuse rupture operation and the secondary fuse rupture operation succeeds. | 2013-06-27 |
20130162330 | PHOTO CELL DEVICES FOR PHASE-SENSITIVE DETECTION OF LIGHT SIGNALS - Embodiments relate to photo cell devices. In one embodiment, a trench-based photo cells provides very fast capture of photo-generated charge carriers, particularly when compared with conventional approaches, as the trenches of the photo cells create depleted regions deep within the bulk of the substrate that avoid the time-consuming diffusion of carriers. | 2013-06-27 |
20130162331 | DIODE STRING VOLTAGE ADAPTER - A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated. | 2013-06-27 |
20130162332 | INTEGRATED CIRCUITS WITH REDUCED VOLTAGE ACROSS GATE DIELECTRIC AND OPERATING METHODS THEREOF - An integrated circuit includes a first pad configured to carry a signal, a first receiver having an input node, a second receiver having an input node, a first pass gate, and a second pass gate. The first pass gate is coupled between the first pad and the input node of the first receiver. The first pass gate is configured to be turned on when the signal on the first pad is greater than a first voltage level. The second pass gate is coupled between the first pad and the input node of the second receiver. The second pass gate is configured to be turned on when the signal on the first pad is less than a second voltage level. | 2013-06-27 |
20130162333 | Apparatus and associated methods - An apparatus including first and second layers of electrically conductive material separated by a layer of electrically insulating material, wherein one or both layers of electrically conductive material include graphene, and wherein the apparatus is configured such that electrons are able to tunnel from the first layer of electrically conductive material through the layer of electrically insulating material to the second layer of electrically conductive material. | 2013-06-27 |
20130162334 | NEGATIVE CHARGE PUMP - Generally, this disclosure provides negative charge pump circuitry that is configured to supply a voltage that is less than a reference voltage (such as ground). The charge pump circuitry includes blocking circuitry that reduces or eliminates charge leakage so that a negative voltage may be developed at the output. The charge pump circuitry generally includes complimentary pairs of MOS switches that switch in a complimentary fashion according to charge developed on complimentary capacitors to provide a negative voltage power supply. | 2013-06-27 |
20130162335 | CHARGE PUMPING APPARATUS USING OPTIMUM POWER POINT TRACKING AND METHOD THEREOF - A charge pumping apparatus includes a voltage pumping unit for pumping an input voltage, a voltage pumping control unit for controlling the voltage pumping unit according to a comparison result between the input voltage and an input criterion voltage and a comparison result between an output voltage output from the voltage pumping unit and an output criterion voltage, and an optimum power point tracking unit for tracking an optimum power point in the case of detecting that the output voltage decreases lower than the output criterion voltage, and adjusting an input impedance to change the input criterion voltage to a voltage corresponding to the optimum power point, wherein the optimum power point is a power point where an input power according to the input voltage becomes a maximum. Since the optimum power point is tracked by measuring only a voltage without a current sensor, a power loss is small. | 2013-06-27 |
20130162336 | Time-Multiplexed-Capacitor DC/DC Converter With Multiple Outputs - A multiple output DC-to-DC voltage converter using a new time-multiplexed-capacitor converter algorithm and related circuit topologies is herein disclosed. One embodiment of this invention includes a flying capacitor, a first output node, a second output node, and a switching network. The switching network configured to provide the following modes of circuit operation: 1) a first mode where the positive electrode of the flying capacitor is connected to an input voltage and the negative electrode of the flying capacitor is connected to ground; 2) a second mode where the negative electrode of the flying capacitor is connected to the input voltage and the positive electrode of the flying capacitor is connected to the first output node; and 3) a third mode where the positive electrode of the flying capacitor is connected to ground and the negative electrode of the flying capacitor is connected to the second output node. | 2013-06-27 |
20130162337 | CHARGE PUMP CIRCUIT AND POWER-SUPPLY METHOD FOR DYNAMICALLY ADJUSTING OUTPUT VOLTAGE - A charge pump circuit and power-supply method for dynamically adjusting output voltage is related to the charge pump circuit having three power-supply modes with different power conversion efficiencies. When supplying power, a pump unit controls the electrical connecting relations of a first flying capacitor, second flying capacitor, first storage capacitor and second storage capacitor through a first clock and second clock with non-overlapping working phases, to convert a source voltage into a positive output voltage and negative output voltage, thereby providing one of the three power-supply modes. | 2013-06-27 |
20130162338 | TUNABLE TRANSCONDUCTANCE-CAPACITANCE FILTER WITH COEFFICIENTS INDEPENDENT OF VARIATIONS IN PROCESS CORNER, TEMPERATURE, AND INPUT SUPPLY VOLTAGE - A transconductance-capacitance (G | 2013-06-27 |
20130162339 | CURRENT COMPENSATING DEVICE - A compensating device is used for providing current compensation of an IC when operating in the high-voltage. The current compensating device includes a detecting unit, a rectifier, a filtering unit and a switching unit. The detecting unit electrically connected to an AC voltage. The rectifier is electrically connected to the detecting unit. The filtering unit is electrically connected to the rectifier. The switching unit is electrically connected to the filtering unit. The switching unit is conducted and provides a current to the IC when the AC voltage is above a predetermined voltage. | 2013-06-27 |
20130162340 | MULTI-CHIP PACKAGE - A multi-chip package includes a single lead and a plurality of inner package chips. Each of the plurality of inner package chips includes at least one pad circuit and an internal circuit. The pad circuit is selectively coupled to the lead and configured to provide a chip address signal corresponding to a connection state to the lead. The inner package chip receives the chip address signal to identify a corresponding inner package chip. | 2013-06-27 |
20130162341 | AUTO-CALIBRATING A VOLTAGE REFERENCE - A method and circuitry for determining a temperature-independent bandgap reference voltage are disclosed. The method includes determining a quantity proportional to an internal series resistance of a p-n junction diode and determining the temperature-independent bandgap reference voltage using the quantity proportional to an internal series resistance. | 2013-06-27 |
20130162342 | REFERENCE VOLTAGE GENERATOR OF SEMICONDUCTOR INTEGRATED CIRCUIT - A reference voltage generation circuit for a semiconductor integrated circuit includes a first reference voltage generation unit configured to generate a reference voltage in mode other than a self-refresh mode, and a second reference voltage generation unit configured to additionally drive an output terminal of the first reference voltage generation unit in an initial reference voltage setting period. | 2013-06-27 |
20130162343 | INTEGRATED CIRCUIT SYSTEM - An integrated circuit system includes a first chip including a first node and configured to generate first identification information indicating the first chip in response to a voltage of the first node, a second chip including a second node and configured to generate second identification information indicating the second chip in response to a voltage of the second node, and a channel connected to the first node and the second node and generate a voltage difference between the first node and the second node. | 2013-06-27 |
20130162344 | DISTRIBUTED LC RESONANT TANKS CLOCK TREE SYNTHESIS - A technique for implementing an clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption. | 2013-06-27 |
20130162345 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING A POWER CONTROLLABLE REGION - A semiconductor integrated circuit capable of testing power control operation in the semiconductor integrated circuit includes a power controllable region. Power control switches have switch series each constituted by a plurality of switch cells. A power controllable region includes output nodes in the switch series. The output nodes output power control signals that have passed through final stages of the respective switch series of the power control switches to outside the power controllable region. A chip on which the semiconductor integrated circuit is mounted has output terminals that output outputs of the output nodes to outside of the chip. When inserting a scan path test, observation flip-flops that load the outputs of the output nodes to data terminals, and load scan data to scan-in terminals are disposed in correspondence with the respective output nodes. Those observation flip-flops are connected to constitute a scan path chain. | 2013-06-27 |
20130162346 | INTERCONNECTION DEVICE IN A MULTI-LAYER SHIELDING MESH - An integrated circuit (IC) comprising a shielding mesh in at least one layer of the IC, the shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage and wherein the shielding mesh comprises a window in which signal lines are routed with less shielding than signal lines which are routed in the shielding mesh. The IC further comprising power supply lines in at least a first layer of the IC, the first layer being different than the at least one layer which contains the shielding mesh, the power supply lines being coupled to the shielding mesh and being larger in width than the first plurality of lines and the second plurality of lines. | 2013-06-27 |
20130162347 | IDENTIFYING CIRCUIT - An identifying circuit is connected between a Universal Serial Bus (USB) interface and a controller. The identifying circuit includes first to fourth electronic switches. When a power adapter connects to the USB interface, the first and fourth electronic switches are not turned on, and the second and third electronic switches are turned on. An identification pin of the controller receives a low level signal and determines that the power adapter connects to the USB interface. When a computer connects to the USB interface, the first and fourth electronic switches are turned on, and the second and third electronic switches are not turned on. The identification pin receives a high level signal and determines that the computer is connected to the USB interface. | 2013-06-27 |
20130162348 | ADAPTIVE PREDISTORTION FOR A NON-LINEAR SUBSYSTEM BASED ON A MODEL AS A CONCATENATION OF A NON-LINEAR MODEL FOLLOWED BY A LINEAR MODEL - Systems and methods for compensating for non-linearity of a non-linear subsystem using predistortion are disclosed. In one embodiment, a system includes a non-linear subsystem and a predistorter configured to effect predistortion of an input signal of the non-linear subsystem such that the predistortion compensates for a non-linear characteristic of the non-linear subsystem. The system also includes an adaptor that adaptively configures the predistorter based on a feedback signal that is representative of an output signal of the non-linear subsystem and an input signal that is representative of the input signal of the non-linear subsystem. The adaptor generally models the non-linear subsystem as a concatenation of a non-linear model that corresponds to the non-linear characteristic of the non-linear subsystem and a linear model that corresponds to a known linear characteristic of the non-linear subsystem. | 2013-06-27 |
20130162349 | Look-Up-Table Digital Predistortion Technique for High-Voltage Power Amplifiers in Ultrasonic Applications - The present invention includes a digital controller for use with an ultrasound power amplifier circuit to increase linearity and efficiency of the ultrasound power amplifier circuit. The digital controller includes a digital signal generator and a memory unit that is coupled to the digital signal generator. The memory unit includes a processor that obtains an output signal from the ultrasound power amplifier circuit, calculates error by obtaining a difference between an ideal output signal and the output signal that is obtained from the ultrasound power amplifier circuit, and equalizes an input signal from the digital signal generator to reduce nonlinearity in the output signal of the ultrasound power amplifier circuit. The memory unit includes a look-up-table for storing values of error. | 2013-06-27 |
20130162350 | POWER AMPLIFIER - There is provided a power amplifier capable of increasing linear output power and efficiency without sacrificing an overall gain by employing a vector modulation function in a driving stage, with no separate vector modulator. The power amplifier includes a driving stage performing vector-modulation on an input RF signal to provide an I channel signal and a Q channel signal having different phases and amplifying the I channel signal and the Q channel signal to set gains; and a power stage amplifying power levels of the signals amplified by the driving stage. | 2013-06-27 |
20130162351 | POWER AMPLIFIER AND LIQUID JET PRINTING APPARATUS - A power amplifier includes: a modulator pulse-modulating a drive waveform signal serving as a reference of a drive signal applied to an actuator and outputting a plurality of modulated signals; a digital power amplifier having a plurality of digital power amplifier stages each including a pair of push-pull switching elements, amplifying the power of the plurality of modulated signals, and outputting multi-value amplified digital signals; and a low pass filter smoothing the amplified digital signals and outputting the drive signal, wherein the modulator includes a control section switching one of a state where the same modulated signal is connected to two or more of the digital power amplifier stages and a state where different modulated signals are connected to different digital power amplifier stages to the other. | 2013-06-27 |
20130162352 | DIFFERENTIAL POWER MANAGEMENT AND POWER AMPLIFIER ARCHITECTURE - Embodiments of the present disclosure relate to radio frequency (RF) transmitter circuitry, which includes non-inverting path power amplifier (PA) circuitry, inverting path PA circuitry, and RF transformer circuitry. The non-inverting path PA circuitry provides a non-inverting RF signal and a first power supply (PS) signal to the RF transformer circuitry, such that the first PS signal has a first ripple voltage. The inverting path PA circuitry provides an inverting RF signal and a second PS signal to the RF transformer circuitry, such that the second PS signal has a second ripple voltage. The RF transformer circuitry additively combines the non-inverting RF signal and the inverting RF signal to provide an RF output signal, such that effects of the first ripple voltage and the second ripple voltage are substantially cancelled from the RF output signal. | 2013-06-27 |
20130162353 | SIGNAL AMPLIFICATION CIRCUIT - A signal amplification circuit includes a differential amplifier configured to receive a first signal and a second signal and generate an output signal, a differential amplifier configured to receive first and second signals and generate an output signal; and a controller configured to control an amount of current flowing in the differential amplifier using the output signal. | 2013-06-27 |
20130162354 | CASCODE AMPLIFIER - A slew rate booster, switchably enabled selector, or other arrangement may be included in a cascode amplifier to keep the current buffer/common gate transistor and the input/common source transistor saturated as the voltage at the source of the current buffer transistor drops during a transient input voltage spike at the gate of the input transistor. In some instances a higher potential may be supplied to a gate of the current buffer transistor during an initial phase of the settling period than during a second phase of the settling period when a lower potential may be applied. Other techniques may be used in different embodiments. Devices and methods are provided. | 2013-06-27 |
20130162355 | PHASE-LOCK IN ALL-DIGITAL PHASE-LOCKED LOOPS - This disclosure relates to an all digital phase-lock loop (ADPLL). The ADPLL determines an error generated by a digitally controlled oscillator (DCO) which is operated using a tuning word, stores information related to the error, and compensates for the error based on the stored information. | 2013-06-27 |
20130162356 | METHODS AND APPARATUS FOR OSCILLATOR FREQUENCY CALIBRATION - In one general aspect, an apparatus can include a phase frequency detector configured to produce a plurality of indicators of relative differences between a frequency of a target oscillator signal and a frequency of a reference oscillator signal. The apparatus can also include a pulse generator configured to produce a plurality of pulses based on the plurality of indicators. The plurality of pulses can include a first portion configured to trigger an increase in the frequency of the target oscillator signal and the plurality of pulses including a second portion configured to trigger a decrease in the frequency of the target oscillator signal. | 2013-06-27 |
20130162357 | OSCILLATOR WITH HIGHLY-ADJUSTABLE BANG-BANG CONTROL - A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal. | 2013-06-27 |
20130162358 | REFERENCE CURRENT GENERATOR CIRCUIT - One aspect of the present invention includes a reference current generator circuit. The circuit includes a bias circuit configured to generate a reference current along a first current path and a second current along a second current path. The reference current and the second current can be proportional. The circuit also includes a first pair of transistors connected in series and configured to conduct the reference current in the first current path. The circuit further includes a second pair of transistors connected in series and configured to conduct the second current in the second current path. The second pair of transistors can be coupled to the first pair of transistors to provide a collective resistance value of the second pair of transistors that is proportional to temperature. | 2013-06-27 |
20130162359 | FREQUENCY JITTER CIRCUIT AND METHOD - An oscillator generates a clock signal according to a voltage, a current and a capacitance, and a frequency jitter circuit and method use a random number to modulate the voltage, the current or the capacitance, or a count value to modulate the capacitance, to jitter the frequency of the clock signal. | 2013-06-27 |
20130162360 | PIEZOELECTRIC OSCILLATOR AND TRANSMITTER - A piezoelectric oscillator includes: a piezoelectric resonator element having a piezoelectric substrate and an excitation electrode formed on a surface of the piezoelectric substrate; a semiconductor circuit element provided with an oscillation circuit for oscillating the piezoelectric resonator element and having a first insulating film formed on a principal surface; a package for airtightly housing the semiconductor circuit element and the piezoelectric resonator element; and a protruding section having at least of a thin film circuit component formed on the first insulating film and connected to the oscillation circuit; and a second insulating film formed on the first insulating film and covering the thin film circuit component. In the oscillator, the piezoelectric resonator element is fixed to an upper surface of the protruding section. | 2013-06-27 |
20130162361 | OSCILLATOR CIRCUIT AND METHOD FOR GENERATING AN OSCILLATION - The invention relates to an oscillator circuit, comprising a clipping element for generating a clipped signal, and a first amplification stage for amplifying and filtering the clipped signal to obtain a filtered signal, wherein the clipping element is configured to generate the clipped signal upon the basis of the filtered signal. | 2013-06-27 |
20130162362 | SURFACE MOUNT PIEZOELECTRIC OSCILLATOR - A surface mount piezoelectric oscillator includes a piezoelectric resonator with a container main body, a plurality of external terminals, a mounting board with an IC chip, a plurality of connecting terminals, and a solder ball. The solder ball bonds the plurality of external terminals and the plurality of connecting terminals by melting and hardening. The solder bonding portion has approximately a circular shape with approximately a same size as a size of the connecting terminal of the mounting board. The solder ball placed on the connecting terminal of the mounting board is melted, self-aligned, and hardened so as to form a solder fillet of nearly axial symmetry. The solder fillet bridges between the both electrodes and bonds the connecting terminal of the mounting board and the solder bonding portion of the external terminal of the piezoelectric resonator. | 2013-06-27 |
20130162363 | MODULATOR, MIXER AND METHOD FOR AMPLITUDE SHIFT KEYING MODULATION - An ASK modulator includes a baseband unit which obtains a sequence comprising at least one amplitude value and adds an additional value to each of the at least one amplitude value to generate a modified sequence; a digital-to-analog converter coupled to the baseband unit, the digital-to-analog converter converts the modified sequence to generate a first signal, the additional value is determined based on a half scale of the digital-analog converter; and a mixer which receives the first signal and a second signal and generate a modulated signal by mixing the first signal with the second signal. | 2013-06-27 |
20130162364 | PRINTED CIRCUIT BOARD - A printed circuit board includes an outer signal layer, a first ground layer, a first ground layer located below the outer signal layer, an inner signal layer located below the first ground layer, an second ground layer located below the inner signal layer, and a first differential signal transmission pair and a second differential signal transmission pair laid on the outer signal layer and the inner signal layer. A value h is equal to a distance between the inner signal layer and its closest ground layer. A distance between the first pair and the second pair is not more than h×3. | 2013-06-27 |
20130162365 | Calibration of a Resonance Frequency Filter - Calibrating a frequency filter includes applying a series of input electrical signals at different frequencies to a shock sensor, using circuitry to identify a particular one of the frequencies as a resonance frequency of the shock sensor based on responses of the shock sensor to the series of input signals, and setting a center frequency of the notch filter equal to the particular frequency identified as the resonance frequency of the shock sensor. | 2013-06-27 |
20130162366 | WIDEBAND, DIFFERENTIAL SIGNAL BALUN FOR REJECTING COMMON MODE ELECTROMAGNETIC FIELDS - Provided are assemblies and processes for efficiently coupling wideband differential signals between balanced and unbalanced circuits. The assemblies include a broadband balun having an unbalanced transmission line portion, a balanced transmission line portion, and a transition region disposed between the unbalanced and balanced transmission line portions. The unbalanced transmission line portion includes at least one ground and a pair of conductive signal traces, each isolated from ground. The balanced portion does not include an analog ground. The transition region effectively terminates the analog ground, while also smoothly transitioning or otherwise shaping transverse electric field distributions between the balanced and unbalanced portions. Beneficially, the balun is free from resonant features that would otherwise limit operating bandwidth, allowing it to operate over a wide bandwidth of 10:1 or greater. Assemblies can include RF chokes with back-to-back baluns, and other elements, such as balanced filters, and also can be implemented as integrated circuits. | 2013-06-27 |
20130162367 | CIRCUIT SUBSTRATE - A circuit substrate includes: a laminate substrate in which a conductive layer and an insulating layer are laminated; a filter chip that has an acoustic wave filter and is provided inside of the laminate substrate; and a chip component that is provided on a surface of the laminate substrate and is connected to the filter chip, at least a part of the chip component overlapping with a projected region that is a region of the filter chip projected in a thickness direction of the laminate substrate. | 2013-06-27 |
20130162368 | LADDER-TYPE SURFACE ACOUSTIC WAVE FILTER AND DUPLEXER INCLUDING THE SAME - A ladder-type surface acoustic wave filter includes a first series resonator having the lowest resonance frequency among a plurality of series resonators; and a second series resonator having a resonance frequency higher than the first series resonator. The film thickness of a dielectric film in the region where the first series resonator is formed is larger than that of a dielectric film in the region where the second series resonator is formed. | 2013-06-27 |
20130162369 | THIN-FILM BULK ACOUSTIC WAVE DELAY LINE - A thin-film bulk acoustic wave delay line device providing true-time delays and a method of fabricating same. An exemplary device can comprise several thin-film layers including thin-film transducer layers, thin-film delay layers, and stacks of additional thin-film materials providing acoustic reflectors and matching networks. The layer material selection and layer thicknesses can be controlled to improve impedance matching between transducers and the various delay line materials. For example, the transducer layers and delay layers can comprise piezoelectric and amorphous forms of the same material. The layers can be deposited on a carrier substrate using standard techniques. The device can be configured so that mechanical waves propagate solely within the thin films, providing a substrate-independent device. The device, so constructed, can be of a small size, e.g. 40 μm per side, and capable of handling high power levels, potentially up to 20 dBm, with low insertion loss of approximately 3 dB. | 2013-06-27 |
20130162370 | SYSTEMS AND METHODS FOR PROVIDING AN ELECTRIC CHOKE - Systems and methods for an electric choke are provided. The choke may be provided as part of a power transmission arrangement that includes a cable for electrically coupling a power source and a powered device having a ground node and a wire separate from the cable providing a path for a common-mode current through the ground node. The power transmission arrangement also includes an unbalanced choke coupled between the power source and the powered device, wherein a number of turns of the cable in the choke is different than a number of turns of the wire in the choke. | 2013-06-27 |
20130162371 | FILTER FOR REMOVING NOISE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a filter for removing noise, which includes: a lower magnetic body; an insulating layer provided on the lower magnetic body and including at least one conductor pattern; and an upper magnetic body including a primary ferrite composite provided on the insulating layer and a secondary ferrite composite provided on the primary ferrite composite to cover a pore formed on a surface of the primary ferrite composite, and a method of manufacturing the same. | 2013-06-27 |
20130162372 | MONOLITHIC CERAMIC ELECTRONIC COMPONENT - A monolithic ceramic electronic component includes at least two types of stacked ceramic layers having different dielectric constants and also includes internal electrodes partially disposed along boundaries between the ceramic layers having different dielectric constants. The internal electrodes include an additive component common to a component included in at least one of the ceramic layers adjacent to each other with the internal electrodes placed therebetween. | 2013-06-27 |
20130162373 | NANO ELECTROMECHANICAL INTEGRATED-CIRCUIT FILTER - A nano electromechanical integrated circuit filter and method of making. The filter comprises a silicon substrate; a sacrificial layer; a device layer including at least one resonator, wherein the resonator includes sub-micron excitable elements and wherein the at least one resonator possess a fundamental mode frequency as well as a collective mode frequency and wherein the collective mode frequency of the at least one resonator is determined by the fundamental frequency of the sub-micron elements. | 2013-06-27 |
20130162374 | TUNABLE BANDPASS FILTER - A bandpass filter has a combline structure having a plurality of cascaded nodes. A plurality of nodes in the filter are connected both to resonant elements (a.k.a. resonators) and non-resonant elements (including elements having inductances and/or capacitances that do not resonate in a predetermined frequency band of interest). The resonant frequencies of the resonant elements may be adjusted, in order to adjust the location of the center frequency and/or the width of the passband of the filter. The characteristics of the resonant and non-resonant elements are selected such that the poles of the filter, when plotted on the complex plane, move substantially along the imaginary axis when the resonant frequencies are adjusted, without substantial movement along the real axis. The resulting bandpass filter has substantially constant losses and substantially constant absolute selectivity over a relatively wide range of bandwidths. | 2013-06-27 |
20130162375 | METHOD FOR PRODUCING METAMATERIAL AND METAMATERIAL - A method for producing a metamaterial including an electromagnetic wave resonator resonating with an electromagnetic wave. The method includes the steps of: (a) forming a support by a nanoimprint method or a photolithography method, the support including a portion on which an electromagnetic wave resonator is to be formed; and (b) vapor-depositing a material which can form the electromagnetic wave resonator on the portion of the support to thereby arrange the electromagnetic wave resonator on the support. | 2013-06-27 |
20130162376 | DC BLOCK USING MICROSTRIP LINE - A DC block is provided. The present DC block includes a first microstrip line of which one end is connected to a first signal line and of which the other end is bent; and a second microstrip line of which one end is connected to a second signal line, and of which the other end is bent, wherein the second microstrip line is placed parallel to the first microstrip line. Accordingly, the size of the DC block is reduced by at least half. | 2013-06-27 |