| 26th week of 2013 patent applcation highlights part 16 |
| Patent application number | Title | Published |
|---|
| 20130161675 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device. The light emitting device comprises a light emitting structure comprising a plurality of compound semiconductor layers; and a light extraction structure on the light emitting structure. The light extraction structure comprises a plurality of first layers and a plurality of second layers which are alternately disposed with each other to have a negative refraction index. | 2013-06-27 |
| 20130161676 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - The invention provides a Group III nitride semiconductor light-emitting device which has a light extraction face at the n-layer side and which provides high light emission efficiency. The light-emitting device is produced through the laser lift-off technique. The surface of the n-GaN layer of the light-emitting device is roughened. On the n-GaN layer, a transparent film is formed. The transparent film satisfies the following relationship: 0.28≦n×d | 2013-06-27 |
| 20130161677 | INTEGRATED POLARIZED LIGHT EMITTING DIODE WITH A BUILT-IN ROTATOR - The invention is directed to an integrated polarized light emitting diode device that has a light emitting diode, a metal grating, an oxide layer, and a built-in photonic crystal rotator. Additional teachings include a method for making the integrated polarized light emitting diode, a method for improving the polarization selectivity and energy efficiency of a light emitting diode, and a method for rotating polarization of a light emitting diode. | 2013-06-27 |
| 20130161678 | SURFACE-TREATED FLUORESCENT MATERIAL AND PROCESS FOR PRODUCING SURFACE-TREATED FLUORESCENT MATERIAL - Provided are a surface treated phosphor having high dispersibility and remarkably improved moisture resistance without degradation in fluorescence properties, and a method of producing the surface treated phosphor. | 2013-06-27 |
| 20130161679 | ELECTROLUMINESCENT ELEMENT, ELECTROLUMINESCENT ELEMENT MANUFACTURING METHOD, DISPLAY DEVICE, AND ILLUMINATION DEVICE - An electroluminescent element ( | 2013-06-27 |
| 20130161680 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes a substrate, a first electrode on the substrate; an intermediate layer on the first electrode, the intermediate layer including an organic light-emitting layer; a second electrode on the intermediate layer, a first inorganic encapsulating layer on the second electrode, the first inorganic encapsulating layer defining a first groove formed therein; a first organic encapsulating layer that is in the first groove defined by the first inorganic encapsulating layer, the first organic encapsulating layer not extending beyond the first groove, and a second inorganic encapsulating layer on the first organic encapsulating layer. | 2013-06-27 |
| 20130161681 | LED WITH VERSATILE MOUNTING WAYS - An LED includes a base, a first lead and a second lead mounted to the base, a light emitting chip electrically connected to the first lead and the second lead, and an encapsulant sealing the chip. The first lead and the second lead each include a first beam and a second beam connected to each other. Each of the first beam and the second beam has two opposite ends protruding beyond two opposite lateral faces of the base, respectively, for electrically connecting with a circuit board. | 2013-06-27 |
| 20130161682 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - There is provided a semiconductor light-emitting element which has an electrode structural body including a connection electrode and a wiring electrode connected to the connection electrode, the wiring electrode stretching along a surface of a semiconductor layered body while being in partial contact with the surface of the semiconductor layered body exposed from an opening formed on the insulation layer. The area of a contact region between the wiring electrode and the semiconductor layered body increases, from a connection end which is connected to the connection electrode, along a direction in which the wiring electrode stretches. | 2013-06-27 |
| 20130161683 | CURABLE SILICONE RESIN COMPOSITION WITH HIGH RELIABILITY AND OPTICAL SEMICONDUCTOR DEVICE USING SAME - An optical semiconductor device that combines low gas permeability and high reliability. A curable silicone resin composition comprising: (A) an alkenyl group-containing organopolysiloxane comprising an organopolysiloxane represented by an average composition formula (1) and containing at least two alkenyl groups per molecule: | 2013-06-27 |
| 20130161684 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting device having a curved light-emitting surface is provided. Further, a highly-reliable light-emitting device is provided. A substrate with plasticity is used. A light-emitting element is formed over the substrate in a flat state. The substrate provided with the light-emitting element is curved and put on a surface of a support having a curved surface. Then, a protective layer for protecting the light-emitting element is formed in the same state. Thus, a light-emitting device having a curved light-emitting surface, such as a lighting device or a display device can be manufactured. | 2013-06-27 |
| 20130161685 | METHOD FOR MANUFACTURING NANO-IMPRINT MOULD, METHOD FOR MANUFACTURING LIGHT-EMITTING DIODE USING THE NANO IMPRINT MOULD MANUFACTURED THEREBY, AND LIGHT-EMITTING DIODE MANUFACTURED THEREBY - A method of manufacturing a light emitting diode, includes a process of forming an n-type nitride semiconductor layer, a light emitting layer, and a p-type nitride semiconductor layer on a temporary substrate, a process of forming a p-type electrode on the p-type nitride semiconductor layer, a process of forming a conductive substrate on the p-type electrode, a process of removing the temporary substrate to expose the n-type nitride semiconductor layer, a process of forming a nanoimprint resist layer on the n-type nitride semiconductor layer, a process of pressing the nanoimprint mold on the nanoimprint resist layer to transfer the nano-pattern onto the nanoimprint resist layer, and a process of separating the nanoimprint mold from the nanoimprint resist layer having the nano-pattern and etching a portion of the nanoimprint resist layer having the nano-pattern to form an n-type electrode. | 2013-06-27 |
| 20130161686 | Curable Organopolysiloxane Composition And Optical Semiconductor Device - A curable organopolysiloxane composition that can be used as a sealant or a bonding agent for optical semiconductor elements and comprises at least the following components: (A) an alkenyl-containing organopolysiloxane that comprises constituent (A-1) of an average compositional formula and constituent (A-2) of an average compositional formula; (B) an organopolysiloxane that contains silicon-bonded hydrogen atoms and comprises constituent (B-1) containing at least 0.5 wt. % of silicon-bonded hydrogen atoms and represented by an average molecular formula, constituent (B-2) containing at least 0.5 wt. % of silicon-bonded hydrogen atoms and represented by an average compositional formula, and, if necessary, constituent (B-3) of an average molecular formula; and (C) a hydrosilylation-reaction catalyst. The composition can form a cured body that possesses long-lasting properties of light transmittance and bondability, and relatively low hardness. | 2013-06-27 |
| 20130161687 | BI-DIRECTIONAL BACK-TO-BACK STACKED SCR FOR HIGH-VOLTAGE PIN ESD PROTECTION, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes. | 2013-06-27 |
| 20130161688 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There are provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate having a front surface and a back surface and having a p-type impurity layer, a low-concentration n-type impurity layer, and an n-type impurity layer disposed in a backward direction from the front surface thereof, the n-type impurity layer having a high-concentration p-type impurity region therein and the n-type impurity layer and the high-concentration p-type impurity region being exposed to the back surface; and a deep trench formed vertically in the semiconductor substrate to be open to the front surface of the semiconductor substrate and having a bottom surface connected to the high-concentration p-type impurity region. Here, an activation ratio of impurities may be increased and damages to a wafer may be prevented during a thin film process. | 2013-06-27 |
| 20130161689 | INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE - A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well. | 2013-06-27 |
| 20130161690 | SEMICONDUCTOR DEVICE - A semiconductor device contains a first conductive type semiconductor substrate, at least one cathode formed on one surface of the semiconductor substrate, an anode formed on the other surface of the semiconductor substrate, and a gate electrode electrically insulated from the cathode, formed on the one surface of the semiconductor substrate to control current conduction between the cathode and the anode. The semiconductor substrate has a thickness of less than 460 rm. | 2013-06-27 |
| 20130161691 | SEMICONDUCTOR DEVICE - A semiconductor device contains a semiconductor substrate, a cathode, an anode, and a gate electrode. The semiconductor device has a cathode segment disposed in a portion corresponding to at least the cathode, an anode segment disposed in a portion corresponding to the anode, a plurality of embedded segments disposed in a portion closer to the cathode segment than to the anode segment, a takeoff segment disposed between the gate electrode and the embedded segments to electrically connect the gate electrode to the embedded segments, and a channel segment disposed between the adjacent embedded segments. | 2013-06-27 |
| 20130161692 | SHIELD WRAP FOR A HETEROSTRUCTURE FIELD EFFECT TRANSISTOR - Devices are disclosed for providing heterojunction field effect transistor (HFETs) having improved performance and/or reduced noise generation. A gate electrode is over a portion of the active region and is configured to modulate a conduction channel in the active region of an HFET. The active region is in a semiconductor film between a source electrode and a drain electrode. A first passivation film is over the active region. An encapsulation film is over the first passivation film. A first metal pattern on the encapsulation film includes a shield wrap over the majority of the active region and is electrically connected to the source electrode | 2013-06-27 |
| 20130161693 | THIN HETEREOSTRUCTURE CHANNEL DEVICE - A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure. | 2013-06-27 |
| 20130161694 | THIN HETEREOSTRUCTURE CHANNEL DEVICE - A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure. | 2013-06-27 |
| 20130161695 | REDUCTION OF THICKNESS VARIATIONS OF A THRESHOLD SEMICONDUCTOR ALLOY BY REDUCING PATTERNING NON-UNIFORMITIES PRIOR TO DEPOSITING THE SEMICONDUCTOR ALLOY - The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability. | 2013-06-27 |
| 20130161696 | TUNNEL FIELD-EFFECT TRANSISTOR AND METHODS FOR MANUFACTURING THEREOF - A tunnel Field Effect Transistor is provided comprising an interface between a source and a channel, the source side of this interface being a layer of a first crystalline semiconductor material being substantially uniformly doped with a metal to the solubility level of the metal in the first crystalline material and the channel side of this interface being a layer of this first crystalline semiconductor material doped with this metal, the concentration decreasing towards the channel. | 2013-06-27 |
| 20130161697 | REPLACEMENT GATE MOSFET WITH RAISED SOURCE AND DRAIN - A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor. | 2013-06-27 |
| 20130161698 | E-MODE HFET DEVICE - The present invention describes a transistor based on a Hetero junction FET structure, where the metal gate has been replaced by a stack formed by a highly doped compound semiconductor and an insulating layer in order to achieve enhancement mode operation and at the same time drastically reduce the gate current leakage. The combination of the insulating layer with a highly doped semiconductor allows the tuning of the threshold voltage of the device at the desired value by simply changing the composition of the semiconductor layer forming the gate region and/or its doping allowing a higher degree of freedom. In one of the embodiment, a back-barrier layer and a heavily doped threshold tuning layer are used to suppress Short Channel Effect phenomena and to adjust the threshold voltage of the device at the desired value. The present invention can be realized both with polar and non-polar (or semi-polar) materials. | 2013-06-27 |
| 20130161699 | SEMICONDUCTOR STRUCTURES HAVING NUCLEATION LAYER TO PREVENT INTERFACIAL CHARGE FOR COLUMN III-V MATERIALS ON COLUMN IV OR COLUMN IV-IV MATERIALS - A semiconductor structure having: a column IV material or column IV-IV material; a nucleation layer of AlN layer or a column HI nitride having more than 60% aluminum content on a surface of the column IV material or column INT-IV material and a layer of column III-V material over the nucleation layer, where the nucleation layer and the layer of column III-V material over the nucleation layer have different crystallographic structures. In one embodiment, the columnffl V nucleation layer is a nitride and the column III-V material of the over the nucleation layer is a non-nitride such as, for example, an arsenide (e.g., GaAs), a phosphide (e.g, InP) or an antimonide (e.g. InSb), or alloys thereof. | 2013-06-27 |
| 20130161700 | METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE - The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness. | 2013-06-27 |
| 20130161701 | IMAGE PICKUP DEVICE - An image pickup device according to the present invention is an image pickup device in which a plurality of pixel are arranged in a semiconductor substrate. Each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion (FD) region, a transfer gate that transfers charges in the first semiconductor region to the FD region, and an amplification transistor whose gate is electrically connected to the FD region. The photoelectric conversion element has an outer edge which has a recessed portion in plan view, a source region and a drain region of the amplification transistor are located in the recessed portion, and the FD region is surrounded by the photoelectric conversion region or is located in the recessed portion in plan view. | 2013-06-27 |
| 20130161702 | INTEGRATED MEMS DEVICE - An integrated MEMS device is provided, including, from bottom up, a bonding wafer layer, a bonding layer, an aluminum layer, a CMOS substrate layer defining a large back chamber area (LBCA), a small back chamber area (SBCA) and a sound damping path (SDP), a set of CMOS wells, a field oxide (FOX) layer, a set of CMOS transistor sources/drains, a first polysilicon layer forming CMOS transistor gates, a second polysilicon layer, said CMOS wells, said CMOS transistor sources/drains and said CMOS gates forming CMOS transistors, an oxide layer embedded with a plurality of metal layers interleaved with a plurality of via hole layers, and a gap control layer, an oxide layer, a first Nitride deposition layer, a metal deposition layer, a second Nitride deposition layer, an under bump metal (UBM) layer made of preferably Al/NiV/Cu and a plurality of solder spheres. | 2013-06-27 |
| 20130161703 | SENSOR ELEMENT ARRAY AND METHOD OF FABRICATING THE SAME - A sensor element array and method of fabricating the same are provided. The sensor element array is disposed on a substrate and includes a first patterned conductive layer, a channel layer, a first insulation layer, a second patterned conductive layer, a second insulation layer, and a third patterned conductive layer. The first patterned conductive layer includes a sensing line, a first power line, a source/drain pattern and a branch pattern. The channel layer includes a first channel and a second channel. Margins of the first insulation layer and the second patterned conductive layer are substantially overlapped. The second patterned conductive layer includes a selecting line, a gate pattern, and a gate connecting pattern. The second insulation layer has a first connecting opening for exposing the gate connecting pattern. The third patterned conductive layer includes a sensing electrode electrically connected to the gate connecting pattern. | 2013-06-27 |
| 20130161704 | TRANSFERRED THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Provided are a transferred thin film transistor and a method of manufacturing the same. The method includes: forming a source region and a drain region that extend in a first direction in a first substrate and a channel region between the source region and the drain region; forming trenches that extend in a second direction in the first substrate to define an active layer between the trenches, the second direction intersecting the first direction; separating the active layer between the trenches from the first substrate by performing an anisotropic etching process on the first substrate inside the trenches; attaching the active layer on a second substrate; and forming a gate electrode in the first direction on the channel region of the active layer. | 2013-06-27 |
| 20130161705 | METHOD AND SYSTEM FOR A GAN VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE - A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure. | 2013-06-27 |
| 20130161706 | JUNCTION FIELD EFFECT TRANSISTOR WITH AN EPITAXIALLY GROWN GATE STRUCTURE - A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs). | 2013-06-27 |
| 20130161707 | Resistive Memory and Methods for Forming the Same - A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor. | 2013-06-27 |
| 20130161708 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate, a die and a medium. The substrate has an upper substrate surface. The substrate has a trench extended downward from the upper substrate surface. The trench has a side trench surface. The die is in the trench. The die has a lower die surface and a side die surface. The lower die surface is below the upper substrate surface. A part of the trench between the side trench surface and the side die surface is filled with the medium. | 2013-06-27 |
| 20130161709 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a carrier transit layer above a substrate, a carrier supply layer above the carrier transit layer, an etching stopper layer above the carrier supply layer, the etching stopper layer being coupled to a gate electrode, and a cap layer above the etching stopper layer, the cap layer being coupled to each of a source electrode and a drain electrode and having a conduction band energy lower than that of the etching stopper layer, wherein a portion of the etching stopper layer on the cap layer includes Silicon. | 2013-06-27 |
| 20130161710 | SEMICONDUCTOR DEVICE HAVING BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer. | 2013-06-27 |
| 20130161711 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode. | 2013-06-27 |
| 20130161712 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor circuit and a capacitor, the capacitor including: a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, the second semiconductor region being provided on the first semiconductor region of the first conductivity type and having a higher concentration of a first conductivity type impurity than the first semiconductor region of the first conductivity type, a semiconductor region of a second conductivity type provided on the second semiconductor region of the first conductivity type, a dielectric film provided on the semiconductor region of the second conductivity type, an upper electrode provided on the dielectric film, a first interconnection provided above the semiconductor region of the second conductivity type and electrically connected to the semiconductor region of the second conductivity type, and a second interconnection electrically connected to the upper electrode. | 2013-06-27 |
| 20130161713 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other. | 2013-06-27 |
| 20130161714 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device capable of accurate data retention even with a memory element including a depletion mode transistor. A gate terminal of a transistor for controlling input of a signal to a signal holding portion is negatively charged in advance. The connection to a power supply is physically broken, whereby negative charge is held at the gate terminal. Further, a capacitor having terminals one of which is electrically connected to the gate terminal of the transistor is provided, and thus switching operation of the transistor is controlled with the capacitor. | 2013-06-27 |
| 20130161715 | VERTICAL TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING SAME - A vertical transistor structure includes a substrate, a plurality of pillars located on the substrate and spaced from each other at a selected distance, a gate line and a plurality of conductors. The pillars are aligned in a straight line in a first direction and have respectively a primary control wall along the first direction and two ancillary control walls perpendicular to the primary control wall. The gate line is connected to the primary control wall in the first direction through a first isolated layer. The conductors are interposed between the ancillary control walls through second isolated layers. By providing the gate line merely on the primary control wall and the conductors to aid the gate line to control ON/OFF of the pillars, problems of etching and separating gate material during gradually shrunken feature size process that are difficult to control etching positions and etching duration can be prevented. | 2013-06-27 |
| 20130161716 | SEMICONDUCTOR DEVICE WITH SELECTIVELY LOCATED AIR GAPS AND METHOD OF FABRICATION - A non-volatile semiconductor memory device comprises a semiconductor substrate and a plurality of gate structures formed on a cell region of the semiconductor substrate. The plurality of gate structures include a first select-gate and a second select-gate disposed on the cell region, the first select-gate and the second select-gate spaced apart from each other. A plurality of cell gate structures are disposed between the first select-gate and the second select-gate. The first select-gate and an adjacent cell gate structure have no air gap defined therebetween. At least a pair of adjacent cell gate structures have an air gap defined therebetween. | 2013-06-27 |
| 20130161717 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional non-volatile memory device that may increase erase operation efficiency during an erase operation using Gate-Induced Drain Leakage (GIDL) current and a method for fabricating the three-dimensional non-volatile memory device. The non-volatile memory device includes a channel structure formed over a substrate including a plurality of inter-layer dielectric layers and a plurality of channel layers that are alternately stacked, and a first selection gate and a second selection gate that are disposed on a first side and a second side of the channel structure, wherein the first selection gate and the second selection gate contact sidewalls of the multiple channel layers, respectively, wherein a work function of a material forming the first selection gate is different from a work function of a material forming the second selection gate. | 2013-06-27 |
| 20130161718 | INTEGRATED CIRCUIT DIE AND METHOD OF MAKING - Integrated circuit dies and methods of making dies are disclosed. An embodiment of a die includes at least one transistor gate, wherein the gate has an area. A conductor is connected to the gate, and wherein the conductor has an area. The area of the conductor is proportional to the area of the gate raised to a power, wherein the power is a function of the failure rate of the gate. | 2013-06-27 |
| 20130161719 | Integrated Nanostructure-Based Non-Volatile Memory Fabrication - Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating. | 2013-06-27 |
| 20130161720 | EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor. | 2013-06-27 |
| 20130161721 | EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor. | 2013-06-27 |
| 20130161722 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device may include a gate structure on a substrate, the gate structure including a first metal; an insulating interlayer covering the gate structure on the substrate; a resistance pattern in the insulating interlayer, the resistance pattern having a top surface lower than a top surface of the insulating interlayer and including a second metal different from the first metal at least at an upper portion thereof; and/or a first contact plug through a first portion of the insulating interlayer, the first contact plug making direct contact with the upper portion of the resistance pattern. | 2013-06-27 |
| 20130161723 | Electronic Device Including a Tunnel Structure - An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region. | 2013-06-27 |
| 20130161724 | 3-DIMENSIONAL NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE DEVICE - A 3-dimensional non-volatile memory device, a memory system including the same, and a method of manufacturing the same comprise vertical channel layers protruding from a substrate, a plurality of interlayer insulating layers and a plurality of conductive layers alternately formed along the vertical channel layers, a charge trap layer surrounding the vertical channel layers, the charge trap layer having a smaller thickness in a plurality of first regions, interposed between the plurality of conductive layers and the vertical channel layers, than in a plurality of second regions, interposed between the plurality of interlayer insulating layers and the vertical channel layers and a blocking insulating layer formed in each of the plurality of first regions, between the plurality of conductive layers and the charge trap layer. | 2013-06-27 |
| 20130161725 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes conductive films and insulating layers alternately stacked on a substrate, substantially vertical channel layers penetrating the conductive films and the insulating layers, multilayer films including a charge storage film interposed between the conductive films and the substantially vertical channel layers, and a first anti-diffusion film formed on etched surfaces of the conductive films. | 2013-06-27 |
| 20130161726 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device. | 2013-06-27 |
| 20130161727 | NON-VOLATILE MEMORY DEVICE HAVING STACKED STRUCTURE, AND MEMORY CARD AND ELECTRONIC SYSTEM INCLUDING THE SAME - Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set. | 2013-06-27 |
| 20130161728 | FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS - A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer. | 2013-06-27 |
| 20130161729 | Methods of Forming Isolation Structures on FinFET Semiconductor Devices - One illustrative method disclosed herein includes performing at least one etching process on a semiconducting substrate to form a plurality of trenches and a plurality of fins for the FinFET device in the substrate, forming a first layer of insulating material in the trenches, wherein an upper surface of the first layer of insulating material is below an upper surface of the substrate, forming an isolation layer within the trenches above the first layer of insulating material, wherein the isolation layer has an upper surface that is below the upper surface of the substrate, forming a second layer of insulating material above the isolation layer, wherein the second layer of insulating material has an upper surface that is below the upper surface of the substrate, and forming a gate electrode structure above the second layer of insulating material. | 2013-06-27 |
| 20130161730 | MEMORY ARRAY STRUCTURE AND METHOD FOR FORMING THE SAME - A memory array structure and a method for forming the same are provided. The memory array structure comprises: a substrate; a plurality of memory cells, each memory cell including a vertical transistor, of which a gate structure is formed in a first trench extending in a first direction; a plurality of word lines in the first direction, each word line formed in the first trench; a plurality of bit lines in a second direction, each bit line formed in lower sides of a semiconductor pillars; a plurality of body lines in the first direction, each body line having a first portion formed on the gate electrodes and a second portion covering a part of a top surface of semiconductor pillar for providing a substrate contact to vertical channel regions; and a plurality of data storage device contacts. | 2013-06-27 |
| 20130161731 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3D) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers. | 2013-06-27 |
| 20130161732 | VERTICAL CHANNEL THIN FILM TRANSISTOR - Disclosed is a vertical channel thin film transistor including a substrate; a drain electrode formed on the substrate; a spacer formed on the substrate while coming into contact with the drain electrode; a source electrode formed on the spacer; an active layer formed on an entire surface of the substrate including the drain electrode and the source electrode and configured to form a vertical channel; a gate insulating layer formed on the active layer; and a gate electrode formed on the gate insulating layer. | 2013-06-27 |
| 20130161733 | SEMICONDUCTOR DEVICE - Disclosed herein a semiconductor device, which comprises: a vertical MOS transistor that has an upper diffusion layer, and a first lower diffusion layer disposed at a lower position than the upper diffusion layer; and a first diode that has a first well isolated from the first lower diffusion layer, and a second lower diffusion layer disposed at a lower position than the upper diffusion layer and formed in the first well. A surge voltage is discharged across the second lower diffusion layer and the first well when the surge voltage is applied. | 2013-06-27 |
| 20130161734 | TRANSISTOR STRUCTURE AND METHOD FOR PREPARING THE SAME - A buried channel transistor has a semiconductor substrate, a trench and a doped region. The semiconductor substrate has a first surface and a well under the first surface. The trench is disposed in the semiconductor substrate and extends from the first surface into the well. The trench includes a buried gate structure inside the trench. The buried gate structure has a first workfunction layer, a second workfunction layer with a dopant type opposite to that of the first workfunction layer. The second workfunction layer is disposed adjacent to the first workfunction layer. The buried gate structure further includes a dielectric layer adjacent to the trench inner sidewall. The dielectric layer separates the workfunction layers from the semiconductor substrate. The doped region is disposed in the semiconductor substrate and located above the well. The dopant type of the doped region is opposite to that of the first workfunction layer. | 2013-06-27 |
| 20130161735 | TRANSISTOR STRUCTURE AND METHOD FOR PREPARING THE SAME - A transistor structure includes a semiconductor substrate; a conductor having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate; a metal layer positioned on the upper block; a cap layer positioned on the metal layer; an upper insulation layer positioned at least on sidewalls of the metal layer and the cap layer; and a lower insulation layer positioned on sidewalls of the upper block of the conductor. | 2013-06-27 |
| 20130161736 | TRENCH METAL OXIDE SEMICONDUCTOR TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF - A trench metal oxide semiconductor transistor device and a manufacturing method thereof are described. The trench metal oxide semiconductor transistor device includes a substrate of a first conductivity type, a drift region of the first conductivity type, a deep trench doped region of a second conductivity type, an epitaxial region of the second conductivity type, a trench gate, a gate insulating layer, a source region, a drain electrode and a source electrode. The drift region has at least one deep trench therein, and the deep trench doped region is disposed in the deep trench. The trench gate passes through the epitaxial region, and a distance between a bottom of the trench gate and a bottom of the deep trench doped region is 0.5˜3 um. | 2013-06-27 |
| 20130161737 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There are provided a semiconductor device and a method of manufacturing the same, capable of removing a shoot-through phenomenon by forming capacitance between an electrode and a lateral surface of a protrusion region of a gate and increasing a gate-source capacitance. The semiconductor device may include: a semiconductor body having a predetermined volume; a source formed on an upper surface of the semiconductor body; a gate formed in a groove of the semiconductor body and having a protrusion region protruded upwardly of the upper surface of the semiconductor body, the groove having a predetermined depth and the protrusion region having a protrusion height altered depending on a level of capacitance to be set; and an electrode electrically connected to the source to form capacitance together with a lateral surface of the protrusion region of the gate. | 2013-06-27 |
| 20130161738 | SEMICONDUCTOR DEVICE - A semiconductor device | 2013-06-27 |
| 20130161739 | DUMMY GATE FOR A HIGH VOLTAGE TRANSISTOR DEVICE - A semiconductor device and methods for forming the same are provided. The semiconductor device includes a first doped region and a second, oppositely doped, region both formed in a substrate, a first gate formed overlying a portion of the first doped region and a portion of the second doped region, two or more second gates formed over the substrate overlying a different portion of the second doped region, one or more third doped regions in the second doped region disposed only between the two or more second gates such that the third doped region and the second doped region having opposite conductivity types, a source region in the first doped region, and a drain region in the second doped region disposed across the second gates from the first gate. | 2013-06-27 |
| 20130161740 | Lateral High-Voltage Transistor with Buried Resurf Layer and Associated Method for Manufacturing the Same - A lateral high-voltage transistor comprising a semiconductor layer of a first conductivity type; a source region of a second conductivity type in the semiconductor layer; a drain region of the second conductivity type in the semiconductor layer; a first isolation layer atop the semiconductor layer between the source and the drain regions; a first well region of the second conductivity type surrounding the drain region; a gate positioned atop the first isolation layer adjacent to the source region; a spiral resistive field plate atop the first isolation layer spiraling between the drain region and the gate, wherein the spiral resistive field plate is coupled in series to the source and drain regions; and a buried layer of the first conductivity type in the first well region, wherein the buried layer is buried beneath a top surface of the first well region below the spiral resistive field plate. | 2013-06-27 |
| 20130161741 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions. | 2013-06-27 |
| 20130161742 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, and a super junction area that is disposed above the substrate. The super junction area may include pillars of different doping types that are alternately disposed. One of the pillars of the super junction area may have a doping concentration that gradually decreases and then increases from bottom to top in a vertical direction of the semiconductor device. | 2013-06-27 |
| 20130161743 | SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS - A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 | 2013-06-27 |
| 20130161744 | FINFET WITH MERGED FINS AND VERTICAL SILICIDE - A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region. | 2013-06-27 |
| 20130161745 | SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE - In one embodiment a transistor structure includes a gate stack disposed on a surface of a semiconductor body. The gate stack has a layer of gate dielectric surrounding gate metal and overlies a channel region in the semiconductor body. The transistor structure further includes a source having a source extension region and a drain having a drain extension region formed in the semiconductor body, where each extension region has a sharp, abrupt junction that overlaps an edge of the gate stack. Also included is a punch through stopper region having an implanted dopant species beneath the channel in the semiconductor body between the source and the drain. There is also a shallow channel region having an implanted dopant species located between the punch through stopper region and the channel. Both bulk semiconductor and silicon-on-insulator transistor embodiments are described. | 2013-06-27 |
| 20130161746 | TRANSISTOR AND METHOD OF FABRICATION - A transistor includes an active layer forming a channel for the transistor, an insulating layer disposed facing a lower face of the active layer, a gate turned toward an upper face of the active layer and a source and a drain disposed on both sides of the gate. At least one among the source and the drain extends at least partly through the active layer and into the insulating layer. | 2013-06-27 |
| 20130161747 | ISOLATION REGION FABRICATION FOR REPLACEMENT GATE PROCESSING - A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer. | 2013-06-27 |
| 20130161748 | STRUCTURE, METHOD AND SYSTEM FOR COMPLEMENTARY STRAIN FILL FOR INTEGRATED CIRCUIT CHIPS - A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer. | 2013-06-27 |
| 20130161749 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a first conductive line coupled with a first pad for receiving a first voltage; a second conductive line coupled with a second pad for receiving a second voltage; a third conductive line arranged to be placed in a floating state; a first electrostatic discharge unit coupled between a third pad for inputting/outputting a signal and the third conductive line through a first common conductive line, wherein the first electrostatic discharge unit is configured to provide a bi-directional electrostatic discharge path between the third pad and the third conductive line according to an electrostatic discharge mode; a second electrostatic discharge unit coupled between the first conductive line and the third conductive line through a second common conductive line; and a third electrostatic discharge unit coupled between the second conductive line and the third conductive line through a third common conductive line. | 2013-06-27 |
| 20130161750 | N-Channel Laterally Diffused Metal-Oxide-Semiconductor Device - The disclosure relates to an n-channel laterally diffused metal-oxide-semiconductor device comprising an n+ source ( | 2013-06-27 |
| 20130161751 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS - A semiconductor device includes a substrate having a channel region, a gate insulation layer on the channel region, a gate electrode on the gate insulation layer, and source and drain regions in recesses in the substrate on both sides of the channel region, respectively. The source and drain regions include a lower main layer whose bottom surface is located at level above the bottom of a recess and lower than that of the bottom surface of the gate insulation layer, and a top surface no higher than the level of the bottom surface of the gate insulation layer, and an upper main layer contacting the lower main layer and whose top surface extends to a level higher than that of the bottom surface of the gate insulation layer, and in which the lower layer has a Ge content higher than that of the upper layer. | 2013-06-27 |
| 20130161752 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor group including first transistors, wherein each of the first transistors includes a first gate, and a first source and a first drain disposed symmetrically at both sides of the first gate and having a bent form; | 2013-06-27 |
| 20130161753 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET. | 2013-06-27 |
| 20130161754 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A manufacturing method of a semiconductor device includes the following steps. First, a substrate is provided. At least one gate trench and a first inter-layer dielectric layer are formed on the substrate. A work function metallic layer is then formed in the gate trench. A first contact hole is then formed in the first inter-layer dielectric layer. A main conductive layer is formed in the gate trench and the first contact hole simultaneously. | 2013-06-27 |
| 20130161755 | THIN FILM TRANSISTOR AND FABRICATING METHOD - A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed. | 2013-06-27 |
| 20130161756 | NANOWIRE TRANSISTOR DEVICES AND FORMING TECHNIQUES - Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein. | 2013-06-27 |
| 20130161757 | CMOS Device for Reducing Charge Sharing Effect and Fabrication Method Thereof - The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase. The present invention can reduce the charge sharing effect due to heavy ions by using a feature that the defect states in the porous silicon trap carriers, the formation of a shallow trench isolation (STI) region and a isolation region underneath only needs one time photolithography, and the process is simple, so that radioresistance performance of an integrated circuit may be greatly increased. | 2013-06-27 |
| 20130161758 | Buried Power Grid Designs and the Methods for Forming Buried Power Grids in CMOS Technologies for Improved Radiation Hardness - Buried power grids are designed as a fine mesh-type pattern of heavily doped diffusion regions with neutral epitaxial region cores to allow the uninterrupted electrical continuity of the epitaxial substrate, thus avoiding floating substrate effects. The buried power grids are formed beneath the epitaxial substrate surface and are powered via electrical contact to adjacent well regions. The buried power grids, when powered, form strongly reverse-biased buried pn junction regions that restrict radiation induced excess charge collection volumes and draw excess charge away from sensitive circuit nodes The method for forming buried power grids requires no uniquely complex process steps and no critical mask alignments to the CMOS devices on the epitaxial top surface. Buried power grids provide enhanced protection to sensitive circuit nodes against logic upsets due to single-particle and prompt dose radiation events and thereby improve the radiation hardness and decreases the latchup susceptibility of CMOS circuits. | 2013-06-27 |
| 20130161759 | METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW - A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate. | 2013-06-27 |
| 20130161760 | Integrated Circuit Including Gate Electrode Tracks Including Offset End-to-End Spacings - An integrated circuit includes a first gate electrode feature of a first gate electrode track that forms a first n-channel transistor as it crosses an n-diffusion region, and a second gate electrode feature of the first gate electrode track that forms a first p-channel transistor as it crosses a p-diffusion region. The first and second gate electrode features of the first gate electrode track are separated by a first end-to-end spacing. The integrated circuit includes a first gate electrode feature of a second gate electrode track that forms a second n-channel transistor as it crosses the n-diffusion region, and a second gate electrode feature of the second gate electrode track that forms a second p-channel transistor as it crosses the p-diffusion region. The first and second gate electrode features of the second gate electrode track are separated by a second end-to-end spacing that is offset from the first end-to-end spacing. | 2013-06-27 |
| 20130161761 | ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME - A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate. | 2013-06-27 |
| 20130161762 | GATE STRUCTURE FOR SEMICONDUCTOR DEVICE - The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening. | 2013-06-27 |
| 20130161763 | SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE - A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form a source extension region and a drain extension region, where the implanted dopant species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source extension and the drain extension implant. The method further includes forming a second spacer surrounding the first spacer, removing the first spacer and the plug to form an opening, and depositing a gate stack in the opening. | 2013-06-27 |
| 20130161764 | REPLACEMENT GATE HAVING WORK FUNCTION AT VALENCE BAND EDGE - Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly. | 2013-06-27 |
| 20130161765 | MIS TYPE SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - The present invention provides a MIS type semiconductor device having a ZrO | 2013-06-27 |
| 20130161766 | GATE ELECTRODE HAVING A CAPPING LAYER - A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. | 2013-06-27 |
| 20130161767 | SEMICONDUCTOR DEVICES HAVING POLYSILICON GATE PATTERNS AND METHODS OF FABRICATING THE SAME - A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern. | 2013-06-27 |
| 20130161768 | MAGNETIC DEVICE HAVING A MAGNETIC MATERIAL IN A CONTACT STRUCTURE COUPLED TO A MAGNETIC ELEMENT AND METHOD OF MANUFACTURE THEREOF - A magnetic device has a contact structure including a magnetic material therein. The contact structure is magnetostatically and/or electrically coupled to a magnetic element such as one having a magnetic tunneling junction (MTJ) multilayer structure. The magnetic material included in the contact structure is configured to compensate for an offset field acting on the free layer of the magnetic element by reference layers of the magnetic element. | 2013-06-27 |
| 20130161769 | MAGNETORESISTIVE ELEMENTS AND MEMORY DEVICES INCLUDING THE SAME - Magnetoresistive elements, and memory devices including the same, include a free layer having a changeable magnetization direction, a pinned layer facing the free layer and having a fixed magnetization direction, and an auxiliary element on a surface of the pinned layer. The auxiliary element has a width smaller than a width of the pinned layer, and a magnetization direction fixed to a direction the same as a direction of the fixed magnetization direction of the pinned layer. | 2013-06-27 |
| 20130161770 | MAGNETORESISTIVE DEVICE AND A METHOD OF FORMING THE SAME - According to embodiments of the present invention, a magnetoresistive device is provided. The magnetoresistive device includes a fixed magnetic layer structure having a fixed magnetization orientation along a first easy axis, a free magnetic layer structure having a variable magnetization orientation along a second easy axis, and an offsetting magnetic layer structure having a magnetization orientation along an axis at least substantially non-parallel to at least one of the first easy axis or the second easy axis, wherein the fixed magnetic layer structure, the free magnetic layer structure and the offsetting magnetic layer structure are arranged one over the other. According to further embodiments of the present invention, a method of forming a magnetoresistive device is also provided. | 2013-06-27 |
| 20130161771 | REDUCING SOURCE LOADING EFFECT IN SPIN TORQUE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY (STT-MRAM) - An apparatus includes a memory cell including a magnetic tunnel junction (MTJ) structure coupled between a bit line and a source line. The MTJ structure includes a free layer coupled to the bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. A physical dimension of the pinned layer produces an unbalanced offset magnetic field which corresponds to a first switching current of the MTJ structure that enables switching from the first state to the second state when a first voltage is applied to the bit line and corresponds to a second switching current that enables switching from the second state to the first state when the first voltage is applied to the source line. | 2013-06-27 |
| 20130161772 | FLEXIBLE RADIATION DETECTORS - Disclosed is a flexible radiation detector including a substrate, a switching device on the substrate, an energy conversion layer on the switching device, a top electrode layer on the energy conversion layer, a first phosphor layer on the top electrode layer, and a second phosphor layer under the substrate. | 2013-06-27 |
| 20130161773 | DETECTOR ELEMENT, RADIATION DETECTOR, MEDICAL DEVICE, AND METHOD FOR PRODUCING SUCH A DETECTOR ELEMENT - A detector element is disclosed, including a semiconducting converter element and a number of pixilated contacts arranged thereon. A radiation detector is also disclosed including such a detector element, along with a medical device having one or more such radiation detectors. Finally, a method for producing a detector element is disclosed, which includes forming pixelated contacts by way of a photolithographic process on the semiconducting converter element using a lithographic mask arranged on a converter element protective layer. | 2013-06-27 |
| 20130161774 | SOLID STATE IMAGING DEVICE - A CCD image sensor is provided with a pixel set. The pixel set is composed of first and second pixels and a microlens. The pixels are arranged side by side in a horizontal direction. The microlens has a hemispheric shape. A diameter of the microlens is larger than a length of a rectangular region, being an external shape of the first and second pixels, in a height direction. The rectangular region has a height and width ratio of approximately 1:2. The pixel sets are arranged in a width direction of the rectangular region to constitute a pixel row. In the CCD image sensor, the pixel rows are arranged in the height direction of the rectangular region, with the adjacent pixel rows shifted from each other in the horizontal direction by half pitch of the rectangular region. | 2013-06-27 |
