26th week of 2009 patent applcation highlights part 21 |
Patent application number | Title | Published |
20090160490 | REFERENCE VOLTAGE GENERATOR OF ANALOG-TO-DIGITAL CONVERTER - A reference voltage generator, which is used in an analog-to-digital converter, minimizes influence of kickback noise by dividing a full scale reference voltage into a number of reference voltages using a ladder resistor unit, and applying the number of reference voltages to a number of comparators, and matches a reference common mode voltage to an input common mode voltage by forming a common feedback loop using another ladder resistor unit which is a replica of the ladder resistor unit. Therefore, since kickback noise is locally discharged by a decoupling capacitor connected to each ladder resistor and a peak value of the kickback noise is also reduced, it is possible to optimize the ladder resistor unit according to power consumption. Also, since the common feedback loop is formed as a replica of the ladder resistor unit, it is possible to match a reference common mode signal to an input common mode signal. | 2009-06-25 |
20090160491 | INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a device connection detection module which monitors a potential of the signal line by disabling the function of a second pull-up resistor by means of a switch circuit and detects that the first or second device has been connected if the potential becomes no higher than a first threshold. The apparatus further includes a device determination module which assesses the potential of the signal line by enabling the function of the second pull-up resistor by means of the switch circuit, and determines, if the potential exceeds a second threshold that is higher than the first threshold, that the first device has been connected, or, if the potential is no higher than the first threshold, that the second device has been connected. | 2009-06-25 |
20090160492 | Glitchless Clock Multiplexer Optimized for Synchronous and ASynchronous Clocks - A circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The circuit comprises an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal. Switching latency is the period in which no clock pulse appears at the final output of the circuit. | 2009-06-25 |
20090160493 | System and Method for Generating a Spread-Spectrum Clock Signal - A circuit for, and method of, generating a spread-spectrum clock signal. In one embodiment, the circuit includes: (a) a modulator configured to generate a modulated control value, and (b) a frequency synthesizer coupled to the modulator and configured to generate a spread-spectrum clock signal based on a variation of the modulated control value, the frequency synthesizer having a directly-derivable frequency response output. | 2009-06-25 |
20090160494 | OUTPUT DRIVING CIRCUITS - An output driving circuit is disclosed, providing an output signal at an output node and comprises an inverter and an output driver. A first P-type transistor and a first N-type transistor of the inverter are coupled in series between high and low voltage sources and controlled respectively by first and second driving signals. A gate oxide layer of the first N-type transistor is thinner than that of the first P-type transistor. The inverter generates a first driving signal. A second P-type transistor and a second N-type transistor of the output driver are coupled in series at the output node between the high and low voltage sources. The second P-type transistor and the second N-type transistor are controlled respectively by the first driving signal and a second driving signal. A falling time of the first driving signal is longer than a falling time of the second driving signal. | 2009-06-25 |
20090160495 | LOW POWER DIFFERENTIAL SIGNALING TRANSMITTER - A low power differential signaling transmitter includes a switchable current source apparatus and a differential signaling generator coupled to the switchable current source apparatus. The switchable current source apparatus receives a first input voltage and a second input voltage, and generates a plurality of reference currents according to the first input voltage and the second input voltage. The differential signaling generator includes a plurality of first transistors, a plurality of second transistors, a first output voltage terminal and a second output voltage terminal. The on or off states of the first transistors and the second transistors are controlled by the reference currents. The first output voltage terminal outputs a first output voltage, and the second output voltage terminal outputs a second output voltage. The first output voltage and the second output voltage are determined according to the on or off states of the first and second transistors. | 2009-06-25 |
20090160496 | Output driver circuit - In an output driver circuit, a replica circuit includes seventh and eighth transistors corresponding to first and second transistors, respectively, ninth and tenth transistors corresponding to third or fifth, and fourth or sixth transistors in a driver circuit, respectively, and a resistor corresponding to a termination resistor. A reference voltage and a voltage of a node between the ninth transistor and the resistor are input to an operational amplifier, and an output signal of the operational amplifier is input to gates of the first and seventh transistors. | 2009-06-25 |
20090160497 | Signal line driving device comprising a plurality of outputs - A driving device that outputs signals of different polarities from plural output terminals includes: a first power source wire that connects power terminals of some of plural first output circuits each outputting a signal of one polarity and power terminals of some of plural second output circuits each outputting a signal of the other polarity; and a second power source wire that connects power terminals of the rest of the plural first output circuits and power terminals of the rest of the plural second output circuits, the second power source wire being different from the first power source wire. | 2009-06-25 |
20090160498 | Semiconductor output circuit for controlling power supply to a load - Between a control terminal (gate) of an output transistor of a source follower configuration and an output terminal to which a load is coupled, a depletion transistor having a relatively lower breakdown voltage (that is, smaller device-area) is provided as a shutdown transistor of the output transistor, to thereby control a conductive state/nonconductive state of the depletion transistor. There are provided: the output transistor of the source follower configuration coupled between a first power supply line and the output terminal; the load coupled between the output terminal and a second power supply line; the depletion transistor coupled between the gate of the output transistor and the output terminal; and a control circuit controlling the conductive state/nonconductive state of the depletion transistor by applying, between a gate and a source thereof, a voltage smaller than a voltage deference between a potential of the first power supply line and a potential of the second power supply line. | 2009-06-25 |
20090160499 | Semiconductor output circuit - To improve a depletion transistor provided between a control terminal of an output transistor and an output terminal coupled to a load not to enter a conductive state when the output transistor is in the conductive state. The output transistor is served as a source follower. Control voltages which controlling the conductive state/nonconductive state of the depletion transistor are supplied to both a control terminal (gate) and a substrate terminal (back gate) of the depletion transistor. | 2009-06-25 |
20090160500 | POWER MANAGEMENT SYSTEMS WITH CHARGE PUMPS - A driving circuit for an N-channel Metal Oxide Semiconductor (NMOS) transistor can include a charge pump unit and a driver coupled to the charge pump. The charge pump can receive a source voltage and output an output voltage higher than the source voltage, where the source voltage is applied to a source terminal of the NMOS transistor. The driver receives the output voltage of the charge pump unit and converts the output voltage to a driving voltage operable for conducting the NMOS transistor. | 2009-06-25 |
20090160501 | CONTROL SIGNAL GENERATING CIRCUIT ENABLING VALUE OF PERIOD OF A GENERATED CLOCK SIGNAL TO BE SET AS THE PERIOD OF A REFERENCE SIGNAL MULTIPLIED OR DIVIDED BY AN ARBITRARY REAL NUMBER - A pulse signal circulates around a ring of delay elements with respective traversal signals being thereby successively outputted from the delay elements. The period of a reference signal is multiplied or divided by a real number to obtain control data specifying a required period of a clock signal as a value having an integer part and a fractional part. The control data are used to select the timings of specific traversal signal, and the clock signal is generated based these selected timings, with the timing selection being repetitively adjusted in accordance with the fractional part of the control data. | 2009-06-25 |
20090160502 | FREQUENCY MULTIPLIER - A frequency multiplier is provided that includes a switching component having a plurality of differential pairs of transistors. The frequency multiplier further includes a gain stage. A common mode feedback generated by the switching component is also provided to the gain stage. | 2009-06-25 |
20090160503 | TRIANGLE WAVE GENERATOR AND SPREAD SPECTRUM CONTROL CIRCUIT THEREOF - A triangle wave generator with function of spreading frequency spectrum is provided. The triangle wave generator includes a switch control circuit, a current generator, an integrator, and a spread spectrum control circuit. The switch control circuit provides an internal clock and a switch control signal. The current generator is coupled to the switch control circuit and provides charge current according to the switch control signal. The integrator is coupled to the current generator and provides a triangle wave signal. The spread spectrum control circuit is coupled to the switch control circuit and the current generator for providing a current control signal according to the internal clock. | 2009-06-25 |
20090160504 | METHODS AND SYSTEMS FOR SYNCHRONIZING A CONTROL SIGNAL OF A SLAVE FOLLOWER WITH A MASTER SOURCE - A method for synchronizing a slave follower with a master source is provided. The method includes defining a relationship between the master source and the slave follower, inputting a first position of the master source, and inputting a first position of the slave follower. The method also includes defining a second position where the slave follower synchronizes with the master source, and fitting a curve between the first position of the slave follower the second position. The curve is fit based on the relationship between the master source and the slave follower, the first position of the slave follower, the first position of the master source, and the second position. The curve is fit to synchronize the slave follower and the master source without exceeding pre-determined boundaries of the slave follower. | 2009-06-25 |
20090160505 | POWER-UP CIRCUIT REDUCING VARIATION IN TRIGGERING VOLTAGE CAUSED BY VARIATION IN PROCESS OR TEMPERATURE IN SEMICONDUCTOR INTEGRATED CIRCUIT - A power-up circuit that can reduce a variation of the triggering voltage that is caused by variations in process or temperature in a semiconductor integrated circuit is described. The power-up circuit includes a first detector for outputting a first triggering voltage signal according to a power voltage level and a second detector for outputting a second triggering voltage signal according to the power voltage level. The power-up circuit also includes an output unit generating and outputting a power-up signal according to the first triggering voltage signal and the second triggering voltage signal and providing the output to various internal circuits. | 2009-06-25 |
20090160506 | POWER-ON CLEAR CIRCUIT - Provided is a power-on clear circuit which normally operates. Even when a rising speed of a power supply voltage is slow, or when the power supply voltage rises from a voltage other than a ground voltage, a voltage of a node (C) is unlikely to become unstable owing to provision of a pull-down element ( | 2009-06-25 |
20090160507 | Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates - In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the adder unit, the adder unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an adder unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the adder unit. it. | 2009-06-25 |
20090160508 | PLL CIRCUIT - Phase jitter of the hybrid control type PLL circuit in a steady state is reduced. A steady state detection circuit determining whether an output of a phase comparison circuit in the hybrid control type PLL circuit frequently changes is provided, determination that a steady state has not been reached is made if the output of the phase comparison circuit does not change for a while, determination that the steady state has been reached if the output of the phase comparison circuit frequently changes, and based on a result of the determination, a control width of controlling a oscillation frequency of a voltage controlled oscillator circuit by a digital control signal is changed or (and) a frequency of changing an analog control signal is changed. Thereby, a control width of the oscillation frequency by the digital control signal after reaching the steady state can be reduced without damaging convergence before reaching the steady state. Therefore, the phase jitter in the steady state can be reduced. | 2009-06-25 |
20090160509 | OVERCLOCKING WITH PHASE SELECTION - A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency. | 2009-06-25 |
20090160510 | BIAS VOLTAGE GENERATION CIRCUIT AND CLOCK SYNCHRONIZING CIRCUIT - Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage. | 2009-06-25 |
20090160511 | PLL CIRCUIT - The PLL circuit includes: a voltage control oscillating circuit including: a voltage-current converter circuit; a current adder; and a current control oscillating circuit, the voltage control oscillating circuit outputting a pulse having a frequency corresponding to a control voltage and a control current; a phase detector which outputs a first control signal and a second control signal based on a phase difference between the pulse and a reference pulse having a frequency which should be generated by the voltage control oscillating circuit; a first charge pump circuit which outputs one of a first charge current and a first discharge current in accordance with the first control signal; a loop filter which generates the control voltage in accordance with the one of the first charge current and the first discharge current, and then outputs the generated control voltage to the voltage control oscillating circuit; and a second charge pump circuit which generates the control current serving as one of a second charge current and a second discharge current in accordance with the second control signal, and then outputs the generated control current to the voltage control oscillating circuit. | 2009-06-25 |
20090160512 | Delay control circuit and delay control method - A delay control circuit in which steady phase error can be eliminated has a first variable delay circuit and a first phase control circuit. The delay control circuit further includes a second variable delay circuit disposed in either a first or second clock path, and a second phase control circuit arranged so as to form an additional feedback loop, which is for canceling steady phase error produced by the first phase control circuit, with respect to the first clock path or second clock path using a delay value applied to the second variable delay circuit. | 2009-06-25 |
20090160513 | Signal generating apparatus and class-D amplifying apparatus - A time period control unit controls a time length “TU” of each of unit terms “U” in a variable manner. A pulse-width modulating unit is arranged by a holding unit, a counting unit, and a waveform generating unit. The holding unit holds thereinto a plurality of data “XD” every unit term “U”, which are sequentially supplied, as data “XE.” The counting unit changes a count value “X” during each of the unit terms “U.” The waveform generating unit generates such a pulse-width modulating signal “S” that pulses “P” have been arranged every unit term “U”, while time points when a large/small relationship between the count value “C” and a numeral value of the data “XE” held by the holding unit is inverted are defined as edge portions of the pulses. | 2009-06-25 |
20090160514 | Chip structure capable of smoothing slope of signal during conversation - The present invention discloses a chip structure capable of smoothing slope of signal during conversion. And the chip structure is suitable for a DC motor which is embedded in a portable electronic device. The DC motor is for adjusting the focal distance of a digital camera which is installed within the portable electronic device. The chip structure comprises an input terminal, a first converter, a control unit, a second converter, an amplifier circuit and an output terminal. The input terminal is for receiving a first digital signal. The first converter is for converting the first digital signal into an analog signal. The control unit is for elongating the transform time of the analog signal. The amplifier circuit is for amplifying the elongated analog signal. The second converter is for converting the elongated analog signal into a second digital signal. And the output terminal outputs the second digital signal. | 2009-06-25 |
20090160515 | Auto-tracking clock circuitry - A system and method for generating a clock signal is disclosed. In various embodiments of the invention disclosed herein, a global clock signal is generated and provided as an input to local clock circuitry operable to generate a local clock signal therefrom. The local clock circuitry comprises logic components that are susceptible to negative bias thermal instability (NBTI) effects resulting in degradation of the local clock signal. Clock propagation adjustment circuitry is used to modify the duty cycle of the global clock signal to compensate for the degradation resulting from NBTI effects thereby providing an optimized local clock signal. | 2009-06-25 |
20090160516 | DUTY CYCLE CORRECTION CIRCUIT FOR HIGH-SPEED CLOCK SIGNALS - The present invention implements an apparatus for correcting duty cycle distortion in high speed clock signals. The apparatus includes delay cells that delay each of first and second differential initial clock signals. The apparatus further includes a latch that generates an output clock signal based on the delayed first and second differential initial clock signals. The apparatus further includes a differential feedback buffer that converts the output clock signal into first and second differential feedback signals. The apparatus further includes a feedback circuit that adjusts the delay cells based on the first and second differential feedback signals. | 2009-06-25 |
20090160517 | FLIP-FLOP - An apparatus comprises a first stage, a second stage, and a switch circuit. The first stage and the second stage are coupled between a first reference voltage and a second reference voltage. The first stage has a first input end for receiving an input signal and a first output end for outputting a first output signal. The second stage has a second input end for receiving the first output signal from the first output end of the first stage and a second output end for outputting a second output signal. The switch circuit is coupled between the second stage and at least one of the first reference voltage and the second reference voltage for receiving a power control signal and for turning on or turning off according to the power control signal such that the current leakage of the second stage is reduced. | 2009-06-25 |
20090160518 | METHOD IMPLEMENTING PERIODIC BEHAVIORS USING A SINGLE REFERENCE - A method for processing information is described. The method includes providing a phase reference, Φ | 2009-06-25 |
20090160519 | PROGRAMMABLE DELAY CIRCUIT WITH INTEGER AND FRACTIONAL TIME RESOLUTION - A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate that provides extra loading to obtain the longer delay for the second path. | 2009-06-25 |
20090160520 | VARIABLE DELAY CIRCUIT AND DELAY AMOUNT CONTROL METHOD - A variable delay circuit comprising a first delay element configured to delay an input signal, a second delay element coupled to the first delay element in parallel and also configured to delay the input signal, a control current supply section configured to supply control currents for adjusting a delay amount of the first delay element and a delay amount of the second delay element, and an output signal selecting section configured to select any one of an output signal from the first delay element and an output signal from the second delay element according to a selecting signal for selecting delay time of the input signal. | 2009-06-25 |
20090160521 | LOW VT DEPENDENCY RC OSCILLATOR - An oscillator utilizes two current sources that have the same temperature and VDD dependency so they generate the same current in changing conditions. Therefore, there is very low VT dependency. The resistor and fringe capacitor temperature coefficient are very low and opposite so they compensate for each other. A comparator with a short period of operation also minimizes VT dependency. | 2009-06-25 |
20090160522 | DC RESTORATION CIRCUIT ALLOWING SPARSE DATA PATTERNS - The present invention provides a device for restoring a DC component in a differential digital data stream. The device comprises a first and second peak detector for detecting peaks in the differential digital data stream, a memory element for storing an average of the first and second detected peak signals during rich data patterns, an error signal selector for error signal selection, and a regulator for negative feedback of a selected error signal. The selected error signal is either the average of the detected peak signals stored on the memory element minus the signal at the output of the first peak detector, or the signal at the output of the second peak detector minus the average of the detected peak signals stored on the memory element. | 2009-06-25 |
20090160523 | Receiving Higher-Swing Input Signals When Components Of An Integrated Circuit Are Fabricated Using A Lower-Voltage Process - An aspect of the present invention provides an input block which can receive input signals of a higher voltage swing when the internal components are fabricated using a lower voltage process. In an embodiment, the input block is designed to prevent current flow into an input signal path when the input signal is at a logic low level. In another embodiment, the input block is designed to recognize a logic value corresponding to a logic high level of input signals at a higher voltage level during a transition from logic low to logic high. | 2009-06-25 |
20090160524 | LEVEL SLIDER CIRCUIT - The invention relates to a level slider circuit having a first level slider ( | 2009-06-25 |
20090160525 | LEVEL SHIFT CIRCUIT - An amplifier including the transistors of a first set operates by a power source VCC | 2009-06-25 |
20090160526 | DIGITAL DIVIDER FOR LOW VOLTAGE LOGEN - Digital divider for low voltage LOGEN. LOGEN is a local oscillator generator. One implementation presented herein provides for a pseudo-complementary metal-oxide-semiconductor (CMOS), in that, it is not a true CMOS type circuitry that has no DC current dissipation, but nevertheless does operate well at relatively high frequencies and relatively low power supply voltage levels. Appropriately placed p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs) and n-channel MOSFETs (e.g., N-MOSFETs) are employed to provide for an all digital divider circuitry. In some embodiments, four active circuitry element levels are stacked between a power supply voltage and ground voltage level. In other embodiments, three active circuitry element levels are stacked between a power supply voltage and ground voltage level. The three active circuitry element levels embodiment provides for a greater area savings (e.g., because of the fewer elements) and also provides reduced input capacitance than the four active circuitry element levels embodiment. | 2009-06-25 |
20090160527 | HIGH FREQUENCY SWITCHING CIRCUIT - There is provided a high frequency switching circuit having good characteristics of high-order harmonics that has little variation. A high frequency switching circuit according to an aspect of the invention may include: a high frequency switch having one end connected to an input terminal receiving a high frequency signal and the other end connected to an output terminal of the high frequency signal, the high frequency switch turned on or off by a control signal; and a capacitor having a predetermined capacitance, and having one end connected the output terminal and the other end connected to a ground by a bonding wire. | 2009-06-25 |
20090160528 | METHOD FOR REGULATING TEMPERATURE - A method and circuit for managing thermal performance of an integrated circuit. Temperature sensing circuits and a plurality of power FETs that are coupled together in parallel are manufactured from a semiconductor substrate. Each temperature sensing circuit monitors the temperature of the portion of the semiconductor substrate near or including a corresponding power FET. When the temperature of the semiconductor substrate near one or more of the power FETs reaches a predetermined value, the corresponding temperature sensing circuit reduces a voltage appearing on the gate of the power FET. The reduced voltage increases the on-resistance of the power FET and channels a portion of its current to others of the plurality of power FETs. The power FET continues operating but with a reduced current flow. When the temperature of the semiconductor substrate falls below the predetermined value, the gate voltage of the power FET is increased to its nominal value. | 2009-06-25 |
20090160529 | Touch Sensor System - A touch sensor assembly. The touch sensor assembly may include a housing, at least one touch sensor and a sensor cover. The sensor cover may identify a touch area associated with each touch sensor. The housing may form a water tight cavity for the sensor cover and the touch sensor when coupled to an housing cover. A raised dome may be provided, e.g. on the sensor cover or another element, to provided tactile feed back. LEDs may be provided for illuminating the touch areas and/or sensing ambient light. A controller may control the illumination level of the LEDs in response to sensed ambient light. Adjacent key suppression algorithms are also provided. | 2009-06-25 |
20090160530 | SEMICONDUCTOR DEVICE WITH REDUCED LAYOUT AREA HAVING SHARED METAL LINE BETWEEN PADS - A semiconductor device with a reduced layout area includes pads disposed between a first voltage line and a second voltage line; first and second driver units adjacently disposed at an upper portion or a lower portion of the respective pads; and a metal line disposed between the pads and supplying power commonly to the first and second driver units. | 2009-06-25 |
20090160531 | MULTI-THRESHOLD VOLTAGE-BIASED CIRCUITS - A circuit and a method of operation to reduce dynamic and static power dissipation in the circuit are disclosed. The circuit is multi-threshold, voltage-biased and includes a p-channel field effect transistor (FET) and an n-channel FET. A source terminal of the p-channel FET interconnects to a higher-voltage rail of a power supply and a source terminal of the n-channel FET interconnects to a lower-voltage rail of the power supply. At least one of the FETs includes a back contact. The circuit may be operated by applying a fixed bias voltage to the back contact. The fixed bias voltage is independent of the power supply voltage which may be varied. In a normal state, the supply voltage is adjusted to decrease dynamic power consumption. In a low power state, the supply voltage is further adjusted to limit leakage current. The circuit may optionally include a second fixed biasing voltage source so that both FETs are biased. | 2009-06-25 |
20090160532 | Charge pump circuit - A charge-pump circuit without reverse current is disclosed. The charge-pump circuit includes: several diode equivalent networks connecting in series, between any two of adjacent diode equivalent networks having a node with a corresponding voltage-boost level, wherein the low voltage end in the diode equivalent network with lowest voltage-boost level is the input of the charge-pump circuit, and the input receives an input voltage signal; a voltage-boost capacitor network having an end to electronically couple to one of the node and the other end to electronically couple to a pulse signal, wherein the pulse signal has a high-voltage level and a low-voltage level to raise a voltage level at the node with voltage-boost as high-voltage level and low-voltage level switches; and a reverse current cut-off circuit electronically coupled to the diode equivalent networks to enable and disable the diode equivalent networks, wherein the reverse current cut-off circuit has two conductive paths. | 2009-06-25 |
20090160533 | DC-DC VOLTAGE CONVERTER HAVING STABILIZED DIVIDED OUTPUT VOLTAGE - A DC-DC voltage converter includes a current comparator converting a fixed reference voltage and an input voltage to a corresponding reference current and input current. The current comparator compares levels of the reference current and input current to output a control signal. A charge pump converts an output voltage to corresponding to a target voltage by performing a charge pumping operation in response to the control signal. An input voltage providing unit divides the output voltage to output the input voltage which is fed back into the current comparator, and as such is capable of reducing the area occupied by the DC-DC voltage converter in the semiconductor device and improving current consumption. | 2009-06-25 |
20090160534 | Circuit Arrangement for Providing a Voltage Supply for a Transistor Driver Circuit - The invention relates to a circuit arrangement for providing a voltage supply for a driver circuit for driving a semiconductor switch. The circuit arrangement has: a first bootstrap circuit which is supplied with a first auxiliary voltage referring to a lower supply potential, the bootstrap circuit comprising a first capacitor which provides a supply voltage for the driver circuit; a first charge pump which is designed to keep the charge in the first capacitor at or above a particular level at least during a particular period of time; a second bootstrap circuit which is supplied with a second auxiliary voltage referring to an upper supply potential, the bootstrap circuit comprising a second capacitor which provides a supply voltage for the first charge pump; and a second charge pump which is designed to generate the second auxiliary voltage. | 2009-06-25 |
20090160535 | TEMPERATURE AND PROCESS-STABLE MAGNETIC FIELD SENSOR BIAS CURRENT SOURCE - A temperature and process-stable magnetic field sensor bias current source provides improved performance in Hall effect sensor circuits. A switched-capacitor sensing element is used to sense either a reference current or the bias current directly. A current mirror may be used to generate the bias current from the reference current, and may include multiple current source transistors coupled through corresponding control transistors that are switched using a barrel shifter to reduce variations in the bias current due to process variation. The current mirror control may be provided via a chopper amplifier to reduce flicker noise and the current mirror control voltage may be held using a track/hold circuit during transitions of the chopper amplifier to further reduce noise due to the chopping action. | 2009-06-25 |
20090160536 | ELECTRONIC DEVICE, LOAD FLUCTUATION COMPENSATION CIRCUIT, POWER SUPPLY, AND TEST APPARATUS - Provided is a load fluctuation compensation circuit, including a first delay circuitry section that delays a clock signal supplied thereto by a delay amount that fluctuates by a prescribed first fluctuation amount in relation to a unit fluctuation amount of a power supply voltage supplied to a performance circuit; a second delay circuitry section that is disposed in parallel with the first delay circuitry section and that delays the clock signal supplied thereto by a delay amount that fluctuates by a second fluctuation amount, which is greater than the first fluctuation amount, in relation to the unit fluctuation amount of the power supply voltage supplied to the performance circuit; a load circuit that is connected to a common power supply wiring in parallel with the performance circuit; and a phase detecting section that detects a phase difference between the clock signal output by the first delay circuitry section and the clock signal output by the second delay circuitry section and that controls an amount of current consumed by the load circuit based on the detected phase difference. | 2009-06-25 |
20090160537 | Bandgap voltage reference circuit - A bandgap voltage reference circuit with an inherent curvature correction which comprises an amplifier having an inverting terminal, a non-inverting terminal and an output terminal is described. A first and second bipolar transistor operable at different current densities are provided each of the transistors being coupled to a corresponding one of the inverting and non-inverting terminals of the amplifier such that a ΔVbe is reflected across a first load element. A current biasing circuit is provided which includes a semiconductor device coupled to each of the first and second bipolar transistors and is configured for applying a non-linear bias current to the first and second bipolar transistors for biasing thereof. | 2009-06-25 |
20090160538 | Low voltage current and voltage generator - A bandgap reference circuit which is operable in low supply conditions is described. Such a circuit includes a second amplifier and a resistor at the output of a bandgap reference cell to create a constant current summing node at which PTAT and CTAT currents are summed. In modifications to the circuit it is possible to also provide a voltage reference node corresponding to the signal provided at the summing node. A further modification enables generation of a second voltage reference whose value is related to the base emitter voltage Vbe of a bipolar transistor. Further modifications provided for the generation of curvature correction within the circuit by biasing each of the first and second bipolar transistors Q1 and Q2 with currents of different forms. | 2009-06-25 |
20090160539 | Voltage reference circuit - A voltage reference circuit comprises a current mirror set, a first resistor, a first MOS transistor, and a second MOS transistor. The output end of the current mirror set is coupled to a first resistor, and the node of the current mirror set is coupled to the first MOS transistor, furthermore, the second MOS transistor is coupled to the first MOS transistor, and the first end and the gate of the second MOS transistor are coupled each other, such that a stable voltage reference will be obtained between the first MOS transistor and the second MOS transistor. | 2009-06-25 |
20090160540 | POWER-UP CIRCUIT FOR REDUCING A VARIATION IN TRIGGERING VOLTAGE IN A SEMICONDUCTOR INTEGRATED CIRCUIT - A power-up circuit for reducing a variation in triggering voltage in a semiconductor integrated circuit is described. The power-up circuit includes a pull-up resistor unit that is connected to a power voltage source. A pull-up resistance adjusting unit varies the resistance value of the pull-up resistor unit. The power-up circuit also includes a pull-down resistor unit that is connected between the pull-up resistor unit and a ground. Finally, the power-up circuit includes a detector connected to a common node of the pull-up resistor unit and the pull-down resistor unit. | 2009-06-25 |
20090160541 | Digital Photo Frame with Power Saving Function and Related Power Saving Method - A digital photo frame having power saving functions includes a display panel, a power generation unit for switching a system power according to a power control signal, a user detection unit installed on the display panel for detecting whether a user exists within a specific range to generate a user detection signal, a central processing unit for adjusting backlight intensity of the display panel when the system power is provided by the power generation unit according to the user detection signal and for generating a power switch-off signal when the backlight intensity of the display panel is turned off according to the user detection signal, and a power control unit for generating the power control signal to switch off the system power when the backlight intensity of the display panel is adjusted to be switched off according to the power switch-off signal. | 2009-06-25 |
20090160542 | STABLE VOLTAGE GENERATING CIRCUIT FOR A DELAY LOCKED LOOP AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME AND METHOD OF GENERATING A STABLE VOLTAGE FOR A DELAY LOCKED LOOP - A stable voltage generating circuit for a delay locked loop for generating a stable internal voltage for a delay locked loop and a semiconductor memory device including the same, and a method of generating a stable voltage for a delay locked loop is disclosed. The voltage generating circuit includes a first detector which compares a feedback voltage that represents the internal voltage for the delay locked loop with a reference voltage and outputs the comparison result as a first detection signal. A second detector detects the escape timing of a power down mode to provide a second detection signal having a configurable enable width interval after the escape timing of the power down mode. Finally, the voltage generating circuit includes a voltage driver which drives and outputs the internal voltage either the first detection signal or the second detection signal is enabled to maintain a stable internal voltage level. | 2009-06-25 |
20090160543 | NOISE PROTECTOR - A noise protector includes a first noise control block for NORing an input signal and a first trimmed input signal and providing an output; a second noise control block for NANDing the input signal and a second trimmed input signal and providing an output; and an output signal generation block for outputting an output signal removed of noise in response to the outputs of the first noise control block and the second noise control block. | 2009-06-25 |
20090160544 | SEMICONDUCTOR INTEGRATED CIRCUIT - A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area | 2009-06-25 |
20090160545 | DUAL VOLTAGE SWITCHING CIRCUIT - A dual voltage switching circuit includes an input terminal receiving a control signal, an output terminal, three transistors, and a Zener diode. The gate of the first transistor is connected to the input terminal. The drain of the first transistor is connected to a standby power and the gate of the second transistor. The drain of the second transistor is connected to a first system power and the gate of the third transistor. The sources of the first transistor and the second transistor are grounded. The drain of the third transistor is connected to the input terminal. The source of the third transistor is connected to a second system power. The anode of the Zener diode is connected to the standby power. The cathode of the Zener diode is connected to the output terminal. The output terminal selectively outputs the standby power or the second system power. | 2009-06-25 |
20090160546 | AM (AMPLITUDE MODULATION) DEMODULATION SYSTEM FOR RFID READER DEVICE - AM (Amplitude Modulation) demodulation system ( | 2009-06-25 |
20090160547 | METHOD AND SYSTEM FOR TRANSITIONING BETWEEN OPERATION STATES IN AN OUTPUT SYSTEM - A closed loop amplifier system comprising a modulator that provides a pulse-width modulated (PWM) output signal based on an input signal, the modulator having a variable closed loop transfer function. The system also comprises a ramp generator that provides a ramp signal to the modulator, the variable closed loop transfer function of the modulator varying as a function of the ramp signal. The system further comprises a controller that controls the ramp generator to provide the ramp signal to adjust the variable closed loop transfer function during transitions between operating states of the amplifier system. | 2009-06-25 |
20090160548 | POWER AMPLIFYING APPARATUS - A power amplifying apparatus includes a high-speed low pass filter which inputs an envelope signal included in a transmission signal therein, a low-speed low pass filter which inputs the envelope signal therein, a determination unit which inputs the envelope signal therein and determines rising or falling of the envelope signal, a selecting unit which selects one of the high-speed low pass filter and the low-speed low pass filter according to a determined result of the determination unit, and a voltage supply unit which generates a voltage based on a signal input according to a selection by the selecting unit and supplies the voltage to a power amplifier which inputs the transmission signal therein so as to amplify a power of the transmission signal. | 2009-06-25 |
20090160549 | Linearised Power Amplifier - A linearised power amplifier including a predistorter and a feedforward circuit is described. By using both a predistorter and a feedforward cancellation system the linearisation of the amplifier is increased. The accuracy of the amplified signal may be further improved by training the predistorter using the error signal produced by the feedforward cancellation system. Improved accuracy in the lineariser results in a reduction in the power requirement of the error amplifier and a relaxation in the phase, amplitude and delay accuracy of the feedforward loop. | 2009-06-25 |
20090160550 | PREDISTORTER - A predistorter for correcting distortion caused by a memory effect in amplifying a signal by an amplifier is provided. In the memory PD | 2009-06-25 |
20090160551 | Switching Amplifier - A switching amplifier includes an input end for receiving an input signal, a reference signal reception end for receiving a reference signal, a feedback end for receiving a feedback signal, an output end for outputting an output signal, an integration circuit for performing integration operation on the input signal according to the output signal and the feedback signal, so as to generate an integration result, a comparison circuit coupled to the integration circuit, the reference signal end, and the output end, for comparing the integration result and the reference signal, so as to generate the output signal for the output end, and a feedback circuit coupled between an output end of the integration circuit and the feedback end, for generating the feedback signal for the feedback end to clamp the integration result to a predetermined value when the integration result reaches the predetermined value. | 2009-06-25 |
20090160552 | APPARATUS AND METHOD FOR CLASS D AMPLIFIER WITH SAMPLING RATE CONVERSION - A class D amplifier is provided. The class D amplifier includes an interpolator, a sampling rate converter, a pulse width modulator, a sigma-delta modulator, and a pulse width modulation (PWM) pulse generator (PPG). The sampling rate converter interpolates the output of the interpolator such that the sampling rate converter up-samples the interpolator output by a factor that is greater than one and less than two. The pulse width modulator outputs a multi-bit digital signal. The sigma-delta modulator performs sigma-delta modulation on the pulse width modulator output, the order of the sigma-delta modulation is programmable, and the output of the sigma-delta modulator is a multi-bit, digital signal. At least one of the orders to which the sigma-delta modulator can be programmed is greater than two. The PPG provides a pulse signal such that the width of each pulse is based on the value of the sigma-delta modulator output. | 2009-06-25 |
20090160553 | DISTORTION SUPPRESSION CIRCUIT FOR DIGITAL CLASS-D AUDIO AMPLIFIER - A digital Class-D amplifier distortion suppression circuit design is disclosed. A distortion suppression feedback loop is described to improve audio performance by suppressing output stage non-linearity and improving power supply noise rejection achieving reduced THD+N. The feedback loop is placed around the power stage. It forces tracking between the audio band signals at the input and output of the power stage by automatically adjusting the gating signal timing based on sensed effective duty ratio error. Error sensing and compensation are performed using techniques that lend to simple circuit implementation. | 2009-06-25 |
20090160554 | AMPLIFIER ARRANGEMENT - A gain-controlled RF amplifier system has an input node and an output node. The system has a plurality of amplifier devices, selectively connectable between the input node and the output node. The amplifier devices are placed in circuit according to a measured gain derived by comparing a magnitude of a signal input to the input node against a magnitude of a signal output from the output node, and a desired value of gain. | 2009-06-25 |
20090160555 | APPARATUS FOR POWER AMPLIFICATION BASED ON ENVELOPE ELIMINATION AND RESTORATION (EER) AND PUSH-PULL SWITCHING - A power amplifying apparatus based on envelope elimination and restoration (EER) includes a voltage amplifier to amplify a high frequency component of an envelope signal, a switching amplifier to generate a low frequency component signal of a drain bias based on a first pulse width modulation (PWM) signal that corresponds to a low frequency component of the envelope signal, and a push-pull switch, connected to the switching amplifier in parallel, to add a high frequency component signal to an output of the switching amplifier by pushing or pulling current to or from the output of the switching amplifier. | 2009-06-25 |
20090160556 | System and Method for Providing a Configurable Inductor Less Multi-Stage Low-Noise Amplifier - In accordance with a particular embodiment of the present invention, an apparatus is offered that includes a configurable feedback low noise amplifier (LNA) connected to a common source connected input transistor to realize a specific value of an input impedance, the input impedance being controlled by transconductance, the overall gain being defined by a global current feedback network. In more specific embodiments, the LNA is used to provide a wide frequency band and a defined input impedance. In other embodiments, the LNA achieves a low noise parameter and low output distortion. Also, the LNA can use a ladder network of grounded switches and floating resistors in order to avoid floating switches in a feedback path. The LNA can increase parametric yield. The LNA can be used to control noise, gain, distortion, and input impedance independently. | 2009-06-25 |
20090160557 | SELF-BIASED CASCODE CURRENT MIRROR - A self-biased cascode current mirror circuit, including a first transistor having a first current electrode, a control electrode, and a second current electrode; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the first current electrode of the first transistor, and a second current electrode coupled to a terminal; a third transistor having a first current electrode configured to provide an output current, a control electrode coupled to the control electrode of the first transistor and the first current electrode of the third transistor, and a second current electrode; and a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to the terminal. | 2009-06-25 |
20090160558 | RF AMPLIFIER - Provided is a radio frequency (RF) amplifier. The RF amplifier includes an amplification circuit amplifying an RF signal, a bias voltage generation circuit supplying a bias voltage of the amplification circuit, and a first bias resistor connected between the amplification circuit ad the bias voltage generation circuit, and having a predetermined resistance allowing the bias voltage to be affected by the RF signal. | 2009-06-25 |
20090160559 | INTEGRATED CIRCUIT INCLUDING IMPEDANCE TO PROVIDE SYMMETRICAL DIFFERENTIAL SIGNALS - One embodiment provides an integrated circuit including an input stage and an impedance. The input stage is configured to receive a single-ended input signal and provide a differential output signal. The impedance is configured to receive the single-ended input signal and provide compensation to the input stage to provide symmetrical differential signals in the differential output signal. | 2009-06-25 |
20090160560 | Phase locked loop and method for controlling the same - Phase locked loop and method for controlling the same includes a phase/frequency detector configured to detect a phase difference between an input clock and a feedback clock to generate an up signal or a down signal depending on the detected phase difference, a charge pump configured to variably control a bandwidth according to a bandwidth control signal input thereinto, the charge pump operating in response to the up signal or the down signal and a voltage controlled oscillator configured to change a frequency according to an output of the charge pump. | 2009-06-25 |
20090160561 | SURFACE-MOUNT TYPE CRYSTAL OSCILLATOR - The surface-mount type crystal oscillator includes a container body made of laminated ceramics, having a flat bottom wall layer, a frame wall defining a recess and a step portion formed at an inner wall of the recess, a crystal blank fixed to the step portion, an IC chip fixed to an inner bottom surface of the recess and a pair of inspection terminals provided on outer side surfaces of the container body and used to measure a vibration characteristic of the crystal blank. The bottom wall layer is made up of a first layer making up an outer bottom surface of the container body and a second layer between the first layer and the frame wall, and the inspection terminals are formed so as to extend across an end face of the second layer and the outer side surface of the frame wall. | 2009-06-25 |
20090160562 | OSCILLATING DEVICE - The present invention provides an oscillating device. The oscillating device includes: a voltage regulating module, a current generating module, and an oscillating module. The voltage regulating module is utilized for generating a control voltage at an output terminal, and the voltage regulating module includes: a first operational amplifier, a first switch element, and a first voltage dividing circuit. The oscillating module includes: a plurality of switch modules connected in series, a current mirror module, and a plurality of capacitor modules. In the oscillating device of the present invention, a frequency of an oscillating signal outputted by the oscillating module will not be affected by voltage offset of an operating voltage, environment temperature variations, or semiconductor process variations. | 2009-06-25 |
20090160563 | SURFACE-MOUNT TYPE CRYSTAL OSCILLATOR - A surface-mount type crystal oscillator includes a container body with a recess, a first holding terminal and a second holding terminal provided in the recess, a crystal blank secured to the first and second holding terminals, and an IC chip including a first terminal and a second terminal on respective opposite sides of one end of the IC chip, the first and second terminals being used to electrically connect the amplification element within the IC chip to the crystal blank. In the recess, the first connection terminal is connected, by wire bonding, to one of a first circuit terminal connected to the first holding terminal and a second circuit terminal connected to the second holding terminal. The second connection terminal is connected, by wire bonding, to one of a third circuit terminal connected to the first holding terminal and a fourth circuit terminal connected to the second holding terminal. | 2009-06-25 |
20090160564 | ENHANCED ALL DIGITAL PHASE-LOCKED LOOP AND OSCILLATION SIGNAL GENERATION METHOD THEREOF - An All Digital PLL (ADPLL) and oscillation signal generation method using the ADPLL is provided for generating a spur-free oscillation signal by improving the frequency resolution of the ADPLL. An all digital phase-locked loop of the present invention includes a digitally controlled oscillator for generating an oscillation signal having a frequency corresponding to an inputted control signal, a re-timer for retiming a reference clock based on the oscillation signal, a feedback circuit for accumulating a number of clocks of the oscillation signal within a time period and generating a phase information of the oscillation signal in synchronization with the retimed reference clock, a sigma-delta modulator for sigma-delta modulating a frequency command signal into a modulation signal having a less number of bits than a number of bits of the frequency command signal, a reference phase accumulator for accumulating phases corresponding to the modulation signal, a phase difference detector for generating a phase difference information between an output signal of the reference phase accumulator and the phase information, and a digital loop filter for filtering the phase difference information to generate the control signal. | 2009-06-25 |
20090160565 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator | 2009-06-25 |
20090160566 | LOW VOLTAGE LOGEN - Low voltage LOGEN. LOGEN is a local oscillator generator. Two separately implemented dividers allow for relatively lower power dissipation while supporting multiple modes of operation within the communication device. Each of these two or more dividers has different phase noise characteristics. These at least two separately implemented dividers also allows for the supporting of at least two modes of operational within an apparatus. In certain applications (e.g., wireless applications), there is a need for relatively low phase noise characteristics therein, and the use of these at least two separately implemented dividers allows for the appropriate implementation of the relatively higher grade dividers in those areas that can benefit more there from. | 2009-06-25 |
20090160567 | Oscillator Circuit with Acoustic Single-Port Surface Wave Resonators - The invention refers to the electrical engineering/electronics field and relates to an oscillator circuit consisting of a combination of two frequency-determining elements and one active electronic circuit, wherein the frequency-determining elements are designed as single-port surface wave resonators with interdigital converters. According to the invention, the two single-port surface wave resonators are connected to each other, avoiding inductive components whereas, in the case of a combination in a parallel circuit, the connection is designed as a combination oscillating at high-frequency anti-resonance, and in the case of a combination in a series circuit, the combination is designed as a combination oscillating at high-frequency resonance. In addition, according to the invention, the ratio of the apertures of the interdigital converters to one another, the ratio of their number of prongs to one another, and the thickness of the electrode layer of the single-port surface wave resonators as well as the propagation direction for acoustic surface waves of the single-port surface wave resonators are selected so that the temperature-dependent change of the phase of the combination and the temperature-dependent change of the total phase of the rest of the elements of the oscillator circuit have signs opposite to one another and that the sum of these phase changes in the thermal operating range of the oscillator circuit is smaller than the value of the phase change of the combination and smaller than the value of the phase change of the rest of the elements of the oscillator circuit. The invention can be used with oscillators and sensors based on acoustic surface waves, in particular with components for which the temperature response of the oscillator frequency can be set. | 2009-06-25 |
20090160568 | CIRCUIT AND METHOD FOR A WIRELESS ACCESSORY OF A MOBLIE DEVICE - The invention relates to a circuit and method for a wireless accessory of a portable computer. The circuit comprises an oscillator circuit ( | 2009-06-25 |
20090160569 | SYSTEMS AND METHODS FOR COMPENSATING FOR VARIATIONS OF THE OUTPUT OF A REAL-TIME CLOCK - Method and systems are provided for adjusting real-time clocks to compensate for frequency offset, temperature effects, and/or aging effects. | 2009-06-25 |
20090160570 | CLOCK SIGNAL GENERATOR - The present invention provides a clock signal generator capable of reducing current consumption and stably outputting a clock signal early. When it is discriminated that the amplitude of an amplification oscillation signal obtained by amplifying an oscillation signal produced from a crystal oscillator according to a constant current value has exceeded threshold amplitude, the clock signal generator generates a clock signal, based on the amplification oscillation signal. When it is discriminated that the total number of clock pulses of the clock signal has exceeded a predetermined pulse number, the clock signal generator reduces the constant current value. | 2009-06-25 |
20090160571 | CIRCUIT AND METHOD FOR GENERATING A CONTINUOUS PULSE SIGNAL - The present invention discloses a circuit and method for generating a continuous pulse signal. The circuit of the present invention comprises: a PWM device generating a clock signal and a PWM signal, and a pulse continuity detector coupled to the PWM device. The pulse continuity detector further comprises: a positive pilot signal generator, a negative pilot signal and a multiplexer. The positive pilot signal generator is coupled to the PWM device to receive the clock signal and the PWM signal and then outputs a positive pilot signal. The negative pilot signal generator is coupled to the PWM device to receive the clock signal and the PWM signal and then outputs a negative pilot signal. The multiplexer is coupled to the PWM device, the positive pilot signal generator and the negative pilot signal generator to receive the PWM signal, the positive pilot signal and the negative pilot signal, and outputs the positive pilot signal or the negative pilot signal according to the PWM signal. Thus, the present invention can provide a continuous pulse signal and prevent the pulse signal from being interrupted. | 2009-06-25 |
20090160572 | COMMUNICATION APPARATUS - A communication apparatus has a local oscillator which performs phase modulation based on a phase component of a baseband signal and outputs a phase modulated signal, a controlling circuit which is supplied with an integer portion included in an amplitude component of the baseband signal and generates and outputs a controlling signal based on a size of the integer portion, a subtractor which is supplied with the integer portion and the controlling signal, subtracts a value of the controlling signal from the integer portion, and outputs a result, a MASH (Multi-stAge-noise-Shaping) circuit which is a second-order delta-sigma modulation means supplied with a fractional portion of the amplitude component, an order of the MASH circuit being switchable between a first order and a second order based on the controlling signal, and an amplifier which sets a voltage value based on an output of the MASH circuit and an output of the subtractor, multiplies the voltage value and the phase modulated signal, and outputs a result. | 2009-06-25 |
20090160573 | GFCI-Compatible Circuit for Plasma Cutting System - In one embodiment, a system is provided that includes a GFCI compatibility control configured to filter noise, improve symmetry between lines, or a combination thereof, when connecting a device to a GFCI-protected power source. In another embodiment a circuit for a torch power unit is provided that includes an inductor comprising a first coil and a second coil, wherein the total inductance for the first coil is substantially the same as the total inductance for the second coil, and a plurality of capacitors coupled to both the first and second coils. Another system is provided that includes a torch power unit. The torch power unit includes a compressor, a motor coupled to the compressor, and a GFCI compatibility control configured to filter noise, improve symmetry between lines, or a combination thereof, when connecting a device to a GFCI-protected power source. | 2009-06-25 |
20090160574 | BOUNDARY ACOUSTIC WAVE FILTER - A boundary acoustic wave filter device includes an electrode structure provided at a boundary between a piezoelectric body and a dielectric body laminated on the piezoelectric body and utilizes an SH-type boundary acoustic wave that propagates along the boundary. In the boundary acoustic wave filter device, the electrode structure includes a longitudinally coupled resonator boundary acoustic wave filter portion that has a first IDT and second and third IDTs arranged respectively on both sides of the IDT in a direction in which the boundary acoustic wave propagates. At portions at which two IDTs are located adjacent to each other in the direction in which the boundary acoustic wave propagates, narrow pitch electrode finger portions are provided in the IDTs, and the pitch of the electrode fingers of the narrow pitch electrode finger portion is different from the pitch of the electrode fingers of each of the narrow pitch electrode finger portions. | 2009-06-25 |
20090160575 | Power Combiners and Dividers Based on Composite Right and Left Handed Metamaterial Structures - Techniques, apparatus and systems that use composite left and right handed (CRLH) metamaterial structures to combine and divide electromagnetic signals at multiple frequencies. The metamaterial properties permit significant size reduction over a conventional N-way radial power combiner or divider. Dual-band serial power combiners and dividers and single-band and dual-band radial power combiners and dividers are described. | 2009-06-25 |
20090160576 | Passive Fourier Transform Circuits and Butler Matrices - The coupling circuit described herein comprises passive analog components for coupling a transceiver to an antenna, such as an antenna array. The coupling circuit transforms an input signal into an appropriate format for each element of the antenna array. The coupling circuit comprises a coupling network having a plurality of inputs and a plurality of outputs. The inputs provide quadriphase versions of at least one input signal. In one embodiment, the coupling circuit performs a Discrete Fourier Transform (DFT) on the input signal. In another embodiment, the coupling circuit performs a Fast Fourier Transform (FFT) on the input signal. In still another embodiment, the FFT performed by the coupling circuit implements a Butler matrix. | 2009-06-25 |
20090160577 | CHARGE SAMPLING FILTER CIRCUIT AND CHARGE SAMPLING METHOD - (Problem) To provide a charge sampling filter circuit and a charge sampling method. | 2009-06-25 |
20090160578 | Filter Design Methods and Filters Based on Metamaterial Structures - Filter design techniques and filters based on metamaterial structures including an extended composite left and right handed (E-CRLH) metamaterial unit cell. | 2009-06-25 |
20090160579 | DIGITAL SIGNAL PROCESSOR - A digital signal processor includes a component for processing a digital signal, a power line for supplying a power to the component, and a decoupling capacitor connected between the power line and a ground. The decoupling capacitor has an equivalent series resistance larger than zero and not larger than 25 mΩ at 100 kHz and an equivalent series inductance larger than zero and not larger than 800 pH at 500 MHz. This digital signal processor does not generate a lot of digital noise, and has a small, thin size. | 2009-06-25 |
20090160580 | COIL LEADING STRUCTURE AND FILTER THEREOF - A filter includes a coil leading structure and at least one coil. The coil leading structure includes a board and at least one pin. The pin is disposed at a side of the board and formed integrally with the board as a monolithic piece. The core is disposed on the board and has at least one end to be coupled with the pin. | 2009-06-25 |
20090160581 | Temperature Stable MEMS Resonator - One embodiment of the present invention sets forth a method for decreasing a temperature coefficient of frequency (TCF) of a MEMS resonator. The method comprises lithographically defining slots in the MEMS resonator beams and filling the slots with oxide. By growing oxide within the slots, the amount of oxide growth on the outside surfaces of the MEMS resonator may be reduced. Furthermore, by situating the slots in the areas of large flexural stresses, the contribution of the embedded oxide to the overall TCF of the MEMS resonator is increased, and the total amount of oxide needed to decrease the overall TCF of the MEMS resonator to a particular target value is reduced. As a result, the TCF of the MEMS resonator may be reduced in a manner that is more effective relative to prior art approaches. | 2009-06-25 |
20090160582 | BAND-PASS FILTER, HIGH-FREQUENCY COMPONENT, AND COMMUNICATION APPARATUS - A band-pass filter according to the present invention includes two or more resonant lines arranged side by side in a direction orthogonal to a laminating direction in a laminate substrate formed by laminating plural dielectric layers. Each of the resonant lines has a first coil pattern portion formed in the dielectric layers and a second coil pattern portion formed in the dielectric layers different from the dielectric layers in which the first coil pattern portion is formed. The first and second coil pattern portions are connected in series and formed in a spiral shape. At least one of the first and second coil pattern portions is formed as parallel lines in the plural dielectric layers. According to such a configuration, a band-pass filter that is reduced in size and reduced in loss is provided. | 2009-06-25 |
20090160583 | HYBRID SURFACE MOUNTABLE PACKAGES FOR VERY HIGH SPEED INTEGRATED CIRCUITS - In one example, a hybrid surface mountable package includes a housing at least partially defining a sealed cavity, two microwave integrated circuits (MIC) chips positioned inside the sealed cavity, and a very-high-speed interconnect connecting the two MIC chips to each other. The very-high-speed interconnect includes strong coupling co-planar waveguide (CPWG) transmission lines. | 2009-06-25 |
20090160584 | MEMS SWITCH WITH IMPROVED STANDOFF VOLTAGE CONTROL - A MEMS switch is provided including a substrate, a movable actuator coupled to the substrate and having a first side and a second side, a first fixed electrode coupled to the substrate and positioned on the first side of the movable actuator to generate a first actuation force to pull the movable actuator toward a conduction state, and a second fixed electrode coupled to the substrate and positioned on the second side of the movable actuator to generate a second actuation force to pull the movable actuator toward a non-conducting state. | 2009-06-25 |
20090160585 | Electromechanical radio frequency switch - An improved electromechanical RF switch provides enhanced reliability and lifespan by incorporating a middle plate between the case and base elements for locating the guide pins, reed holders and reeds to increase accuracy in critical component alignment. The middle plate reduces required precision during assembly of the switch, thus increasing assembly accuracy while reducing labor cost. The guide pins are made of a hard insulator such as glass to generate less wear particles, and the reed holder has a groove filled with lubricant to trap any wear particles that result from sliding friction during switch operation. Optionally, a low-friction bushing is used within the case bore to further reduce sliding friction during reed holder travel. The reeds are made of thin, flexible metal and have ends shaped so that when the ends contact switching terminals, a wiping action removes any surface contamination from both the reed ends and the terminals. | 2009-06-25 |
20090160586 | Protection Switch - A protection switch includes a plurality of single-pole protection switch modules in a mechanically coherent unit forming a multi-pole protection switch configuration. Each module includes a housing, a switching arm, a moving contact on the switching arm pivotably movable against a fixed contact between closed and open positions, a manual operating mechanism for adjusting the switching arm between the closed and open positions and a tripping mechanism for automatically resetting the switching arm into the open position upon a tripping condition. The manual operating mechanisms of all modules are coupled so that the modules are only switched jointly. The tripping mechanisms of all modules are coupled so that the tripping mechanism of each also trips all others. A one-piece coupling is insertable between adjoining modules for both mechanically fixing the modules to one another and coupling the manual operating mechanisms and the tripping mechanisms of the adjoining protection switch modules. | 2009-06-25 |
20090160587 | DEVICE WITH CONTACTLESS ADJUSTMENT MEANS - The invention relates to a device comprising an integrally closed enclosure ( | 2009-06-25 |
20090160588 | ELECTROMAGNETIC OPERATING DEVICE FOR SWITCH - An electromagnetic operating device for a switch comprises a fixed yoke ( | 2009-06-25 |
20090160589 | DEVICE WITH AN ELECTROMAGNET, CLUTCH, AND METHOD FOR PRODUCING AN ELECTROMAGNET - The invention relates to an apparatus having an electromagnet, comprising a coil and magnetic-field guide means, which at least partially surround the coil. According to the invention, the coil is provided with a sprayed or cast casing, wherein the magnetic-field guide means are formed from a material which comprises ferromagnetic metal particles and plastic material. The invention also relates to a clutch having an apparatus such as this, and to a method for production of an electromagnet. | 2009-06-25 |