26th week of 2009 patent applcation highlights part 16 |
Patent application number | Title | Published |
20090159990 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and/or a method of manufacturing the same that may include: Forming a gate insulating film over a semiconductor substrate in a gate region. Forming a first gate pattern over the gate insulating film. Forming a second gate pattern over the first gate pattern, such that the second gate pattern is wider than the first gate pattern. Forming sidewall spacers at both sides of the first gate pattern and the second gate pattern, such that spaces are formed between the sidewall spacers and the first gate pattern below the second gate pattern. | 2009-06-25 |
20090159991 | CMOS DEVICES WITH DIFFERENT METALS IN GATE ELECTRODES USING SPIN ON LOW-K MATERIAL AS HARD MASK - A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer. | 2009-06-25 |
20090159992 | SEMICONDUCTOR DEVICE HAVING A POLYSILICON ELECTRODE - A method of manufacturing a semiconductor device such as a MOS transistor. The device comprises a polysilicon gate ( | 2009-06-25 |
20090159993 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and/or a method for manufacturing a semiconductor device. A method may include at least one of the following: Forming a first oxide layer on a silicon substrate. Depositing a polysilicon layer on the first oxide layer. Forming a pattern on the polysilicon layer and the first oxide layer to expose a portion of the silicon substrate forming a polysilicon layer pattern and a first oxide layer pattern. Forming a second oxide layer on the entire surface of the silicon substrate. Forming a pattern on the second oxide layer to expose a portion of the silicon substrate. Growing a silicon on the exposed silicon substrate to form a silicon epitaxial layer. Removing the second oxide layer formed on the polysilicon layer pattern. | 2009-06-25 |
20090159994 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Semiconductor devices and manufacturing methods thereof are provided. A semiconductor device can include a gate dielectric, a gate electrode, sidewall spacers, and source and drain regions. The gate electrode can include an electrode seed layer and an electrode metal layer. In another embodiment, the gate electrode can be formed of a deposited metal silicon layer. | 2009-06-25 |
20090159995 | Method to deposit particles on charge storage apparatus with charge patterns and forming method for charge patterns - The present invention discloses a method to deposit particles on a charge storage apparatus with charge patterns and a forming method for charge patterns. The forming method for charge patterns includes providing the charge storage apparatus having an electrically conducting substrate and a charge storage media layer. The charge storage apparatus is disposed in a vacuum or an anhydrous environment. An electrode and the electrically conducting substrate are utilized to conduct a first voltage and a second voltage respectively to form an electric field. Charges are then stored into the charge storage media layer of the charge storage apparatus through the electric field and the charge patterns are then formed. Accordingly, particles are deposited on the charge pattern-defined areas. | 2009-06-25 |
20090159996 | Method Of Producing Microsprings Having Nanowire Tip Structures - A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring may then be removed, allowing the engineered stresses in the microspring to cause the structure to bend out of plane, elevating the nanowire off the substrate and out of plane. Use of the nanowire as a contact is thereby provided. The nanowire may be clamped at the tip of the microspring for added robustness. The nanowire may be coated during the formation process to provide additional functionality of the final device. | 2009-06-25 |
20090159997 | WAFER LEVEL PACKAGE STRUCTURE AND PRODUCTION METHOD THEREFOR - A wafer level package structure, in which a plurality of compact sensor devices with small variations in sensor characteristics are formed, and a method of producing the same are provided. This package structure has a semiconductor wafer having plural sensor units, and a package wafer bonded to the semiconductor wafer. The semiconductor wafer has a first metal layer formed with respect to each of the sensor units. The package wafer has a bonding metal layer at a position facing the first metal layer. Since a bonding portion between the semiconductor wafer and the package wafer is formed at room temperature by a direct bonding between activated surfaces of the first metal layer and the bonding metal layer, it is possible to prevent that variations in sensor characteristics occur due to residual stress at the bonding portion. | 2009-06-25 |
20090159998 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is flexible and superiority in physical strength. As a method for manufacturing a semiconductor device, an element layer including a plurality of integrated circuits is formed over one surface of a substrate; a hole having curvature is formed in part of one surface side of the substrate; the substrate is thinned (for example, the other surface of the substrate is ground and polished); and the substrate is cut off so that a cross section of the substrate has curvature corresponding to a portion where the hole is formed; whereby a laminated body including an integrated circuit is formed. Further, a thickness of the substrate, which is polished, is 2 μm or more and 50 μm or less. | 2009-06-25 |
20090159999 | QUANTUM DOT SOLAR CELL WITH ELECTRON RICH ANCHOR GROUP - A solar cell may including a quantum dot, an electron conductor and a bridge molecule disposed between the quantum dot and the electron conductor. The bridge molecule may include a quantum dot anchor that bonds to the quantum dot and an electron conductor anchor that bonds to the electron conductor. The quantum dot anchor may be an electron-rich anchor group that includes a Group 5A element. The solar cell may also include a hole conductor that is configured to reduce the quantum dot once the quantum dot absorbs a photon and ejects an electron through the bridge molecule and into the electron conductor. | 2009-06-25 |
20090160000 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SENSOR - An image sensor and a method for manufacturing the sensor are provided for reducing loss of light reflected from photodiodes, and thus, improving light efficiency. The method of manufacturing an image sensor can include providing a semiconductor substrate having a photodiode; and then forming a reflective film frame on the photodiode, the reflective film frame having sidewalls that are inclined with respect to the uppermost surface of the photodiode; and then forming an opening over the surface of the reflective film frame and corresponding to the photodiode by forming a reflective film on the sidewalls of the reflective film frame. | 2009-06-25 |
20090160001 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SENSOR - An image sensor and a method for manufacturing the same are disclosed. The image sensor manufacturing method may include forming a hard mask pattern over a semiconductor substrate to cover a photodiode region; forming convex photodiodes by wet-etching the photodiode region in the semiconductor substrate using the hard mask pattern; removing the hard mask pattern; forming an interlayer insulating film over the photodiode; forming color filter layers aligned with the photodiodes over the interlayer insulating film; and forming microlenses over the color filter layers. The resulting image sensor can transduce a greater quantity of light as compared to the related art, owing to an increased unit surface area, resulting in enhanced optical efficiency characteristics. | 2009-06-25 |
20090160002 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor may include an image sensor may include a photodiode formed over a semiconductor substrate. An interlayer dielectric, which may include a plurality of metal wires in a transistor region, may be formed over the semiconductor substrate, including a waveguide dielectric for guiding incident light in a photodiode region. A refractive layer may be formed at a bottom of the waveguide dielectric in the interlayer dielectric. A color filter may be formed over an upper surface of the interlayer dielectric. An overcoat may be formed over the color filter. A micro lens may be formed over the interlayer dielectric. Accordingly, high reflectivity at a bottom of the wave guide can be effectively restrained while guaranteeing reflectivity of the wave guide with respect light which is not vertically incident. | 2009-06-25 |
20090160003 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to an image sensor and a method for manufacturing the same. According to embodiments, an image sensor may include a semiconductor substrate and a transistor. An interlayer insulating layer, including a metal line, may be formed on and/or over the semiconductor substrate. A lower electrode may be formed on and/or over the metal line and may be connected with the metal line. A spacer may be formed on a sidewall of the lower electrode. A photo diode may be formed on and/or over an interlayer insulating layer including the lower electrode and the spacer. | 2009-06-25 |
20090160004 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device. According to embodiments, a method may include forming a metal layer on and/or over a lower structure formed on and/or over a semiconductor substrate, forming neighboring metal lines by patterning the metal layer by a photolithography process, forming an insulating layer on and/or over a surface of the lower structure and forming a void between the metal lines, and performing heat treatment to the metal lines and the insulating layer having the void. According to embodiments, a void may be used as a buffer against expansion of the metal lines in sintering due to a difference in a thermal expansion coefficient. This may prevent a blister phenomenon that may separate an insulating film from metal lines. | 2009-06-25 |
20090160005 | Image Sensor and Method for Manufacturing the Same - An image sensor includes circuitry, a metal interconnection, a first substrate, a metal ion-implanted insulating layer, and a photodiode. The circuitry is formed on and/or over the first substrate, and the metal ion-implanted insulating layer is formed on and/or over the metal interconnection. The photodiode is formed in a crystalline semiconductor layer over the metal ion-implanted insulating layer. | 2009-06-25 |
20090160006 | Systems and methods for biasing high fill-factor sensor arrays and the like - A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding. | 2009-06-25 |
20090160007 | Systems and Methods for biasing high fill-factor sensor arrays and the like - A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding. | 2009-06-25 |
20090160008 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device that includes an n-type semiconductor substrate and an upper electrode formed on an upper face of the semiconductor substrate and a method of manufacturing the semiconductor device are provided. A p-type semiconductor region is repeatedly formed in the semiconductor substrate in at least one direction parallel to the substrate plane so as to be exposed on an upper face of the semiconductor substrate. The upper electrode includes a metal electrode portion; and a semiconductor electrode portion made of a semiconductor material whose band gap is narrower than that of the semiconductor substrate. The semiconductor electrode portion is provided on each p-type semiconductor region exposed on the upper face of the semiconductor substrate. The metal electrode portion is in Schottky contact with an n-type semiconductor region exposed on the upper face of the semiconductor substrate, and is in ohmic contact with the semiconductor electrode portion. | 2009-06-25 |
20090160009 | Semiconductor array and method for manufacturing a semiconductor array - Semiconductor array and method for manufacturing a semiconductor array, wherein
| 2009-06-25 |
20090160010 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - A semiconductor device and a method for manufacturing the device capable of preventing an LDD region and a lower portion of the gate electrode from overlapping each other to achieve desirable device performance are disclosed. Embodiments relate to a semiconductor device and a method for manufacturing the device that may minimize overlap between an LDD region and a lower portion of the gate electrode. Minimizing overlap may maximize device performance and minimize the generation of defects between gate electrodes. | 2009-06-25 |
20090160011 | ISOLATOR AND METHOD OF MANUFACTURING THE SAME - The present invention relates to an isolator and a method of manufacturing the same. An isolator according to the present invention includes a silicon wafer, protective devices formed in predetermined regions of the silicon wafer, and a transformer formed in a predetermined region on the silicon wafer, the transformer having at least two coil patterns spaced apart from each other. According to the present invention, an isolator can be protected from impulses generated by ESD and surge, so that its reliability can be improved, and its size can be considerably decreased. Further, the number of wire bonding times is decreased, so that performance of a chip can be enhanced, and packaging efficiency can be improved, thereby increasing productivity. | 2009-06-25 |
20090160012 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a first device, a silicon epitaxial layer formed on and/or over the first device, a second device formed on and/or over the silicon epitaxial layer, and a connection via formed through the silicon epitaxial layer, which may electrically interconnect the first device and the second device. According to embodiments, a method for fabricating a semiconductor device may include forming a first device, forming a silicon epitaxial layer on and/or over the first device, forming a connection via through the silicon epitaxial layer, and forming a second device on and/or over the silicon epitaxial layer such that the second device may be electrically connected to the connection via. | 2009-06-25 |
20090160013 | SEMICONDUCTOR DEVICE HEAT DISSIPATION STRUCTURE - A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer. | 2009-06-25 |
20090160014 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and/or a method for manufacturing a semiconductor device. A method may include at least one of the following: Forming a first semiconductor layer over a semiconductor substrate. Forming a second semiconductor layer over the first semiconductor layer. Forming a trench through the first and second semiconductor layers. The trench may be fulled with an isolation film. The portion of the trench in the first semiconductor layer may have a width larger than a minimum width of the portion of the trench in the second semiconductor layer. | 2009-06-25 |
20090160015 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region. | 2009-06-25 |
20090160016 | SEMICONDUCTOR DEVICE - A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench. | 2009-06-25 |
20090160017 | Semiconductor device having capacitor, transistor and diffusion resistor and manufacturing method thereof - In manufacturing a semiconductor device including a substrate having a (111)-plane orientation and an off-set angle in a range between 3 degrees and 4 degrees, a capacitor, a transistor and a diffusion resistor are formed in the substrate, each of which are separated by a junction separation layer. A first silicon nitride film is formed by low pressure CVD over a surface of the substrate except a bottom portion of a contact hole and a portion over the junction separation layer, and a silicon oxide film is formed by low pressure CVD over the first silicon nitride film. A second silicon nitride film as a protecting film is formed by plasma CVD so as to cover the semiconductor device finally. Therefore, the semiconductor device having high reliability can be obtained. | 2009-06-25 |
20090160018 | INDUCTOR AND MANUFACTURING METHOD THREOF - An inductor includes an inductor wiring made of a metal layer and having a spiral planar shape. In a cross-sectional shape in a width direction of the inductor wiring, the inductor wiring has a larger film thickness at least in its inner side end than in its middle part. | 2009-06-25 |
20090160019 | SEMICONDUCTOR CAPACITOR - A capacitor structure is provided. The capacitor structure includes a plurality of first conductive lines paralleled disposed in a conductive layer on a substrate, wherein the first conductive lines are isolated to each other in the conductive layer and are grouped into a first electrode group and a second electrode group, an insulating layer formed on the first conductive lines and in the space between the first conductive lines, a second conductive line formed on the insulating layer electrically connected to the first conductive lines of the first electrode group, and a third conductive line formed on the insulating layer electrically connected to the first conductive lines of the second electrode group. | 2009-06-25 |
20090160020 | Moisture Barrier Capacitors in Semiconductor Components - Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node. | 2009-06-25 |
20090160021 | Corona prevention in high power MMICs - The present invention is drawn to an MMIC capacitor comprising a dielectric material interposed between a metal top plate and a metal bottom plate; and a passivation layer having the composition of the dielectric material and applied to the capacitor components such that thickness of the layer eliminates a corona effect. The invention also includes a method for passivating a layer of SiNi material onto a top plate having a thickness sufficient to reduce a corona effect dependent on an applied voltage. | 2009-06-25 |
20090160022 | METHOD OF FABRICATING MIM STRUCTURE CAPACITOR - The present invention relates to a method of fabricating a MIM structure capacitor. The method includes sequentially depositing a nitride film, a Ti film, and a TiN film over a lower electrode metal layer, the nitride film being an insulating layer, and a combination of the Ti/TiN layers being a upper metal electrode, for the MIM structure capacitor. The method further includes coating a photoresist layer on the upper electrode metal layer and patterning the photoresist layer, then selectively etching the upper metal electrode layer, and the nitride film by using the patterned photoresist layer as an etch mask, and finally removing nitride remaining on sidewalls of the MIM structure capacitor through a wet cleaning process. | 2009-06-25 |
20090160023 | Semiconductor device and manufacturing method thereof - An insulation film ( | 2009-06-25 |
20090160024 | VERTICAL RESISTORS AND BAND-GAP VOLTAGE REFERENCE CIRCUITS - A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first doped-type region receives a control bias, the second doped-type region receives a reference bias, and a resistance between the second doped-type region and the substrate is adjusted in response to a voltage difference between the control bias and the reference bias. | 2009-06-25 |
20090160025 | LATERAL BIPOLAR TRANSISTOR - A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers. | 2009-06-25 |
20090160026 | Nitride semiconductor free-standing substrate and method for making same - A nitride semiconductor free-standing substrate includes a nitride semiconductor crystal and an inversion domain with a density of not less than 10/cm | 2009-06-25 |
20090160027 | Methods of Manufacturing Semiconductor Devices and Optical Proximity Correction - Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined. | 2009-06-25 |
20090160028 | METHOD FOR FORMING GAPS IN MICROMECHANICAL DEVICE AND MICROMECHANICAL DEVICE - An exemplary method for forming gaps in a micromechanical device includes providing a substrate. A first material layer is deposited over the substrate. A sacrificial layer is deposited over the first material layer. A second material layer is deposited over the sacrificial layer such that at least a portion of the sacrificial layer is exposed. The exposed portion of the sacrificial layer is etched by dry etching. The remaining portion of the sacrificial layer is etched by wet etching to form gaps between the first material layer and the second material layer. One or more bulges are formed at one side of the second material layer facing the first material layer, and are a portion of the sacrificial layer remaining after the wet etching. | 2009-06-25 |
20090160029 | Scribe Seal Structure for Improved Noise Isolation - Disclosed is a semiconductor wafer with an array of integrated circuit chips with scribe lane structures forming edge and intra-chip seals for use in protecting the IC circuitry. Substantially parallel scribe seal structures extend around the periphery of each chip; the two scribe seal structures have a separation gap. Preferred embodiments of the invention also include wafers of ICs each having two or more distinctive circuitry blocks such as analog and digital circuitry, separated by an intra-chip seal. Preferred embodiments of also include ICs having two or more distinctive circuit blocks separated by a scribe seal structure with a separation gap and a routing channel for use in passing signals among the circuit blocks. | 2009-06-25 |
20090160030 | METHODS FOR FORMING THROUGH WAFER INTERCONNECTS AND STRUCTURES RESULTING THEREFROM - The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed. | 2009-06-25 |
20090160031 | Semiconductor Device and Method for Fabricating the Same - A semiconductor device capable of preventing damage to a thermal oxide layer in a trench, and a method for fabricating the same are disclosed. The device includes a trench in a field region of a semiconductor substrate; a pad oxide layer on the surface of the semiconductor substrate outside the trench; a thermal oxide layer on sidewalls of the trench; a nitride layer covering the thermal oxide layer; an insulating layer filling the trench; and a spacer covering the thermal oxide layer outside the trench. | 2009-06-25 |
20090160032 | Printed Electronic Device and Transistor Device and Manufacturing Method Thereof - An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap. | 2009-06-25 |
20090160033 | SEMICONDUCTOR OPTICAL ELEMENT - A light receiving element | 2009-06-25 |
20090160034 | MESA SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention provides a mesa semiconductor device and a method of manufacturing the same which minimize the manufacturing cost and prevents contamination and physical damage of the device. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N− type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the end portion of the anode electrode. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line. | 2009-06-25 |
20090160035 | MESA SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention provides a mesa semiconductor device and a method of manufacturing the same which enhance the yield and productivity. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N− type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the P type semiconductor layer on the outside of the mesa groove. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line. | 2009-06-25 |
20090160036 | PACKAGE WITH MULTIPLE DIES - A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package. | 2009-06-25 |
20090160037 | METHOD OF PACKAGING INTEGRATED CIRCUITS - A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality of second leads over the first leadframe. The method further includes electrically connecting each of the second leads to both an associated I/O pad and a first lead. | 2009-06-25 |
20090160038 | Semiconductor package with leads on a chip having multi-row of bonding pads - A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package. | 2009-06-25 |
20090160039 | METHOD AND LEADFRAME FOR PACKAGING INTEGRATED CIRCUITS - A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite the first side of the lead. Additionally, each of the first and second sides of the first set of leads each include at least two solder pads. Each solder pad on a lead of the first set of leads is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. In various embodiments, I/O pads from at least two dice are physically and electrically connected to the opposing sides of the leads. | 2009-06-25 |
20090160040 | LOW TEMPERATURE CERAMIC MICROELECTROMECHANICAL STRUCTURES - A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method provides for processing and manufacturing is steps limiting a maximum exposure of an integrated circuit upon which the MEMS is manufactured during MEMS manufacturing to below a temperature wherein CMOS circuitry is adversely affected, for example below 400° C., and sometimes to below 300° C. or 250° C., thereby allowing direct manufacturing of the MEMS devices onto electronic integrated circuits, such as Si CMOS circuits. | 2009-06-25 |
20090160041 | Substrate package structure - A substrate package structure is disclosed herein. The substrate package structure includes a packaging substrate provided with a plurality of chip carriers set at one surface of the packaging substrate, wherein those chip carriers are formed by intersecting a plurality of cutting streets; a plurality of through holes set at those cutting streets and set around those chip carriers; and a plurality of molding areas set on another surface of the packaging substrate and opposite to those chip carriers, wherein those molding areas are adjacent to those through holes. Hence, those through holes may be flowed by the molding compound to form a plurality of molding bumps around those chip carriers so as to improve the crack problem of the chip and/or the substrate. | 2009-06-25 |
20090160042 | Managed Memory Component - A system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along an obverse side of a flex circuit. In a preferred embodiment, the lower surface of the body of the leaded packaged IC contacts the surface of the flex circuitry. The semiconductor die is disposed beneath the leaded package IC and, in preferred embodiments, disposed in a window that passes through at least a part of the flex circuitry and is attached to a conductive layer of the flex circuitry. In other embodiments, the semiconductor die is attached to the body of the leaded packaged IC. The flex circuitry preferably employs at least two conductive layers and, in preferred embodiments, the leaded packaged IC is connected to the flex circuitry at one layer while the semiconductor die is connected to the flex circuitry at the other conductive layer. In preferred modules, the leaded packaged IC is preferably a flash memory device and the semiconductor die is preferably a controller. | 2009-06-25 |
20090160043 | Dice Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration - A dice rearrangement package structure is provided, which a dice having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover the dices and the plurality of pads being exposed; one ends of plurality of metal traces is electrically connected to the each pads; a protection layer is provided to cover the active surface and the other ends of the exposed metal traces is electrically connected to the plurality of conductive elements, the characteristic in that the package body is a B-stage material. | 2009-06-25 |
20090160044 | SEMICONDUCTOR MODULE MOUNTING STRUCTURE - The semiconductor module mounting structure includes a semiconductor module including therein a semiconductor device and electrodes exposed to both surfaces thereof, a wiring substrate having a mounting surface on which the semiconductor module is mounted, and a heat radiating body for dissipating heat from the semiconductor module. The wiring substrate is formed with a ground wiring such that at least a part of the ground wiring is exposed to a back surface thereof opposite to the mounting surface. The exposed surface of the ground wiring exposed to the back surface is in thermal contact with the heat radiating body. At least one of the electrodes exposed to one of the both surfaces opposed to the wiring substrate is in electrical contact with the ground wiring through a through hole formed in the wiring substrate. | 2009-06-25 |
20090160045 | WAFER LEVEL CHIP SCALE PACKAGING - A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip. | 2009-06-25 |
20090160046 | ELECTRONIC DEVICE AND METHOD - An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. | 2009-06-25 |
20090160047 | DOWNHOLE TOOL - A downhole tool having at least one semiconductor device, including: a die; a bonding pad which is attached to the surface of the die; a bonding wire which is attached to the bonding pad; a bonding point which is formed on the bonding pad for connecting the bonding wire to the bonding pad; an encapsulating resin encapsulating the die and being provided with a cavity such that a connecting portion of the bonding point and the bonding pad is exposed out of the resin in the cavity; and a lid on the encapsulating resin to cover the cavity. | 2009-06-25 |
20090160048 | Semiconductor Unit, and Power Conversion System and On-Vehicle Electrical System Using the Same - A semiconductor device includes a semiconductor chip and leads electrically connected to the electrodes of the semiconductor chip. A hollow radiator base houses the semiconductor device which is molded with high-thermal-conductivity resin having an electrical insulating property. The radiator base has a cooling-medium channel therein or radiating fins on the outside. Alternatively, the radiator base is housed in a second radiator base. | 2009-06-25 |
20090160049 | Semiconductor device - A semiconductor device of the present invention includes a semiconductor chip; an internal pad for electrical connection formed on a surface of the semiconductor chip; a stress relaxation layer formed on the semiconductor chip and having an opening for exposing the internal pad; a connection pad made of a metal having solder wettability, formed on a part facing the opening of the internal pad and provided with a protruding portion protruding on the stress relaxation layer; a metal flange made of a metal having solder wettability, encompassing the periphery of the protruding portion and formed with a smaller thickness than a protruding amount of the protruding portion onto the stress relaxation layer; and a solder terminal for electrical connection with outside formed on the protruding portion and the metal flange. | 2009-06-25 |
20090160050 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND WAFER - A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion. | 2009-06-25 |
20090160051 | Semiconductor Chip, Method of Fabricating the Same and Semiconductor Chip Stack Package - Provided are a semiconductor chip, a method of fabricating a semiconductor chip, and a semiconductor chip stack package. The semiconductor chip includes a semiconductor substrate and a semiconductor device on the semiconductor substrate. A dielectric covers the semiconductor device. A top metal is on the dielectric and electrically connected to the semiconductor device. A deep via penetrates the semiconductor substrate and the dielectric. An interconnection connects the deep via and the top metal electrically. A bump is in contact with the top metal and the interconnection. | 2009-06-25 |
20090160052 | UNDER BUMP METALLURGY STRUCTURE OF SEMICONDUCTOR DEVICE PACKAGE - The under bump metallization (UBM) structure of semiconductor device comprises a substrate having a bonding pad disposed on an active surface; a UBM adhered on the bonding pad, wherein the UBM includes lateral embedded portions and the size of the UBM is larger than the size of the bonding pad; a dielectric layer over the UBM having opening that is smaller than the size of the UBM so as to allow the lateral embedded portions being embedded into the dielectric layer with a desired dimension; and a conductive ball melted on the UBM within the opening defined by the dielectric layer. | 2009-06-25 |
20090160053 | METHOD OF MANUFACTURING A SEMICONDUCOTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. One embodiment provides a carrier. Semiconductor chips are placed over the carrier. The semiconductor chips include contact elements. A polymer material is applied over the semiconductor chips and the carrier. The polymer material is removed until the contact elements are exposed. The carrier is removed from the semiconductor chips. | 2009-06-25 |
20090160054 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor device is provided which reduces the contact resistance at the interface between a P-type electrode and a nitride semiconductor layer. A nitride semiconductor device includes a P-type nitride semiconductor layer and a P-type electrode formed on the P-type nitride semiconductor layer. The P-type electrode is formed by successive laminations of a metal layer of a metal having a work function of 5.1 eV or more, a Pd layer of palladium, and a Ta layer of tantalum on the P-type nitride semiconductor layer. | 2009-06-25 |
20090160055 | IC solder reflow method and materials - Embodiments of IC manufacture resulting in improved electromigration and gap-fill performance of interconnect conductors are described in this application. Reflow agent materials such as Sn, Al, Mn, Mg, Ag, Au, Zn, Zr, and In may be deposited on an IC substrate, allowing PVD depositing of a Cu layer for gap-fill of interconnect channels in the IC substrate. The Cu layer, along with reflow agent layer, may then be reflowed into the interconnect channels, forming a Cu alloy with improved gap-fill and electromigration performance. Other embodiments are also described. | 2009-06-25 |
20090160056 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same. The method can include forming a plurality of vias in a first interlayer insulation layer formed on a semiconductor substrate; and then forming a photoresist pattern over the first interlayer insulation layer to expose a portion of the first interlayer insulation layer and expose each via; and then forming a trench around an upper portion of each via by etching the exposed first interlayer insulation layer using the photoresist pattern as an etching mask; and then forming a metal layer over the first interlayer insulation layer including each trench; and then forming a plurality of metal lines over the vias and each trench by patterning the metal layer; and then forming a second interlayer insulation layer over the metal lines. Therefore, void generation between the metal lines during the highly integrated aluminum wiring process can be prevented. | 2009-06-25 |
20090160057 | Semiconductor device and method of manufacturing the same - A semiconductor device is provided in which penetration of a metal into a high impurity-doped active region from a side wall portion of a contact hole is prevented by reducing an aspect ratio to improve coverage of a titanium nitride film for the side wall portion of the contact hole, and in which increase in current consumption is eliminated. In a semiconductor device including an interlayer insulating film formed on a silicon substrate, and a interconnection formed of a barrier metal film and an aluminum alloy film and connected to the silicon substrate through a contact hole of the interlayer insulating film, a low-concentration impurity layer is epitaxially grown on a bottom surface of the contact hole, whereby the aspect ratio is reduced to improve coverage of the titanium nitride film for the side wall portion of the contact hole, and penetration of the metal into the high impurity-doped active region from the side wall portion of the contact hole is prevented. | 2009-06-25 |
20090160058 | Structure and process for the formation of TSVs - An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer. | 2009-06-25 |
20090160059 | Semiconductor Device Having Improved Adhesion and Reduced Blistering Between Etch Stop Layer and Dielectric Layer - One aspect of the invention provides a method of forming a semiconductor device ( | 2009-06-25 |
20090160060 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Embodiments relate to a method of manufacturing a semiconductor device having a porous low-k dielectric layer. According to embodiments, a method may include forming an inter metal dielectric (IMD) layer on and/or over a semiconductor substrate, forming copper lines having a stepped structure in the IMD layer, forming a barrier insulating layer on and/or over upper surfaces of the copper lines and the IMD layer, exposing a portion of the upper surface of the IMD layer by photolithography and etching processes, and forming air cavities in the IMD layer using a wet etching process on and/or over the exposed portion of the upper surface of the IMD layer. According to embodiments, a value of the dielectric constant (k) of the IMD layer or the porous low-k dielectric layer may be close to that of a vacuum state. | 2009-06-25 |
20090160061 | Introducing a Metal Layer Between Sin and Tin to Improve CBD Contact Resistance for P-TSV - The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench; a silicon nitride layer disposed over the conductive pad and in the TSV trench; a titanium layer disposed on the silicon nitride layer; a titanium nitride layer disposed on the titanium layer; and a copper layer disposed on the titanium nitride layer. | 2009-06-25 |
20090160062 | Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features. | 2009-06-25 |
20090160063 | Semiconductor Device - A semiconductor device includes a semiconductor substrate; a sealing resin layer formed on a top face of the semiconductor substrate; a metal post formed on the top face of the semiconductor substrate such that a top face of the metal post is exposed through the sealing resin layer; a projecting electrode formed on the top face of the metal post; and a low-elasticity resin layer made of a resin material with an elasticity modulus lower than that of the sealing resin layer and formed on the top face of the sealing resin layer such that part of the low-elasticity resin layer lies between the projecting electrode and the sealing resin layer. | 2009-06-25 |
20090160064 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - A semiconductor device and a method for manufacturing the device that minimizes a line width while maximizing integration density of the semiconductor device. The method includes forming an interlayer insulating film on a semiconductor substrate, and then forming a first via hole in the interlayer insulating film, and then forming a resin material in the first via hole, and then forming a plurality of second via holes in the interlayer insulating film laterally, and then forming a resin material in the second via holes, and then simultaneously forming a plurality of third via holes in the interlayer insulating film and a trench spatially above and corresponding to the first via hole, and then removing the resin formed in the first via hole and the second via holes, and then simultaneously forming metal layers in the first via hole and the second and third via holes and the trench. | 2009-06-25 |
20090160065 | Reconstituted Wafer Level Stacking - A stacked microelectronic assembly is fabricated from a structure which includes a plurality of first microelectronic elements having front faces bonded to a carrier. Each first microelectronic element may have a first edge and a plurality of first traces extending along the front face towards the first edge. After exposing at least a portion of the first traces, a dielectric layer is formed over the plurality of first microelectronic elements. After thinning the dielectric layer, a plurality of second microelectronic elements are aligned and joined with the structure such that front faces of the second microelectronic elements are facing the rear faces of the plurality of first microelectronic elements. Processing is repeated to form the desirable number of layers of microelectronic elements. In one embodiment, the stacked layers of microelectronic elements may be notched at dicing lines to expose edges of traces, which may then be electrically connected to leads formed in the notches. Individual stacked microelectronic units may be separated from the stacked microelectronic assembly by any suitable dicing, sawing or breaking technique. | 2009-06-25 |
20090160066 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, AND FABRICATION METHOD THEREOF - Semiconductor elements and methods for fabricating semiconductor elements that allow semiconductor elements having the same function to utilize different packaging methods. An exemplary semiconductor element includes a first semiconductor element portion, including an internal circuit, electrodes electrically connected to the internal circuit, and a first insulating layer covering the internal circuit while exposing the electrodes; and a second semiconductor element portion electrically connected to the electrodes and formed on the first insulating layer, the second semiconductor element portion including a wiring layer having a first pad and a second pad, and a second insulating layer configured to cover either one of the first pad or the second pad while exposing the other one of the first pad and the second pad. | 2009-06-25 |
20090160067 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package is described that includes two dice. The active surface of each die includes a plurality of I/O pads. The active surface of the first die is positioned adjacent first surfaces of the leads of a leadframe such that I/O pads from the first die are arranged adjacent corresponding solder pad surfaces on the first surfaces. Similarly, the active surface of the second die is positioned adjacent second surfaces of the leads opposite the first surfaces such that I/O pads from the second die are arranged adjacent corresponding solder pad surfaces on the second surfaces. A plurality of solder joints are arranged to physically and electrically connect I/O pads from the first or second die to associated adjacent solder pad surfaces on the leads. In this way, a single leadframe can be utilized to package two dice, one on either side of the leads of the leadframe. | 2009-06-25 |
20090160068 | FLIP-CHIP PACKAGE AND METHOD OF FORMING THEREOF - A flip-chip package is disclosed. The flip-chip package includes a substrate comprising at least one build-up layer. At least one longitudinal trench is formed in at least one build-up layer of the substrate. The at least one longitudinal trench filled with a conductive material. A conductive plane may be disposed at least partially on the at least one longitudinal trench. An insulating layer may cover the conductive plane and, at least in part, at least one build-up layer of the substrate. The solder resist layer may include a plurality of openings partially exposing the conductive plane. A plurality of conductive pads may be disposed on the conductive plane through the plurality of openings. A method for fabricating the flip-chip package is also disclosed. | 2009-06-25 |
20090160069 | Leadless alignment of a semiconductor chip - There is disclosed a mounting technique for mounting a semiconductor chip of the leadless or so-called flip chip type to a header. The header has an insert made of glass or other suitable non-conductive material within the header hollow. Mounted into the glass insert are a series of conductive metal pins which are placed in areas so that when a chip is mounted in the header, the chip makes contact with these conductive pins and allows one to make outside connections. Also positioned in the header are a series of nonconductive guide pins. These pins are placed in suitable positions in the header to enable one to contact the outside surfaces of the chip when the chip is placed in the header. In this manner, the chip is constrained from movement from side to side or from rotation. However, due to the positioning of the nonconductive pins within the header, it is possible to move the chip up and down while mounting. | 2009-06-25 |
20090160070 | METAL LINE IN A SEMICONDUCTOR DEVICE - A semiconductor having a metal line and a method of manufacturing a metal line in a semiconductor device is disclosed. In one example embodiment, a method of manufacturing a metal line in a semiconductor device includes various acts. A metal film for a metal line is formed on an interlayer dielectric layer of a semiconductor substrate. A silicon oxide hard mask film is formed on the metal film. A bottom anti-reflection (BARC) layer is formed on the hard mask film. The BARC layer, the hard mask film, and the metal film are selectively dry etched to form a metal line. | 2009-06-25 |
20090160071 | Die rearrangement package structure using layout process to form a compliant configuration - A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a polymer material with at least one slit is provided to cover the active surface and the pads is exposed from said slits; one ends of a plurality of metal traces is electrically connected to each pads; a protective layer is provided to cover the active surface of the dies and each metal traces, and the other ends of the metal traces being exposed; a plurality of connecting elements is electrically connected other ends of the metal traces, the characterized in that: the package body is a B-stage material. | 2009-06-25 |
20090160072 | VENTURI APPARATUS - An improved venturi apparatus for the incorporation of air into a liquid. The preferred embodiment of the invention comprises a funnel section, a cylindrical section, and a frusto-conical section. Lateral tubes extend from the cylindrical section so as to form an acute angle relative to the central axis of the cylindrical section, thereby preventing leakage of liquid out through the lateral tubes during use and subsequent handling. | 2009-06-25 |
20090160073 | Method for cast molding contact lenses - An improved method of cast molding contact lenses, wherein a lens forming mixture is cured in the lens-shaped cavity formed between molding surfaces of a male and female mold sections, wherein the improvement comprises at least one of sections is injection molded from a controlled rheology polypropylene. | 2009-06-25 |
20090160074 | Method for making contact lenses - The instant invention pertains to a method and a fluid composition for producing contact lenses with improved lens quality and with increased product yield. The method of the invention involves adding a phospholipid into a fluid composition including a lens-forming material in an amount sufficient to reduce an averaged mold separation force by at least about 40% in comparison with that without the phospholipids. | 2009-06-25 |
20090160075 | METHODS FOR FABRICATING CUSTOMIZED INTRAOCULAR LENSES - In one aspect, the present invention provides methods for custom fabrication of IOLs. In some embodiments, such methods call for measuring one or more aberrations of a patient's eye, and determining the profile of at least one surface of an IOL that would ameliorate, and control those aberrations. The surface profile can then be imparted to a surface of a starting lens (or a lens blank) via ablation, e.g., by utilizing an excimer laser beam. In some other embodiments, the measured aberrations can be utilized to determine the profile of at least one surface of a wafer mold. A wafer mold having that surface profile can then be fabricated, e.g., by ablating a slab or an existing wafer of appropriate material, and the mold can be used to fabricate an IOL suitable for implantation in the patient's eye. | 2009-06-25 |
20090160076 | Arrangement for Guiding a Mold Set Relative to a Hot Runner in a Molding System and a Method Thereof - Provided are an arrangement for guiding a mold set relative to a hot runner in the molding system and a method thereof. For example, an arrangement for guiding a mold set relative to a hot runner, the mold set including a cavity half and a core half, the mold set and the hot runner for use in a molding machine, is provided. The arrangement comprises a guiding member disposed on the hot runner; a guided member disposed on the cavity half; the guiding member and the guided member configured to cooperate to guide the mold set relative to the hot runner in a first direction and, sequentially, in a second direction, the second direction traversing the first direction. | 2009-06-25 |
20090160077 | AQUEOUS BINDER FOR FIBROUS OR GRANULAR SUBSTRATES - Aqueous binders for fibrous and granular substrates, based on itaconic acid copolymers. | 2009-06-25 |
20090160078 | DEVICE AND METHOD FOR PREPARATION OF A PROFILED ELEMENT FROM AN ELASTOMERIC THERMOPLASTIC GEL - A device for preparing a flat profiled element from an elastomeric thermoplastic gel includes: | 2009-06-25 |
20090160079 | Single stage drawing for MPD-I yarn - The invention relates to a continuous dry spinning process for preparing a fiber from a polymer solution having concentrations of polymer, salt, solvent and water. After the fiber is extruded and quenched, the fiber is placed in contact with a conditioning solution comprising concentrations of solvent, salt, and water. The conditioning solution acts upon the fiber to plasticize the fiber prior to being drawn. The conditioning solution has concentrations of solvent, salt, and water so that the fiber is plasticized to the extent necessary for drawing but does not plasticize the fiber to such an extent as to re-dissolve the fiber into a polymeric solution. A heat-treated fiber manufactured from this process has improved shrinkage and can be colored to darker shades. | 2009-06-25 |
20090160080 | High-speed meta-aramid fiber production - The invention relates to a continuous dry spinning process for preparing a fiber from a polymer solution having concentrations of polymer, salt, solvent and water. After the fiber is extruded and quenched, the fiber is placed in contact with a conditioning solution comprising concentrations of solvent, salt, and water. The conditioning solution acts upon the fiber to plasticize the fiber prior to being drawn. The conditioning solution has concentrations of solvent, salt, and water so that the fiber is plasticized to the extent necessary for drawing but does not plasticize the fiber to such an extent as to re-dissolve the fiber into a polymeric solution. A heat-treated fiber manufactured from this process has improved shrinkage and can be colored to darker shades. | 2009-06-25 |
20090160081 | Rapid plasticization of quenched yarns - The invention relates to a continuous dry spinning process for preparing a fiber from a polymer solution having concentrations of polymer, salt, solvent and water. After the fiber is extruded and quenched, the fiber is placed in contact with a conditioning solution comprising concentrations of solvent, salt, and water. The conditioning solution acts upon the fiber to plasticize the fiber prior to being drawn. The conditioning solution has concentrations of solvent, salt, and water so that the fiber is plasticized to the extent necessary for drawing but does not plasticize the fiber to such an extent as to re-dissolve the fiber into a polymeric solution. A heat-treated fiber manufactured from this process has improved shrinkage and can be colored to darker shades. | 2009-06-25 |
20090160082 | Multistage draw with relaxation step - The invention relates to a continuous dry spinning process for preparing a fiber from a polymer solution having concentrations of polymer, salt, solvent and water. After the fiber is extruded and quenched, the fiber is placed in contact with a conditioning solution comprising concentrations of solvent, salt, and water. The conditioning solution acts upon the fiber to plasticize the fiber prior to being drawn. The conditioning solution has concentrations of solvent, salt, and water so that the fiber is plasticized to the extent necessary for drawing but does not plasticize the fiber to such an extent as to re-dissolve the fiber into a polymeric solution. A heat-treated fiber manufactured from this process has improved shrinkage and can be colored to darker shades. | 2009-06-25 |
20090160083 | SWEPT LEG SPIDER FOR AN EXTRUSION APPARATUS - A spider for an extrusion apparatus located upstream from a die, through which a profile is extruded. The spider can have an outer housing with a central flow passage therethrough. An inner hub can be positioned within the central passage for supporting an inner portion of the die. At least one spider leg can be secured to the outer housing and the inner hub, and support the inner hub within the central passage. The at least one spider leg can recess radially rearwardly outwardly in the downstream direction such that molten polymer flowing through the central passage flows around the at least one spider leg, separating and rejoining together earlier in inner radial regions close to the inner hub than in outer radial regions close to the outer housing for reducing spider lines on inside surfaces of extruded profiles. | 2009-06-25 |
20090160084 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A lead frame is equipped between an upper die with which a gate port and an air vent part are not formed in a cavity part | 2009-06-25 |
20090160085 | DEVICE AND METHOD FOR THE PRODUCTION OF A ROOF TILE WITH AT LEAST ONE WATER BARRIER - The invention relates to an arrangement and a method for providing a roof tile with at least one water stop. With the arrangement it becomes possible to press a water stop, comprised of a material differing from that of the roof tile, into a roof tile blank. After the water stop has been pressed in, it is partially disposed with its edge in the material of the roof tile blank in the proximity of the watercourse, of the central brim and of the lateral beading. | 2009-06-25 |
20090160086 | METHOD FOR MAKING MULTI-LAYERED MOLDED ARTICLES - A method of forming a multi-layered molded article includes: providing a source of soft material ( | 2009-06-25 |
20090160087 | IN-MOLD DECORATION METHOD & APPARATUS - A method and apparatus to form and in mold decoration part utilizing an IML/IML process or an IMD/IML process. The processes prepare inlays or decorations then load the inlays or decorations in to a mold, the decorations and inlays are formed on the inner and outer surfaces of the part with the part resin through the injection mold process, the in mold decoration part is then formed and ejected. | 2009-06-25 |
20090160088 | GOLF BALL AND DIE FOR MOLDING THE SAME - There are provided a golf ball in which the depths of dimples after grinding, which greatly affect the trajectory of golf ball, can be controlled readily and exactly, and a golf ball molding die for manufacturing the golf ball. The golf ball molding die in accordance with the present invention comprises two die bodies in which a cavity for molding a golf ball is formed by joining the die bodies to each other; and a protrusion formed on the cavity side surface of at least one of the die bodies, the protrusion having a uniform height from the surface or an imaginary spherical surface on which the protrusion is assumed to be absent toward the center of the cavity, wherein when a parting line is at latitude zero degree, the protrusion is arranged in the range of from latitude about 10 degrees to latitude about 80 degrees. | 2009-06-25 |
20090160089 | Process for Producing Polyimide Film - The invention is directed to a process for producing polyimide film, including stretching, at 150° C. to 380° C. and a stretch ratio of 1.2 to 4.0, an unstretched polyimide film which is formed from a polyimide having a repeating unit represented by formula (1): | 2009-06-25 |