| 25th week of 2010 patent applcation highlights part 19 |
| Patent application number | Title | Published |
|---|
| 20100155892 | Semiconductor Constructions - Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second material is formed over the first material. The second material may be one or both of polycrystalline and amorphous silicon. A third material is formed over the second material. A pattern is transferred through the first material, second material, third material, and oxide to form openings. Capacitors may be formed within the openings. Some embodiments include semiconductor constructions in which an oxide is over a substrate, a first material is over the oxide, and a second material containing one or both of polycrystalline and amorphous silicon is over the first material. Third, fourth and fifth materials are over the second material. An opening may extend through the oxide; and through the first, second, third, fourth and fifth materials. | 2010-06-24 |
| 20100155893 | Method for Forming Thin Film Resistor and Terminal Bond Pad Simultaneously - Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires. | 2010-06-24 |
| 20100155894 | Fabricating Bipolar Junction Select Transistors For Semiconductor Memories - A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced. | 2010-06-24 |
| 20100155895 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a P type silicon substrate; a deep N well in the P type silicon substrate; a P grade region in the deep N well; a P | 2010-06-24 |
| 20100155896 | HIGH-FREQUENCY BIPOLAR TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF - A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region. | 2010-06-24 |
| 20100155897 | DEEP TRENCH VARACTORS - A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes. At least one doped well is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells may be connected in parallel to provide a varactor having complex voltage dependency of capacitance. The buried plate layer and another doped well connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench. | 2010-06-24 |
| 20100155898 | METHOD FOR ENHANCING TENSILE STRESS AND SOURCE/DRAIN ACTIVIATION USING Si:C - A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure to create a strain layer. The strain layer is annealed using a millisecond anneal process. Subsequent ion implantation steps are used to dope the source/drain region, and the source/drain extension with phosphorus ions, so that the doped regions remain above the strain layer. A second millisecond anneal step activates the source/drain region and the source/drain extension. The strain layer enhances carrier mobility within a channel region of the semiconductor structure, while also preventing diffusion of P within the structure. | 2010-06-24 |
| 20100155899 | ETCHING METHOD, ETCHING MASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - An etching method forms a metal-fluoride layer at a temperature of 150° C. or higher at least as a part of an etching mask formed over a semiconductor layer; patterns the metal-fluoride layer; and etches the semiconductor layer using the patterned metal-fluoride layer as a mask. According to the etching method, an etching-resistant semiconductor layer such as a Group III-V nitride semiconductor can be easily etched by a relatively simpler process. | 2010-06-24 |
| 20100155900 | FABRICATING A GALLIUM NITRIDE DEVICE WITH A DIAMOND LAYER - In one aspect, a method includes fabricating a device. The device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer. | 2010-06-24 |
| 20100155901 | FABRICATING A GALLIUM NITRIDE LAYER WITH DIAMOND LAYERS - In one aspect, a method includes fabricating a gallium nitride (GaN) layer with a first diamond layer having a first thermal conductivity and a second diamond layer having a second thermal conductivity greater than the first thermal conductivity. The fabricating includes using a microwave plasma chemical vapor deposition (CVD) process to deposit the second diamond layer onto the first diamond layer. | 2010-06-24 |
| 20100155902 | Manufacturing Method of Nitride Substrate, Nitride Substrate, and Nitride-Based Semiconductor Device - A manufacturing method of a nitride substrate includes the steps of: preparing a ground substrate; forming a mask on the ground substrate; placing the ground substrate in a reactor, and heating the ground substrate to a temperature of 850° C. to 1100° C. In the step of heating the ground substrate, HCl and NH | 2010-06-24 |
| 20100155903 | Annealed wafer and method for producing annealed wafer - An annealed wafer having enhanced gettering effects for Cu is produced by heating a silicon substrate containing a nitrogen concentration of 5×10 | 2010-06-24 |
| 20100155904 | SEMICONDUCTOR DEVICE HAVING CMP DUMMY PATTERN AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a CMP dummy pattern and a method for manufacturing the same are provided. The warpage of a wafer can be prevented by forming the CMP dummy pattern in the same direction and/or at the same angle as a pattern of a cell region. Accordingly, overlay error caused by etching residues is reduced, thereby improving the yield of the semiconductor device. | 2010-06-24 |
| 20100155905 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A device portion forming step includes an assisting layer forming step of forming a planarization assisting layer, which covers a plurality of conductive films, over a first planarizing layer before forming a second planarizing layer. In the assisting layer forming step, the planarization assisting layer is formed so that a height of the planarization assisting layer from a surface of the first planarizing layer located on a side opposite to the substrate layer becomes equal between at least a part of a region where the conductive films are formed, and at least a part of a region where no conductive film is formed. | 2010-06-24 |
| 20100155906 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING PATTERNS FOR THE SEMICONDUCTOR DEVICE - Provided are a method of forming patterns for a semiconductor device in which a pattern density is doubled by performing double patterning in a part of a device region while patterns having different widths are being simultaneously formed, and a semiconductor device having a structure to which the method is easily applicable. The semiconductor device includes a plurality of line patterns extending parallel to each other in a first direction. A plurality of first line patterns are alternately selected in a second direction from among the plurality of line patterns and each have a first end existing near the first side. A plurality of second line patterns are alternately selected in the second direction from among the plurality of line patterns and each having a second end existing near the first side. The first line patterns alternate with the second line patterns and the first end of each first line pattern is farther from the first side than the second end of each second line pattern. | 2010-06-24 |
| 20100155907 | SEMICONDUCTOR DEVICE HAVING AN INORGANIC COATING LAYER APPLIED OVER A JUNCTION TERMINATION EXTENSION - A semiconductor device includes an inorganic coating layer to at least partially cover a junction termination extension. | 2010-06-24 |
| 20100155908 | PASSIVATION STRUCTURE AND FABRICATING METHOD THEREOF - A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality of first openings and second openings respectively exposing the metal pads in the main die region and the scribe line region on the chip, and forming a second patterned passivation layer filling the first openings in the scribe line region and having a plurality of third openings corresponding to the first openings thus exposing the metal pads in the main die region. | 2010-06-24 |
| 20100155909 | METHOD TO ENHANCE CHARGE TRAPPING - Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device. | 2010-06-24 |
| 20100155910 | METHOD FOR THE SELECTIVE ANTIREFLECTION COATING OF A SEMICONDUCTOR INTERFACE BY A PARTICULAR PROCESS IMPLEMENTATION - The invention refers to an efficient process for selectively rendering a semiconductor surface antireflective which is part of integrated circuits. The antireflective effect is based interference effects of a simple layer or a layer system. For example, an oxide layer and super-imposed silicon nitride layer form the system, wherein the silicon nitride layer is deposited in an earlier phase of the fabrication of the integrated circuit as a protective layer (“silicide block layer”) and also serves as an etch stop layer for the optical window. | 2010-06-24 |
| 20100155911 | ESD Protection Diode in RF pads - A diode is provided. The diode includes first and second diffusion layers formed in a substrate, a first metal coupled to the first diffusion layer, and a second metal coupled to the second diffusion layer that has width that is smaller than a width of the second diffusion layer. | 2010-06-24 |
| 20100155912 | APPARATUS FOR SHIELDING INTEGRATED CIRCUIT DEVICES - A high reliability radiation shielding integrated circuit apparatus comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose of tolerance of the circuit die. In one embodiment, an integrated circuit apparatus for use in high reliability applications is disclosed. The integrated circuit apparatus is designed to be highly reliable and protect integrated circuit die from failing or becoming unreliable due to radiation, mechanical forces, thermal exposure, or chemical contaminates. | 2010-06-24 |
| 20100155913 | THERMALLY ENHANCED THIN SEMICONDUCTOR PACKAGE - A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package. | 2010-06-24 |
| 20100155914 | Power Module Having Stacked Flip-Chip and Method of Fabricating the Power Module - Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. The method includes forming bumps on power and control device chips on a wafer level; separately sawing the power and control device chips into individual chips; adhering the power device chip onto a thermal substrate and the control device chip onto an interconnecting substrate; combining a lead frame, the thermal substrate, and the interconnecting substrate with one another in a multi-jig; and sealing the power and control device chips, and the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. | 2010-06-24 |
| 20100155915 | STACKED POWER CONVERTER STRUCTURE AND METHOD - A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad. | 2010-06-24 |
| 20100155916 | CHIP PACKAGE STRUCTURE AND THE METHOD THEREOF WITH ADHERING THE CHIPS TO A FRAME AND FORMING UBM LAYERS - A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of the package structure is larger than the height of the chips; a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended out to cover the surface of the package structure; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is exposed; a plurality of patterned UBM layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UBM layer and is electrically connected to one end of the exposed portion of the patterned metal traces. | 2010-06-24 |
| 20100155917 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a semiconductor element having a light receiving region or a light emitting region on which a transparent member is attached, and a plurality of electrode pads; a substrate on which the semiconductor element is provided; and a resin covering the semiconductor element and side surfaces of the transparent member. The first area corresponding to part of an upper surface of the semiconductor element, which part is covered with the resin is smaller than the second area corresponding to parts of a lower surface of the semiconductor element and a lower surface of the substrate, which parts are covered with the resin. | 2010-06-24 |
| 20100155918 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a stack board with a side having a connect contact next to a connect edge and a top contact next to a top edge perpendicular to the connect edge, and a bottom contact on an opposite side; mounting a circuit assembly having an assembly end next to the connect contact and an edge pad over the stack board; connecting the edge pad with the stack board; and applying an edge encapsulant over the connect contact and over the assembly end with the edge encapsulant extending no more than half the width of the stack board. | 2010-06-24 |
| 20100155919 | High-density multifunctional PoP-type multi-chip package structure - Provided is a high-capacity multifunctional multichip package (MCP) structure in which a multifunctional MCP capable of, for example, high-speed image processing and communications, is mounted on a high-capacity memory package capable of storing various data, e.g., moving images, pictures, or music files. The high-capacity memory package may be efficiently applied to a mass storage of a mobile device. However, an eight-stage-plus chip stacking structure should overcome yield loss during assembly and test processes. To do this, a memory package may be divided into a pair of package to form upper and lower package stacks. To physically connect the pair of packages, molding members may be installed opposite each other and fixed to each other using an adhesive member. Also, to electrically connect the pair of packages, one of the packages may be formed using a flexible PCB substrate capable of bending. The flexible PCB substrate of the one of the packages may be connected to both sides of the other of the packages, and the two packages may be thermally bonded to each other under pressure using solder balls and ball lands. | 2010-06-24 |
| 20100155920 | Stacked semiconductor package, semiconductor package module and method of manufacturing the stacked semiconductor package - Provided are a stacked-type semiconductor package using a stud bump, a semiconductor package module, and a method of fabricating the stacked-type semiconductor package. The stacked-type semiconductor package may include a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package may include a first circuit board and at least one conductive member extending upward from the first circuit board. The second semiconductor package may include a second circuit board, and a stud bump being inserted from the second circuit board into the at least one conductive member of the first semiconductor package in order to electrically connect the first semiconductor package and the second semiconductor package. | 2010-06-24 |
| 20100155921 | SEMICONDUCTOR APPARATUS - The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR | 2010-06-24 |
| 20100155922 | Semiconductor Device and Method of Forming Recessed Conductive Vias in Saw Streets - A semiconductor die has an insulating material disposed in a peripheral region around the die. A blind via is formed through the gap. A conductive material is deposited in the blind via to form a conductive via. A conductive layer is formed between the conductive via and contact pad on the semiconductor die. A protective layer is formed over the front side of the semiconductor die. A portion of the insulating material and conductive via is removed from a backside of the semiconductor die opposite the front side of the semiconductor die so that a thickness of the conductive via is less than a thickness of the semiconductor wafer. The insulating material and conductive via are tapered. The wafer is singulated through the gap to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically interconnected through the conductive vias. | 2010-06-24 |
| 20100155923 | Microball assembly methods, and packages using maskless microball assemblies - A method of forming a microball grid array includes adhering a microball precursor material to a transfer medium under conditions to reflect a selective charge pattern. The method includes transferring the microball precursor material from the transfer medium across a gap and to an integrated circuit substrate under conditions to reflect the selective charge pattern. The method includes achieving the microball grid array without the aid of a mask. | 2010-06-24 |
| 20100155924 | SEMICONDUCTOR MODULE - A semiconductor module includes first and second sub-units, each including at least one semiconductor chip, a first contact element having a first contact side, and a second or third contact element having a second or third contact side, respectively. The semiconductor chip has opposing first and second main electrode sides. The first main electrode side of the chip is thermally connected to the first contact side, and the second main electrode side is thermally connected to the second or third contact side. In the first sub-unit, a first fixation means connects the first and second contact elements and the chip together. In the second sub-unit, a second fixation means connects the first and third contact elements and the chip together. A flexible element, which is arranged between the first contact element and the first contact element, is electrically and thermally connected to the first contact elements. | 2010-06-24 |
| 20100155925 | RESIN-SEALED PACKAGE AND METHOD OF PRODUCING THE SAME - A method of producing a resin-sealed package is provided with: providing an electronic component which has a plurality of terminals on one face, a first support member and a second support member; temporarily fixing said electronic component to a surface of said first support member by a first adhesive agent layer, to face said terminals with said first support member; fixing said second support member having a second adhesive agent layer to said electronic component while interposing said electronic component between said first support member and said second support member to face said second adhesive agent layer with a back face side of said electronic component; resin sealing said electronic component between said first support member and said second support member; peeling said first support member and said first adhesive agent layer from said electronic component and a sealing resin; and stacking an insulating resin layer and a wiring layer which is electrically connected to said terminals of said electronic component, on said electronic component and said sealing resin. | 2010-06-24 |
| 20100155926 | INTEGRATED CIRCUIT PACKAGING SYSTEM FOR FINE PITCH SUBSTRATES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a substrate including: patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof. | 2010-06-24 |
| 20100155927 | Semiconductor packages with stiffening support for power delivery - Embodiments of the invention relate to semiconductor packages in which electrical power is delivered to die-side components removably installed in sockets formed between a package stiffener and an electrical conductor. To this purpose, the package stiffener and the electrical conductor may be electrically coupled to the power and ground terminals of the semiconductor package. | 2010-06-24 |
| 20100155928 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME - A semiconductor package includes: a wiring board; and a semiconductor device which is formed on the wiring board; wherein the semiconductor device includes: a semiconductor chip; and a penetration electrode, one end of which is fixed on one plane of the semiconductor chip, and the other end of which penetrates the semiconductor chip and is fixed on the other plane of the semiconductor chip, the penetration electrode penetrating the semiconductor chip in such a manner that the penetration electrode is not contacted to a wall plane of the semiconductor chip by a space portion formed in the semiconductor chip; and the wiring board and the semiconductor device are electrically connected via the penetration electrode. | 2010-06-24 |
| 20100155929 | Chip-Stacked Package Structure - A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer. | 2010-06-24 |
| 20100155930 | STACKABLE SEMICONDUCTOR DEVICE ASSEMBLIES - A semiconductor device assembly includes a substrate and a semiconductor die adjacent to a first surface of the substrate. The substrate also includes a second surface opposite from the first surface, an opening extending from the first surface and the second surface, contact pads on the first surface, and substrate pads on the second surface, adjacent to the opening. Bond pads of the semiconductor die are aligned with the opening through the substrate. Intermediate conductive elements, such as bond wires, extend from bond pads of the semiconductor die, through the opening, to substrate pads on the opposite, second surface of the substrate. An encapsulant, which fills the opening and covers the intermediate conductive elements, protrudes beyond a plane in which the second surface of the substrate is located. Another electronic device, such as another semiconductor device package, may communicate electrically with the die of the semiconductor device assembly through the contact pads on the first surface of the substrate. In some embodiments, the other electronic device may be stacked with the semiconductor device assembly. | 2010-06-24 |
| 20100155931 | Embedded Through Silicon Stack 3-D Die In A Package Substrate - An integrated circuit package has a die or die stack with through silicon vias embedded in a package substrate. A method of producing an integrated circuit package embeds at least one die with a through silicon via in a package substrate. The package substrate provides a protective cover for the die or die stack. | 2010-06-24 |
| 20100155932 | BONDED SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING MECHANISM - A bonded substrate comprising two semiconductor substrates is provided. Each semiconductor substrate includes semiconductor devices. At least one through substrate via is provided between the two semiconductor substrates to provide a signal path therebetween. The bottom sides of the two semiconductor substrate are bonded by at least one bonding material layer that contains a cooling mechanism. In one embodiment, the cooling mechanism is a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. In another embodiment, the cooling mechanism is a conductive cooling fin with two end portions and a contiguous path therebetween. The cooling fin is connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. | 2010-06-24 |
| 20100155933 | Package for semiconductor devices - To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin. | 2010-06-24 |
| 20100155934 | MOLDING COMPOUND INCLUDING A CARBON NANO-TUBE DISPERSION - A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electromechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than 10 microns. | 2010-06-24 |
| 20100155935 | Protective coating for semiconductor substrates - Methods for coating a protective material on a semiconductor substrate to protect a back surface thereof from defects are provided, by depositing a diamond-like coating (DLC) material thereon at a low temperature, e.g. between about 150° C. to about 350° C. | 2010-06-24 |
| 20100155936 | METHOD OF THINNING A SEMICONDUCTOR SUBSTRATE - A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 μm. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed. | 2010-06-24 |
| 20100155937 | Wafer structure with conductive bumps and fabrication method thereof - A wafer structure with conductive bumps and fabrication method thereof are disclosed herein. Conductive bumps are later converted into conductive balls. A central area and a marginal area are defined on the wafer. To achieve heights among conductive balls formed on the wafer structure, the sizes (can be but not limited to one) of under bump metallurgy (UBM) layer blocks in the central area are smaller than that in the marginal area. The fabrication procedure for forming under bump metallurgy layer blocks of different size includes depositing a photoresist layer on the metallurgy layer and pattern the photoresist with a photomask of smaller opening area for the central area than for the marginal area, and removing the photoresist layer and the portion of metallurgy layer under the photoresist layer. | 2010-06-24 |
| 20100155938 | FACE-TO-FACE (F2F) HYBRID STRUCTURE FOR AN INTEGRATED CIRCUIT - An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL. | 2010-06-24 |
| 20100155939 | CIRCUIT BOARD AND FABRICATION METHOD THEREOF AND CHIP PACKAGE STRUCTURE - A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed. | 2010-06-24 |
| 20100155940 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode. | 2010-06-24 |
| 20100155941 | SEMICONDUCTOR DEVICE - A semiconductor device includes multiple electrode pads provided in an interconnection layer over a semiconductor substrate; an insulating layer provided on the interconnection layer so as to expose portions of the electrode pads; multiple conductive layers having their respective first ends connected to the exposed portions of the corresponding electrode pads so as to extend therefrom on the insulating layer; and multiple protruding electrodes provided at respective second ends of the conductive layers, wherein the conductive layers extend in a given direction relative to the electrode pads. | 2010-06-24 |
| 20100155942 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a connection electrode formed on a side of a semiconductor element substrate opposed to a bump, where the semiconductor element substrate includes a semiconductor element; a passivation layer covering the semiconductor element substrate and an end portion of the connection electrode; and a barrier metal layer covering the connection electrode and a portion of the passivation layer so as to be electrically connected to the bump. A recess is formed in a portion of the passivation layer connected with the barrier metal layer. | 2010-06-24 |
| 20100155943 | SEMICONDUCTOR CHIP USED IN FLIP CHIP PROCESS - A semiconductor chip for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip. | 2010-06-24 |
| 20100155944 | SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate and including a plurality of first portions and a second portion disposed between two of the first portions adjacent to each other; and an interconnect electrically connected to the electrode and extending over one of the first portions of the resin protrusion. A lower portion of a side surface of the second portion includes a portion which extends in a direction intersecting a direction in which the resin protrusion extends. | 2010-06-24 |
| 20100155945 | SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor chip; a plurality of electrodes formed on the semiconductor chip and arranged along one side of the semiconductor chip; a resin protrusion formed on the semiconductor chip and extending in a direction which intersects the side; and a plurality of electrical connection sections formed on the resin protrusion and electrically connected to the respective electrodes. | 2010-06-24 |
| 20100155946 | Solder limiting layer for integrated circuit die copper bumps - An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material. | 2010-06-24 |
| 20100155947 | SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE - Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed. | 2010-06-24 |
| 20100155948 | TOOLING METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES FABRICATED THEREOF - A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two adjacent device lines overlapping the active region, forming a first block pattern corresponding to the first region on a photomask when the device-to-device spacing width is equal to a predetermined value, and transferring the first block pattern to the substrate. | 2010-06-24 |
| 20100155949 | LOW COST PROCESS FLOW FOR FABRICATION OF METAL CAPPING LAYER OVER COPPER INTERCONNECTS - Semiconductor devices and methods are disclosed for improving electrical connections to integrated circuits. A process flow and device with a dual/single damascene interconnect structure overlying an existing interconnect structure in a semiconductor wafer is provided. A capping layer is formed thereon that comprises nickel/palladium layers within a bond pad opening. The layers are polished using a chemical mechanical polishing (CMP) technique so that the capping layers are within the opening. | 2010-06-24 |
| 20100155950 | IMPLEMENTATION OF A METAL BARRIER IN AN INTEGRATED ELECTRONIC CIRCUIT - A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation step and a nitridation step of the cobalt-based metal material of the metal layer are performed. The antidiffusion properties of copper atoms (for example) and the antioxidation properties of the metal barrier are improved. | 2010-06-24 |
| 20100155951 | Copper interconnection structure and method for forming copper interconnections - A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of oxygen to manganese (y/x) less than 2. | 2010-06-24 |
| 20100155952 | Copper interconnection structures and semiconductor devices - A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer and a barrier layer including a metal element and copper, formed between the insulating layer and the interconnection body. An atomic concentration of the metal element in the barrier layer is accumulated toward an outer surface of the barrier layer facing the insulating layer, and an atomic concentration of copper in the barrier layer is accumulated toward an inner surface of the barrier layer facing the interconnection body. The inner surface of the barrier layer comprises copper surface orientation of {111} and {200}, and an intensity of X-ray diffraction peak from the inner surface of the barrier layer is stronger for the {111} peak than for the {200} peak. | 2010-06-24 |
| 20100155953 | Conductive oxide electrodes - Conductive oxide electrodes are described, including a bi-layer barrier structure electrically coupled with an adhesion layer, and an electrode layer, wherein the bi-layer barrier structure includes a first barrier layer electrically coupled with the adhesion layer, and a second barrier layer electrically coupled with the first barrier layer and to the electrode layer. The conductive oxide electrodes and their associated layers can be fabricated BEOL above a substrate that includes active circuitry fabricated FEOL and electrically coupled with the conductive oxide electrodes through an interconnect structure that can also be fabricated FEOL. The conductive oxide electrodes can be used to electrically couple a plurality of non-volatile re-writeable memory cells with conductive array lines in a two-terminal cross-point memory array fabricated BEOL over the substrate and its active circuitry, the active circuitry configured to perform data operations on the memory array. | 2010-06-24 |
| 20100155954 | Methods of forming low interface resistance rare earth metal contacts and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure. | 2010-06-24 |
| 20100155955 | METHOD FOR MANUFACTURING SYSTEM-IN-PACKAGE - A method of manufacturing a System In Package (SIP) and devices thereof. A method of manufacturing a SIP may include providing a first chip having a first substrate region and/or a first metal connection portion. A method of manufacturing a SIP may include providing a second chip having a second substrate region and/or a second metal connection portion. A method of manufacturing a SIP may include bonding a first metal connection portion with a second metal connection portion, which may stack a second chip with a first chip. A method of manufacturing a SIP may include subjecting a second substrate region to reactive ion etching to expose a portion of a second metal connection portion and/or to form a deep contact hole. A method of manufacturing a SIP may include treating a surface of a deep contact hole with tetra-methyl ammonium hydroxide and/or nitric acid. | 2010-06-24 |
| 20100155956 | FILL PATTERNING FOR SYMMETRICAL CIRCUITS - A fill-placement method, according to which symmetrical fill patterns are used to insert fill tiles into one or more interconnect levels corresponding to symmetrical circuitry. The fill-placement method can be used, for example, in the fabrication of an integrated circuit having at least two complementary portions for which relatively tight circuit-matching requirements need to be met. | 2010-06-24 |
| 20100155957 | PAD LAYOUT STRUCTURE OF SEMICONDUCTOR CHIP - Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides. | 2010-06-24 |
| 20100155958 | BONDING PAD STRUCTURE AND MANUFACTURING METHOD THEREOF - A bonding pad structure of a semiconductor device and a method of manufacturing the same reduce the likelihood of peel-off defects from occurring. The bonding pad structure includes a substrate, an interlayer insulation layer on the substrate, an upper wiring layer on the interlayer insulation layer, and a plurality of lower wiring layers disposed in the interlayer insulation layer between the upper wiring layer and the substrate and configured to prevent the interlayer insulation layer from cracking especially during a wire bonding process in which a wire is bonded to the upper wiring layer. For example, the respective areas occupied by the lower wiring layers sequentially increase in the interlayer insulation layer in a downward direction from the upper wiring layer towards the substrate. Also, each of the lower wiring layers may project further inwardly toward a central part of the bonding pad than the lower layer of wiring disposed above it in the interlayer insulation layer. | 2010-06-24 |
| 20100155959 | Semiconductor Devices Having Narrow Conductive Line Patterns and Related Methods of Forming Such Semiconductor Devices - Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction. | 2010-06-24 |
| 20100155960 | SEMICONDUCTOR DEVICE - The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction. | 2010-06-24 |
| 20100155961 | MICROMECHANICAL COMPONENT HAVING WAFER THROUGH-PLATING AND CORRESPONDING PRODUCTION METHOD - A wafer through-plating through a semiconductor substrate and a method for producing this wafer through-plating. At least one via hole is inserted in the front side of a semiconductor substrate, in this context, in order to form the wafer through-plating using a trench etching process. The semiconductor material of the side wall of the via hole is then porously etched in an electrochemical etching process. A metal is introduced into the via hole in order to produce the electrical contact-making connection. In order to enable the electrical connection from the front side to the back side of the semiconductor substrate, the via hole is opened from the back side, for example, by thinning the semiconductor substrate. This opening may be made, in this context, before or after the metal is introduced into the via hole. | 2010-06-24 |
| 20100155962 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, a diffusion region provided on a surface portion of a first surface of the semiconductor substrate, a first line provided on the first surface of the semiconductor substrate, a through-hole penetrating the semiconductor substrate in the thickness direction, and a through-hole electrode provided in the through-hole, and contacting a rear surface of the first line and extending to a second surface opposite the first surface of the semiconductor substrate. The semiconductor device further includes a recess provided on the second surface of the semiconductor substrate and a second line provided in the recess and electrically connected to the through-hole electrode. | 2010-06-24 |
| 20100155963 | DUMMY VIAS FOR DAMASCENE PROCESS - An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances into the dielectric layer, the conductive vias extending through the dielectric layer to the semiconductor layer, and the dummy vias extending through the dielectric layer to a distance above the semiconductor layer. | 2010-06-24 |
| 20100155964 | Adhesive Tape, Semiconductor Package and Electronics - An adhesive tape electrically connecting conductive members contains a resin, a solder powder and a curing agent having flux activity, wherein the solder powder and the curing agent having flux activity are contained in the resin. | 2010-06-24 |
| 20100155965 | SEMICONDUCTOR DEVICE - A semiconductor device includes: the mounting surface of the wiring substrate exposed from the semiconductor element is covered by a solder-resist layer, a part of the solder-resist layer covering the mounting surface of the wiring substrate at a dropping-commencing point at which dropping of a liquid-state under-filling agent filled in a gap between the semiconductor element and the mounting surface of the wiring substrate is commenced is extended in an area of the wiring substrate covered by the semiconductor element, and a gap between the semi conductor element at the dropping-commencing point and the vicinity thereof and an extension portion of the solder-resist layer is formed to be narrower than the gap between the semi conductor element and the mounting surface of the wiring substrate so that liquid drops of the under-filling agent dropped at the dropping-commencing point are sucked into the gap by a capillary phenomenon. | 2010-06-24 |
| 20100155966 | GRID ARRAY PACKAGES - A semiconductor device assembly includes a substrate and a semiconductor die adjacent to a first surface of the substrate. The substrate also includes a second surface opposite from the first surface, an opening extending from the first surface and the second surface, contact pads on the second surface, and substrate pads on the second surface, adjacent to the opening. Bond pads of the semiconductor die are aligned with the opening through the substrate. Intermediate conductive elements, such as bond wires, extend from bond pads of the semiconductor die, through the opening, to substrate pads on the opposite, second surface of the substrate. An encapsulant, which fills the opening and covers the intermediate conductive elements, protrudes beyond a plane in which the second surface of the substrate is located. Discrete conductive elements, such as solder balls, may protrude from the contact pads of the substrate. | 2010-06-24 |
| 20100155967 | INTEGRATED CIRCUITS ON A WAFER AND METHOD OF PRODUCING INTEGRATED CIRCUITS - Integrated circuits (Ia, Ib) on a wafer ( | 2010-06-24 |
| 20100155968 | Overlay Metrology Target - In one embodiment, a metrology target for determining a relative shift between two or more successive layers of a substrate may comprise; an first structure on a first layer of a substrate and an second structure on a successive layer to the first layer of the substrate arranged to determine relative shifts in alignment in both the x and y directions of the substrate by analyzing the first structure and second structure overlay. | 2010-06-24 |
| 20100155969 | RESIN PASTE FOR DIE BONDING, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - The die bonding resin paste of the invention comprises a polyurethaneimide resin represented by the following general formula (I), a thermosetting resin, a filler and a printing solvent. | 2010-06-24 |
| 20100155970 | METHOD OF COOLING A MULTIPHASE WELL EFFLUENT STREAM - A method of processing a multiphase well effluent mixture comprises: transferring the multiphase well effluent mixture (G+L) via a multiphase well effluent flowline ( | 2010-06-24 |
| 20100155971 | GAS MIXTURE SUPPLYING METHOD AND APPARATUS - A gas mixture supplying method includes supplying plural kinds of gases through gas supply lines connected to a common pipeline and supplying a gas mixture of the plural kinds of gases from a gas outlet of the common pipeline into a region where the gas mixture is used through a gas mixture supply line. When a typical gas supplied in a gaseous state from a gas supply unit and a liquid source gas vaporized by heating a liquid source material supplied from a liquid source material supply unit by a vaporizing unit are supplied simultaneously, the liquid source gas is supplied from one of the gas supply lines provided at a position closer to the gas outlet than that for the typical gas, and the liquid source gas is supplied to a downstream side of a filter for removing particles in the typical gas. | 2010-06-24 |
| 20100155972 | INJECTION MOLDED OPHTHALMIC LENS MOLD - An ophthalmic lens mold comprising a mold half having a front side and a back side, wherein an optical surface on the front side is formed by a film or sheet material and wherein the main body of the mold half is formed by an injection moldable bulk material. The film or sheet material may be provided by over-molded in an injection molding process with the injection moldable bulk material. Also provided is a respective mold assembly comprising the ophthalmic lens mold and a method for making an ophthalmic lens with the ophthalmic lens mold. | 2010-06-24 |
| 20100155973 | OPTICAL LENS OR LENS GROUP, PROCESS FOR THE PRODUCTION THEREOF, AS WELL AS OPTICAL IMAGE ACQUISITION DEVICE - The invention relates to an optical hybrid lens. According to the invention, the lens consists of a substrate ( | 2010-06-24 |
| 20100155974 | METHOD AND DEVICE FOR PRODUCING STRUCTURED OPTICAL MATERIALS - The invention relates to a method for producing structured optical materials. It also relates to a device for producing structured optical materials, and to use of the method. | 2010-06-24 |
| 20100155975 | MOLD RELEASE SHEET - The present invention relates to a mold half for making an ophthalmic lens, in particular a contact lens, wherein the mold half comprises a release sheet removably arranged on the mold surface of said mold half to separate a lens forming material from the mold surface, as well as to a method for applying a removable mold release sheet to said mold half. The mold half of the invention comprises a vacuum means to removably attach said release sheet to said mold surface, and preferably the mold half further comprises a pinch-off rim for forming the edge of said ophthalmic lens. | 2010-06-24 |
| 20100155976 | REUSABLE LENS MOLDS AND METHODS OF USE THEREOF - Described herein are devices for producing ophthalmic lenses including at least one mold half defining an optical surface where the mold half is made from a polymer that includes an aromatic polyimide, a polyphenylene, or a combination thereof. The devices exhibit numerous advantages including, but not limited to, good chemical resistance, durability, machineability, and UV absorbing properties. Also described are methods for producing ophthalmic lenses using the devices described herein. The ophthalmic lenses produced with the devices described herein exhibit excellent optical properties when compared to lenses produced from conventions molds. | 2010-06-24 |
| 20100155977 | OPTICAL DEVICE, METHOD OF PRODUCING THE SAME, OPTICAL PICKUP, AND OPTICAL INFORMATION PROCESSING DEVICE - An optical device having a sub-wavelength grating formed in a specified region is disclosed that is able to prevent wave front degradation accompanying a phase difference of a polarized light beam passing through the optical device. The optical device includes a circular-belt-like region where the sub-wavelength diffraction grating is formed, and a center portion where the sub-wavelength diffraction grating is not formed. A vertically polarized light beam used for operations on a blue-light optical recording medium A has a phase difference in the sub-wavelength diffraction grating to be an integral multiple of 2π and hence is transmitted through the sub-wavelength diffraction grating. A horizontally polarized light beam used for operations on a blue-light optical recording medium is diffracted by the sub-wavelength diffraction grating. The light path length L | 2010-06-24 |
| 20100155978 | Biocidal metal-doped materials and articles made therefrom - Inorganic materials doped with biocidal metals are useful for medical devices such as prosthetic implants, heart valves, surgical tools, endoscopes, orthodontics appliances and the like. | 2010-06-24 |
| 20100155979 | METHOD FOR RECYCLING ALL WASTE PLASTICS IN PARTICULAR MIXED PLASTICS - A method for the recycling of all types of waste plastic, in particular mixed plastic (MP), in which compactate, in particular agglomerate, is ground from flakes or other plastic parts in at least one refiner stage in the presence of water, from which fine particles are removed from the ground material emerging from the refiner stage with the process water, the remaining ground material is washed and/or mechanically dehydrated and dried or the dehydrated ground material is again ground in another refiner stage in the presence of water and then dehydrated and dried, wherein the grinding of the compactate is performed in at least one refiner stage using a disk refiner (toothed disk refiner), the disks of which have engaging teeth, which are arranged separated on concentric circles, wherein there is a hole between neighboring teeth of a circle and the holes of a circle are each big enough that the particles to be ground or ground up to that point can pass through freely. | 2010-06-24 |
| 20100155980 | INJECTION MOLDING MACHINE AND METHOD FOR MOLD-ADJUSTING - An injection molding machine and a method for mold-adjusting are provided. The injection molding machine comprises a mold-adjusting mechanism mounted to one side of the fixed platen and being coaxial with the tie bars. Each of the mold-adjusting mechanisms is constructed the same comprising a support frame ( | 2010-06-24 |
| 20100155981 | MOLDING DIE AND METHOD FOR MOLDING A MOLDED ARTICLE - A molding die and a method for molding a molded article including a foam layer made up of faces extended in a plurality of directions are provided, by which all of the faces can grow up to a predetermined expansion ratio or more. To this end, a molding die | 2010-06-24 |
| 20100155982 | METHOD OF PREPARING A POLYETHYLENE MICROPOROUS FILM FOR A RECHARGEABLE BATTERY SEPARATOR - Disclosed are a polyethylene microporous film and a method of preparing the same. The polyethylene microporous film, which has a laminated structure comprising B layer/A layer/B layer, prepared by melt-mixing a polyethylene and an aliphatic hydrocarbon solvent together at controlled mixing ratios to separately form an A layer and a B layer having different porosities, and then coextruding the A and B layers, thus exhibiting excellent mechanical properties, such as strength and elongation, and high-temperature stability. Therefore, the polyethylene microporous film is suitable for use in a rechargeable battery separator. | 2010-06-24 |
| 20100155983 | Malleable vase and method of producing said vase - A malleable vase constructed from silicone rubber or other malleable material and a method of producing said vase. | 2010-06-24 |
| 20100155984 | MANUFACTURING ONE-PIECE COMPOSITE SECTIONS USING OUTER MOLD LINE TOOLING - A method for manufacturing composite parts. A temporary removal layer may be placed on an inner mold line tool. A composite material may be laid up on the inner mold line tool for a composite part. The inner mold line tool may be positioned with the composite part inside an outer mold line tool. The composite part and the temporary removal layer may be transferred from the inner mold line tool to the outer mold line tool. The inner mold line tool and the temporary removal layer may be removed from inside of the outer mold line tool after transferring the composite part and the temporary removal layer to the outer mold line tool. | 2010-06-24 |
| 20100155985 | Apparatus and Method for Cooling Part Cake in Laser Sintering - A part cake defining a build produced by laser sintering and the surrounding unfused powder is contained in an enclosure, aid the enclosure includes displaceable wall portions for compressing the part cake to support the build against distortion during rapid cooling from a cooling fluid. The enclosure enables the part cake to be quickly and reliably cooled either within the laser sintering system or outside the laser sintering system. A source of cooling fluid connects to the enclosure and a lid holds the part cake in place as cooling fluid is forced through the pore volume of the cake. An inert gas blanket apparatus is also provided to reduce or prevent oxidation of the part cake and/or to cool the part cake. Once the part cake is cooled, the build produced by laser sintering may be removed from the part cake. | 2010-06-24 |
| 20100155986 | LOW-STRESS MOLDED GASKET AND METHOD OF MAKING SAME - A molded discrete low stress gasket is constructed of restructured filled PTFE for use in corrosive or severe chemical environments under relatively low bolt loads. The gasket has a gasket surface and includes a raised outer sealing ring and a raised inner sealing ring. The gasket may constructed from a restructured filled PTFE material, with the sealing rings deforming at lower pressures than the remaining portions of the gasket. | 2010-06-24 |
| 20100155987 | METHOD AND GASKETS FOR CASTING ACRYLIC FILMS - The present invention relates to a method for casting an acryl film, which includes the steps of injecting a material of the acryl film into a space that is formed from a pair of substrates and a gasket positioned between a pair of substrates, and curing the material of the acryl film. The shrinkage ratio of the gasket is not less than 10% after the acryl film is subjected to the curing step, or the shrinkage ratio of the gasket after the acryl film is subjected to the curing step is the same as or larger than the shrinkage ratio of the material of the acryl film. | 2010-06-24 |
| 20100155988 | PROCESS AND METHOD FOR MODIFYING POLYMER FILM SURFACE INTERACTION - The invention provides a modification of a polymer film surface interaction properties. In this process a polymer carrier object is covered by a chemical composition, comprising photo-polymerizable compounds, photo-initiators or catalysts with the ability to initiate polymerization and semi-fluorinated molecules. The so-produced polymer mold contains semi-fluorinated moieties, which are predominantly located on the surface and on the surface near region of the patterned surface. The polymer mold is suitable as a template with modified properties in a nano-imprint lithography process. | 2010-06-24 |
| 20100155989 | STAMPER FOR TRANSFERRING FINE PATTERN AND METHOD FOR MANUFACTURING THEREOF - An object of the present invention is to provide a stamper for transferring fine pattern and a method for manufacturing the stamper, the stamper has a fine structure layer to improve a continuous transferring property of the resinous stamper, and to allow accurate and continuous transferring. In order to achieve the above object, the present invention provides a stamper for transferring fine pattern, including: a fine structure layer on a supporting substrate, in which the fine structure layer is a polymer of a resinous compound whose principal component is silsesquioxane derivative having a plurality of polymerizable functional groups. | 2010-06-24 |
| 20100155990 | METHOD FOR MANUFACTURING KEYPAD OF PORTABLE TERMINAL - Disclosed is a method for manufacturing a keypad of a portable terminal, in which a metal thin layer ( | 2010-06-24 |
| 20100155991 | METHOD OF MANUFACTURING A BUSHING - A bushing can include a shoulder, a ring, and a ground shield. The ring can be arranged circumferentially around a first outside diameter of the bushing, wherein the ring includes a channel. The ground shield can include a semiconductive rubber collar that forms part of an outer surface of the bushing and extends circumferentially under a portion of the ring. The insulative portion can be adjacent to the ring and disposed over a portion of the ground shield. A method of manufacturing the bushing can include placing the ring and the ground shield into a mold, the ground shield including holes therein, and injecting insulative material into the mold to create an insulative layer within a cavity formed by the ring and the ground shield, the holes in the ground shield allowing some of the insulating material to flow therethrough to create the insulative portion adjacent the ring. | 2010-06-24 |
