| 25th week of 2011 patent applcation highlights part 20 |
| Patent application number | Title | Published |
|---|
| 20110147865 | INTEGRATED HYBRID HALL EFFECT TRANSDUCER - A Hall effect transducer in a semiconductor wafer comprises a first layer of semiconducting material, a second layer of semiconducting material, and a contact structure configured to provide a path for electrical current to pass through the second layer. The second layer has higher electron hole mobility than the first layer, and is epitaxially grown atop the first layer. | 2011-06-23 |
| 20110147866 | SPIN-CURRENT SWITCHED MAGNETIC MEMORY ELEMENT SUITABLE FOR CIRCUIT INTEGRATION AND METHOD OF FABRICATING THE MEMORY ELEMENT - A method of fabricating a spin-current switched magnetic memory element includes providing a wafer having a bottom electrode, forming a plurality of layers, such that interfaces between the plurality of layers are formed in situ, in which the plurality of layers includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers, lithographically defining a pillar structure from the plurality of layers, and forming a top electrode on the pillar structure. | 2011-06-23 |
| 20110147867 | METHOD OF VERTICALLY MOUNTING AN INTEGRATED CIRCUIT - A method of mounting a first integrated circuit ( | 2011-06-23 |
| 20110147868 | SEMICONDUCTOR DEVICE - In a multi-core semiconductor device, a data bus between CPUs or the like consumes a larger amount of power. By provision of a plurality of CPUs which transmit data by a backscattering method of a wireless signal, a router circuit which mediates data transmission and reception between the CPUs or the like, and a thread control circuit which has a thread scheduling function, a semiconductor device which consumes less power and has high arithmetic performance can be provided at low cost. | 2011-06-23 |
| 20110147869 | INTEGRATED INFRARED SENSORS WITH OPTICAL ELEMENTS, AND METHODS - An infrared (IR) radiation sensor device ( | 2011-06-23 |
| 20110147870 | PHOTODETECTOR WITH VALENCE-MENDING ADSORBATE REGION AND A METHOD OF FABRICATION THEREOF - According to an embodiment, a photodetector is provided, including a detector region, a first contact region forming an interface with the detector region, and a first valence mending adsorbate region between the first contact region and the detector region. | 2011-06-23 |
| 20110147871 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device and a method of manufacturing the same, which have a device structure ensuring high degrees of reliability and mass-productivity at low cost. | 2011-06-23 |
| 20110147872 | OPTICAL DEVICE, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING THE SAME - An optical device includes a semiconductor device, a light receiving part formed on the main surface of the semiconductor device, and a transparent board laminated above the main surface of the semiconductor device, with an adhesive material interposed between the transparent board and the main surface of the semiconductor device. A serrated part is formed on at least one of (i) the main surface that is of the transparent board and faces the semiconductor device and (ii) the back surface of the transparent board. | 2011-06-23 |
| 20110147873 | OPTICAL SEMICONDUCTOR DEVICE, AND OPTICAL PICKUP DEVICE AND ELECTRONIC DEVICE USING THE OPTICAL SEMICONDUCTOR DEVICE - A semiconductor substrate is bonded to a glass board in a peripheral portion of the semiconductor substrate by an adhesive layer. A hollow region is formed in a portion surrounded by the semiconductor substrate, the glass board, and the adhesive layer. In the hollow region, reinforcing adhesive layers are formed on a back surface of the semiconductor substrate and at positions corresponding to bumps provided at regular intervals. The reinforcing adhesive layers allow the semiconductor substrate to have strength withstanding to a load of a testing probe. | 2011-06-23 |
| 20110147874 | PHOTODIODE ISOLATION IN A PHOTONIC INTEGRATED CIRCUIT - Consistent with the present disclosure, a current blocking layer is provided between output waveguides carrying light to be sensed by the photodiodes in a balanced photodetector, and the photodiodes themselves. Preferably, the photodiodes are provided above the waveguides and sense light through evanescently coupling with the waveguides. In addition, the current blocking layer may include alternating p and n-type conductivity layers, such that, between adjacent ones of such layers, a reverse biased pn-junction is formed. The pn-junctions, therefore, limit the amount of current flowing from one photodiode of the balanced detector to the other, thereby improving performance. | 2011-06-23 |
| 20110147875 | IMAGE SENSOR WITH WELL BOUNCE CORRECTION - An image sensor includes a pixel array having photoactive pixels and dark reference pixels. The photoactive pixels can be configured in a sub-array within the pixel array. Well contacts are only placed along opposing sides or edges of the sub-array of photoactive pixels or along opposing sides or edges of the pixel array. | 2011-06-23 |
| 20110147876 | SOLID-STATE IMAGING DEVICE, ELECTRONIC MODULE AND ELECTRONIC APPARATUS - A solid-state imaging device including an imaging area formed of a plurality of pixels arrayed in a two-dimensional matrix is provided. The solid-state imaging device includes: a photoelectric conversion portion including a charge accumulation region provided on a semiconductor substrate; a read transistor for reading electric charges from the photoelectric conversion portion; and a gettering site for separating metal impurities within the semiconductor substrate from at least the photoelectric conversion portion. The photoelectric conversion portion is provided on the surface side of the semiconductor substrate, and the gettering site is provided on the rear side away from the semiconductor substrate. | 2011-06-23 |
| 20110147877 | Multi-Band, Reduced-Volume Radiation Detectors and Methods of Formation - A broadband radiation detector includes a first layer having a first type of electrical conductivity type. A second layer has a second type of electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region. A third layer has the second type of electrical conductivity type and an energy bandgap responsive to radiation in a second spectral region comprising longer wavelengths than the wavelengths of the first spectral region. The broadband radiation detector further includes a plurality of internal regions. Each internal region may be disposed at least partially within the third layer and each internal region may include a refractive index that is different from a refractive index of the third layer. The plurality of internal regions may be arranged according to a regularly repeating pattern. | 2011-06-23 |
| 20110147878 | High Quantum Efficiency Optical Detectors - An optical detector includes a detector surface operable to receive light, a depleted field region coupled to the underside of the detector surface, a charge collection node underlying the depleted field region, an active pixel area that includes the portion of the depleted field region above the charge collection node and below the detector surface, and two or more guard regions coupled to the underside of the detector surface and outside of the active pixel area. The depleted field region includes an intrinsic or a near-intrinsic material. The charge collection node has a first width, and the guard regions are separated by a second width that is greater than the first width of the charge collection node. The guard regions are operable to prevent crosstalk to an adjacent optical detector. | 2011-06-23 |
| 20110147879 | WAFER STRUCTURE TO REDUCE DARK CURRENT - A wafer structure for an image sensor includes a substrate that has a given conductivity type, a given dopant concentration, and a given concentration of oxygen. An intermediate epitaxial layer is formed over the substrate. The intermediate epitaxial layer has the same conductivity type and the same, or substantially the same, dopant concentration as the substrate but a lower oxygen concentration than the substrate. A thickness of the intermediate epitaxial layer is greater than the diffusion length of a minority carrier in the intermediate layer. A device epitaxial layer is formed over the intermediate epitaxial layer. The device epitaxial layer has the same conductivity type but lower dopant and oxygen concentrations than the substrate. | 2011-06-23 |
| 20110147880 | POWER SEMICONDUCTOR DEVICE WITH NEW GUARD RING TERMINATION DESIGN AND METHOD FOR PRODUCING SAME - A power semiconductor device, such as a power diode, and a method for producing such a device, are disclosed. The device includes a first layer of a first conductivity type, a second layer of a second conductivity type arranged in a central region on a first main side of the first layer, a third electrically conductive layer arranged on the second layer, and a fourth electrically conductive layer arranged on the first layer at a second main side opposite to the first main side. A junction termination region surrounds the second layer with self-contained sub-regions of the second conductivity type. A spacer region is arranged between the second layer and the junction termination region and includes a self-contained spacer sub-region of the second conductivity type which is electrically disconnected from the second layer. This spacer sub-region has a width for enabling a reliable alignment of a shadow mask during an ion implantation such that an implanted lifetime control region having carrier lifetime reducing defects may be restricted to a central area while no such defects are implanted into the junction termination region to improve electrical characteristics. | 2011-06-23 |
| 20110147881 | HYBRID SUBSTRATE WITH IMPROVED ISOLATION AND SIMPLIFIED METHOD FOR PRODUCING A HYBRID SUBSTRATE - A hybrid substrate comprises first and second active areas made from semiconductor materials laterally offset from one another and separated by an isolation area. The main surfaces of the isolation area and of the first active area form a plane. The hybrid substrate is obtained from a source substrate successively comprising layers made from a first and second semiconductor materials separated by an isolation layer. A single etching mask is used to pattern the isolation area, first active area and second active area. The main surface of the first active area is released thereby forming voids in the source substrate. The etching mask is eliminated above the first active area. A first isolation material is deposited, planarized and etched until the main surface of the first active area is released. | 2011-06-23 |
| 20110147882 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an interlayer dielectric with a single-layer structure having a plurality of pores. The porosity of the interlayer dielectric per unit volume varies in a thickness direction. | 2011-06-23 |
| 20110147883 | SEMICONDUCTOR BODY WITH A BURIED MATERIAL LAYER AND METHOD - Disclosed is a method for forming a buried material layer in a semiconductor body, and a semiconductor arrangement including a buried material layer. | 2011-06-23 |
| 20110147884 | Contacting and Filling Deep-Trench-Isolation with Tungsten - Electrically isolated, deep trench isolation (DTI) structures, are formed in a wafer, and a portion of the DTI structures are converted to electrically connected structures to provide a shielding function, or to provide connection to deep buried layers. In one aspect, DTI structures include a polysilicon filling over a liner layer disposed on the inner surface of a deep trench, the polysilicon is removed by isotropic etching, and the deep trench is re-filled with a conductive material. Alternatively, the polysilicon filling remains and a contact is formed to provide an electrical connection to the polysilicon. In another aspect, a deep trench is disposed in the wafer such that a lower portion thereof is located within a deep buried layer, and after the polysilicon is removed, an anisotropic etch removes a portion of the deep trench liner from the bottom of the deep trench, thereby allowing a tungsten deposition to make electrical contact with the deep buried layer. | 2011-06-23 |
| 20110147885 | FORMATION OF IMPROVED SOI SUBSTRATES USING BULK SEMICONDUCTOR WAFERS - The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer. | 2011-06-23 |
| 20110147886 | SEMICONDUCTOR DEVICE WITH FUSE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor with a fuse includes providing a substrate, forming an insulation layer over the substrate, forming a polysilicon hard mask to form a metal contact over the insulation layer, forming a first mask pattern to form a fuse over the polysilicon hard mask, and removing the polysilicon hard mask exposed by the first hard mask pattern to form a polysilicon fuse connected to a portion of the polysilicon hard mask. | 2011-06-23 |
| 20110147887 | STACK CAPACITOR OF MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates. | 2011-06-23 |
| 20110147888 | METHODS TO FORM MEMORY DEVICES HAVING A CAPACITOR WITH A RECESSED ELECTRODE - Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes. | 2011-06-23 |
| 20110147889 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating film over a silicon substrate, the insulating film having an opening and a contact plug in the opening, the contact plug having a first top that is lower than an upper face of the insulating film. | 2011-06-23 |
| 20110147890 | MIM CAPACITOR STRUCTURE HAVING PENETRATING VIAS - The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as to partially overlap each other while relatively positionally deviating from each other in a direction orthogonal to the opposed direction thereof. The plurality of capacitance elements are stacked in the opposed direction. | 2011-06-23 |
| 20110147891 | CAPACITOR AND A METHOD OF MANUFACTURING THE SAME - A capacitor ( | 2011-06-23 |
| 20110147892 | Bipolar Transistor with Pseudo Buried Layers - A structure and fabrication method for a bipolar transistor with shallow trench isolation (STI) comprises a collector formed by implanting first electric type impurity in active area; pseudo buried layers at the bottom of STI at both sides of active area by implanting heavy dose of first electric type impurity; deep contacts through field oxide to connect to pseudo buried layers and to pick up the collector; a base, a thin film deposited on the collector and doped with second electric type impurity; an emitter, a polysilicon film doped by heavy dose implant of first electric type impurity. This transistor has smaller device area, less parasitic effect, less photo layers and lower process cost. | 2011-06-23 |
| 20110147893 | BIPOLAR TRANSISTORS WITH HUMP REGIONS - By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required. | 2011-06-23 |
| 20110147894 | LOW CAPACITANCE SEMICONDUCTOR DEVICE - A semiconductor device includes a diode, a passivation layer and a conductive layer. The diode includes an epitaxial layer on a semiconductor substrate, and first and second diode contacts on different planes. The passivation layer has a planar top surface, and includes multiple consecutive layers of a benzocyclobutene (BCB) material formed on the diode, an aggregate thickness of the passivation layer exceeding a thickness of the epitaxial layer. The conductive layer is formed on the top surface of passivation layer, the conductive layer connecting with the first and the second diodes contact through first and second openings in the passivation layer, respectively. The passivation layer enhances a capacitive isolation between the conductive layer and the diode. | 2011-06-23 |
| 20110147895 | Apparatus and Method for Controlling Semiconductor Die Warpage - A semiconductor die has through silicon vias arranged to reduce warpage. The through silicon vias adjust the coefficient of thermal expansion of the semiconductor die, permit substrate deformation, and also relieve residual stress. The through silicon vias may be located in the edges and/or corners of the semiconductor die. The through silicon vias are stress relief vias that can be supplemented with round corner vias to reducing warpage of the semiconductor die. | 2011-06-23 |
| 20110147896 | CLUSTER JET PROCESSING METHOD, SEMICONDUCTOR ELEMENT, MICROELECTROMECHANICAL ELEMENT, AND OPTICAL COMPONENT - A method for processing a sample using an electrically neutral reactive cluster is provided. The surface of a sample is processed by jetting out a mixed gas that is composed of a reactive gas and a gas with a boiling point lower than that of the reactive gas from a gas jetting part of a vacuum process room in which the sample is placed by a pressure in a range in which the mixed gas is not liquefied, in a predetermined direction, while adiabatically-expanding the mixed gas, thereby generating a reactive cluster and jetting the reactive cluster against the sample in the vacuum process room. | 2011-06-23 |
| 20110147897 | OFFSET FIELD GRID FOR EFFICIENT WAFER LAYOUT - Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines. | 2011-06-23 |
| 20110147898 | METHOD FOR DICING A SEMICONDUCTOR WAFER, A CHIP DICED FROM A SEMICONDUCTOR WAFER, AND AN ARRAY OF CHIPS DICED FROM A SEMICONDUCTOR WAFER - A method for dicing a semiconductor wafer, including: cutting a reference slot in a back main surface of the wafer; cutting a back slot in the back main surface, the back slot positioned with respect to the reference slot; determining a desired location for a chip edge with respect to the reference slot; and applying radiant energy in a path such that a series of reformed regions are formed within the wafer along the path. A crystalline structure of the wafer is modified in the series of reformed regions and an alignment of an edge of the laser is with respect to the desired location for the chip edge and in alignment with the back slot. The method includes separating the wafer along the series of reformed regions to divide portions of the wafer on either side of the series of reformed regions. | 2011-06-23 |
| 20110147899 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING - A method of manufacturing an integrated circuit packaging system includes: providing an inner lead and an outer lead, the inner lead having an inner peripheral side with a non-linear contour; forming a bump contact, having a groove in and a mesa from the inner lead or the outer lead, the groove adjacent to the mesa; mounting a first device adjacent to the inner lead; connecting a second device to the mesa; and forming an encapsulation material over the first device, the inner lead, and the outer lead and covering the second device. | 2011-06-23 |
| 20110147900 | DIELECTRIC LAYER FOR FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THEREOF - The present disclosure is related to a dielectric layer comprising a rare-earth aluminate (RE | 2011-06-23 |
| 20110147901 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes forming a lead frame including providing a tie bar plate, forming conductive columns on the tie bar plate, forming a dielectric layer on the conductive columns, applying a conductive shield layer on the dielectric layer, and exposing the conductive columns through the dielectric layer and the conductive shield layer; forming a base package substrate; mounting a base integrated circuit die on the base package substrate; mounting the tie bar plate, over the base integrated circuit die, conductively coupled to the base package substrate to form the conductive shield layer into an electro-magnetic interference shield; and removing the tie bar plate to expose the conductive columns from the dielectric layer. | 2011-06-23 |
| 20110147902 | Integrated Circuit Comprising Light Absorbing Adhesive - The invention relates to a structure | 2011-06-23 |
| 20110147903 | Leadframe Circuit and Method Therefor - An integrated circuit leadframe device supports various chip arrangements. As consistent with various embodiments, a leadframe includes a plurality of banks of conductive integrated circuit chip connectors. Each bank has a plurality of conductive strips respectively having an end portion, the end portions of each of the strips in the bank being substantially parallel to one another and arranged at an oblique angle to end portions of strips in at least one of the other banks. Each of the end portions has a tip extending to an interior portion of the leadframe device and separated from the other tips by a gap. A fastening material is arranged on at least some of the conductive strips and configured to fasten an integrated circuit chip to the conductive strips | 2011-06-23 |
| 20110147904 | SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS USING THE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - This invention provides a semiconductor device with increased moisture resistance. The semiconductor device includes: a semiconductor substrate; an optical element provided in a front surface of the semiconductor substrate; a light-transmissive substrate provided above the front surface of the semiconductor substrate; an adhesive layer provided between the front surface of the semiconductor substrate and a front surface of the light-transmissive substrate, and fixing the light-transmissive substrate to the semiconductor substrate; and an insulating film covering a lateral surface of said adhesive layer which is not in contact with the light-transmissive substrate and the semiconductor substrate. | 2011-06-23 |
| 20110147905 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor element, upper through-hole conductor portions and lower through-hole conductor portions are formed such that pore size A of the joint surface of the upper through-hole conductor portion and the lower through-hole conductor portion is smaller than pore size B of the upper through-hole conductor portion on the major surface of the semiconductor element and pore size C of the lower through-hole conductor portion on the other surface of the semiconductor element. Further, electrode portions are formed respectively on the top surfaces of the upper through-hole conductor portions and protrusions | 2011-06-23 |
| 20110147906 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit with an adhesive attached thereto; connecting the integrated circuit and a plated interconnect pad; attaching an embedded interconnect to the plated interconnect pad; and forming an encapsulation, having an encapsulation first side and an encapsulation second side, around the integrated circuit, the embedded interconnect, and the plated interconnect pad with the embedded interconnect exposed from the encapsulation second side and the plated interconnect pad and the adhesive exposed from the encapsulation second side. | 2011-06-23 |
| 20110147907 | ACTIVE PLASTIC BRIDGE CHIPS - A system for proximity communication between semiconductor chips includes a package assembly. The package assembly includes a plurality of bridge circuits made of organic or plastic semiconductor material. A plurality of base chips are assembled to the package assembly. The package assembly positions and aligns the plurality of base chips such that the bridge circuits bridge the base chips and enable proximity communication between the base chips. | 2011-06-23 |
| 20110147908 | Module for Use in a Multi Package Assembly and a Method of Making the Module and the Multi Package Assembly - The module comprises a first substrate and at least one chip mounted on the first substrate. A second substrate is mounted to the first substrate and has an opening therein. The opening is lined with the at least one chip. The second substrate is overmolded and the first substrate is electrically connected to the second substrate by at least one first electrical connector. At least one second electrical connector extends from the second substrate through the overmold and has its exposed ends for electrical connection to an external module. The external module may be mounted to the first module in order to form a package on package assembly. | 2011-06-23 |
| 20110147909 | SEMICONDCUTOR CHIP STACK AND MANUFACTURING METHOD THEREOF - A semiconductor chip stack includes a first chip and a second chip. The first chip includes a first circuit formed in the first chip with a first integration density, and the second chip includes a second circuit in the second chip with a second integration density smaller than the first integration density. The first chip further includes at least a through-silicon via formed therein for electrically connecting the first chip and the second chip. | 2011-06-23 |
| 20110147910 | METHOD FOR STACKING DIE IN THIN, SMALL-OUTLINE PACKAGE - Several embodiments of microelectronic device packaging configurations with lead frames without downsets are disclosed herein. In one embodiment, the configuration includes a pair of microelectronic dies with active surfaces facing one another, and a lead frame positioned between the dies. The lead frame has no downset and extends from between the dies and protrudes out of an encapsulant material. In one embodiment the lead frame is connected to both an upper and a lower die. In other embodiments, the lead frame is connected to a first die by wirebonds and is not connected to a second die. The first and second die may be connected to one another by interconnects such as solder ball interconnects. | 2011-06-23 |
| 20110147911 | STACKABLE CIRCUIT STRUCTURES AND METHODS OF FABRICATION THEREOF - Stackable circuit structures and methods of fabrication are provided employing first level metallization directly on a chips-first layer(s), which includes: a chip(s), each with a pad mask over its upper surface and openings exposing its contact pads; electrically conductive structures; and structural dielectric material surrounding the side surfaces of the chips and the conductive structures. Each chips-first layer further includes a metallization layer on the front surface of the layer, residing at least partially on the pad mask and extending over an edge of the chip. Together, the pad mask and the structural material electrically isolate the metallization layer from the chip. Input/output interconnect structures physically and electrically contact the metallization layer over the front surface and/or the lower surfaces of the electrically conductive structures at the back surface of the chips-first layer, to facilitate input/output connection to chips of the layers in a stack. | 2011-06-23 |
| 20110147912 | METHODS AND APPARATUSES TO STIFFEN INTEGRATED CIRCUIT PACKAGE - A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate. | 2011-06-23 |
| 20110147913 | MICROELECTRONIC PACKAGE AND METHOD FOR A COMPRESSION-BASED MID-LEVEL INTERCONNECT - A microelectronic package includes first substrate ( | 2011-06-23 |
| 20110147914 | Clad Solder Thermal Interface Material - A clad solder thermal interface material is described. In one example the material has a a first layer of solder having a melting temperature lower than a temperature of a particular solder reflow furnace, a second layer of solder clad to the first layer of solder, the second layer having a melting temperature higher than the temperature of the solder reflow furnace, and a third layer of solder clad to the second layer of solder opposite the first layer, the third layer having a melting temperature lower than the temperature of the solder reflow furnace. | 2011-06-23 |
| 20110147915 | COMBINED POWER MESH TRANSITION AND SIGNAL OVERPASS/UNDERPASS - A zipper structure includes a first contiguous full-dense-mesh (FDM) array of a first supply in top metal and a second contiguous FDM array of a second supply in top-1 metal, a third contiguous FDM array of the second supply in top metal and a fourth contiguous FDM array of the first supply in top-1 metal, and a signal line, such that portions of the first contiguous FDM array and the second contiguous FDM array overlap and portions of the third contiguous FDM array and the fourth contiguous FDM array overlap. The Zipper structure facilitates connecting the first contiguous FDM array to the fourth contiguous FDM array by VIAs and a first connector lines and the second contiguous FDM array to the third contiguous FDM array by VIAs and a second connector lines, such that portion of the signal line overlaps with the first connector lines and the second connector lines. | 2011-06-23 |
| 20110147916 | Semiconductor Chip Device with Solder Diffusion Protection - Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip that has a substrate and a first active circuitry portion extending a first distance into the substrate. A barrier is formed in the first semiconductor chip that surrounds but is laterally separated from the first active circuitry portion and extends into the substrate a second distance greater than the first distance. | 2011-06-23 |
| 20110147917 | INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED COMPONENTS - This document discusses, among other things, a semiconductor die package having a first and a second discrete components embedded into a dielectric substrate. An integrated circuit (IC) die is surface mounted on a first side of the dielectric substrate. The semiconductor die package includes a plurality of conductive regions on the second side of the dielectric substrate for mounting the semiconductor die package. A plurality of through hole vias couple the IC die to the first and second discrete components and the plurality of conductive regions. | 2011-06-23 |
| 20110147918 | ELECTRONIC DEVICE AND METHOD OF PRODUCING THE SAME - An electronic device includes a wiring board; a semiconductor device arranged at an upper side of the wiring board with an electrically conductive member being arranged therebetween; a covering member arranged at an upper side of the semiconductor device; and a supporting member arranged at a lower side of the wiring board, the supporting member having a convex portion facing the wiring board, the supporting member being connected to the covering member and supporting the wiring board at the convex portion. | 2011-06-23 |
| 20110147919 | WINDOW BALL GRID ARRAY (BGA) SEMICONDUCTOR PACKAGES - Embodiments of the present disclosure provide window ball grid array semiconductor packages. A semiconductor package includes a substrate having (i) a first surface, (ii) a second surface that is opposite to the first surface, and (iii) an opening formed between the first surface of the substrate and the second surface of the substrate. The semiconductor package further includes a semiconductor die having (i) a first surface and (ii) a second surface that is opposite to the first surface, the first surface of the semiconductor die being electrically coupled to the second surface of the substrate by one or more interconnect bumps; one or more bonding wires that electrically couple the first surface of the semiconductor die to the first surface of the substrate through the opening of the substrate; and a first electrically insulative structure disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and the one or more interconnect bumps. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate. | 2011-06-23 |
| 20110147920 | APPARATUS AND METHOD FOR EMBEDDING COMPONENTS IN SMALL-FORM-FACTOR, SYSTEM-ON-PACKAGES - According to various aspects of the present disclosure, an apparatus is disclosed that includes a small form factor mobile platform including a system-on-package architecture, the system-on-package architecture arranged as a stack of layers including: a first layer having a first conformable material; a second layer having a second conformable material; a third layer having a third material; and one or more electronic components embedded within the stack of layers, wherein the first conformable material, the second conformable material, or both are configured to allow high frequency signal routing. | 2011-06-23 |
| 20110147921 | Flange for Semiconductor Die - A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema. | 2011-06-23 |
| 20110147922 | STRUCTURES AND METHODS TO REDUCE MAXIMUM CURRENT DENSITY IN A SOLDER BALL - Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance. | 2011-06-23 |
| 20110147923 | Surface Mounting Integrated Circuit Components - An electronic apparatus may include a first component solder bonded to a second component. The first component may be, for example, an integrated circuit. The first component may have an array of metallic protrusions. Those protrusions may be coupled to circuit elements within said first component. The second component may include a plurality of solder portions coupled to the second component and engaged by the protrusions on the first component in a soldered connection. | 2011-06-23 |
| 20110147924 | WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A wiring substrate includes an insulating layer, a wiring layer buried in the insulating layer, and a connection pad connected to the wiring layer via a via conductor provided in the insulating layer and in which at least a part is buried in an outer surface side of the insulating layer, wherein the connection pad includes a first metal layer (a first copper layer) arranged on the outer surface side, an intermediate metal layer (a nickel layer) arranged on a surface of an inner layer side of the first metal layer, and a second metal layer (a second copper layer) arranged on a surface of an inner layer side of the intermediate metal layer, and a hardness of the intermediate metal layer is higher than a hardness of the first metal layer and the second metal layer. | 2011-06-23 |
| 20110147925 | PRE-SOLDERED LEADLESS PACKAGE - The invention relates to a method of manufacturing a semiconductor device, the method comprising: i) providing a substrate carrier comprising a substrate layer and a patterned conductive layer, wherein the patterned conductive layer defines contact pads; ii) partially etching the substrate carrier using the patterned conductive layer as a mask defining contact regions in the substrate layer; iii) providing the semiconductor chip; iv) mounting said semiconductor chip with the adhesive layer on the patterned conductive layer such that the semiconductor chip covers at least one of the trenches and part of the contact pads neighboring the respective trench are left uncovered for future wire bonding; v) providing wire bonds between respective terminals of the semiconductor chip and respective contact pads of the substrate carrier; vi) providing a molding compound covering the substrate carrier and the semiconductor chip, and vii) etching the backside (S | 2011-06-23 |
| 20110147926 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier - A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch. | 2011-06-23 |
| 20110147927 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor chip having an element formation surface on which at least one element is formed and including a plurality of electrode pads formed on the element formation surface, an interconnect substrate having a principal surface facing the element formation surface of the semiconductor chip and including a plurality of connection pads formed at positions of the principal surface facing the respective corresponding electrode pads, and a plurality of solder bumps provided between the respective corresponding electrode pads and connection pads, and configured to electrically connect the respective corresponding electrode pads and connection pads together. An UBM layer is formed on a portion of each solder bump closer to the corresponding electrode pad and a barrier metal layer is formed on a portion of each solder bump closer to the corresponding connection pad, and the two layers have substantially the same composition of major materials. | 2011-06-23 |
| 20110147928 | MICROELECTRONIC ASSEMBLY WITH BOND ELEMENTS HAVING LOWERED INDUCTANCE - Microelectronic assemblies can have multiple conductive bond elements, e.g., bond wires, or a lead bond and a bond wire, extending between a pair of a substrate contact and a chip contact. E.g., a first bond wire can have ends joined to the contacts of the chip and substrate. A second bond wire can be joined to the ends of the first bond wire so that the second bond wire does not touch either the chip contact or the substrate contact to which the first bond wire is joined. In one example, a bond wire has a looped connection with first and second ends joined at a first contact and a middle portion joined to a second contact. In one example, first and second bond elements, e.g., bond wires or lead bonds can connect first and second pairs of a substrate contact with a chip contact. A third bond element, e.g., a bond wire or bond ribbon, can be joined to ends of the first and second bond elements. | 2011-06-23 |
| 20110147929 | THROUGH MOLD VIA POLYMER BLOCK PACKAGE - Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed. | 2011-06-23 |
| 20110147930 | Semiconductor Component of Semiconductor Chip Size with Flip-Chip-Like External Contacts - A semiconductor component and a method for its production in semiconductor chip size, can have a semiconductor chip, which has external contacts of the semiconductor component that are arranged in the manner of a flip-chip on its active upper side. The semiconductor chip can be encapsulated by a plastic compound at least on its rear side and its side edges. The outer contacts, which can be arranged on external contact connecting areas, can project from the active upper side. | 2011-06-23 |
| 20110147931 | LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 2011-06-23 |
| 20110147932 | CONTACT-BASED ENCAPSULATION - An electrical connection between two chips includes an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal, different from the barrier metals, trapped between the first barrier metal and the second barrier metal, the first barrier metal, the malleable conductive metal and the second barrier metal forming a complete electrically conductive path between the IC pad of the first chip and the IC pad of the second chip. | 2011-06-23 |
| 20110147933 | MULTIPLE SURFACE FINISHES FOR MICROELECTRONIC PACKAGE SUBSTRATES - Multiple surface finishes are applied to a substrate for a microelectronics package by applying a first surface finish to connection pads of a first area of the substrate masking the first area of the substrate without masking a second area of the substrate, applying a second different surface finish to connection pads of the second area of the substrate, and removing the mask. | 2011-06-23 |
| 20110147934 | Metal Plugged Substrates with No Adhesive Between Metal and Polyimide - In a method and apparatus for fabricating a semiconductor device having a flexible tape substrate, a hole is punched in the flexible tape substrate. The flexible tape substrate includes a metal layer attached to a polyimide layer without an adhesive there between. A cover is placed on the metal layer to cap a base of the hole. A metal is deposited on the cover exposed at the base of the hole, the metal being used to form a bond with the metal layer. The metal being deposited causes the hole to be plugged up to a selective height. Upon removal of the cover, the metal may also be deposited on the metal layer to increase a thickness of the metal layer. | 2011-06-23 |
| 20110147935 | METHOD AND SYSTEM FOR BINDING HALIDE-BASED CONTAMINANTS - A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided. | 2011-06-23 |
| 20110147936 | SEMICONDUCTOR DEVICE AND DAMASCENE STRUCTURE - The present invention provides a semiconductor device, including a silicon-containing material, a conductive layer deposited on the silicon-containing material, and a diffusion barrier layer interposed between the silicon-containing material and the conductive layer, wherein the diffusion barrier layer contains a rare earth scandate. The present invention further provides a damascene structure containing the rare earth scandate as diffusion barrier. | 2011-06-23 |
| 20110147937 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In one exemplary embodiment, a method of manufacturing a semiconductor device is disclosed in which a damascene interconnect is formed above an underlying insulating film. The method includes forming an interconnect insulating film above the underlying insulating film such that a film density of the interconnect insulating film is relatively greater at a lower side thereof and relatively less at an upper side thereof. The interconnect insulating film is anisotropically dry etched to form an interconnect trench. The interconnect trench is wet etched such that an upper portion of a vertical cross section thereof exhibits a positive taper. A barrier metal film is formed along an inner surface of the interconnect trench including the positive taper. Further, the interconnect trench is filled with an interconnect conductor by plating over the barrier metal film. | 2011-06-23 |
| 20110147938 | CONDUCTIVE VIA HOLE AND METHOD FOR FORMING CONDUCTIVE VIA HOLE - Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver. | 2011-06-23 |
| 20110147939 | METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS - A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer. | 2011-06-23 |
| 20110147940 | ELECTROLESS CU PLATING FOR ENHANCED SELF-FORMING BARRIER LAYERS - Methods and an apparatus are described for an integrated circuit within which an electroless Cu plated layer having an oxygen content is formed on the top of a seed layer comprising Cu and Mn. The integrated circuit is then exposed to a sufficient high temperature to cause the self-formation of a MnSiOx barrier layer. | 2011-06-23 |
| 20110147941 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - A semiconductor apparatus with a penetrating electrode having a high aspect ratio is manufactured with a low-temperature process. A first electrode | 2011-06-23 |
| 20110147942 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory device of an embodiment includes: after forming a first interconnection layer and a memory cell layer above a semiconductor substrate, forming first lines by forming first grooves extending in first direction; forming a thin film on the side walls of the first grooves; forming a stack structure by filling an interlayer insulating film in the first grooves; forming a second interconnection layer above the stack structure; forming second lines by forming second grooves extending in second direction; removing the thin film exposed at bottom of the second grooves; and forming columnar memory cells by removing the memory cell layer exposed at bottom of the second grooves. The thin film has higher etching rate than the interlayer insulating film, and is removed prior to portions of the memory cell layer adjoining the thin film. | 2011-06-23 |
| 20110147943 | WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS - An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board). | 2011-06-23 |
| 20110147944 | PLANARISING DAMASCENE STRUCTURES - Manufacturing a damascene structure involves: forming a sacrificial layer ( | 2011-06-23 |
| 20110147945 | SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING GENERATION OF CRACKS IN SEMICONDUCTOR CHIP DURING MANUFACTURING PROCESS - A semiconductor device includes a chip stacked body where a plurality of semiconductor chips are stacked, and penetration electrodes respectively formed in the semiconductor chips are electrically interconnected in stacking order of the semiconductor chips, a first support member that is disposed to face a first semiconductor chip formed in one end of the chip stacked body, and including electrodes electrically connected to the penetration electrodes of the first semiconductor chip, and a wiring board that is disposed to face a second semiconductor chip formed in an end opposed to the one end of the chip stacked body, and including external electrodes on a surface opposed to a surface facing the second semiconductor chip that is to be electrically connected to the penetration electrodes of the second semiconductor chip. | 2011-06-23 |
| 20110147946 | WAFER-LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME - A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern. | 2011-06-23 |
| 20110147947 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an ELK film formed on a semiconductor substrate, a SiN film formed on the ELK film, and a plurality of interconnects formed in the ELK film and the SiN film to be located substantially at an equal height. The plurality of interconnects are provided in a non-dense interconnect region having a first interconnect area ratio which indicates a ratio of an area occupied by the interconnects per unit area, and a dense interconnect region having a second interconnect area ratio which is higher than the first interconnect area ratio. A height of an upper surface of a part of the SiN film located in the dense interconnect region is lower than a height of an upper surface of a part of the SiN film located in the non-dense interconnect region. | 2011-06-23 |
| 20110147948 | FORMING METHOD AND STRUCTURE OF POROUS LOW-K LAYER, INTERCONNECT PROCESS AND INTERCONNECT STRUCTURE - A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer. | 2011-06-23 |
| 20110147949 | HYBRID INTEGRATED CIRCUIT DEVICE - An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die. | 2011-06-23 |
| 20110147950 | METALLIZATION LAYER STRUCTURE FOR FLIP CHIP PACKAGE - The present invention discloses a metallization layer structure for flip chip package, which comprises an UBM layer formed on a metal pad, whereby a fine-quality tin-based solder ball can be formed on the metal pad. The UBM layer is a NiZnP layer formed via the reduction and oxidization of a solution containing nickel sulfate (Ni | 2011-06-23 |
| 20110147951 | WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate includes a wiring layer, an insulating layer formed on the wiring layer, a connection pad formed on the insulating layer, and a via conductor formed to penetrate the insulating layer, and connecting the wiring layer and the connection pad, wherein the wiring layer located under the connection pad is formed to have via receiving electrode portion whose area is smaller than an area of the connection pad, and a wiring portion separated from the via receiving electrode portion, in an area corresponding to the connection pad, and the via receiving electrode portion is connected to the connection pad via the via conductor. | 2011-06-23 |
| 20110147952 | DICING DIE-BONDING FILM - The invention relates to a dicing die-bonding film having a pressure-sensitive adhesive layer ( | 2011-06-23 |
| 20110147953 | MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. | 2011-06-23 |
| 20110147954 | SEMICONDUCTOR DEVICE, AND RESIN COMPOSITION USED FOR SEMICONDUCTOR DEVICE - A semiconductor device of the present invention ( | 2011-06-23 |
| 20110147955 | SILICONE RESIN COMPOSITION AND A CURED PRODUCT THEREOF - The present invention provides a silicone resin composition comprising (A) an organopolysiloxane having at least two alkenyl groups, (B) an organohydrogenpolysiloxane having at least two hydrogen atoms each bonded to a silicon atom, (C) a catalyst comprising a platinum group metal, (D) fine silicone particles, and (E) a (meth)acrylate compound. The present silicone resin composition cures in a short time to form a cured product having excellent adhesion strength with solder resists and copper substrates. | 2011-06-23 |
| 20110147956 | METHOD OF DOSING A LENS FORMING MATERIAL INTO A MOLD - There is described a method of dosing a lens forming material into a mold ( | 2011-06-23 |
| 20110147957 | PROCESS AND APPARATUS FOR DISPENSING A FLOWABLE MATERIAL INTO A MOLD - A process for dispensing a flowable material including a volatile solvent into a mold, in particular a material for forming an ophthalmic lens, e.g. a contact lens, is disclosed. The process includes the steps of providing a mold; providing a dispenser; arranging the mold underneath the dispenser; dispensing the flowable material including the volatile solvent into the mold, the step of dispensing being performed in a local gas atmosphere substantially preventing the solvent from evaporating from the flowable material. | 2011-06-23 |
| 20110147958 | LENS MOLDS WITH PROTECTIVE COATING FOR PRODUCTION OF OPHTHALMIC LENSES - This invention is directed to improved lens molds for the production of ophthalmic lenses, in particular colored contact lenses. The invention involves protective coatings for extended use and repair of reusable glass or quartz molds as well as for improved mold release and print-on-mold properties. The invention is also directed to a method of making the improved lens molds and their use in the manufacture of ophthalmic lenses, in particular colored contact lenses. | 2011-06-23 |
| 20110147959 | METHOD OF SEPARATING EXCESS LENS FORMING MATERIAL FROM A MOLDED OPHTHALMIC LENS, IN PARTICULAR A CONTACT LENS - There is described a method of separating excess lens forming material from a molded ophthalmic lens, in particular a contact lens. After polymerization and/or cross-linking of a lens forming material (P) within a mold cavity ( | 2011-06-23 |
| 20110147960 | METHOD OF REMOVING EXCESS LENS FORMING MATERIAL FROM A MOLDED OPHTHALMIC LENS SUCH AS A CONTACT LENS - There is described a method of removing excess lens forming material from a molded ophthalmic lens ( | 2011-06-23 |
| 20110147961 | Hydrophilic Liquid Encapsulates - A process of forming a population of microcapsules is described comprising a liquid hydrophilic core material and a wall material at least partially surrounding the core material. The liquid hydrophilic core material can be anionic, cationic, or neutral but polar. The microcapsule population is formed by providing liquid hydrophilic core material; providing an oil continuous phase which is low boiling and preferably nonflammable, the oil continuous phase comprising preferably one or more organic oil materials such as esters with chain length up to about 42 carbons. A mixture is formed by dispersing the liquid hydrophilic material in the oil continuous phase. Either an oil soluble or dispersible monofunctional amine acrylate or monofunctional amine methacrylate, along with acid; or alternatively monofunctional acid acrylate or monofunctional acid methacrylate along with base; or alternatively, monofunctional amine acrylate or monofunctional amine methacrylate along with acid acrylate or methacrylate; is added. A multifunctional acrylate or methacrylate monomer or oligomer is provided along with an initiator. Optionally a surfactant is also added to form the mixture. Emulsification is achieved by subjecting the mixture to high shear agitation and heating the mixture for a time sufficient to enable forming a prepolymer which migrates to the liquid hydrophilic material, thereby forming prepolymers adhered to the hydrophilic core materials. Heating is carried out or light exposure or both for a time and temperature sufficient to crosslink the prepolymers. | 2011-06-23 |
| 20110147962 | Spray-Drying Process - A process for preparing a spray-dried detergent powder having (i) detersive surfactant; and (ii) other detergent ingredients; wherein the process comprises the steps of: (a) forming an aqueous detergent slurry in a mixer; (b) transferring the aqueous detergent slurry from the mixer through at least one pump to a spray nozzle; (c) contacting alkoxylated anionic detersive surfactant and/or acid precursor thereof to the aqueous detergent slurry after the mixer and before the spray nozzle to form a mixture; (d) spraying the mixture through the spray nozzle into a spray-drying tower; and (e) spray-drying the mixture to form a spray-dried powder. | 2011-06-23 |
| 20110147963 | Spray-Drying Process - A process for preparing a spray-dried detergent powder including the steps of (i) mid-chain branched detersive surfactant; and (ii) other detergent ingredients; wherein the process includes the steps of: (a) forming an aqueous detergent slurry in a mixer; (b) transferring the aqueous detergent slurry from the mixer through at least one pump to a spray pressure nozzle; (c) contacting mid-chain branched detersive surfactant and/or acid precursor thereof to the aqueous detergent slurry after the mixer and before the spray pressure nozzle to form a mixture; (d) spraying the mixture through the spray pressure nozzle into a spray-drying tower; and (e) spray-drying the mixture to form a spray-dried powder. | 2011-06-23 |
| 20110147964 | Spray-Drying Process - A process for preparing a spray-dried powder having:
| 2011-06-23 |
