25th week of 2012 patent applcation highlights part 18 |
Patent application number | Title | Published |
20120153352 | HIGH INDIUM CONTENT TRANSISTOR CHANNELS - The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the formation of high mobility transistor channels from high indium content alloys, wherein the high indium content transistor channels are achieved with a barrier layer that can substantially lattice match with the high indium content transistor channel. | 2012-06-21 |
20120153353 | BURIED OXIDATION FOR ENHANCED MOBILITY - A method patterns at least one pair of openings through a protective layer and into a substrate. The openings are positioned on opposite sides of a channel region of the substrate. The method forms sidewall spacers along the sidewalls of the openings and removes additional substrate material from the bottom of the openings. The material removal process creates an extended bottom within the openings. The method forms a first strain producing material within the extended bottom of the openings. The method removes the sidewall spacers and forms a second material within the remainder of the openings between the first strain producing material and the top of the openings. The method removes the protective layer and forms a gate dielectric and a gate conductor on the horizontal surface on the substrate adjacent the channel region. The second material comprises source and drain regions. | 2012-06-21 |
20120153354 | PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACKS AND AN EMBEDDED STRESSOR BY PERFORMING A SECOND EPITAXY STEP - When forming sophisticated transistors, for instance comprising high-k metal gate electrode structures, a significant material loss of an embedded strain-inducing semiconductor material may be compensated for, or at least significantly reduced, by performing a second epitaxial growth step after the incorporation of the drain and source extension dopant species. In this manner, superior strain conditions may be achieved, while also the required drain and source dopant profile may be implemented. | 2012-06-21 |
20120153355 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate. | 2012-06-21 |
20120153356 | HIGH ELECTRON MOBILITY TRANSISTOR WITH INDIUM GALLIUM NITRIDE LAYER - Disclosed embodiments include a high electron mobility transistor (HEMT) with an indium gallium nitride layer set as one of a plurality of barrier sublayers and methods for forming such a HEMT. Other embodiments are also be described and claimed. | 2012-06-21 |
20120153357 | CONTACT INTEGRATION FOR THREE-DIMENSIONAL STACKING SEMICONDUCTOR DEVICES - Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck. | 2012-06-21 |
20120153358 | INTEGRATED HEAT PILLAR FOR HOT REGION COOLING IN AN INTEGRATED CIRCUIT - The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit level. The trapped thermal energy may be transferred through the circuit with thermally conductive structures or elements that may be produced as part of a standard integrated circuit process. The localized and passive removal of thermal energy achieved at the circuit level rather just at the package level is both more effective and more efficient. | 2012-06-21 |
20120153359 | NICKEL-SILICIDE FORMATION WITH DIFFERENTIAL PT COMPOSITION - Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions. | 2012-06-21 |
20120153360 | METHOD AND DEVICE FOR REGENERATING A HYDROGEN SENSOR - The regeneration method relates to a hydrogen sensor, which comprises a transistor of the MOS type whose gate is covered with a palladium catalyst and which is placed in a low-pressure enclosure. After a leak has been detected, a voltage is imposed on the gate of the transistor by means of an electronic circuit in order to regenerate the catalyst. The electronic circuit comprises a low-frequency DC generator and a switch for changing from the “measurement” mode to the “regeneration” mode, and vice versa. | 2012-06-21 |
20120153361 | FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses. | 2012-06-21 |
20120153362 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region. | 2012-06-21 |
20120153363 | SEMICONDUCTOR DEVICE WITH BURIED GATES AND FABRICATION METHOD THEREOF - A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer. | 2012-06-21 |
20120153364 | OXIDE MATERIAL AND SEMICONDUCTOR DEVICE - An object is to provide a material suitably used for a semiconductor included in a transistor, a diode, or the like. Another object is to provide a semiconductor device including a transistor in which the condition of an electron state at an interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film is favorable. Further, another object is to manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. A semiconductor device is formed using an oxide material which includes crystal with c-axis alignment, which has a triangular or hexagonal atomic arrangement when seen from the direction of a surface or an interface and rotates around the c-axis. | 2012-06-21 |
20120153365 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first buried bit line ( | 2012-06-21 |
20120153366 | Semiconductor Device Comprising Self-Aligned Contact Bars and Metal Lines With Increased Via Landing Regions - When forming metal lines of the metal zero level, a reduced bottom width and an increased top width may be achieved by using appropriate patterning regimes, for instance using a spacer structure after forming an upper trench portion with a top width, or forming the lower portion of the trenches and subsequently applying a further mask and etch regime in which the top width is implemented. In this manner, metal lines connecting to self-aligned contact bars may be provided so as to exhibit a bottom width of 20 nm and less, while the top width may allow reliable contact to any vias of the metallization system. | 2012-06-21 |
20120153367 | SEMICONDUCTOR APPARATUS - A power supply wiring and a pad are arranged on a first wiring layer. Then, the power supply wiring and the pad are arranged so as not to be mutually overlapped. Signal wirings are arranged on a second wiring layer. Another signal wiring is arranged on a layer different from the second wiring layer. The other signal wiring is arranged below the pad so as to be overlapped with the pad. The signal wirings and the other signal wiring are mutually connected by a plug. A buffer is arranged between the pad and the other signal wiring. | 2012-06-21 |
20120153368 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - To realize miniaturization/high integration and increase in the amount of accumulated charges, and to give a memory structure having a high reliability. A 1 transistor 1 capacitor (1T1C) structure having 1 ferroelectric capacitor structure and 1 selection transistor every memory cell is adopted, and respective capacitor structures are disposed respectively in either one layer of interlayer insulating films of 2 layers having different heights from the surface of a semiconductor substrate. | 2012-06-21 |
20120153369 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral circuit region, and an active region defined by a device isolation film, at least one dummy gate formed over the active region to expose a center part and both ends of the active region, a bit line contact plug formed between the dummy gates so as to be coupled to the center part of the active region, and a storage node contact plug that is spaced apart from the bit line contact plug by the dummy gate and is coupled to both ends of the active region. As a result, the problem that the storage node contact hole is not open in the semiconductor device can be solved, resulting in improved semiconductor device characteristics. | 2012-06-21 |
20120153370 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate. | 2012-06-21 |
20120153371 | DYNAMIC RANDOM ACCESS MEMORY CELL AND ARRAY HAVING VERTICAL CHANNEL TRANSISTOR - A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, a drain layer, an assisted gate, a control gate, a source layer, and a capacitor. The vertical channel transistor has an active region formed by the semiconductor pillar. The drain layer is formed at the bottom of the semiconductor pillar. The assisted gate is formed beside the drain layer, and separated from the drain layer by a first gate dielectric layer. The control gate is formed beside the semiconductor pillar, and separated from the active region by a second gate dielectric layer. The source layer is formed at the top of the semiconductor pillar. The capacitor is formed to electrical connect to the source layer. | 2012-06-21 |
20120153372 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME - Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon. | 2012-06-21 |
20120153373 | GATE STRUCTURE - A gate structure is described, including a dielectric layer, a gate conductive layer and a stacked cap structure. The dielectric layer is disposed between a substrate and the gate conductive layer. The gate conductive layer is disposed between the dielectric layer and the stacked cap structure. The stacked cap structure disposed on the gate conductive layer includes at least two insulating layers having different materials and contacting each other. | 2012-06-21 |
20120153374 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate; a memory cell region formed in the semiconductor substrate and including a plurality of memory cells; a peripheral circuit region formed in the semiconductor substrate; a first element isolation trench with a first width formed in the memory cell region; a second element isolation trench with a second width greater than the first width formed in the peripheral circuit region; a first oxide film formed along an inner surface of the first element isolation trench; a first coating oxide film formed along the first oxide film and filling the first element isolation trench; a second oxide film formed along a sidewall of the second element isolation trench; a third oxide film formed above a bottom of the second element isolation trench; and a second coating oxide film formed above the third oxide film and filling the second element isolation trench. | 2012-06-21 |
20120153375 | Nonvolatile semiconductor memory device - Provided is an electrically erasable and programmable nonvolatile semiconductor memory device whose tunnel region formed in the drain region has the second conductivity-type low-impurity-concentration region with the first tunnel insulating film for solely injecting electrons disposed thereon, and the first conductivity-type low-impurity-concentration region with the second tunnel insulating film for solely ejecting electrons disposed thereon, both regions fixed to the same potential as the drain region and having a lower impurity concentration than that of the drain region. | 2012-06-21 |
20120153376 | STACKED METAL FIN CELL - A NAND device including a source, a drain and a channel located between the source and drain. The NAND device also includes a plurality of floating gates located over the channel and a plurality of electrically conducting fins. Each of the plurality of electrically conducting fins is located over one of the plurality of floating gates. The plurality of electrically conducting fins include a material other than polysilicon. The NAND device also includes a plurality of control gates. Each of the plurality of control gates is located adjacent to each of the plurality of floating gates and each of the plurality of electrically conducting fins. | 2012-06-21 |
20120153377 | EDGE ROUNDED FIELD EFFECT TRANSISTORS AND METHODS OF MANUFACTURING - Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners. | 2012-06-21 |
20120153378 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device prevents separation between the channel region and the semiconductor substrate to prevent the floating body effect and to guarantee a sufficient overlap between a gate and a junction region. The semiconductor device includes a vertical pillar including a vertical channel, a diffusion control layer contained in the vertical pillar, and a junction region formed close to the diffusion control layer in the vertical pillar. | 2012-06-21 |
20120153379 | SEMICONDUCTOR DEVICES WITH VERTICAL CHANNEL TRANSISTORS - Semiconductor devices with vertical channel transistors, the devices including semiconductor patterns disposed on a substrate, first gate patterns disposed between the semiconductor patterns on the substrate, a second gate pattern spaced apart from the first gate patterns by the semiconductor patterns, and conductive lines crossing the first gate patterns. The second gate pattern includes a first portion extending parallel to the first gate patterns and a second portion extending parallel to the conductive lines. | 2012-06-21 |
20120153380 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a first trench by etching a substrate, forming first spacers on sidewalls of the first trench, forming a second trench by etching the substrate under the first trench, forming second spacers on sidewalls of the second trench, forming a third trench, which has a wider width than a width between the second spacers, by etching the substrate under the second trench, forming a liner layer on the surface of the third trench, and exposing one of the sidewalls of the second trench by selectively removing the second spacers. | 2012-06-21 |
20120153381 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. A method for forming a semiconductor device includes forming a trench by etching a semiconductor substrate, forming a barrier metal layer having a thickness of 100 Å or less over a surface of the trench, forming a nucleation layer over the barrier metal layer, configured to include a β-tungsten (β-W) structure, and forming a bulk layer over the nucleation layer so as to bury the bottom of the trench. As a result, resistivity can be reduced and a stable-phase barrier metal layer can be obtained. In addition, productivity is improved so that gate resistance is prevented from increasing. | 2012-06-21 |
20120153382 | SEMICONDUCTOR DEVICE - A semiconductor device includes a trench extending from a surface of a P-base layer to a surface of a P-well layer. The trench has a trench end portion defined in the surface of the P-well layer and in a direction in which the trench extends. The trench has first and second regions. The first region extends from the trench end portion to get into the surface of the P-base layer near a boundary between the P-base layer and the P-well layer. The second region extends in the surface of the P-base layer from an end portion of the first region. A trench width is greater in the first region than in the second region. | 2012-06-21 |
20120153383 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other. | 2012-06-21 |
20120153384 | Semiconductor Power Device Having A Top-side Drain Using A Sinker Trench - A semiconductor package device houses a die which comprises a power device, and the die further includes a silicon region over a substrate, a first plurality of trenches extending in the silicon region; a contiguous sinker trench extending along the perimeter of the die so as to completely surround the first plurality of trenches, the sinker trench extending from a top surface of the die through the silicon region, the sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench; and a plurality of interconnect balls arranged in a grid array, an outer group of the plurality of interconnect balls electrically connecting to the conductive material in the sinker trench. | 2012-06-21 |
20120153385 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device that secures a contact margin between a storage node contact plug and an active region and a method for fabricating the same. A method for fabricating a semiconductor device includes forming a device isolation layer defining active regions extending in a first direction a substrate, forming a first trench extending across the active regions and the device isolation layer by selectively etching the substrate, forming a second trench under the first trench to isolate the active regions which are adjacent in the first direction by selectively etching the substrate, and forming a gate electrode filling the first and second trenches. | 2012-06-21 |
20120153386 | SEMICONDUCTOR COMPONENT WITH A SPACE SAVING EDGE STRUCTURE - A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array. | 2012-06-21 |
20120153387 | TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM - Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm | 2012-06-21 |
20120153388 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device in which a reliable high voltage p-channel transistor is formed without an increase in cost and the number of manufacturing steps. The transistor includes: a semiconductor substrate having a main surface and a p-type region therein; a p-type well region located over the p-type region and in the main surface, having a first p-type impurity region to obtain a drain electrode; an n-type well region adjoining the p-type well region along the main surface and having a second p-type impurity region to obtain a source electrode; a gate electrode between the first and second p-type impurity regions along the main surface; and a p-type buried channel overlying the n-type well region and extending along the main surface. The border between the n-type and p-type well regions is nearer to the first p-type impurity region than the gate electrode end near to the first p-type impurity region. | 2012-06-21 |
20120153389 | STRUCTURE AND METHOD HAVING ASYMMETRICAL JUNCTION OR REVERSE HALO PROFILE FOR SEMICONDUCTOR ON INSULATOR (SOI) METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) - A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided. | 2012-06-21 |
20120153390 | TRANSISTORS WITH ISOLATION REGIONS - A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions. | 2012-06-21 |
20120153391 | MODULAR LOW STRESS PACKAGE TECHNOLOGY - A semiconductor subassembly, a modular sidewall element having modular dimensions that accommodates placement of the semiconductor subassembly in a modular layout and a semiconductor substrate base element coupled to the modular sidewall element. The semiconductor substrate base element has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element and the semiconductor substrate base element configured to form a base of the semiconductor subassembly. | 2012-06-21 |
20120153392 | MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE, AND PIXEL STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - A manufacturing method for a semiconductor structure, and a pixel structure and a manufacturing method for the same are provided. The manufacturing method for the semiconductor structure includes following steps. A substrate is provided. A first conductive layer is formed and patterned by using a first mask patterned. A first material film, including a first semiconductor layer, is formed and patterned by using a second mask. A second conductive layer is formed and patterned by using a third mask. A second material film, including a first dielectric layer, a second semiconductor layer and a second dielectric layer, is formed and patterned with using a fourth mask. The second dielectric layer is pattern by using a fifth mask. A third material film, including a third conductive layer, is formed and patterned by using a sixth mask. | 2012-06-21 |
20120153393 | Transistor, Semiconductor Device Comprising the Transistor and Method for Manufacturing the Same - The invention relates to a transistor, a semiconductor device comprising the transistor and manufacturing methods for the transistor and the semiconductor device. The transistor according to the invention comprises: a substrate comprising at least a base layer, a first semiconductor layer, an insulating layer and a second semiconductor layer stacked sequentially; a gate stack formed on the second semiconductor layer; a source region and a drain region located on both sides of the gate stack respectively; a back gate comprising a back gate dielectric and a back gate electrode formed by the insulating layer and the first semiconductor layer, respectively; and a back gate contact formed on a portion of the back gate electrode. The back gate contact comprises an epitaxial part raised from the surface of the back gate electrode, and each of the source region and the drain region comprises an epitaxial part raised from the surface of the second semiconductor layer. As compared to a conventional transistor, the manufacturing process of the transistor of the invention is simplified and the cost of manufacture is reduced. | 2012-06-21 |
20120153394 | METHOD FOR MANUFACTURING A STRAINED CHANNEL MOS TRANSISTOR - A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate. | 2012-06-21 |
20120153395 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region. A maximum of an impurity concentration distribution in the first impurity region in a depth direction is closer to the insulating surface than a maximum of an impurity concentration distribution in the second impurity region in a depth direction. | 2012-06-21 |
20120153396 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device including a switch circuit includes a first gate electrode provided between a source region and a drain region of an FET and a second gate electrode provided between the first gate electrode and the drain region. The semiconductor device also includes a control terminal electrically connected to an intermediate region between the first gate electrode and the second gate electrode, the control terminal being placed at a ground potential corresponding to ON state of the FET, and the control terminal being placed at a positive potential or a negative potential corresponding to OFF state of the FET. | 2012-06-21 |
20120153397 | Stressed Fin-FET Devices with Low Contact Resistance - An FET device includes a plurality of Fin-FET devices. The fins of the Fin-FET devices are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device. | 2012-06-21 |
20120153398 | Encapsulation of Closely Spaced Gate Electrode Structures - Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures. | 2012-06-21 |
20120153399 | Low-Diffusion Drain and Source Regions in CMOS Transistors for Low Power/High Performance Applications - The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors. | 2012-06-21 |
20120153400 | TUNNELING TRANSISTORS - A transistor including a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region. | 2012-06-21 |
20120153401 | Differential Threshold Voltage Adjustment in PMOS Transistors by Differential Formation of a Channel Semiconductor Material - In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors. | 2012-06-21 |
20120153402 | EMBEDDED SIGMA-SHAPED SEMICONDUCTOR ALLOYS FORMED IN TRANSISTORS BY APPLYING A UNIFORM OXIDE LAYER PRIOR TO CAVITY ETCHING - When forming sophisticated transistors requiring an embedded semiconductor alloy, the cavities may be formed with superior uniformity on the basis of, for instance, crystallographically anisotropic etch steps by providing a uniform oxide layer in order to reduce process related fluctuations or queue time variations. The uniform oxide layer may be formed on the basis of an APC control regime. | 2012-06-21 |
20120153403 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a substrate, a device isolation layer at the substrate and defining an active region, and a gate electrode on the substrate and extending across the active region. The active region includes a first active region and a second active region, and the first and second active regions are arranged at opposing sides of a centerline of the gate electrode. At least one of the first and second active regions has a width decreasing from a region outside the gate electrode toward the centerline of the gate electrode, and the first and second active regions are asymmetric with respect to the centerline of the gate electrode. | 2012-06-21 |
20120153404 | ANTI-FUSE DEVICE AND SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME - An anti-fuse device includes a gate electrode on a semiconductor substrate, a gate insulating layer between the semiconductor substrate and the gate electrode, junction regions in the semiconductor substrate adjacent the gate electrode, and at least one anti-breakdown material layer between the junction regions, the gate insulating layer being between the gate electrode and the anti-breakdown material layer. | 2012-06-21 |
20120153405 | Semiconductor Device Comprising a Contact Structure with Reduced Parasitic Capacitance - In sophisticated semiconductor devices, at least a portion of the interlayer dielectric material of the contact level may be provided in the form of a low-k dielectric material which may, in some illustrative embodiments, be accomplished on the basis of a replacement gate approach. Hence, superior electrical performance, for instance with respect to the parasitic capacitance, may be accomplished. | 2012-06-21 |
20120153406 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate, forming a dipole capping layer over the gate dielectric layer, stacking a metal gate layer and a polysilicon layer over the dipole capping layer, and forming a gate pattern by etching the polysilicon layer, the metal gate layer, the dipole capping layer, and the gate dielectric layer. | 2012-06-21 |
20120153407 | LIGHT-ASSISTED BIOCHEMICAL SENSOR - A light-assisted biochemical sensor based on a light addressable potentiometric sensor is disclosed. The light-assisted biochemical sensor comprises a semiconductor substrate and a sensing layer, which are used to detect the specific ion concentration or the biological substance concentration of a detected solution. Lighting elements fabricated directly on the back surface of the semiconductor substrate directly illuminate the light to the semiconductor substrate, so as to enhance the photoconduction property of the semiconductor substrate. And then, the hysteresis and the sensing sensitivity of the light-assisted biochemical sensor are respectively reduced and improved. In addition, due to its characteristics of integration, the light-assisted biochemical sensor not only reduces the fabrication cost but also has portable properties and real-time detectable properties. As a result, its detection range and the application range are wider. | 2012-06-21 |
20120153408 | MEMS DEVICE FORMING METHOD AND DEVICE WITH MEMS STRUCTURE - A method of forming a MEMS device by encapsulating a MEMS element with a sacrificial layer portion deposited over a substrate arrangement, the portion defining a cavity for the MEMS element, forming at least one strip of a further sacrificial material extending outwardly from the portion, forming a cover layer portion over the sacrificial layer portion, the cover layer portion terminating on the at least one strip, removing the sacrificial layer portion and the at least one strip, the removal of the at least one strip defining at least one vent channel extending laterally underneath the cover layer portion and sealing the at least one vent channel. A device including such a packaged micro electro-mechanical structure. | 2012-06-21 |
20120153409 | Thin Semiconductor Device Having Embedded Die Support and Methods of Making the Same - Ultra-thin semiconductor devices, including piezo-resistive sensing elements can be formed a wafer stack that facilitates handling many thin device dice at a wafer level. Three embodiments are provided to form the thin dice in a wafer stack using three different fabrication techniques that include anodic bonding, adhesive bonding and fusion bonding. A trench is etched around each thin die to separate the thin die from others in the wafer stack. A tether layer, also known as a tether, is used to hold thin dice or dice in a wafer stack. Such as wafer stack holds many thin dice together at a wafer level for handling and enables easier die picking in packaging processes. | 2012-06-21 |
20120153410 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a semiconductor chip body having a first surface and a second surface that faces away from the first surface, and including a plurality of bonding pads disposed on the first surface. Also, the semiconductor chip includes a distance maintaining member attached to the first surface of the semiconductor chip body and electrically connected with a circuit pattern. | 2012-06-21 |
20120153411 | SPIN TORQUE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY IN DISK BASE WITH REDUCED THRESHOLD CURRENT - A semiconductor memory device includes a magnetic tunneling junction (MTJ); and a magnetic feature aligned with the MTJ and approximate the MTJ. When viewed in a direction perpendicular to the MTJ and the magnetic feature, the magnetic feature has a disk shape, and the MTJ has an elliptical shape and is positioned within the disk shape. | 2012-06-21 |
20120153412 | WRITE CURRENT REDUCTION IN SPIN TRANSFER TORQUE MEMORY DEVICES - The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element. | 2012-06-21 |
20120153413 | Non-Volatile Memory Cell with Lateral Pinning - An apparatus and associated method for a non-volatile memory cell, such as an STRAM cell. In accordance with various embodiments, a magnetic free layer is laterally separated from an antiferromagnetic layer (AFM) by a non-magnetic spacer layer and medially separated from a synthetic antiferromagnetic layer (SAF) by a magnetic tunneling junction. The AFM pins the magnetization of the SAF through contact with a pinning region of the SAF that laterally extends beyond the magnetic tunneling junction. | 2012-06-21 |
20120153414 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes: a plurality of magnetic tunnel junction elements arranged on a semiconductor substrate; and a plurality of selection transistors electrically connected to first ends of the plurality of magnetic tunnel junction elements. A plurality of first bit lines are respectively connected to the first ends of the magnetic tunnel junction elements via one or more of the selection transistors. A plurality of upper electrodes are respectively connected to second ends of the plurality of magnetic tunnel junction elements. A plurality of second bit lines are respectively connected to the second ends of the magnetic tunnel junction elements via the upper electrodes. The upper electrodes extend along the second bit lines, and one of the upper electrodes is commonly connected to the second ends of the plurality of magnetic tunnel junction elements arranged in an extending direction of the second bit lines. | 2012-06-21 |
20120153415 | MOUNTING STRUCTURE OF CHIP TYPE ELECTRIC ELEMENT AND ELECTRIC APPARATUS HAVING CHIP TYPE ELECTRIC ELEMENT ON FLEXIBLE BOARD - A mounting structure for mounting a chip type electric element on a flexible board includes: the flexible board having a first land, on which a first lead terminal of another electric element is soldered; and the chip type electric element having a long side. A whole of the long side of the chip type electric element faces a long side of the first land. A length of the long side of the first land is defined as IA, and a distance between one long side of the first land and one long side of the chip type electric element is defined as IB, the one long side of the first land facing the chip type electric element but opposite to the one long side of the chip type electric element. The length of IA is equal to or larger than the distance of IB. | 2012-06-21 |
20120153416 | PHOTOELECTRIC CONVERSION ELEMENT - An object is to provide a photoelectric conversion element with high conversion efficiency. In a photoelectric conversion element with a fine periodic structure on a light-receiving surface side, focus is given to the traveling direction of light that is reflected off another surface. The photoelectric conversion element may be given a structure in which a textured structure that reflects light to the other surface is provided, and light that travels from the light-receiving surface side to the other surface side is reflected so that a component that travels along the photoelectric conversion layer increases. By the distance traveled by the reflected light inside the photoelectric conversion layer increasing, the light that enters the photoelectric conversion element is more easily absorbed by the photoelectric conversion layer and less easily released from the light-receiving surface side, and a photoelectric conversion element with high conversion efficiency can be provided. | 2012-06-21 |
20120153417 | Laser Power Converter for Data Detection and Optical-to-Electrical Power Generation - The present disclosure provides a high-speed laser power converter (LPC). The LPC is able to be cascaded. The LPC has a high-speed photodiode (PD) performance even operated under a forward bias operational voltage. Thus, the present disclosure can generate power (instead of consume power) during high-speed data transmission in an optical interconnect (OI) system using 850 nano-meters (nm) wavelength vertical cavity surface-emitting laser (VCSEL). | 2012-06-21 |
20120153418 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a solid-state imaging device includes photodiodes provided in a substrate, and includes semiconductor regions of a first conductivity type, respectively, and an element isolation region provided in the substrate, includes a semiconductor region of a second conductivity type, and configured to electrically isolate the photodiodes from each other. The element isolation region is tilted in a direction of the center of an image area in which the photodiodes are arrayed. | 2012-06-21 |
20120153419 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A semiconductor device, which is configured as a backside illuminated solid-state imaging device, includes a stacked semiconductor chip which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit; a semiconductor-removed region in which a semiconductor section of a part of the first semiconductor chip unit is completely removed; and a plurality of connection wirings which is formed in the semiconductor-removed region and connects the first and second semiconductor chip units to each other. | 2012-06-21 |
20120153420 | OPTICAL STRUCTURE OF SEMICONDUCTOR PHOTOMULTIPLIER AND FABRICATION METHOD THEREOF - Disclosed is an optical structure formed in an upper side of a semiconductor photomultiplier having a plurality of microcells. The optical structure includes: a first dielectric body formed in an upper side of a dead area between light receiving areas of the respective microcells and having a cross-sectional structure in which a lower side is wider than an upper side; and a second dielectric body formed in the upper side of the light receiving area of each microcell and having a cross-sectional structure in which a lower side is narrower than an upper side, and a refractive index of the second dielectric body is higher than that of the first dielectric body. | 2012-06-21 |
20120153421 | BARRIER FILM AND PRODUCTION METHOD THEREOF - Provided are a barrier film production method and a barrier film comprising at least one organic layer and two or more inorganic layers on a surface of a plastic film, wherein, under an atmosphere of at least 0.3 atmospheric pressure and at most 1.1 atmospheric pressure (1 atmospheric pressure is 1.01325×105 Pa), an organic layer coating liquid is applied on at least one surface of the plastic film, and dried to form the organic layer, thereafter, an inorganic layer coating liquid containing an inorganic compound is applied and dried on the organic layer to laminate at least 2 to 6 inorganic layers, and thereafter, at least two layers of the laminated inorganic layers are subjected to a modification process. | 2012-06-21 |
20120153422 | Imaging Device with Filtering of the Infrared Radiation - An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation. | 2012-06-21 |
20120153423 | SILICON PHOTOMULTIPLIER WITH TRENCH ISOLATION - The present invention relates to a silicon photomultiplier with trench isolation for maintaining the photon detection efficiency high while increasing the dynamic range, by reducing the degradation of the effective fill factor that follows the increase of cell number density intended for a dynamic range enhancement. | 2012-06-21 |
20120153424 | HARDMASK COMPOSITION, METHOD OF FORMING A PATTERN USING THE SAME, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE PATTERN - A hard mask composition, a method of forming a pattern, and a semiconductor integrated circuit device, the hard mask composition including a solvent; and a compound, the compound including a structural unit represented by the following Chemical Formula 1: | 2012-06-21 |
20120153425 | PROCESS FOR FABRICATING INTEGRATED-CIRCUIT CHIPS - Integrated-circuit chips are fabricated according to a process wherein weak portions are formed in a substrate wafer surrounding a plurality of locations. An integrated-circuit chip is defined at each location by destroying the weak portions so as to singulate integrated-circuit chips. | 2012-06-21 |
20120153426 | VOID-FREE WAFER BONDING USING CHANNELS - A method of bonding first and second microelectronic elements includes pressing together a first substrate containing active circuit elements therein with a second substrate, with a flowable dielectric material between confronting surfaces of the respective substrates, each of the first and second substrates having a coefficient of thermal expansion less than 10 parts per million/° C., at least one of the confronting surfaces having a plurality of channels extending from an edge of such surface, such that the dielectric material between planes defined by the confronting surfaces is at least substantially free of voids and has a thickness over one micron, and at least some of the dielectric material flows into at least some of the channels. | 2012-06-21 |
20120153427 | INTEGRATED CIRCUIT AND METHOD OF FABRICATING SAME - A method includes providing a substrate with at least one semiconducting layer. The method also includes forming a plurality of isolation barriers within the at least one semiconducting layer, thereby forming a plurality of device islands. The method further includes inserting a plurality of electronic devices into a portion of the at least one semiconducting layer such that each electronic device is substantially isolated from each other electronic device by the device islands. | 2012-06-21 |
20120153428 | ELECTRONIC DEVICES, CIRCUITS AND THEIR MANUFACTURE - A method of manufacturing an electronic device, comprising a layer of semiconductive material and at least one insulative feature arranged to interrupt the layer of semiconductive material, comprises: providing a layer of semiconductive material, and a layer of compressible material supporting the layer of semiconductive material; and forming the or each insulative feature by a method comprising displacing a respective selected portion of the layer of semiconductive material towards the compressible material so as to compress compressible material under the or each displaced portion and separate at least partly the or each displaced portion from undisplaced semiconductive material. | 2012-06-21 |
20120153429 | 3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL - A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure. | 2012-06-21 |
20120153430 | INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS - A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously. | 2012-06-21 |
20120153431 | INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT - Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s). | 2012-06-21 |
20120153432 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a substrate, a control element provided on the substrate, a resin provided on the control element and a memory element provided above the control element. The memory element is in contact with the resin and electrically connected to the control element provided within a region therebeneath in plan view parallel to a surface of the substrate. | 2012-06-21 |
20120153433 | Tuning the Efficiency in the Transmission of Radio-Frequency Signals Using Micro-Bumps - A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump. | 2012-06-21 |
20120153434 | METAL-INSULATOR-METAL CAPACITORS WITH HIGH CAPACITANCE DENSITY - Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes. | 2012-06-21 |
20120153435 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED GROUND OR POWER DISTRIBUTION - A microelectronic assembly includes a dielectric element having at least one aperture and electrically conductive elements thereon including terminals exposed at the second surface of the dielectric element; a first microelectronic element having a rear surface and a front surface facing the dielectric element, the first microelectronic element having a plurality of contacts exposed at the front surface thereof; a second microelectronic element having a rear surface and a front surface facing the rear surface of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at the front surface and projecting beyond an edge of the first microelectronic element; and an electrically conductive plane attached to the dielectric element and at least partially positioned between the first and second apertures, the electrically conductive plane being electrically connected with one or more of the contacts of at least one of the first or second microelectronic elements. | 2012-06-21 |
20120153436 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM USING THE SAME - Capacitance blocks (first block and second block) respectively formed on two different adjacent common pad electrodes are electrically connected in series through an upper electrode. A distance between two adjacent capacitance blocks connected in series through an upper electrode film for the upper electrode corresponds to a distance between opposing lower electrodes disposed in an outermost perimeter of each capacitance block, and is two or less times than a total film thickness of the upper electrode film embedded between the two adjacent capacitance blocks. | 2012-06-21 |
20120153437 | ESD PROTECTION STRUCTURE FOR 3D IC - An electrostatic discharge (ESD) protection structure for a 3D IC is provided. The ESD protection structure includes a first active layer, a through-silicon via (TSV) device and a second active layer. The TSV is disposed in the first active layer, and the second active layer is stacked with the first active layer. The second active layer includes a substrate and an ESD protection device, wherein the ESD protection device having a doping area embedded in the substrate, and the ESD protection device electrically connects the TSV device. | 2012-06-21 |
20120153438 | MULTIPLE NOBLE METALS FOR LIFETIME SUPPRESSION FOR POWER SEMICONDUCTORS - Certain embodiments combine the use of two or more noble metal impurities (e.g., gold, platinum, palladium, iridium, etc.) to suppress the lifetime of power semiconductors such as diodes. The noble metals may be applied using various methods including, for example, the application of thin films from a liquid suspension of the noble metals (e.g., gold and platinum) and/or alloys thereof onto the wafer and/or the coating the wafer with a layer of the noble metals (e.g., gold and platinum) from high vacuum metal deposition by electron beam or sputtering. The application and drive of the impurities may be simultaneous or sequential. | 2012-06-21 |
20120153439 | STACKED LAYERS OF NITRIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer. | 2012-06-21 |
20120153440 | EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICE AND METHOD OF PRODUCING THE SAME - An epitaxial substrate for electronic devices, in which current flows in a lateral direction and of which warpage configuration is properly controlled, and a method of producing the same. The epitaxial substrate for electronic devices is produced by forming a bonded substrate by bonding a low-resistance Si single crystal substrate and a high-resistance Si single crystal substrate together; forming a buffer as an insulating layer on a surface of the bonded substrate on the high-resistance Si single crystal substrate side; and producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate. The resistivity of the low-resistance Si single crystal substrate is 100 Ω·cm or less, and the resistivity of the high-resistance Si single crystal substrate is 1000 Ω·cm or more. | 2012-06-21 |
20120153441 | OVERLAY MARK ENHANCEMENT FEATURE - An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature. | 2012-06-21 |
20120153442 | SILICON NITRIDE FILM AND PROCESS FOR PRODUCTION THEREOF, COMPUTER-READABLE STORAGE MEDIUM, AND PLASMA CVD DEVICE - Provided is a process of forming a silicon nitride film having concentration of hydrogen atoms below or equal to 9.9×10 | 2012-06-21 |
20120153443 | PACKAGED SEMICONDUCTOR CHIPS WITH ARRAY - A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device. | 2012-06-21 |
20120153444 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. | 2012-06-21 |
20120153445 | HYBRID SUBSTRATES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME AND METHODS FOR FABRICATING SEMICONDUCTOR PACKAGES - Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer. | 2012-06-21 |
20120153446 | MICROELECTRONIC PACKAGES WITH ENHANCED HEAT DISSIPATION AND METHODS OF MANUFACTURING - Several embodiments of microelectronic packages with enhanced heat dissipation and associated methods of manufacturing are disclosed herein. In one embodiment, a microelectronic package includes a semiconductor die having a first side and a second side opposite the first side and a lead frame proximate the semiconductor die. The lead frame has a lead finger electrically coupled to the first side of the semiconductor die. The microelectronic package also includes an encapsulant at least partially encapsulating the semiconductor die and the lead frame. The encapsulant does not cover at least a portion of the second side of the semiconductor die. | 2012-06-21 |
20120153447 | MICROELECTRONIC FLIP CHIP PACKAGES WITH SOLDER WETTING PADS AND ASSOCIATED METHODS OF MANUFACTURING - Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame. | 2012-06-21 |
20120153448 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor. | 2012-06-21 |
20120153449 | NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a non-leaded package structure is provided. An upper surface and a lower surface of a metal base plate are patterned so as to form a plurality of first protruding parts and at least a second protruding part on the upper surface and to form a plurality of first recess patterns on the lower surface corresponding to the first protruding parts. A first solder layer is formed in each of the first recess patterns respectively. A chip is mounted on the second protruding part and electrically connected to the first protruding parts with a plurality of bonding wires. An encapsulant is formed on the upper surface. A back etching process is performed on the lower surface to partially remove the metal base plate until the encapsulant is exposed and a lead group including at least a die pad and a plurality of leads is defined. | 2012-06-21 |
20120153450 | SELF-ORGANIZING NETWORK WITH CHIP PACKAGE HAVING MULTIPLE INTERCONNECTION CONFIGURATIONS - In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc. Among other things, the use of backend side interconnects allows maximum surface area of the chip package to be utilized and provides increased reliability. These advantages are especially realized when used in conjunction with vertical TSVs. | 2012-06-21 |
20120153451 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention comprises a semiconductor element, a main electrode connected to the semiconductor element, and a case for sealing the semiconductor element. The main electrode is provided, extending outside of the case from the inside thereof, and an external thread or an internal thread to be fastened to an external terminal is provided integrally on an extended portion of the main electrode, which extends outside of the case. | 2012-06-21 |