25th week of 2013 patent applcation highlights part 74 |
Patent application number | Title | Published |
20130159581 | METHOD AND APPARATUS FOR REMAPPING INTERRUPT TYPES - A method and apparatus are provided for controlling system management interrupts is disclosed. The method comprises: receiving an interrupt signal; determining a type associated with the interrupt signal; using the determined type to access control information indicating an action to be applied to the determined type of interrupt; and blocking, passing or remapping the interrupt signal in response to the control information. The apparatus comprises a memory, an interrupt unit and a logic circuit. The memory is adapted to store control information regarding a plurality of types of interrupt signals. The interrupt unit is adapted to receive the interrupt signal, and use the interrupt type contained in the interrupt signal to access the control information stored in the memory. The logic circuit is adapted to block, pass or remap said interrupt signal in response to the control information. | 2013-06-20 |
20130159582 | Resource Reservation for an External Device that is Not Available at Startup of a Host Computer - A system and method for reserving resources of a host computer for use by an external device configured to be coupled to an expansion bus of the host computer are described. The host computer may be configured to execute device resource software that operates at a startup of the host computer to reserve one or more resources for the external device. The external device may not be available during the startup of the host computer, e.g., because the external device is not powered on or is not physically connected to the host computer. The device resource software may subsequently detect that the external device becomes available after the startup of the host computer. In response, the device resource software may enable the external device to use the one or more resources that were previously reserved at the startup of the host computer. | 2013-06-20 |
20130159583 | Computer Wall Docking Station - A wall-mounted docking station for a portable computer connects the portable computer to a media entertainment system. The media entertainment system can have multiple zones throughout a room and/or a building, and can play audio, video, images, or other media stored on the portable computer to any zone or a combination of zones. Preferably, the docking station also provides power to the portable computer, and could optionally provide both power and data connectivity over a power line. | 2013-06-20 |
20130159584 | DATA BUS INVERSION CODING - Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY. | 2013-06-20 |
20130159585 | CONTROL SYSTEM AND RELAY APPARATUS - A bus interface receives, via a bus, a control signal for controlling an electronic circuit, and outputs a signal corresponding to the received control signal to the electronic circuit. A signal maintaining circuit maintains the value of the signal to be output from the bus interface to the electronic circuit in accordance with an instruction from a reset control circuit. When the bus becomes unusable due to termination of operations of the control device or the like, the reset control circuit causes the signal maintaining circuit to maintain the value of the output signal to the electronic circuit, and subsequently resets the bus interface so as to restore the bus. | 2013-06-20 |
20130159586 | MOTOR VEHICLE CONTROL SYSTEM WITH SIMPLIFIED INFORMATION EXCHANGE - A control system includes a gateway controller and a remote controller. The gateway controller is configured to embed an HTTP request in a CAN bus-compatible message and transmit the CAN bus-compatible message onto a CAN bus. The remote controller is configured to receive the CAN bus-compatible message from the CAN bus, extract the HTTP request from the CAN bus-compatible message, and create an HTTP response to the HTTP request. | 2013-06-20 |
20130159587 | Interconnect Redundancy for Multi-Interconnect Device - A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths. | 2013-06-20 |
20130159588 | COMPUTING DEVICE AND METHOD FOR TESTING SOL FUNCTION OF A MOTHERBOARD OF THE COMPUTING DEVICE - A method for testing a serial over local area network (SOL) function of a motherboard of a computing device. The method determines that the SOL function is normal if forward data can be transmitted from the serial port of the motherboard to a network interface controller (NIC) of the motherboard through a predefined path, and backward data can be transmitted from the NIC to the serial port through a predefined reverse path. The method determines that the SOL function is abnormal if the forward data cannot be transmitted from the serial port to the NIC through the predefined path, or the backward data cannot be transmitted from the NIC to the serial port through the predefined reverse path. | 2013-06-20 |
20130159589 | BUS CONTROL DEVICE AND BUS CONTROL METHOD - A bus control device includes a storing unit that stores therein a threshold related to bus width of a bus that is a transfer path for data, a comparing unit that compares, when the bus width is reduced, the reduced bus width with the threshold stored in the storing unit, and a selecting unit that selects, on the basis of the result of the comparison performed by the comparing unit, an interrupt operation performed on a processor that performs a process related to a reduction of the bus width. | 2013-06-20 |
20130159590 | LOW LATENCY, HIGH BANDWIDTH DATA COMMUNICATIONS BETWEEN COMPUTE NODES IN A PARALLEL COMPUTER - Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core. | 2013-06-20 |
20130159591 | VERIFYING DATA RECEIVED OUT-OF-ORDER FROM A BUS - In an embodiment, load transactions are issued to a bus. The load transactions are stalled if the bus cannot accept additional load transactions, and the load transactions are restarted after the bus can accept the additional load transactions. Responses are received from the bus to the load transactions out-of-order from an order that the load transactions were sent to the bus. The responses comprise data and index values that indicate an order that the load transactions were received by the bus. The data is compared in the order that the load transactions were received by the bus against expected data in the order that the load transaction were sent to the bus. | 2013-06-20 |
20130159592 | Accessing A Logic Device Through A Serial Interface - Methods, apparatuses, and computer program products for accessing a logic device through a serial interface are provided. Embodiments include receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding to a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request. Embodiments also include identifying in the non-linear address mode a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request. | 2013-06-20 |
20130159593 | APPARATUS, SYSTEM, AND METHOD FOR ANALYZING AND MANAGING DATA FLOW OF INTERFACE APAPRATUSES - An apparatus, a system, and a method for analyzing and managing data flow of interface apparatuses are provided. The system includes a host and the interface apparatuses. In the host, a first controller provides data of a first channel and a second channel through a first interface port. Each interface apparatus has a second interface port, a second controller, a switch, and a third interface port. The second interface port serially connected to the first interface port receives data of the two channels and divides the same to be transmitted on a first transmission path and a second transmission path. The second controller processes data transmitted on the first transmission path. The switch switches data transmitted on the two transmission paths according to a control signal issued by the first controller. The third interface port is connected to the switch for outputting the switched data of the two channels. | 2013-06-20 |
20130159594 | Negotiation Between Multiple Processing Units for Switch Mitigation - A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus. | 2013-06-20 |
20130159595 | Serial Interface for FPGA Prototyping - In aspects of serial interface for FPGA prototyping, an advanced crossbar interconnect (AXI) bridge structure enables serial data communication between field programmable gate arrays (FPGA) in a system-on-chip (SoC). The AXI bridge structure includes a parallel interface configured to receive AXI data signals from an AXI component implemented at a first FPGA. A transmit (TX) engine is configured to packetize the AXI data signals into an AXI data packet, and transmit the AXI data packet to a second FPGA via a serial link. The AXI bridge structure also includes a receive (RX) engine configured to receive an additional AXI data packet from the second FPGA via the serial link, and extract AXI data signals from the additional AXI data packet. The parallel interface is further configured to provide the additional AXI data signals to the AXI component. | 2013-06-20 |
20130159596 | TECHNIQUES FOR MEMORY DE-DUPLICATION IN A VIRTUAL SYSTEM - Techniques for memory de-duplication in a virtual system are described. An apparatus may comprise a first processor circuit coupled to a second processor circuit. A memory unit may be coupled to the first processor circuit and the second processor circuit, the memory unit to store private memory pages and shared memory pages for multiple virtual machines. A memory management application may be operative on the first processor circuit and the second processor circuit in a shared manner to perform memory de-duplication operations on the private memory pages stored in the memory unit to form shared memory pages. The memory management application may perform sequential memory de-duplication operations on the first processor circuit, and parallel memory de-duplication operations on the second processor circuit. Other embodiments are described and claimed. | 2013-06-20 |
20130159597 | HYBRID STORAGE DEVICE AND METHOD OF OPERATING THE SAME - The inventive concept herein relates to data storage devices, and more particularly, to a hybrid storage device including a plurality of storage media. The hybrid storage device may include first and second storage media storing a plurality of data blocks according to a data type and a hybrid controller configured to copy a data block having a change type to the first storage medium if a data type of the data block stored in the second storage medium is changed. | 2013-06-20 |
20130159598 | METHOD OF MASSIVE PARALLEL PATTERN MATCHING AGAINST A PROGRESSIVELY-EXHAUSTIVE KNOWLEDGE BASE OF PATTERNS - A method of pattern and image recognition and identification includes building a data store of known patterns or images having known attributes and comparing those patterns to unknown patterns. The data store and comparison processing may be distributed across processors. A digital pattern recognition engine on each of the processors has the ability to compare a known pattern from the data store and an unknown pattern and compare the two patterns to determine whether the patterns constitute a match based on match criteria. If the comparison indicates a match, the match may be communicated to the data store and added as a known pattern with detected attributes to the data store. If the comparison does not indicate a match, the pattern may be flagged, transmitted to manual recognition, or further processed using character thresholding or cutting or slicing the pattern. | 2013-06-20 |
20130159599 | Systems and Methods for Managing Data in a Device for Hibernation States - The present application is directed to systems and methods for managing data in a device for hibernation states. In one implementation, the device includes an interface and a processor. The interface is coupled with a first memory and a second memory. The processor is in communication with the first and second memories via the interface. The processor is configured to read first data from the first memory, generate image data of the data stored in the first memory based on the first data, and write to the second memory prior to the device entering an initial hibernation state the image data of the data stored in the first memory. The processor is further configured to, after the device awakes from the initial hibernation state, read the image data from the second memory, reconstruct the first data based on the image data, and write the first data to the first memory. | 2013-06-20 |
20130159600 | Systems and Methods for Performing Variable Flash Wear Leveling - Systems and methods for performing wear leveling are disclosed. In one implementation, a controller partitions a memory block into at least a first partition and a second partition. The controller utilizes the first partition of the memory block for storage of data blocks until the first partition reaches a first end of life condition. After the first partition reaches the first end of life condition, the controller utilizes the first partition for storage of data blocks associated with a compression ratio that is less than a compression threshold until the first portion reaches a second end of life condition. The controller additionally utilizes the second partition for the storage of data blocks until the second partition reaches the first end of life condition. | 2013-06-20 |
20130159601 | Controller and Method for Virtual LUN Assignment for Improved Memory Bank Mapping - A controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies, each having a respective plurality of memory blocks, some of which are good and some of which are bad. The controller determines a number of good blocks in each memory die. Based on the determined number of good blocks in each memory die, the controller selects a memory die from each of the multi-chip memory packages to access in parallel, wherein the selected memory dies are not necessarily all in the same relative position in each multi-chip package. The controller then creates a metablock from a set of good blocks from each of the selected memory dies, wherein a maximum number of metablocks that can be created across the selected memory dies is determined by a lowest number of good blocks in the selected memory dies. | 2013-06-20 |
20130159602 | UNIFIED MEMORY ARCHITECTURE - Various embodiments of the present invention relate to a Unified Memory Architecture. The Unified Memory Architecture may use MRAM, phase change memory, and/or any other storage having similar features. | 2013-06-20 |
20130159603 | Apparatus, System, And Method For Backing Data Of A Non-Volatile Storage Device Using A Backing Store - Methods, storage controllers, and systems for backing data of a non-volatile storage device using a backing store are described. One method includes satisfying storage operations using a non-volatile storage device, determining an age for data stored on the non-volatile storage device, and copying data of the non-volatile storage device having an age that satisfies a data retention time threshold to a dedicated backing store. One storage controller includes an operations module that satisfies storage operations using a non-volatile storage device, an age module that determines an age for data stored on the non-volatile storage device, and a backup module that copies data of the non-volatile storage device having an age that satisfies a data retention time threshold to a dedicated backing store. | 2013-06-20 |
20130159604 | MEMORY STORAGE DEVICE AND MEMORY CONTROLLER AND DATA WRITING METHOD THEREOF - A memory storage device is provided. The memory storage device includes a connector, a rewriteable non-volatile memory module, a second temporary memory and a memory controller having a first temporary memory. The memory controller receives a write command and the write data, and temporarily stores the write data into the first temporary memory. The memory controller also copies the write data into the second temporary memory from the first temporary memory and, based on the write command, writes the write data into the rewriteable non-volatile memory module. Additionally, the memory controller determines whether a program fail occurs when executing the write command. If the program fail occurs, the memory controller reads the write data from the second temporary memory and re-execute the write command. Therefore, a write speed of the memory storage device can be effectively improved. | 2013-06-20 |
20130159605 | DATA MERGING METHOD FOR NON-VOLATILE MEMORY MODULE, AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A data merging method for merging valid data of one logical block in a rewritable non-volatile memory module is provided. The method includes assigning a plurality of log physical blocks for the logical block. The method also includes performing a data arrangement operation and a data move operation with a partial synchronization manner to copy the valid data of the logical block into the lower physical pages of the log physical blocks from a first data physical block and at least one spare physical block while programming the valid data of the logical block into a second data physical block from the lower physical pages of the log physical blocks in units of each physical page group. The method further includes remapping the logical block to the second physical block. Accordingly, the method can effectively shorten the time of merging valid data and improving the reliability of data writing. | 2013-06-20 |
20130159606 | SYSTEM AND METHOD FOR CONTROLLING SAS EXPANDER TO ELECTRONICALLY CONNECT TO A RAID CARD - In a method for controlling a SAS expander to electronically connect to a RAID card in an electronic device, a plurality of different types for RAID cards, and configuration parameters of the SAS expander corresponding to each type of the RAID cards are preset. Information of the RAID card is read if the SAS expander is electronically connected the RAID card. The method further determines whether the RAID card matches the SAS expander. If the RAID card does not match the SAS expander, the configuration parameters of the SAS expander corresponding to the RAID card is read, and the read configuration parameters and the read information of the RAID card are written into a firmware file in the storage system. The method further stores the firmware file into a flash memory of the SAS expander. | 2013-06-20 |
20130159607 | MEMORY SYSTEM AND A PROGRAMMING METHOD THEREOF - A method of programming a storage device includes determining, at a controller of the storage device, that a first program mode of a plurality of program modes is to be entered in response to first information, wherein the first information includes a parameter associated with temperature, power consumption or input/output workload, and changing, using the controller, a program ratio of a first programming and a second programming of the storage device in the first program mode. | 2013-06-20 |
20130159608 | BRIDGE CHIPSET AND DATA STORAGE SYSTEM - A data storage system includes: a data storage medium configured to store data; a main controller configured to control an operation of the data storage medium; and a bridge chipset configured to convert a signal provided from the main controller according to a control information provided from an external source to the data storage medium and the main controller and to provide the converted signal to the data storage medium. | 2013-06-20 |
20130159609 | PROCESSING UNIT RECLAIMING REQUESTS IN A SOLID STATE MEMORY DEVICE - An apparatus and method for processing unit reclaiming requests in a solid state memory device. The present invention provides a method of managing a memory which includes a set of units. The method includes selecting a unit from the set of units having plurality of subunits. The method further includes determining a number of valid subunits m to be relocated from the units selected for a batch operation where m is at least 2. The selecting is carried out by a unit reclaiming process. | 2013-06-20 |
20130159610 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE RELATED METHOD OF OPERATION - A non-volatile semiconductor memory device includes a flash memory including plural blocks of memory cells, and a controller. The controller is configured to program a block of memory cells of the flash memory, to determine a first time period elapsed in which a given percentage of memory cells of the block of memory cells are programmed, and to compare the first time period with a reference second time period. The flash memory and controller are further configured, based on a comparison result between the first time period and the reference time period, to change an operational parameter associated with the block of memory cells, the changed operational parameter being in effect during at a next operational access of the block of memory cells. | 2013-06-20 |
20130159611 | SYSTEMS AND METHODS FOR PROVIDING LOAD ISOLATION IN A SOLID-STATE DEVICE - Systems for automatically calibrating a storage memory controller are disclosed. In some embodiments, the systems may be realized as a solid state device system with an electro-static discharge (ESD) protection capability. The system can include a memory controller electrically coupled to a channel, where the memory controller is configured to select at least one of a plurality of flash memory devices. The system can also include at least one isolation device including an ESD protection circuit, configured to electrically couple the channel to the at least one of the plurality of flash memory devices and to decouple the channel from the remaining of the plurality of flash memory devices. | 2013-06-20 |
20130159612 | Programmable Drive Strength in Memory Signaling - Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input. | 2013-06-20 |
20130159613 | METHODS, APPARATUSES, AND COMPUTER PROGRAM PRODUCTS FOR ENHANCING MEMORY ERASE FUNCTIONALITY - A method, apparatus, and computer program product are provided for enhancing memory erase functionality. An apparatus may include a block-based mass memory and a controller configured to receive an erase command from a host device comprising an indication of a location of a block in the mass memory storing memory allocation data. The controller may be further configured to access the memory allocation data based at least in part upon the indicated location. The controller may additionally be configured to determine, based at least in part upon the memory allocation data, blocks within the mass memory that have been freed by the host device. The controller may also be configured to erase the freed blocks. Corresponding methods and computer program products are also provided. | 2013-06-20 |
20130159614 | PAGE BUFFERING IN A VIRTUALIZED, MEMORY SHARING CONFIGURATION - An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with instructions executable by the processor. The instructions including first virtual machine instructions configured to access the volatile memory with a first virtual machine. The instructions including second virtual machine instructions configured to access the volatile memory with a second virtual machine. The instructions including virtual machine monitor instructions configured to page data out from a shared memory to a reserved memory section in the volatile memory responsive to the first virtual machine or the second virtual machine paging the data out from the shared memory or paging the data in to the shared memory. The shared memory is shared across the first virtual machine and the second virtual machine. The volatile memory includes the shared memory. | 2013-06-20 |
20130159615 | DDR RECEIVER ENABLE CYCLE TRAINING - A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed. | 2013-06-20 |
20130159616 | SELF TERMINATED DYNAMIC RANDOM ACCESS MEMORY - A method for operating a memory system and a memory buffer device. The method includes receiving an external clock signal from a clock device of a CPU of a host computer to a buffer device, and receiving an ODT signal from the CPU to a command port of the buffer device. Buffer device provides the self-termination information internally to the common data bus by automatically detecting the read or write command on the common command bus and adjust the termination resistor array in a pre-determined value and timing fashion so that information can be read from or write to a data line of only one of the plurality of DIMM devices coupled together through a common data bus interface. All DIMM devices other than the DIMM device being read can be maintained in a termination state to prevent any signal from traversing to the common the common data bus interface. | 2013-06-20 |
20130159617 | MEMORY SYSTEM, AND A METHOD OF CONTROLLING AN OPERATION THEREOF - A memory system that includes a memory device and a memory controller. The memory device includes a plurality of memory cells, and a first storage unit configured to store information about a weak cell from among the plurality of memory cells. The memory controller is configured to transmit an operation command signal to the memory device, and control an operation of the memory device by using the information about the weak cell provided from the first storage unit. If the operation command signal is related to an operation to be performed using a first of the memory cells and the first memory cell is the weak cell, the memory device is configured to transmit the information about the weak cell to the memory controller. | 2013-06-20 |
20130159618 | NEAREST NEIGHBOR SERIAL CONTENT ADDRESSABLE MEMORY - A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs. | 2013-06-20 |
20130159619 | STORAGE SYSTEM HAVING A CHANNEL CONTROL FUNCTION USING A PLURALITY OF PROCESSORS - Host-connected storage system, including: channel adaptor with local router having processor and transfer list index/processor number information, and a protocol processor for host and router data exchange; and plural storage nodes each including a processor and disk drive and providing the disk drive to the host as a logical unit, wherein processor number information including logical unit and processor number of the node, wherein transfer list index/processor number information including processor number identifying the processor and index information identifying a transfer list including instruction sent to the protocol processor, wherein the router determines a first processor transfer destination of a write request via the processor number information on receiving the write request from the host through the protocol processor, wherein the first processor generates a first transfer list including processing instructed to the protocol processor, and first index information indexing the first transfer list on receiving the write request. | 2013-06-20 |
20130159620 | STORAGE SYSTEM AND METHOD FOR CONTROLLING MEMORY IN STORAGE SYSTEM - According to a storage system of a prior art adopting a cluster structure, various types of large-capacity memories were arranged to enhance the access performance, so that the system required a dedicated control circuit, and there was difficulty in realizing cost reduction and improvement of access performance simultaneously. In order to solve the problems, the present invention provides a storage system in which a group of memories is integrated to MPU memories directly coupled to MPUs in respective controller units, wherein each MPU memory is divided into a duplication information area and a non-duplication information area, and attribute information for controlling accesses thereto are provided. Further, each duplication information area is provided with a double master information area capable of referring to a first memory and a second memory and a single master information area capable of referring only to either the first memory or the second memory, and the accesses thereto are performed based on the attribute information. | 2013-06-20 |
20130159621 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD, AND STORAGE MEDIUM - An information processing apparatus connected to a first storage device and a second storage device via a storage control device, the information processing apparatus includes a transfer unit configured to cause the storage control device to transfer to a rebuilding state after the setting unit has set the password for the second storage device. | 2013-06-20 |
20130159622 | CHAINED, SCALABLE STORAGE DEVICES - Described embodiments access data in a chained, scalable storage system. A primary agent of one or more storage devices receives a host request including a logical address from a host coupled to the primary agent. The primary agent determines, based on the logical address, a corresponding physical address in at least one of the storage devices and generates, based on the physical address, a sub-request for each determined physical address in the storage devices. The primary agent sends, via a storage device interface network operable independently of the host, the sub-requests to the storage devices. The storage device interface network is a peer-to-peer network coupling the storage devices to the primary agent. The primary agent receives sub-statuses in response to the sub-requests, and determines an overall status. The primary agent provides the overall status to the host such that the host is coupled to the storage devices without a switch. | 2013-06-20 |
20130159623 | PROCESSOR WITH GARBAGE-COLLECTION BASED CLASSIFICATION OF MEMORY - Improved memory management in a processor is provided using garbage collection utilities. The processor includes higher performance memory units and lower performance memory units and a memory management unit. The memory management unit includes a garbage collection utility programmed to identify high use memory blocks and low use memory blocks within the higher and lower performance memory units. The memory management unit is also configured to move the high use memory blocks to higher performance memory and move the low use memory blocks to lower performance memory. The method comprises determining performance characteristics of available memory to identify higher performance memory and lower performance memory. Next memory block use metrics are analyzed to identify high use memory blocks and low use memory blocks. Finally, high use memory blocks are moved to the higher performance memory while the low use memory blocks are moved to the lower performance memory. | 2013-06-20 |
20130159624 | STORING THE MOST SIGNIFICANT AND THE LEAST SIGNIFICANT BYTES OF CHARACTERS AT NON-CONTIGUOUS ADDRESSES - In an embodiment, an indicator is set to indicate that all of a plurality of most significant bytes of characters in a character array are zero. A first index and an input character are received. The input character comprises a first most significant byte and a first least significant byte. The first most significant byte is stored at a first storage location and the first least significant byte is stored at a second storage location, wherein the first storage location and the second storage location have non-contiguous addresses. If the first most significant byte does not equal zero, the indicator is set to indicate that at least one of a plurality of most significant bytes of the characters in the character array is non-zero. The character array comprises the first most significant byte and the first least significant byte. | 2013-06-20 |
20130159625 | INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD - An information processing device includes an internal memory which is capable of performing processing faster than an external memory, and a memory controller which controls data transfer between the internal memory and the external memory. The memory controller controls a first data transfer and a second data transfer. The first data transfer is a data transfer from the external memory to the internal memory, and the second data transfer is a data transfer from the internal memory to the external memory. The second data transfer transfers a part of the data area of the internal memory transferred in the first data transfer, and the data area which is read out in a non-continuous way from the internal memory is transferred in place to the external memory in the second data transfer. | 2013-06-20 |
20130159626 | OPTIMIZED EXECUTION OF INTERLEAVED WRITE OPERATIONS IN SOLID STATE DRIVES - A method for data storage includes receiving a plurality of data items for storage in a memory, including at least first data items that are associated with a first data source and second data items that are associated with a second data source, such that the first and second data items are interleaved with one another over time. The first data items are de-interleaved from the second data items, by identifying a respective data source with which each received data item is associated. The de-interleaved first data items and the de-interleaved second data items are stored in the memory. | 2013-06-20 |
20130159627 | SYSTEM AND METHOD FOR MANAGING A CACHE USING FILE SYSTEM METADATA - Systems and methods for management of a cache are disclosed. In general, embodiments described herein store access counts in file system metadata associated with files in the cache. By encoding access counts in the file system metadata, file I/O operations are reduced. Preferably, the reference count is encoded in an access count timestamp in the file system metadata. The access counts can be decoded based on the difference between the access count time stamp and a base time value, with larger differences reflecting a larger access count. The cache can be aged by advancing the base time value, thereby causing the access count for a file to drop. The base time value can also be stored in file system metadata, thereby reducing file I/O operations when performing aging. | 2013-06-20 |
20130159628 | METHODS AND APPARATUS FOR SOURCE OPERAND COLLECTOR CACHING - Methods and apparatus for source operand collector caching. In one embodiment, a processor includes a register file that may be coupled to storage elements (i.e., an operand collector) that provide inputs to the datapath of the processor core for executing an instruction. In order to reduce bandwidth between the register file and the operand collector, operands may be cached and reused in subsequent instructions. A scheduling unit maintains a cache table for monitoring which register values are currently stored in the operand collector. The scheduling unit may also configure the operand collector to select the particular storage elements that are coupled to the inputs to the datapath for a given instruction. | 2013-06-20 |
20130159629 | METHOD AND SYSTEM FOR HASH KEY MEMORY FOOTPRINT REDUCTION - A system and method are disclosed for storing data in a hash table. The method includes receiving data, determining a location identifier for the data wherein the location identifier identifies a location in the hash table for storing the data and the location identifier is derived from the data, compressing the data by extracting the location identifier; and storing the compressed data in the identified location of the hash table. | 2013-06-20 |
20130159630 | SELECTIVE CACHE FOR INTER-OPERATIONS IN A PROCESSOR-BASED ENVIRONMENT - The present invention provides embodiments of methods and apparatuses for selective caching of data for inter-operations in a heterogeneous computing environment. One embodiment of a method includes allocating a portion of a first cache for caching for two or more processing elements and defining a replacement policy for the allocated portion of the first cache. The replacement policy restricts access to the first cache to operations associated with more than one of the processing elements. | 2013-06-20 |
20130159631 | TRANSACTIONAL-CONSISTENT CACHE FOR DATABASE OBJECTS - A system and method for providing a transactional-consistent cache for database objects is disclosed. New data is received by a cache manager. The cache manager updates an entry of a cache with the new data received by the cache manager, by registering the updating of the entry with the new data with an invalidator. The registering includes a timestamp. An invalidation event is then generated by the invalidator. The invalidation event includes a notification about the updating of the entry of the cache with the new data received by the cache manager according to the timestamp. | 2013-06-20 |
20130159632 | MEMORY SHARING BY PROCESSORS - A method of memory sharing implemented by logic of a computer memory control unit, the control unit comprising at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N≧2 non-cooperative processors via the second interfaces, the logic operatively coupled to the first and second interfaces. The method includes receiving, via the second interfaces, a request to access data of the main physical memory from a first processor of the set; evaluating if a second processor has previously accessed the data requested by the first processor; and deferring the request from the first processor when the evaluation is positive, or, granting the request from the first processor when the evaluation is negative. | 2013-06-20 |
20130159633 | QOS MANAGEMENT IN THE L2 CACHE - Methods and apparatuses for assigning a QoS level to memory requests based on the number of currently outstanding memory requests. One or more processors of a processor complex issue memory requests to a L2 cache. The L2 cache controller assigns a QoS level to the memory request based on whether the number of outstanding memory requests is above or below a programmable threshold. If the number is above the threshold, then new requests typically do not impair processor performance since the processor is already waiting for a large number of previous memory requests, and so the new memory request is assigned a low priority level. If the number of outstanding memory requests is below the threshold, then the new memory request is assigned a high priority level. | 2013-06-20 |
20130159634 | Systems and Methods for Handling Out of Order Reporting in a Storage Device - Various embodiments of the present invention provide systems and methods for handling out of order reporting in a storage device. | 2013-06-20 |
20130159635 | SYSTEM AND METHOD FOR MAINTAINING MEMORY PAGE SHARING IN A VIRTUAL ENVIRONMENT - In a virtualized system using memory page sharing, a method is provided for maintaining sharing when Guest code attempts to write to the shared memory. In one embodiment, virtualization logic uses a pattern matcher to recognize and intercept page zeroing code in the Guest OS. When the page zeroing code is about to run against a page that is already zeroed, i.e., contains all zeros, and is being shared, the memory writes in the page zeroing code have no effect. The virtualization logic skips over the writes, providing an appearance that the Guest OS page zeroing code has run to completion but without performing any of the writes that would have caused a loss of page sharing. The pattern matcher can be part of a binary translator that inspects code before it executes. | 2013-06-20 |
20130159636 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF INFORMATION PROCESSING APPARATUS - An information processing apparatus includes a directory. Information is registered with the directory in a first format having entries corresponding to data storage areas, respectively. The information indicates a CPU that stores data stored in a data storage area of one information processing part of plural information processing parts or an information processing part having the CPU. The information processing part converts into a second format. The second format is such that an entry registered in such a way that data is not to be used from among the plural entries of the first format is removed and the number of the entries is reduced. | 2013-06-20 |
20130159637 | SYSTEM AND METHOD FOR OPTIMALLY CREATING STORAGE OBJECTS IN A STORAGE SYSTEM - Systems and methods that enable the optimal creation of a storage object within a virtual storage system are disclosed. In accordance with embodiments, an optimal location with the storage system is determined in response to receiving an indication that a storage object is to be created within the storage system. The system and method prioritize physical storage resources in which to create the storage object, prioritize components to be provided access to the created storage object, and prioritize the interface between the physical storage resources and the accessing component. The storage object is optimally created within the storage system based on the priorities and based, at least in part, on other created storage objects. | 2013-06-20 |
20130159638 | INFORMATION PROCESSING APPARATUS AND MEMORY ACCESS METHOD - A node includes a first converting unit that performs conversion between a logical address and a physical address. The node includes a second converting unit that performs conversion between the physical address and processor identification information for identifying a processor included in a each of a plurality of nodes. The node includes a transmitting unit that transmits transmission data including the physical address and the processor identification information for accessing a storing area indicated by the physical address. The node includes a local determining unit that determines whether an access, indicated by the transmission data received from another nodes, is an access to a local area or an access to a shared area based on the physical address included in the transmission data received by the receiving unit. | 2013-06-20 |
20130159639 | Optimizing for Page Sharing in Virtualized Java Virtual Machines - Methods, systems, and computer programs manage memory of a runtime environment executing on a virtual machine. A runtime environment, such as a Java Virtual Machine, may deterministically arrange immutable data within memory such that a hypervisor may perform page sharing on the immutable data. The runtime environment may page-align the immutable data within memory. The runtime environment may further store the immutable within memory using self-referenced or self-relative pointers. | 2013-06-20 |
20130159640 | SYSTEM AND METHOD OF READING AND WRITING OPERATING PARAMETERS AND DATA FOR A CONTROL DEVICE - The present disclosure provides a system for reading and writing operating parameters and real-time data for a control device. The system includes a power source, and a read/write device powered by the power source, the read/write device configured to conduct modulation of the power supply voltage based on a predetermined encoding mode. The system also includes a control device powered by the read/write device, wherein operating parameters and data information are exchanged between the control device and the read/write device, and the control device is configured to conduct demodulation of an output voltage transmitted by the read/write device. The system further includes power lines electrically connecting the power source to the read/write device and the read/write device to the control device. | 2013-06-20 |
20130159641 | NON-VOLATILE MEMORY STORAGE APPARATUS, MEMORY CONTROLLER AND DATA STORING METHOD - A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system. | 2013-06-20 |
20130159642 | Method of Writing Firmware, Firmware Storage Medium, and Electronic Device - Writing only incompatible firmware is reliably prevented without limiting writing other firmware. A firmware storage area is reserved in printer memory, and an evaluation area for writing evaluation data is reserved in the boot sector at the beginning of the firmware storage area. When the firmware overwriting process starts, the printer control unit gets the evaluation data, which is firmware data overwritten to a fixed address set as the evaluation area, and based on this evaluation data determines whether to complete or abort the firmware writing process. | 2013-06-20 |
20130159643 | DETECTING TAMPERING OF DATA DURING MEDIA MIGRATION, AND STORAGE DEVICE - A method for detecting at a migration destination medium a change in data during media migration between write once read many (WORM) media according to one embodiment includes writing data for WORM from a migration source medium to the migration destination medium; holding an identifier (ID) of the source medium in a non-user storage area in the destination medium; and holding information indicating a feature of the data in the non-user storage area. | 2013-06-20 |
20130159644 | DATA STORAGE DEVICE GENERATING REDUNDANCY FOR DATA PATH PROTECTION OF A PARITY SECTOR - A data storage device is disclosed comprising a non-volatile memory. A write command is received comprising a first logical block address (LBA) and first user data, and a second LBA and second user data. The first LBA is mapped to a first physical block address (PBA) for addressing a first memory segment. The second LBA is mapped to a second PBA for addressing a second memory segment. First redundancy is generated in response to the first user data, second redundancy in generated in response to the second user data, and parity data is generated in response to the first and second user data. Third redundancy is generated in response to the parity data and in response to at least one of the first LBA and the first PBA and at least one of the second LBA and the second PBA. | 2013-06-20 |
20130159645 | DATA SELECTION FOR MOVEMENT FROM A SOURCE TO A TARGET - In one aspect of the present description, in connection with storing a first deduplicated data object in a primary storage pool, described operations include determining the duration of time that the first data object has resided in the primary storage pool, and comparing the determined duration of time to a predetermined time interval. In addition, described operations include, after the determined duration of time meets or exceeds the predetermined time interval, determining if the first data object has an extent referenced by another data object, and determining whether to move the first data object from the primary storage pool to a secondary storage pool as a function of whether the first data object has an extent referenced by another data object after the determined duration of time meets or exceeds the predetermined time interval. Other features and aspects may be realized, depending upon the particular application. | 2013-06-20 |
20130159646 | SELECTING FILES TO BACKUP IN A BLOCK LEVEL BACKUP - Provided are a computer program product, method, and system for backing-up a volume of blocks of data in a storage system. Selection is received of selected files in a volume indicating files to backup. A determination is made from the selected files blocks in the files to backup. A volume backup map is generated indicating the determined blocks to backup. A file list of the selected files to backup and the volume backup map are stored in backup information for the backup. The blocks indicated to backup in the volume backup map are copied to a backup file on a block-by-block basis. | 2013-06-20 |
20130159647 | COMPUTER SYSTEM AND RECLAMATION CONTROL METHOD - A computer system and reclamation control method capable of effectively utilizing storage resources of a storage system even under the circumstance where the storage system is operated according to thin provisioning and a file server can obtain snapshots. | 2013-06-20 |
20130159648 | DATA SELECTION FOR MOVEMENT FROM A SOURCE TO A TARGET - In one aspect of the present description, in connection with storing a first deduplicated data object in a primary storage pool, described operations include determining the duration of time that the first data object has resided in the primary storage pool, and comparing the determined duration of time to a predetermined time interval. In addition, described operations include, after the determined duration of time meets or exceeds the predetermined time interval, determining if the first data object has an extent referenced by another data object, and determining whether to move the first data object from the primary storage pool to a secondary storage pool as a function of whether the first data object has an extent referenced by another data object after the determined duration of time meets or exceeds the predetermined time interval. Other features and aspects may be realized, depending upon the particular application. | 2013-06-20 |
20130159649 | Selecting a Primary-Secondary Host Pair for Mirroring Virtual Machines - A method for mirroring virtual machines from a primary host to a secondary host. The method includes tracking changes for each of a plurality of memory pages and processor states for one or more primary host virtual machines. Responsive to an occurrence of a checkpoint, the primary host virtual machines are stopped. A determination is made if each of the memory pages is frequently changed. In response to the memory page being frequently changed, the frequently changed memory page is marked as being writeable and copied to a buffer. In response to the memory page being infrequently changed, the infrequently changed memory page is marked as being read only. The one or more primary host virtual machines are resumed. A copy of the memory pages, the buffer and changes to the processor states are transmitted to the secondary host. | 2013-06-20 |
20130159650 | BACKUP METHOD AND INFORMATION PROCESSING APPARATUS - A backup method may include discontinuing a process of a working system virtual machine (VM) operating within a physical machine (PM) of a processing apparatus, first duplicating data of a state of the working system VM in a memory of the PM, as a duplicating system VM, second duplicating data of contents of a working system virtual recording medium used to realize the working system VM, in a duplicating system virtual recording medium forming the duplicating system VM, within a storage apparatus of the processing apparatus, and resuming the process of the working system VM, The discontinuing and the first resuming may maintain consistency between the data in the memory and the storage apparatus. | 2013-06-20 |
20130159651 | STORAGE SYSTEM AND STORAGE MIGRATION METHOD - A storage system and storage migration method where migration may be carried out to an access destination of a host apparatus without stopping the exchange of data between the host apparatus and the storage apparatus. This system is provided with a host apparatus inputting and outputting requests for data, a migration source storage apparatus having logical unit(s) correlated to storage regions of physical devices for storing the data, a migration destination storage apparatus having logical unit(s). The system also has an editing unit for editing configuration control information relating to the logical unit(s) for the migration source so as to match with settings for the migration destination storage apparatus, an importing unit for importing edited configuration control information to the migration destination storage apparatus, and a mapping unit for mapping the logical unit(s) of the migration source to the logical unit(s) of the migration destination. | 2013-06-20 |
20130159652 | CONTINUOUS DATA PROTECTION OVER INTERMITTENT CONNECTIONS, SUCH AS CONTINUOUS DATA BACKUP FOR LAPTOPS OR WIRELESS DEVICES - A portable data protection system is described for protecting, transferring or copying data using continuous data protection (CDP) over intermittent or occasional connections between a computer system or mobile device containing the data to be protected, transferred or copied, called a data source, and one or more computer systems that receive the data, called a data target. CDP can be broken down logically into two phases: 1) detecting changes to data on a data source and 2) replicating the changes to a data target. The portable data protection system uses a method that performs the first phase continuously or near continuously on the data source, and the second phase when a connection is available between the data source and the data target. | 2013-06-20 |
20130159653 | Predictive Lock Elision - In at least one embodiment, a method includes determining whether to elide a lock operation based on success of or failure of one or more previous transactional memory operations associated with one or more respective previous lock elisions. In at least one embodiment of the method, the lock operation is associated with a first access of a shared resource and the one or more previous lock elisions are associated with respective one or more previous accesses of the shared resource. | 2013-06-20 |
20130159654 | Electronic Device and Save Data Recording Method - A virtual capacity acquisition unit acquires a size of virtual capacity of a save data area from an application. A storage capacity acquisition unit acquires a size of save data of the application. A writing control unit prohibits the application from writing the save data exceeding the virtual capacity in a recording device. A free space acquisition unit acquires a size of free space of the recoding device, and the writing control unit prohibits the writing of save data whose size is larger than that of the free space. | 2013-06-20 |
20130159655 | STORAGE SYSTEM FOR SUPPORTING USE OF MULTIPLE KEYS - A storage system that enables the use of a plurality of keys respectively stored in a plurality of storage units of a storage device is provided. The storage system includes a storage device including a first storage unit and a second storage unit that are recognized as a single storage device, wherein the first storage unit is configured to store a first key, the second storage unit is configured to store a second key different from the first key, and a controller is configured to transmit to the storage device one of a first key-read control signal that includes information about the first storage unit and a second key-read control signal that includes information about the second storage unit and receive the first key and the second key as identification information of the storage device in response to the first key-read control signal and the second key-read control signal, respectively. | 2013-06-20 |
20130159656 | CONTROLLER, COMPUTER-READABLE RECORDING MEDIUM, AND APPARATUS - A controller includes a memory that stores a program, and a processor that executes, based on the program, a procedure comprising, recording migration data from a source to a destination assigned to a plurality of storages based on information for indicating a position of a recording area which is between areas in which data is recorded in units of blocks, receiving a request to release at least one of the plurality of storages during data migration and migrating recorded data recorded in the at least one of the plurality of storages to other recording area formed in other storages of the plurality of storages, and releasing the at least one of the plurality of storages after migrating the recorded data. | 2013-06-20 |
20130159657 | MEMORY CONTROLLER WITH FAST REACQUISITION OF READ TIMING TO SUPPORT RANK SWITCHING - Techniques for performing fast timing reacquisition of read timing in a memory controller to support rank switching device are described. During operation, a memory controller receives read data for a read operation, wherein the read data includes a calibration preamble. The memory controller uses the calibration preamble to perform a fast timing reacquisition operation to compensate for a timing drift between a clock path and a data path for the read data. In particular, the memory controller performs the fast timing reacquisition by adjusting a data delay line coupled to a clock path associated with a control loop, wherein the control loop controls a data clock which is used to receive read data at the memory controller. | 2013-06-20 |
20130159658 | DYNAMIC RECORD MANAGEMENT FOR SYSTEMS UTILIZING VIRTUAL STORAGE ACCESS METHOD (VSAM) - When using virtually stored data sets, such as virtual storage access method (VSAM) data sets, while the data set is open (referred to as an open time) static data set characteristics and/or job parameters have been defined for the VSAM data set. In one approach, a method for modifying a virtual storage access method (VSAM) data set includes opening a VSAM data set; and modifying a VSAM control block structure for the VSAM data set. | 2013-06-20 |
20130159659 | MULTI-LEVEL DATA PARTITIONING - Based on one or more first columns of a table partitioned at a first level over multiple first level partitions, a first partition criteria is evaluated for a data record. Each of the at least first level partitions is further partitioned into a same number of second-level partitions using a same second partitioning method for all first level partitions. One first level partition is identified for storage of the data record, for example by determining the one of the at least two data server processes using the first partition criteria and a first partitioning method that differs from the second partitioning method. Based on one or more second columns of the table, a second partition criteria is evaluated for the data record, and the data record is stored in one of the second-level partitions of the at least two first level partitions. | 2013-06-20 |
20130159660 | SYSTEM AND METHOD FOR IDENTIFYING A CHARACTER-OF-INTEREST - A method of generating an output vector to identify a character-of-interest using a sparse distributed memory (SDM) module. The method includes obtaining a feature vector having a vector address. The feature vector is based on a character-of-interest in an acquired image. The method also includes identifying activated locations from hard locations by determining relative distances between the vector address and the stored vector location addresses. Stored content counters of the activated locations include first and second stored sub-sets of counters. The method also includes combining the counters of the first stored sub-sets of the activated locations using a first summation thread to provide a first combined sub-set of values. The method also includes combining the counters of the second stored sub-sets of the activated locations using a second summation thread to provide a second combined sub-set of values. The first and second summation threads are run in parallel. | 2013-06-20 |
20130159661 | HARDWARE MONITOR - A monitor includes a register configured to store at least two contexts and a context change value. A context selector is configured to select at least one of the two contexts for context monitoring. The selection is made dependent on whether the context change value matches a first part of a memory access address. | 2013-06-20 |
20130159662 | Working Set Swapping Using a Sequentially Ordered Swap File - Techniques described enable efficient swapping of memory pages to and from a working set of pages for a process through the use of large writes and reads of pages to and from sequentially ordered locations in secondary storage. When writing pages from a working set of a process into secondary storage, the pages may be written into reserved, contiguous locations in a dedicated swap file according to a virtual address order or other order. Such writing into sequentially ordered locations enables reading in of clusters of pages in large, sequential blocks of memory, providing for more efficient read operations to return pages to physical memory. | 2013-06-20 |
20130159663 | MEMORY MANAGEMENT UNIT FOR A MICROPROCESSOR SYSTEM, MICROPROCESSOR SYSTEM AND METHOD FOR MANAGING MEMORY - The invention pertains to a memory management unit for a microprocessor system, the memory management unit being connected or connectable to at least one processor core of the microprocessor system and being connected or connectable to a physical memory of the microprocessor system. The memory management unit is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit comprises a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit is adapted to prevent write access to the second register table by a process not in hypervisor mode. The memory management unit is further adapted to allow write access to the first register table of a process running in or under supervisor mode to reconfigure the physical address information indicated in the first register table with memory mapping information relating to at least one physical address, if the at least one physical address is in the allowed address range, and to prevent write access to the first register table of the process running in or under supervisor mode if the at least one physical address is not in the allowed address range. The invention also pertains to a microprocessor system and a method for managing memory. | 2013-06-20 |
20130159664 | Infrastructure Support for Accelerated Processing Device Memory Paging Without Operating System Integration - In a CPU of the combined CPU/APD architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to an APD, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations. | 2013-06-20 |
20130159665 | SPECIALIZED VECTOR INSTRUCTION AND DATAPATH FOR MATRIX MULTIPLICATION - A data processing element includes an input unit configured to provide instructions for scalar, vector and array processing, and a scalar processing unit configured to provide a scalar pipeline datapath for processing a scalar quantity. Additionally, the data processing element includes a vector processing unit coupled to the scalar processing unit and configured to provide a vector pipeline datapath employing a vector register for processing a one-dimensional vector quantity. The data processing element further includes an array processing unit coupled to the vector processing unit and configured to provide an array pipeline datapath employing a parallel processing structure for processing a two-dimensional vector quantity. A method of operating a data processing element and a MIMO receiver employing a data processing element are also provided. | 2013-06-20 |
20130159666 | REDUCING ISSUE-TO-ISSUE LATENCY BY REVERSING PROCESSING ORDER IN HALF-PUMPED SIMD EXECUTION UNITS - Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction. | 2013-06-20 |
20130159667 | Vector Size Agnostic Single Instruction Multiple Data (SIMD) Processor Architecture - A computer has a memory adapted to store a first plurality of instructions encoded with a first vector size and a second plurality of instructions encoded with a second vector size. An execution unit executes the first plurality of instructions and the second plurality of instructions by processing vector units in a uniform manner regardless of vector size. | 2013-06-20 |
20130159668 | PREDECODE LOGIC FOR AUTOVECTORIZING SCALAR INSTRUCTIONS IN AN INSTRUCTION BUFFER - A circuit arrangement, method, and program product for substituting a plurality of scalar instructions in an instruction stream with a functionally equivalent vector instruction for execution by a vector execution unit. Predecode logic is coupled to an instruction buffer which stores instructions in an instruction stream to be executed by the vector execution unit. The predecode logic analyzes the instructions passing through the instruction buffer to identify a plurality of scalar instructions that may be replaced by a vector instruction in the instruction stream. The predecode logic may generate the functionally equivalent vector instruction based on the plurality of scalar instructions, and the functionally equivalent vector instruction may be substituted into the instruction stream, such that the vector execution unit executes the vector instruction in lieu of the plurality of scalar instructions. | 2013-06-20 |
20130159669 | LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM OF VIRTUAL THREADS ACROSS MULTIPLE HARDWARE THREADS - A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core. | 2013-06-20 |
20130159670 | COUNTER OPERATION IN A STATE MACHINE LATTICE - Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers. | 2013-06-20 |
20130159671 | METHODS AND SYSTEMS FOR DETECTION IN A STATE MACHINE - A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D-flip flop including an output coupled to a second input of the AND gate. | 2013-06-20 |
20130159672 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 2013-06-20 |
20130159673 | PROVIDING CAPACITY GUARANTEES FOR HARDWARE TRANSACTIONAL MEMORY SYSTEMS USING FENCES - A method is provided that includes determining a number of outstanding out-of-order instructions in an instruction stream. The method includes determining a number of available hardware resources for executing out-of-order instructions and inserting fencing instructions into the instruction stream if the number of outstanding out-of-order instructions exceeds the determined number of available hardware resources. A second method is provided for compiling source code that includes determining a speculative region. The second method includes generating machine-level instructions and inserting fencing instructions into the machine-level instructions in response to determining the speculative region. A processing device is provided that includes cache memory and a processing unit to execute processing device instructions in an instruction stream. The processing device includes an out-of-order speculation supervisor unit to determine hardware resource availability and generate an indication to insert fencing instructions in response to the availability. Computer readable storage media are also provided. | 2013-06-20 |
20130159674 | INSTRUCTION PREDICATION USING INSTRUCTION FILTERING - A method and circuit arrangement for selectively predicating instructions in an instruction stream based upon a predication filter criteria defined by a predication filter, which describes types or patterns of instructions that should be predicated. Predication logic compares a respective instruction of an instruction stream to predication filter criteria to determine whether the respective instruction matches the predication filter criteria, and the respective instruction is selectively predicated based on whether the respective instruction matches the predication filter criteria. | 2013-06-20 |
20130159675 | INSTRUCTION PREDICATION USING UNUSED DATAPATH FACILITIES - A method and circuit arrangement for selectively predicating an instruction in an instruction stream based upon a value corresponding to a predication register address indicated by a portion of an operand associated with the instruction. A first compare instruction in an instruction stream stores a compare result in at a register address of a predication register. The register address of the predication register is stored in a portion of an operand associated with a second instruction, and during decoding the second instruction, the predication register is accessed to determine a value stored at the register address of the predication register, and the second instruction is selectively predicated based on the value stored at the register address of the predication register. | 2013-06-20 |
20130159676 | INSTRUCTION SET ARCHITECTURE WITH EXTENDED REGISTER ADDRESSING - A method and circuit arrangement selectively repurpose bits from a primary opcode portion of an instruction for use in decoding one or more operands for the instruction. Decode logic of a processor, for example, may be placed in a predetermined mode that decodes a primary opcode for an instruction that is different from that specified in the primary opcode portion of the instruction, and then utilize one or more bits in the primary opcode portion to decode one or more operands for the instruction. By doing so, additional space is freed up in the instruction to support a larger register file and/or additional instruction types, e.g., as specified by a secondary or extended opcode. | 2013-06-20 |
20130159677 | INSTRUCTION GENERATION - Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command. | 2013-06-20 |
20130159678 | Code optimization by memory barrier removal and enclosure within transaction - A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by enclosing the code section within a transaction that employs hardware transactional memory of the computing device, and removing the memory barrier instructions from the code section. Execution of the code section as has been enclosed within the transaction can be monitored to yield monitoring results. Where the monitoring results satisfy an abort threshold corresponding to excessive aborting of the execution of the code section as has been enclosed within the transaction, the code section is split into code sub-sections, and each code sub-section enclosed within a separate transaction that employs the hardware transactional memory. Splitting the code section sections and enclosing each code sub-section within a separate transaction can decrease occurrence of the code section aborting during execution. | 2013-06-20 |
20130159679 | Providing Hint Register Storage For A Processor - In one embodiment, the present invention includes a method for receiving a data access instruction and obtaining an index into a data access hint register (DAHR) register file of a processor from the data access instruction, reading hint information from a register of the DAHR register file accessed using the index, and performing the data access instruction using the hint information. Other embodiments are described and claimed. | 2013-06-20 |
20130159680 | SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PARALLELIZING LARGE NUMBER ARITHMETIC - Methods, systems, and computer program products for the performance of arithmetic operations on large numbers. The addition of large numbers may be parallelized by adding corresponding sections of the numbers in parallel. The multiplication of large numbers may be accomplished by applying a multiplier to a multiplicand after the latter is divided into sections, where the multiplication of the sections is performed in parallel. Products for each section are saved in high and low order vectors, which may then be aligned and added. The comparison of two large numbers may be performed by comparing the numbers, section by section, in parallel. In an embodiment, these processes may be performed in a graphics processing unit (GPU) having multiple cores. In an embodiment, such a GPU may be integrated into a larger die that also incorporates one or more conventional central processing unit (CPU) cores. | 2013-06-20 |