25th week of 2013 patent applcation highlights part 25 |
Patent application number | Title | Published |
20130154665 | POWER DETECTION CIRCUIT - There is provided a power detection circuit capable of appropriately adjusting detection voltage characteristics by using simple configuration. The power detection circuit includes a first resistor having current applied thereto to adjust a detection voltage value of input power, an element having an applied voltage and a load characteristic changed according to the input power, and a second resistor connected to the element and having current applied thereto when resistance of the element becomes relatively low, to adjust the detection voltage value of the input power. Detection voltage characteristics may be appropriately adjusted using a simple configuration. | 2013-06-20 |
20130154666 | LEAK DETECTION DEVICE, AND COATING INTENDED FOR A FLUID TRANSPORT OR STORAGE MEMBER AND COMPRISING SAID DETECTION DEVICE - The invention relates in particular to a method of covering a duct for transporting or storing a fluid in a device for detecting a leak of the fluid, the device comprising a layer of insulating fibrous material arranged to surround the duct and a layer of conductive material that extends against the layer of insulating material, the conductive material being essentially constituted by fibers of carbon or graphite, wherein the layer of insulating material is secured to the wall of the duct by strapping ties around said layer. | 2013-06-20 |
20130154667 | DETECTION OF CHARGING CABLE - A method is provided for detecting a state of a connection between an electrically driven motor vehicle ( | 2013-06-20 |
20130154668 | DEVICE FOR TESTING A SURFACE AND ASSOCIATED METHOD - The device according to the invention comprises a holder and a transmitter supported by the holder, the transmitter being capable of transmitting an electromagnetic signal toward the surface any transmission frequency (Fe). It includes a receiver for receiving a signal reflected on the surface. The device comprises a guide assembly for guiding the movement of the holder to move the transmitter and the receiver across from the surface, tangentially relative to the surface. It comprises an extraction unit for extracting, in the signal received by the receiver, a shifted frequency component of the transmission frequency resulting from a local impedance variation of the surface. The extraction unit produces an extracted signal representative of the state of the surface from the shifted frequency component. | 2013-06-20 |
20130154669 | Housings for inductive proximity sensors - Inductive Proximity Sensors are non-contact sensing devices used in manufacturing processes to sense metal targets. In practice, it is common for objects to contact the sensor causing the sensor to malfunction. An inductive sensor with improved durability is required. An inductive proximity sensor includes an exterior housing, an interior sensing coil and electronic circuit, and a connector. The Exterior housing is produced from one piece of metal bar, bored from one end to the tip of the other end, leaving the cylindrical tube open only on one end. The Exterior Housing is produced with an Inside Dimension that is smaller than previous proximity sensors and places the coil and electronic circuit further away from the Outside Dimension of the Exterior Housing. The interior sensing coil and electronic circuit are protected by the thick casing of the Exterior housing to improve structural rigidity and the longevity of operation in manufacturing processes. | 2013-06-20 |
20130154670 | Method and Apparatus for Detecting Smoke in an ION Chamber - A smoke detection sensor ion chamber has a capacitance and a change in the permittivity of that capacitance dielectric (ionized air in the chamber) may be used to detect the presence of smoke therein. Smoke from typical fires is mainly composed of unburned carbon that has diffused in the surrounding air and rises with the heat of the fire. The permittivity of the carbon particles is about 10 to 15 times the permittivity of clean air. The addition of the carbon particles into the air in the ion chamber changes in the permittivity thereof that is large enough to measure by measuring a change in capacitance of the ion chamber. | 2013-06-20 |
20130154671 | Real-time, label-free detection of nucleic acid amplification in droplets using impedance spectroscopy and solid-phase substrate - A method for detecting presence of nucleic acid amplification in a test droplet. A set of detection electrodes are provided in contact with a fluidic channel. The test droplet is provided in vicinity of the detection electrodes through the fluidic channel. An alternate current (AC) power at a first frequency is applied across the set of detection electrodes. A first measurement value that reflects electrical impedance of the test droplet at the first frequency is obtained. This value is compared with a corresponding reference value, wherein the corresponding reference value is obtained by measuring a reference droplet containing known amplified nucleic acid or known unamplified nucleic acid at the first frequency. The presence of amplified nucleic acid in the test droplet is thus determined based on the comparison. | 2013-06-20 |
20130154672 | Method and System for Battery Current Measurement Calibration - A sensor for monitoring battery current includes a shunt and a current source. The shunt has a resistance with an actual value. The current source is configured to provide a known value of current through the shunt. A controller is configured to generate a measured value of the current through the shunt as a function of a measured value of voltage drop across the shunt caused by the current through the shunt and an assumed value of the resistance of the shunt. The controller is further configured to detect the assumed value of the resistance of the shunt as being different than the actual value of the resistance of the shunt when the known and measured values of the current differ. | 2013-06-20 |
20130154673 | MEASURING FLOATING BODY VOLTAGE IN SILICON-ON-INSULATOR (SOI) METAL-OXIDE-SEMICONDUCTOR-FIELD-EFFECT-TRANSISTOR (MOSFET) - In one embodiment, a body region of a body-contacted silicon-on-insulator (SOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) is connected to a gate of another MOSFET in a sensing circuit to form a floating body node. The voltage at the floating body node is accurately obtained at the output of the sensing circuit and used to provide an estimate of required floating body voltage over a full device operating range. | 2013-06-20 |
20130154674 | METHOD OF HIGH VOLTAGE DETECTION AND ACCURATE PHASE ANGLE MEASUREMENT IN CORDLESS PHASING METERS - A high voltage detection device comprises a probe comprising an electrode for contacting a high voltage electrical line. The electrode is connected in series with a resistor. A meter comprises a housing enclosing an electrical circuit for measuring line voltage. The electrical circuit comprises an input circuit for connection to the probe. The input circuit is adapted to suppress high frequency noise pick up by the probe and develop a bipolar voltage representing measured line voltage. A voltage detection circuit comprises a differential amplifier circuit for converting the bipolar voltage to a proportionate voltage signal. A signal processing circuit receives the proportionate voltage signal and drives the display for displaying the measured line voltage. | 2013-06-20 |
20130154675 | SUBSTRATE HOLDING DEVICE AND METHOD, AND INSPECTION APPARATUS AND METHOD USING THE SUBSTRATE HOLDING DEVICE AND METHOD - Non-contact type displacement sensors which measure the height of a substrate surface are installed above the substrate in order to hold the upper surface of the substrate at a desired height or to maintain the flatness of the substrate. A substrate mounting device is such that a plurality of grooves and of barriers are provided on the upper surface of a table and air is supplied between the substrate and the table to enable the pressure of air to displace the substrate. In addition, the substrate mounting device has such a structure as to make it possible to deform the substrate into an arbitrary convex-concave shape or to make the substrate flat by feeding back the output of the displacement sensor. | 2013-06-20 |
20130154676 | CABLE FATIGUE MONITOR AND METHOD THEREOF - A monitor for determining the operation condition of at least one cable that suffers bending and/or twisting and constitutes an electrical loop and a method thereof are provided. The monitor comprises a test electrical signal generator ( | 2013-06-20 |
20130154677 | APPARATUS AND METHOD FOR TESTING PAD CAPACITANCE - A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor. | 2013-06-20 |
20130154678 | Electrically Conductive Pins For Microcircuit Tester - The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board including a rocker base protrusion, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface. | 2013-06-20 |
20130154679 | TESTING SYSTEM - Disclosed is a testing system, which includes a thin film transistor substrate. The thin film transistor substrate includes a plurality of thin film transistors and a plurality of connecting pads. Each of the thin film transistors includes a first electrode, a second electrode, and a third electrode. The thin film transistor substrate further includes a testing pad. One of the first electrode and the second electrode of each of the thin film transistors is electrically connected with one of the connecting pads. The third electrode and the other one of the first electrode and the second electrode of each of the thin film transistors are electrically connected with the testing pad. The testing system of the present invention is capable of decreasing the cost of the testing system and the complexity of disposed circuits. | 2013-06-20 |
20130154680 | SIGNAL TRANSMISSION LINES WITH TEST PAD - A pair of signal transmission lines includes an aggressor line, a victim line, a first test pad, and a second test pad. The first test pad is in the aggressor line. The victim line is parallel to the aggressor line. A second test pad is in the victim line. The first test pad, on the aggressor line, is misaligned with the second test pad, on the victim line, to reduce the incidence and amplitude of any crosstalk generated. | 2013-06-20 |
20130154681 | SUBSTRATE INSPECTION JIG AND SUBSTRATE INSPECTION METHOD - A substrate inspection jig for use in inspection of an electrical property of a printed board to be inspected on which an electronic component is mounted includes a spacer which is mounted on the printed board to be inspected, a conductive plate which is connected to the spacer, and is disposed along an arrangement direction of electrode terminals of the electronic component to be inspected, and a fastener which fastens the spacer on the printed board to be inspected, wherein the plate is disposed above the printed board to be inspected so as to avoid contact with the printed board to be inspected, and a predetermined potential of the printed board to be inspected is set to the plate through the spacer or/and the fastener. | 2013-06-20 |
20130154682 | PROBE ASSEMBLY, PROBE CARD INCLUDING THE SAME, AND METHODS FOR MANUFACTURING THESE - Quality of connection portions between respective probes and respective wires in a probe assembly is improved. Also, time required for work for connection between the probes and the wires is shortened. Further, improper connection between the probes and the wires is eliminated. A probe assembly includes an electric insulating substrate, a plurality of probes supported on one surface of the substrate, a plurality of through holes provided in the substrate to respectively correspond to the plurality of probes and filled with a conductive material attached to the respective probes, and a plurality of conductive membranes formed on the other surface of the substrate and respectively attached to the conductive material in the plurality of through holes. | 2013-06-20 |
20130154683 | ELECTRICAL CHARACTERISTIC MEASURING APPARATUS AND METHOD OF SOLAR CELL - In one exemplary embodiment, an electrical characteristic measuring apparatus of solar cell comprises a resilient metal attached to a bus bar of a solar cell and a conducting device located at one end of the resilient metal. The resilient metal has an open via, and the conducting device contacts with the bus bar through the open via. The electrical characteristic measuring apparatus is attached to the bus bar located at a front plane of solar cell. The resilient metal and the conducting device, respectively, connect electrically to a testing device contacted to electrode located at the back plane of solar cell. Thus the resilient metal, the testing device, and the electrode of the back plane form a current measuring loop, and the conducting device, the testing device, and the electrode of the back plane form a voltage measuring loop. | 2013-06-20 |
20130154684 | BIAS COMPENSATION METHOD AND SYSTEM FOR MINIMIZING PROCESS, VOLTAGE AND TEMPERATURE CORNER VARIATIONS - A system and method for calibrating bias in a data transmission system including a calibrated bias having impedance calibration for accommodating parameter variations in the data transmission system. A current mirror receives and balances bias currents between the calibrated bias and an output driver from the data transmission system. A digital compensation logic circuit is connected to the calibrated bias to adjust the calibrated bias for variations in parameters causing a current tail effect. A calibration logic circuit adjusts calibration due to variations in operational parameters, such that the tail current variations are minimized. | 2013-06-20 |
20130154685 | BOOLEAN LOGIC IN A STATE MACHINE LATTICE - Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell. | 2013-06-20 |
20130154686 | Method and Apparatus for Facilitating Communication Between Programmable Logic Circuit and Application Specific Integrated Circuit with Clock Adjustment - A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain. | 2013-06-20 |
20130154687 | Semiconductor Device Having Features to Prevent Reverse Engineering - It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices. | 2013-06-20 |
20130154688 | Method for Detecting a Working Area and Device Therefor - A method for detecting a position with respect to a mobile working machine includes providing a current signal in a boundary conductor, which surrounds the defined area, in accordance with a boundary signal that is provided, the boundary signal corresponding to a pseudo-accident signal; and receiving a detection signal of a magnetic field. The method further includes generating a reconstructed boundary signal from the detection signal; providing a reference signal which has a bit pattern corresponding to the boundary signal provided; carrying out a correlation method in order to determine a time-based correlation offset between the reference signal and the reconstructed boundary signal and a correlation value between the reference signal and the reconstructed boundary signal, which are displaced in relation to each other by the correlation offset determined; and determining a position inside or outside the defined area as a function of the correlation value determined. | 2013-06-20 |
20130154689 | IMPEDANCE CALIBRATION CIRCUIT - An impedance calibration circuit may include a first reference voltage generator configured to generate a first reference voltage in response to reference voltage calibration signals, a second reference voltage generator configured to provide a second reference voltage as a conversion voltage, an impedance calibration signal generator configured to compare the conversion voltage with the first reference voltage and generate impedance calibration signals when an enable signal is activated, and a register configured to store the impedance calibration signals finally calibrated and generate reference voltage calibration signals in response to the stored impedance calibration signals. | 2013-06-20 |
20130154690 | NESTED DIGITAL DELTA-SIGMA MODULATOR - Methods and systems are disclosed that provide a radio frequency synthesizer that generates precise frequencies over a large radio frequency range. The radio frequency synthesizer can provide a high resolution of frequency generation and still provide precise frequencies over a range of radio frequencies. The precision and resolution while maintaining a large operating range come from the ability of the frequency synthesizer to generate frequencies as a product of a plurality of moduli. For example, the frequency can be generated from a reference frequency using a first modulus and a second modulus. The plurality of modulo can be implemented using nested digital delta-sigma modulators in a fractional-N frequency synthesizer. | 2013-06-20 |
20130154691 | MULTI-PHASE CLOCK GENERATION APPARATUS AND METHOD - A multi-phase clock generator may receive an input clock signal as an input. The clock generator may also receive an inverse of the input clock signal. The clock generator may produce a plurality of output clock signals having different phases. The phases of the output clock signals may be evenly spaced. The output clock signals may have a similar waveform to the input clock signal, with a frequency that is lower than the input clock signal by a division factor. | 2013-06-20 |
20130154692 | LOW-POWER PROGRAMMABLE OSCILLATOR AND RAMP GENERATOR - A circuit for generating a signal comprising a first transistor having a drain, a gate and a source. A second transistor having a drain, a source and a gate coupled to the gate of the first transistor to form a current mirror. A current source coupled to the source of the first transistor. A diode-connected transistor having a drain coupled to the source of the second transistor, a source and a gate that forms an output. A variable resistor having a first terminal coupled to the source of diode-connected transistor and a second terminal. A capacitor coupled to the second terminal of the variable resistor. | 2013-06-20 |
20130154693 | TIMING CIRCUIT CALIBRATION IN DEVICES WITH SELECTABLE POWER MODES - Techniques are provided which may be implemented in various methods, apparatuses, and/or articles of manufacture for use by a device that is operable in a plurality of modes, including “higher power mode” and a “lower power mode”. A timing circuit may be set based, at least in part, on a phase value obtained from a signal from a ground-based transmitter, and operation of the device may be selectively transitioned to a lower power mode wherein the device uses the timing circuit. In certain example implementations, operation of the device to the lower power mode may be selectively transition and based, at least in part, on a determination that one or more attribute values satisfy a profile test indicating that the electronic device is likely to be within a characterized environment, and/or a determination that the electronic device is likely to be in a constrained motion state. | 2013-06-20 |
20130154694 | PHASE-LOCKED LOOP FREQUENCY STEPPING - A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division. | 2013-06-20 |
20130154695 | PHASE LOCK LOOP WITH ADAPTIVE LOOP BANDWIDTH - Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors. | 2013-06-20 |
20130154696 | CHARGE PUMP CIRCUIT AND PHASE LOCK LOOP CIRCUIT - A charge pump circuit is provided. The charge pump circuit includes a current driving unit, a current draining unit, a switch, and a voltage splitting circuit. The current driving circuit receives a first control signal to transmit a driving current to the first end or the second end according to the first control signal. The current draining unit receives a second control signal to drain a draining current from the first end or the second end according to the second control signal. The switch is coupled between the first end and the second end, and the switch is turned on or turned off according to a power down control signal. The voltage splitting circuit receives a reference power voltage, and is coupled to the first end. The voltage splitting circuit provides a splitting power to the first end by splitting the voltage of the reference power voltage. | 2013-06-20 |
20130154697 | PLL CIRCUIT - A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator. | 2013-06-20 |
20130154698 | DELAY-LOCKED LOOP WITH PHASE ADJUSTMENT - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 2013-06-20 |
20130154699 | REFERENCE FREQUENCY GENERATION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND ELECTRONIC DEVICE - An oscillator circuit complementarily increases or reduces, in response to a transition of a signal level of a reference clock, a signal level of a first oscillation signal and a signal level of a second oscillation signal. An oscillation control circuit compares the first and second oscillation signals to a comparison voltage, and transitions the signal level of the reference clock in accordance with a result of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. A reference voltage control circuit increases or reduces the reference voltage according to a frequency difference between a basis clock and the reference clock. | 2013-06-20 |
20130154700 | Delay-Locked Loop with Dynamically Biased Charge Pump - A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output. | 2013-06-20 |
20130154701 | CHARGE PUMP, PHASE FREQUENCY DETECTOR AND CHARGE PUMP METHODS - A phase/frequency detector for control signal to controlling a charge pump includes: a core circuit arranged to output a first phase signal and a second phase signal according to a phase/frequency difference between a reference clock signal and an input clock signal; and a timing circuit coupled to the core circuit and arranged to generate a first control signal and a second control signal for controlling the charge pump according to the first phase signal and the second phase signal, wherein only one of the first control signal and the second control signal is indicative of an enabled operation when the reference clock signal and the input clock signal are substantially identical in phase. | 2013-06-20 |
20130154702 | DUTY CYCLE CORRECTION CIRCUIT AND DELAY LOCKED LOOP CIRCUIT INCLUDING THE SAME - A duty cycle correction circuit includes: a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal; a duty cycle detection section configured to detect a duty cycle of the output clock signal and generate an up-down signal; a noise detection signal generation section configured to detect a variation of the up-down signal and generate the noise detection signal; and a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal. | 2013-06-20 |
20130154703 | Method and System to Measure and Compensate undue DCO Frequency Peaks at GFSK Ramp Down - One embodiment of the invention relates to a communication system having an amplitude modulation path, a frequency deviation component, a characterization component, a peak cancellation component and a compensation unit. The amplitude modulation path is configured to provide an amplitude modulation signal. The frequency deviation component is configured to generate a frequency deviation signal. The characterization component is configured to generate characterization coefficients according to the amplitude modulation signal and the frequency deviation signal. The peak cancellation component is configured to identify peaks according to the amplitude modulation signal and generate a peak cancellation signal to compensate for peak distortion by the identified peaks. The compensation unit utilizes the characterization coefficients, the amplitude modulation signal and the peak cancellation signal to generate a correction signal that compensates for peak distortions and amplitude modulation to frequency modulation effects. | 2013-06-20 |
20130154704 | Method and System for Compensating Mode Conversion Over a Communications Channel - A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power. | 2013-06-20 |
20130154705 | ELECTRONIC DEVICE - An electronic device according to one or more embodiments of the present invention comprises an output line, a current mirror circuit and a comparator. Current signals from a plurality of signal sources are output to the output line. The current mirror circuit is electrically connected to the output line. The comparator is configured to compare a mirrored current signal from the current mirror circuit with a reference current signal. The comparator is configured to output a signal representing a comparison result of amplitudes of the mirrored current signal and the reference current signal. | 2013-06-20 |
20130154706 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area. | 2013-06-20 |
20130154707 | RECOVERABLE AND RECONFIGURABLE PIPELINE STRUCTURE FOR STATE-RETENTION POWER GATING - A system, electronic circuit, and method are disclosed. A method embodiment comprises receiving a control signal associated with a power gating operation mode of an electronic circuit, applying a reference voltage to the electronic circuit based upon the power gating operation mode, and maintaining data representing a state of a logic stage of the electronic circuit based upon the power gating operation mode. Maintaining comprises, in the described embodiment, storing data of a state of a first logic stage of the electronic circuit within a first storage element in a first power gating operation mode, and recovering data of a state of a second logic stage of the electronic circuit utilizing the data of the state of the first logic stage of the electronic circuit within the first storage element in a second power gating operation mode. | 2013-06-20 |
20130154708 | CONFIGURABLE FLIP-FLOP - A configurable flip-flop can be operated in a normal mode and a buffer mode. In the normal mode, the flip-flop latches data at the flip-flop input based on a clock signal. In the buffer mode, the flip-flop provides data at the flip-flop input to the flip-flop output, independent of the clock signal. | 2013-06-20 |
20130154709 | SYSTEMS AND METHODS FOR OUTPUT CONTROL - The present disclosure provides an output control circuit including a signal feedback circuit and an enable control circuit, wherein the signal feedback circuit is configured to compare an output voltage with a set output voltage threshold and to output a disable signal to an enable control circuit when the output voltage arrives at the set output voltage threshold, and wherein the enable control circuit is configured to stop an operation of a translation circuit, upon reception of the disable signal from the signal feedback circuit. | 2013-06-20 |
20130154710 | ADAPTIVE CASCODE CIRCUIT USING MOS TRANSISTORS - The present invention relates to a cascode circuit using MOS transistors. In one embodiment, an adaptive cascode circuit can include: (i) a main MOS transistor; (ii) n adaptive MOS transistors coupled in series to the drain of the main MOS transistor, where n can be an integer greater than one; (iii) a shutdown clamping circuit connected to the gates of the n adaptive MOS transistors, where the shutdown clamping circuit may have (n+1) shutdown clamping voltages no larger than rated gate-drain voltages of the main MOS transistor and n adaptive MOS transistors; and (iv) n conduction clamping circuits coupled correspondingly to the gates of the adaptive MOS transistors, where the n conduction clamping circuits may have n conduction clamping voltages no larger than the conduction threshold voltages of the adaptive MOS transistors. | 2013-06-20 |
20130154711 | METHOD, POWER UNIT, AND POWER SYSTEM HAVING GATE VOLTAGE LIMITING CIRCUIT - A power unit (e.g., inverter module) includes a housing and a switch attached to the housing. The switch may be configured to be electrically coupled to a remotely-mounted drive circuit through two or more wire leads. The power unit also includes a clamping circuit electrically coupled to terminals of the switch and in parallel with the switch. The clamping circuit may be disposed inside the housing or on an outer surface of the housing, and is configured to limit a voltage across the switch. | 2013-06-20 |
20130154712 | Multiplexer with Level Shifter - A level shifting multiplexer is disclosed. In one embodiment, a multiplexer is coupled to receive a first input signal from circuitry in a first power domain and a second input signal from circuitry in a second power domain. The multiplexer is configured to output a selected one of the first and second input signals to circuitry in the second power domain. The multiplexer also includes a level shifter circuit. When the first input signal is selected, the level shifter circuit may be enabled. When enabled, the level shifter circuit may level shift the first signal such that its voltage swing corresponds to that of the second voltage domain. The multiplexer may also include isolation circuitry configured to inhibit the level shifter. | 2013-06-20 |
20130154713 | VOLTAGE LEVEL SHIFTER - A level shifter includes a latch supplied at a first voltage, and first and second series connections of first and second switch elements and first and second biased elements in series with first and second branches of the latch respectively. Third and fourth switch elements are connected in parallel with the first and second series connections respectively. The input signal, at a voltage different from the first voltage, activates the third or fourth switch element during a transition period after a change of state of the input signal one way or the other to change the state of the latch, and deactivates the third or fourth switch element and activates the first or second switch element to maintain the state of the latch during a stabilization period following the transition period. The transition periods are shortened, reducing current consumption and transfer delay times. | 2013-06-20 |
20130154714 | CURRENT-MODE SAMPLE AND HOLD FOR DEAD TIME CONTROL OF SWITCHED MODE REGULATORS - A system for current mode sample and hold, comprising a first PMOS transistor configured to generate a current to be sampled. A diode-connected NMOS transistor coupled to the first PMOS transistor and configured to receive the current. A switch coupled to the diode-connected NMOS transistor and configured to sample a gate-source voltage of the diode-connected NMOS transistor. A capacitor coupled to the switch and configured to stored the gate-source voltage of the diode-connected NMOS transistor. A second NMOS transistor coupled to the capacitor and configured to generate a current equal to the sampled current value. | 2013-06-20 |
20130154715 | Bootstrapped Switch with a Highly Linearized Resistance - Systems and methods are disclosed for operating a highly linearized resistance for a switch through use of a bootstrapped features. In one exemplary implementation, there is provided a method and system that implements a method for operating a circuit configured to provide a highly linearized resistance including receiving a signal via a bootstrapped switch, coupling the received signal to a gate if the received signal is high, receiving a signal via a switch control input coupled to a high impedance element. Moreover, the method includes coupling the high impedance element to the gate and turning off the switch via a gate turn off when the gate turn off pulls the gate low. | 2013-06-20 |
20130154716 | Circuit Topology for a Phase Connection of an Inverter - A circuit for a phase connection of an inverter includes upper and lower bridge halves and respectively associated upper and lower bridge segments. Each bridge half has an outer switch and an inner switch connected in series. Each bridge segment has a diode and the inner switch of the associated bridge half connected in series. An output of the circuit is respectively connected to upper and lower potentials through the outer switches and is further connected to a center potential applied between the upper and lower potentials through each of the upper and lower bridge segments. Each bridge half further has a parallel power switch. The parallel switch of each bridge half is connected in parallel to the series-connected outer and inner switches of the bridge half. The output of the circuit is further respectively connected to the upper and lower potentials through the parallel switches. | 2013-06-20 |
20130154717 | SWITCHING CIRCUITS AND METHODS OF TESTING - A switching circuit for connection to a load and to a voltage source is provided. The switching circuit comprises: at least one switching devices for switching on and off power to the load a pulldown device for shorting out the load thereby isolating the load from the voltage source; and a controller operable while the load is shorted to activate at least one of the switching devices at a time, wherein a current passes through the or each activated switching device and is measurable to test whether the or each activated switching device is operating correctly. | 2013-06-20 |
20130154718 | Fully Capacitive Coupled Input Choppers - A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed. | 2013-06-20 |
20130154719 | CONNECTION STRUCTURE BETWEEN SUBSTRATE AND FPCB FOR TOUCH PANEL - Disclosed herein is a connection structure between a substrate and a flexible printed circuit board (FPCB) for a touch panel, including: a substrate; first sensing electrodes; second sensing electrodes; first electrode wirings; second electrode wirings; and a flexible printed circuit board connected to the substrate so as to be electrically connected to the first and second electrode wirings, wherein a first connection portion of the first electrode wiring and a second connection portion of the second electrode wiring to which the flexible printed circuit board is electrically connected are formed on the upper and lower surfaces of the substrate, respectively, so as to face each other in a vertical direction. Therefore, the flexible printed circuit substrate may be connected to the substrate by a single assembling process. | 2013-06-20 |
20130154720 | CONSTANT VGS SWITCH - This document discusses, among other things, a signal switch circuit including a first field effect transistor (FET) configured to couple a first node to a second node in an on-state and a charge pump circuit configured to provide a first supply voltage to control the FET, wherein a reference voltage of the charge pump circuit is coupled to a well of the FET to maintain a constant gate to source voltage of the FET during the on-state. | 2013-06-20 |
20130154721 | SWITCHED-CAPACITOR, CURVATURE-COMPENSATED BANDGAP VOLTAGE REFERENCE - In a novel aspect, producing a reference bandgap voltage includes generating a proportional to absolute temperature (PTAT) voltage difference based on respective voltages across a first pair of diodes. The PTAT voltage difference is sampled and scaled using a switched-capacitor amplifier. The switched-capacitor amplifier also is used to sample and scale a difference in voltages across a second pair of diodes, one of which is biased with a PTAT current and the other of which is biased with a current that exhibits little or no linear temperature dependency. The scaled voltage differences are combined with a voltage corresponding to a voltage across the diode that is biased with the PTAT current so as to at least partially compensate for linear and non-linear temperature-dependent components of the voltage across the diode. | 2013-06-20 |
20130154722 | VOLTAGE-STABILIZING CIRCUIT - A voltage-stabilizing circuit includes a comparator and an RC circuit. A positive input of the comparator receives an enable signal. A negative input of the comparator receives a reference voltage. The RC circuit includes a first resistor and a capacitor. A first terminal of the capacitor is connected to an output of the comparator, a second terminal of the capacitor is grounded through a first resistor, and the first terminal of the capacitor is further connected to an enable pin of a power integrated circuit. | 2013-06-20 |
20130154723 | PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD - The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. | 2013-06-20 |
20130154724 | INTERLEAVED NOISE REDUCTION CIRCUIT AND METHOD - In accordance with an embodiment, a noise reduction circuit includes one or more phase sampling circuits that receive an electromagnetic signal and splits the signal into an illuminated component and an ambient component. The illuminated component is transmitted along an illuminated signal path and converted to a digital signal and the ambient component is transmitted along an ambient signal path and converted to a digital signal. The digitized ambient component is subtracted from the digitized illuminated component to generate a light signal with a reduced noise component. | 2013-06-20 |
20130154725 | CHARGE DOMAIN FILTER AND METHOD THEREOF - A charge domain filter (CDF) and a method thereof are provided. The CDF includes an amplifier, a first switch-capacitor network (SCN), a second SCN, a third SCN and a fourth SCN. Input terminals of the first and the second SCNs are coupled to first and second output terminals of the amplifier, respectively. Input and output terminals of the third SCN are coupled to output terminals of the first and the second SCNs, respectively. Input and output terminals of the fourth SCN are coupled to output terminals of the second and the first SCNs, respectively. A mode control terminal of the third SCN receives a first mode signal to set an impulse response mode of the third SCN. A mode control terminal of the fourth SCN receives a second mode signal to set an impulse response mode of the fourth SCN. | 2013-06-20 |
20130154726 | SECOND ORDER ACTIVE HIGH-PASS FILTER WITH CROSS-COUPLED FEEDBACK FOR Q ENHANCEMENT - An apparatus comprising an input circuit, a cross coupled active circuit and an output circuit. The input circuit may be configured to generate a first portion of an intermediate signal in response to an input signal. The cross coupled active circuit may be configured to generate a second portion of the intermediate signal in response to a feedback of an output signal. The output circuit may be configured to generate the output signal in response to the intermediate signal. The output signal may pass frequencies above a target frequency. | 2013-06-20 |
20130154727 | DISTRIBUTED RESONANT CLOCK GRID SYNTHESIS - A method of implementing a VLSI clock network is implemented. That method includes a step of generating an initial VLSI clock grid for incorporation on a silicon die. An input grid buffer is then sized and implemented for the VLSI clock grid. LC tanks are then placed and sized in the VLSI clock grid to implement a resonant tank clock grid and the input grid buffer is resized. A check of the resonant tank design criteria is then made. If the design criteria are met the resonant VLSI clock grid with its LC tanks is implemented. If not, another attempt at implementing a suitable LC tanks placement and sizing is made. The process iterates until a VLSI clock grid that meets the design criteria is obtained. | 2013-06-20 |
20130154728 | Adaptive Filtering of Blocker Signals in Demodulators - Some embodiments of the invention relate a transimpedance amplifier circuit having a negative feedback network that provides additional filtering of an out-of-band transmitted signal is provided herein. In one embodiment, the transimpedance amplifier circuit has a first pole, transimpedance amplifier having a multi-stage operational amplifier with an input terminal and an output terminal. An RC feedback network extends from the output terminal to the input terminal. A negative feedback network, extending from an internal node of the multi-stage operational amplifier to an input terminal of the single pole, transimpedance amplifier provides a negative feedback signal with an amplitude having an opposite polarity as the out-of-band transmitted signal. The negative feedback signal suppresses the out-of-band-transmitted signals within the demodulator circuit, thereby improving linearity of the transimpedance amplifier circuit. | 2013-06-20 |
20130154729 | DYNAMIC LOADLINE POWER AMPLIFIER WITH BASEBAND LINEARIZATION - Radio frequency (RF) amplification devices and methods of amplifying RF signals are disclosed. In one embodiment, an RF amplification device includes a control circuit and a Doherty amplifier configured to amplify an RF signal. The Doherty amplifier includes a main RF amplification circuit and a peaking RF amplification circuit. The control circuit is configured to activate the peaking RF amplification circuit in response to the RF signal reaching a threshold level. In this manner, the activation of the peaking RF amplification circuit can be precisely controlled. | 2013-06-20 |
20130154730 | USING A NEW SYNCHRONIZATION SCHEME FOR A MULTI-CHANNEL CLASS-D AMPLIFIER - Various embodiments are described herein for a multi-channel class-D amplifier and an associated processing method. In general, the multi-channel class-D amplifier comprises a signal source that provides a plurality of input signals and generates synchronization information; and a plurality of class-D amplifier channel modules, each class-D amplifier channel module being configured to process a corresponding input signal from the plurality of input signals according to the synchronization information to produce an output signal. The switching frequencies employed by the plurality of class-D amplifier channel modules are substantially similar to one another and the processing of the plurality of input signals is offset in time across the plurality of class-D amplifier channel modules. | 2013-06-20 |
20130154731 | N WAY DOHERTY AMPLIFIER - A device including a Doherty amplifier, the Doherty amplifier having an amplifier input and output. At least one main amplifier is coupled to the input via a main input impedance and to the output via a main output impedance and additional amplifiers, each amplifier being coupled to the input via respective additional input impedances. Each additional amplifier has a respective additional amplifier output coupled to a respective pair of additional impedances connected in series and having a respective connection node between them. The device also has a first additional amplifier having their respective additional impedances coupled between its respective output and the amplifier output, the pair of additional impedances having first and second impedances, the first impedance being connected to the respective additional amplifier output and to the connection node, the second impedance being coupled between their respective connection node and the connection node of the previous additional amplifier. | 2013-06-20 |
20130154732 | POWER MANAGEMENT IN TRANSCEIVERS - Various embodiments are directed to apparatuses and methods to reduce average power dissipation in transceiver stages such as power amplifiers and low noise amplifiers (LNAs) that process signals of varying output amplitudes. Power dissipation may be reduced by varying the supply voltage in sympathy with the amplitude of the signal and/or the stage current density which may also be varied in sympathy with the signal amplitude. | 2013-06-20 |
20130154733 | METHOD FOR SYNTHESIZING SIGMA-DELTA MODULATOR - A method for synthesizing Sigma-Delta Modulator, which selects at least a system configuration and parameters, substitute a noise transfer formula into said system configuration to obtain coefficients. Using a least-square method to obtain a stability equation, and calculating an ideal performance of said system configuration based on said parameters and stability equation. Substitute the coefficients into non-ideal effect models, and acquire the circuit specification of an operation amplifier in said system configuration in a hierarchic approach to calculate the circuit performance of the operation amplifier. Determine whether said circuit specification of said operation amplifier has a solution based on related specification equation. If an answer is positive, calibrate length and width of transistors in said operation amplifier, until it meets the requirements of said circuit specification. Base on the said transistors to implement Sigma Delta Modulator, the target performance can be achieved from the circuit simulation result. | 2013-06-20 |
20130154734 | Orthogonal Basis Function Set for Digital Predistorter - A predistorter applies a distortion function to an input signal to predistort the input signal. The output of the distortion function is modeled as the sum of the output signals from the orthogonal basis functions weighted by corresponding weighting coefficients. Techniques are described for orthogonalizing the basis function output signals depending on the distribution of the input signal. | 2013-06-20 |
20130154735 | RF POWER AMPLIFIER AND OPERATING METHOD THEREOF - The present invention reduces the size of a power detection circuit. An RF power amplifier includes an RF amplifier circuit and a power detection circuit. The RF amplifier circuit subjects an RF input signal having a predetermined frequency band to power amplification and generates an RF amplifier output signal. The input terminal of the power detection circuit is coupled to the output of the RF amplifier circuit. The power detection circuit detects a harmonic component having a harmonic frequency that is a whole number multiple of the frequency of a fundamental wave component of the RF amplifier output signal, and generates at an output terminal a detected signal indicative of the signal level of the fundamental wave component of the RF amplifier output signal. The power detection circuit includes an input circuit, which detects the harmonic component, and an output circuit, which generates the detected signal at the output. | 2013-06-20 |
20130154736 | Transient Signal Suppression for a Class-D Audio Amplifier Arrangement - A Class-D amplifier arrangement is disclosed that implements an auxiliary feedback loop and a primary feedback loop. The auxiliary feedback loop operates upon an input signal when the Class-D amplifier arrangement is operating under a power-up condition and a power-down condition so that a modulated signal is confined within the auxiliary feedback loop during the power-up condition and the power-down condition. The confinement of the modulated signal within the auxiliary feedback loop during the power-up condition and the power-down condition diverts transient signals coupled onto the modulated signal from an output device. The primary feedback loop operates upon the input signal when the Class-D amplifier arrangement is operating under a normal condition so that the modulated signal is introduced to the output device during the normal condition. | 2013-06-20 |
20130154737 | COMPARATOR AND AMPLIFIER - A comparator has a differential pair circuit, a current control circuit, and a latch. The differential pair circuit has first and second comparator transistors, and is arranged to compare a first input and a second input according to a clock signal to generate a result indicating whether a difference of the first and second inputs exceeds an internal offset. The current control circuit is coupled in series with the differential pair circuit, and configured to provide unequal abilities of drawing currents for the first and second comparator transistors. | 2013-06-20 |
20130154738 | AMPLIFIER AND FILTER HAVING VARIABLE GAIN AND CUTOFF FREQUENCY CONTROLLED LOGARITHMICALLY ACCORDING TO DIGITAL CODE - A variable gain amplifier circuit is provided. The circuit includes an operational amplifier for amplifying and outputting an input signal according to a cutoff frequency and a gain, a feedback resistor for changing a first resistance according to a first digital control code value which determines the cutoff frequency, and an input resistor for changing a second resistance according to a second digital control code value which is determined based on a difference of the first digital control code value and a gain code value. The gain is determined by a ratio of the first resistance and the second resistance and linearly changes on a decibel (dB) basis according to the first digital control code value, the cutoff frequency is inversely proportional to the first resistance and linearly changes on a log scale, and the variable gain can be easily set using the control code. | 2013-06-20 |
20130154739 | ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR - Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. | 2013-06-20 |
20130154740 | TECHNIQUES FOR PGA LINEARITY - Techniques for designing a highly linear programmable gain amplifier (PGA). In an aspect, the PGA includes a plurality of feedback switches selectively coupling an output of an operational amplifier (op amp) to an input of the op amp via a corresponding series-coupled feedback resistance. The PGA may further include a plurality of input switches selectively coupling an input of the op amp to a PGA input voltage via a corresponding series-coupled input resistance. The switches are designed such that the ratio of on-resistances between any two switches is substantially equal to the ratio of the corresponding series-coupled resistances. In an exemplary embodiment, transistors implementing the switches may be accordingly sized to implement the desired on-resistance ratios. | 2013-06-20 |
20130154741 | APPARATUS AND CIRCUIT FOR AMPLIFYING BASEBAND SIGNAL - An operational amplifier circuit is provided. The operational amplifier circuit includes a differential amplifier of a cascade structure and a switched-capacitor type Common-Mode FeedBack (CMFB) circuit. The differential amplifier amplifies a difference between two input signals to output an anode output voltage and a negative output voltage. The switched-capacitor type CMFB circuit averages the anode output voltage and the negative output voltage of the differential amplifier, compares the average voltage with a reference voltage to generate a feedback signal based on a result of the comparison, and provides the feedback signal to the differential amplifier. Therefore, power consumption is reduced and a battery use time of a wireless terminal can be extended. Also, since an operational amplifier gain of each analog filter terminal is not negatively affected, a Direct Current (DC) offset is reduced, thereby improving signal quality. | 2013-06-20 |
20130154742 | Low Noise Amplifier for Multiple Channels - An amplifier system has an amplifier for amplifying a plurality of input signals from a plurality of different channels, and a plurality of demodulators each operatively coupled with the amplifier for receiving amplified input signals from the amplifier. Each demodulator is configured to demodulate a single amplified input channel signal from a single channel of the plurality of different channels. The system thus also has a plurality of filters, coupled with each of the demodulators, for mitigating the noise. | 2013-06-20 |
20130154743 | CLASS AB AMPLIFIERS - An amplifier includes a first switch and a second switch each having a first terminal and a second terminal. The first terminals of the first and second switches respectively communicate with a first tank circuit and a second tank circuit. The second terminal of the second switch communicates with the second terminal of the first switch. A first capacitance having a first terminal connected directly to (i) the second terminal of the first switch and (ii) the second terminal of the second switch. A second terminal of the first capacitance is connected directly to a first input voltage of the amplifier. A first load is connected across (i) the first terminal of the first switch and (ii) the first terminal of the second switch. The amplifier generates a first output across the first load. | 2013-06-20 |
20130154744 | Non-Linear Capacitance Compensation - Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages. | 2013-06-20 |
20130154745 | CLIPPING CIRCUIT, DIFFERENTIAL AMPLIFYING CIRCUIT, AND AMPLIFYING CIRCUIT - There is provided a clipping circuit in which a first input terminal receives a first signal, a second input terminal receives a second signal, a first variable resistive element has a control terminal electrically connected to the second input terminal and has a threshold, first and second ends of the first variable resistive element are connected to first input terminal and a reference voltage, respectively, the second variable resistive element has a control terminal electrically connected to the first input terminal and has a threshold, first and second ends thereof are connected to a second input terminal and the reference voltage, respectively, a first bias applying unit applies a bias voltage lower than the threshold to the control terminal regarding the first variable resistive element, and a second bias applying unit applies a bias voltage lower than the threshold to the control terminal regarding the second variable resistive element. | 2013-06-20 |
20130154746 | VARIABLE GAIN AMPLIFIER CIRCUIT - A variable gain amplifier circuit ( | 2013-06-20 |
20130154747 | MILLIMETER WAVE POWER AMPLIFIER - A millimeter wave power amplifier is disclosed. In an exemplary embodiment, a MM wave power amplifier (PA) includes a plurality of amplifier stages coupled together to receive a MM wave input signal and produce an amplified MM wave output signal, and one or more feedback elements coupled across the amplifier stages, each feedback element coupled across an odd number of the amplifier stages to increase an operating bandwidth of the PA. | 2013-06-20 |
20130154748 | Apparatus and Method for Thermal Interfacing - An apparatus ( | 2013-06-20 |
20130154749 | OSCILLATOR FOR GENERATING OUTPUT SIGNAL WITH ADJUSTABLE FREQUENCY - An oscillator is provided and includes a resistance unit, a capacitance unit, a first inverter and a second inverter. The resistance unit is serially connected between a first reference point and a second reference point. The capacitance unit is coupled between the first reference point and an output point, and includes capacitors. One terminal of each of the capacitors is coupled to the output point, and the other terminal of each of the capacitors is coupled to the first reference point or a reference ground according to a control signal. The input terminal of the first inverter is coupled to the first reference point, and the output terminal of the first inverter is coupled to the second reference point. The input terminal of the second inverter is coupled to the output terminal of the first inverter, and the output terminal of the second inverter is coupled to the output point. | 2013-06-20 |
20130154750 | OSCILLATOR REGENERATION DEVICE - A negative resistance device for a multiphase oscillator is disclosed. The negative resistance device is coupled to taps of the multiphase oscillator so that it injects no energy into the oscillator when the oscillator is most sensitive to noise, thereby decreasing the phase noise of the oscillator. The negative resistance device also guarantees the direction of movement of a traveling wave past the taps of the multiphase oscillator. | 2013-06-20 |
20130154751 | VOLTAGE CONTROLLED OSCILLATOR - A voltage controlled oscillator includes a split ring resonator (SRR) configured to have meta-material characteristics fabricated on a board, and an energy compensation circuit configured to cause resonant oscillation of the SRR. The energy compensation circuit is fabricated in the form of an integrated circuit. | 2013-06-20 |
20130154752 | VOLTAGE-CONTROLLED OSCILLATOR - A voltage-controlled oscillator circuit includes a first transistor, a second transistor, a first resonator circuit, a second resonator circuit, a first current path and a second current path. A drain of the first transistor is coupled to a gate of the second transistor and to a first end of the first resonator circuit. A source of the first transistor is coupled to the first current path and to a first end of the second resonator circuit. A drain of the second transistor is coupled to a gate of the first transistor and to a second end of the first resonator circuit. A source of the second transistor is coupled to the second current path and a second end of the second resonator circuit. | 2013-06-20 |
20130154753 | Oscillation circuit and oscillation system - An oscillation circuit includes a threshold voltage extraction module, a positive temperature coefficient voltage generation module, an addition module, a common-source amplifier module, a charge and discharge module, and a clock output terminal. The common-source amplifier module includes a first field effect transistor (FET) and a second FET. The addition module includes a first operational amplifier, a second operational amplifier, a third FET, a fourth FET, a fifth FET, a sixth FET, a first resistor, a second resistor, and a third resistor. The charge and discharge module includes a seventh FET, an eighth FET, a charge and discharge FET, a first switch, a second switch, a first comparator, a second comparator, a first nor gate and a second nor gate. An oscillation system is further provided. The oscillation circuit and the oscillation system of the present invention have simple structures and are easy to implement. | 2013-06-20 |
20130154754 | TUNING OF MEMS OSCILLATOR - A method is provided for tuning a microelectromechanical systems (MEMS) oscillator comprising an acoustic resonator and a tuning and amplification circuit arranged in a loop. The method comprises determining an initial oscillation frequency of the oscillator, modifying a capacitance of the tuning and amplification circuit according to the initial oscillation frequency, and adjusting a power level of the oscillator according to the modified capacitance. | 2013-06-20 |
20130154755 | METHOD AND APPARATUS FOR IMPROVED HIGH ORDER MODULATION - Methods, systems and software are provided for high order signal modulation based on improved signal constellation and bit labeling designs for enhanced performance characteristics, including decreased power consumption. According to the improved signal constellation and bit labeling designs for enhanced performance characteristics, designs for 8-ary, 16-ary, 32-ary and 64-ary signal constellations are provided. According to an 8-ary constellation, improved bit labeling and bit coordinates are provided for a 1+7APSK signal constellation. According to a 16-ary constellation, improved bit labeling and bit coordinates are provided for a 6+10APSK signal constellation. According to three 32-ary constellations, improved bit labeling and bit coordinates are provided for a 16+16APSK signal constellation and two 4+12+16APSK signal constellations. According to two 64-ary constellations, improved bit labeling and bit coordinates are provided for an 8+16+20+20APSK signal constellation and a 12+16+16+20APSK signal constellation. | 2013-06-20 |
20130154756 | METHOD FOR THE PHASE MODULATION OF A CARRIER SIGNAL TRANSMITTED FROM A TRANSMITTER TO A CONTACTLESS TRANSPONDER, AND DEVICE FOR IMPLEMENTING SAME - A method for phase modulation of a carrier signal from a transmitter to a contactless transponder in which data is coded as consecutive symbols, each corresponding to a predefined number of carrier cycles, and in which a symbol time is at least two cycles of the carrier signal includes, at the transmitter, spreading a phase jump of a symbol in relation to a preceding symbol over a first part of the symbol time. The establishment of the phase jump is completed in the first part of the symbol time. The periods of the cycles are constant during a second part of the symbol time. | 2013-06-20 |
20130154757 | COMPOSITE ELECTRONIC MODULE - In a composite electronic module, electronic components including magnetic substances are mounted on a substrate such that lines of magnetic force generated by a permanent magnet of a non-reciprocal circuit element are concentrated to the non-reciprocal circuit element side. Therefore, even when a metal yoke is omitted, for example, it is possible to reduce the number of lines of magnetic force generated by the permanent magnet and which leak to the outside of the substrate, and hence to significantly reduce and prevent the influence of a magnetic field generated by the permanent magnet upon other electronic components that are arranged near or adjacent to the composite electronic module around the substrate. | 2013-06-20 |
20130154758 | BALUN WITH INTERMEDIATE NON-TERMINATED CONDUCTOR - A balun comprising first and second transmission lines having a shared intermediate conductor. The first transmission line may include first and second conductors. The first conductor may have a first end for conducting an unbalanced signal relative to a circuit ground and a second end for conducting a balanced signal. The second conductor may have first and second ends proximate the respective first and second ends of the first conductor. The first and second ends of the second conductor may be open-circuited. The second transmission line may include the second conductor and a third conductor having a first end connected to circuit ground and a second end for conducting the balanced signal. The second conductor may surround the first and third conductors, and one or more ferrite sleeves may surround the second conductor. | 2013-06-20 |
20130154759 | WAVEGUIDE, INTERPOSER SUBSTRATE INCLUDING THE SAME, MODULE, AND ELECTRONIC APPARATUS - A waveguide includes: a waveguide portion including a first surface and a second surface that are opposed to each other; a first transmission line provided on the first surface of the waveguide portion; a second transmission line provided on the second surface of the waveguide portion; and a first conversion structure inputting a signal from the first transmission line to the waveguide portion and converting the signal. | 2013-06-20 |
20130154760 | BONDING WIRE IMPEDANCE MATCHING CIRCUIT - An impedance matching circuit is provided. The present impedance matching circuit is able to match impedance using a transformer which is arranged inside a dielectric substrate and arranged to overlap with a bonding pad area and an end of a transmission line, thereby enabling transmitting signals at a desired frequency with a minimum insertion loss without using a very thin transmission line which is several to dozens of μm wide or specially designed antennas in order to compensate for inductance. Thus, the present impedance matching circuit may be applied to various millimeter bands. | 2013-06-20 |
20130154761 | System and Method for a Radio Frequency Switch - In accordance with an embodiment, a filter network is configured to be coupled to a first switch, a second switch, and an output port. The filter network includes a first filter coupled between the first switch and the output port, and the second filter coupled between the second switch and the output port. The first filter has a pass band having a first frequency range that includes a first frequency, and a stop band that includes a second frequency that is a distortion product of the first frequency. The second filter has a second frequency range that includes the second frequency and the stop band that includes the first frequency. The second frequency range is higher in frequency than the first frequency range. | 2013-06-20 |
20130154762 | MEMS Switches in an Integrated Circuit Package - Methods and systems for MEMS switches fabricated in an integrated circuit package are disclosed and may include controlling switching of RF components, and signals handled by the RF components, within an integrated circuit. One or more MEMS switch arrays embedded within a multi-layer package bonded to the integrated circuit may be utilized for the switching and signal control. The RF components and one or more MEMS switch arrays may be integrated in the multi-layer package. The RF components may be electrically coupled to the integrated circuit via the one or more MEMS switch arrays. The MEMS switch arrays may be electrostatically or magnetically activated. The RF components may be coupled to one or more capacitor arrays in the integrated circuit. The RF components may include transformers, inductors, transmission lines, microstrip and/or coplanar waveguide filters and/or surface mount devices. The integrated circuit may be coupled to the multiple-layer package utilizing a flip-chip bonding technique. | 2013-06-20 |
20130154763 | ELASTIC WAVE BRANCHING FILTER - An elastic wave surface acoustic wave duplexer includes an antenna terminal, a transmission filter, a reception filter, and a plurality of elastic wave resonators connected in series between the antenna terminal and the reception filter. The reception filter is a longitudinally coupled resonator-type surface acoustic wave filter including a plurality of IDT electrodes and arranged along a propagation direction of elastic wave. A combined capacitance of the plurality of surface acoustic wave resonators is smaller than a capacitance of the IDT electrodes and included in the plurality of IDT electrodes and connected to the antenna terminal. | 2013-06-20 |
20130154764 | IN-PHASE H-PLANE WAVEGUIDE T-JUNCTION WITH E-PLANE SEPTUM - In an example embodiment, an in-phase H-plane T-junction can comprise: a first waveguide port; a second waveguide port; a third waveguide port, wherein the third waveguide port can be a common port; and an E-plane septum. The first, second, and third waveguide ports can be in the H-plane and can be each connected to each other in a T configuration. The T-junction can be configured such that microwave signals in a first band can be in-phase with each other at the first and second waveguide ports, and microwave signals in a second band can be in-phase with each other at the first and second waveguide ports. The H-plane T-junction can be at least one of a power combiner and a power divider. | 2013-06-20 |