25th week of 2013 patent applcation highlights part 18 |
Patent application number | Title | Published |
20130153964 | FETs with Hybrid Channel Materials - Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET. | 2013-06-20 |
20130153965 | STRAINED TRANSISTOR INTEGRATION FOR CMOS - Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area. | 2013-06-20 |
20130153966 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer made of an Al | 2013-06-20 |
20130153967 | Compound Semiconductor Device with Buried Field Plate - A semiconductor device includes a first compound semiconductor material and a second compound semiconductor material on the first compound semiconductor material. The second compound semiconductor material comprises a different material than the first compound semiconductor material such that the first compound semiconductor material has a two-dimensional electron gas (2DEG). The semiconductor device further includes a buried field plate disposed in the first compound semiconductor material and electrically connected to a terminal of the semiconductor device. The 2DEG is interposed between the buried field plate and the second compound semiconductor material. | 2013-06-20 |
20130153968 | Semiconductor Device - A semiconductor device and a method of making the same. The device includes a semiconductor substrate having an AlGaN layer on a GaN layer. The device also includes first contact and a second contact. The average thickness of the AlGaN layer varies between the first contact and the second contact, for modulating the density of an electron gas in the GaN layer between the first contact and the second contact. | 2013-06-20 |
20130153969 | STRUCTURE FOR MOSFET SENSOR - A structure for a metal-oxide-semiconductor field-effect transistor (MOSFET) sensor is provided. The structure includes a MOSFET, a sensing membrane, and a reference electrode. The reference electrode and the sensing membrane are formed on the first surface of the MOSFET and are arranged in such a way that the reference electrode and the sensing membrane are uniformly and electrically coupled to each other. Thus, the electric field between the sensing membrane and the reference electrode is uniformly distributed therebetween to stabilize the working signal of the MOSFET sensor. | 2013-06-20 |
20130153970 | TRANSISTOR STRUCTURE, METHOD FOR MANUFACTURING A TRANSISTOR STRUCTURE, FORCE-MEASURING SYSTEM - A transistor structure includes a first terminal region, a second terminal region and a channel region therebetween in a semiconductor substrate. Additionally, the transistor structure includes a control electrode associated with the channel region, the control electrode having a control electrode portion which is elastically deflectable under the action of a force and spaced apart from the channel region. The distance between the control electrode portion and the channel region is changed based on the action of force. | 2013-06-20 |
20130153971 | V-GROOVE SOURCE/DRAIN MOSFET AND PROCESS FOR FABRICATING SAME - A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed. | 2013-06-20 |
20130153972 | V-Groove Source/Drain Mosfet and Process For Fabricating Same - A structure includes a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate and a silicided source/drain region formed in a V-shaped groove between the first and second adjacent gate structures. The silicided source/drain region formed in the V-shaped groove extend substantially from an edge of the first gate structure to an opposing edge of the second gate structure. | 2013-06-20 |
20130153973 | IMAGE SENSOR PIXELS WITH JUNCTION GATE PHOTODIODES - Image sensor pixels are provided having junction gate photodiodes. A group of pixels may have a shared floating diffusion region and a shared source-follower transistor. The source-follower transistor may be a JFET source-follower with a gate that forms the floating diffusion region. The JFET source-follower may be a vertical or lateral JFET. A reset diode may be forward-biased to reset the floating diffusion region. Each pixel may have a JFET that serves as a charge transfer barrier between the junction gate photodiode and the floating diffusion region. The charge transfer barrier JFET may be a lateral JFET. The image sensor pixels may be formed without any metal-oxide-semiconductor devices. | 2013-06-20 |
20130153974 | TWO-STEP SILICIDE FORMATION - One embodiment of the present invention comprises a transistor having a source/drain region within a substrate, an extension region within the substrate adjoining the source/drain region and extending toward a gate on the substrate, and a dielectric spacer against the gate wherein the dielectric spacer covers at least part of the extension region. A silicide intermix layer is formed over both the source/drain region and a portion of the extension region. A silicide contact is formed through the silicide intermix layer over the source/drain region. | 2013-06-20 |
20130153975 | Device Having a Plurality of Photosensitive Microcells Arranged in Row or Matrix Form - The invention provides a Silicon Photomultiplier (SiPM). The SiPM includes a plurality of microcells, a nonlinear element integrated in each one of the plurality of microcells, and a trigger line for outputting a summated current of the plurality of microcells, wherein the nonlinear element provides for a separated timing and energy signal. | 2013-06-20 |
20130153976 | SOLID-STATE IMAGING APPARATUS, METHOD OF MANUFACTURING SOLID-STATE IMAGING APPARATUS AND ELECTRONIC DEVICE - Provided is a solid-state imaging apparatus including: a plurality of photoelectric conversion units; an element isolation unit that performs element isolation between the plurality of photoelectric conversion units; and a diffusion prevention unit that prevents diffusion of a dark current component generated on an interfacial surface of the element isolation unit to a region surrounding the dark current component generation region. | 2013-06-20 |
20130153977 | PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device according to one or more embodiments includes a plurality of photoelectric conversion units. A readout portion is configured to output current signals to an output line. Each of the current signals is based on an amount of charges generated by a corresponding one of the photoelectric conversion units. The readout portion includes a plurality of transistors including at least a plurality of first input transistors and a plurality of second input transistors. Each of the first input transistors and a corresponding one of the second input transistor form a differential pair. Of the plurality of the transistors, any transistors repeatedly arranged correspondingly to every one or more of the photoelectric conversion units have the same conductivity type. | 2013-06-20 |
20130153978 | 3D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer. | 2013-06-20 |
20130153979 | THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures. | 2013-06-20 |
20130153980 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device manufacturing method including forming a gate insulating film, a first silicon film, an inter-electrode insulating film, a second silicon film, and a processing insulating film on a semiconductor substrate; embedding an inter-gate insulating film between the gate electrodes of the memory cell transistors and the selector gate transistors; detaching the processing insulating film to expose an upper surface of the second silicon film, and processing the inter-gate insulating film so that an upper surface of the inter-gate insulating film is substantially at the same level as the upper surface of the second silicon film; exposing an upper portion of the second silicon film by etching the inter-gate insulating film between the gate electrodes of two adjacent ones of the selector gate transistors down to a first depth while leaving a contact region of a first width between the gate electrodes; performing silicidation of the upper portion of the second silicon film of each of the gate electrodes; and forming an inter-layer insulating film after the silicidation. | 2013-06-20 |
20130153981 | NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A nonvolatile memory device, and method of forming the same, discloses a semiconductor device including floating gates that each have a first region that overlaps with a corresponding junction and that each have a second region that does not overlap the corresponding junction. The first region and the second region have different work functions. | 2013-06-20 |
20130153982 | SEMICONDUCTOR DEVICE CAPABLE OF REDUCING INFLUENCES OF ADJACENT WORD LINES OR ADJACENT TRANSISTORS AND FABRICATING METHOD THEREOF - A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO | 2013-06-20 |
20130153983 | 3-D NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE 3-D NONVOLATILE MEMORY DEVICE, AND METHOD OF MANUFACTURING THE 3-D NONVOLATILE MEMORY DEVICE - A three dimensional (3-D) nonvolatile memory device includes a first pipe gate layer, a second pipe gate disposed over the first pipe gate layer, word lines formed over the second pipe gate layer, memory channel layers configured to penetrate the word lines, a pipe channel layer formed in the first pipe gate layer, where the pipe channel layer is to come in contact with the bottom surface of the second pipe gate layer and couple the lower ends of the memory channel layers, a memory layer configured to surround the pipe channel layer and the memory channel layers, and a first gate insulating layer interposed between the first pipe gate layer and the memory layer. | 2013-06-20 |
20130153984 | Semiconductor Constructions, NAND Unit Cells, Methods of Forming Semiconductor Constructions, and Methods of Forming NAND Unit Cells - Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells. | 2013-06-20 |
20130153985 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al | 2013-06-20 |
20130153986 | HIGH-K DIELECTRICS WITH GOLD NANO-PARTICLES - A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor. | 2013-06-20 |
20130153987 | ELECTRONIC DEVICE COMPRISING A CONDUCTIVE STRUCTURE AND AN INSULATING LAYER WITHIN A TRENCH AND A PROCESS OF FORMING THE SAME - An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench. | 2013-06-20 |
20130153988 | ELECTRONIC DEVICE INCLUDING A TRENCH WITH A FACET AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME - An electronic device can include a transistor structure including a semiconductor layer overlying a substrate and a trench extending into the semiconductor layer having a tapered shape. In an embodiment, the tapered shape includes a facet. The transistor structure can include a source region and a drain region wherein different portions of the drain regions are disposed adjacent to the primary surface and within the trench. In another embodiment, different facets may be spaced apart from each other. Processes of forming the tapered etch can be tailored based on the needs or desires of a fabricator. | 2013-06-20 |
20130153989 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes. | 2013-06-20 |
20130153990 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device and a method for manufacturing the same, a pillar pattern is formed in an alternating pattern and a one side contact (OSC) is formed without using a tilted ion implantation process or a mask, resulting in formation of a vertical gate. The semiconductor device includes an alternating or zigzag-type pillar pattern formed over a semiconductor substrate, a first hole formed between pillars of the pillar pattern, a passivation layer formed over a sidewall of the first hole, a second hole formed by partially etching a lower part of the first hole, a bit line formed in the second hole, and a contact formed at a lower part of the pillar pattern. | 2013-06-20 |
20130153991 | ELECTRONIC DEVICE COMPRISING CONDUCTIVE STRUCTURES AND AN INSULATING LAYER BETWEEN THE CONDUCTIVE STRUCTURES AND WITHIN A TRENCH AND A PROCESS OF FORMING THE SAME - An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow R | 2013-06-20 |
20130153992 | ELECTRONIC DEVICE INCLUDING A TAPERED TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME - An electronic device can include a semiconductor layer, and a trench extending into the semiconductor layer and having a tapered shape. In an embodiment, the trench includes a wider portion and a narrower portion. The electronic device can include a doped semiconductor region that extends to a narrower portion of the trench and has a dopant concentration greater than a dopant concentration of the semiconductor layer. In another embodiment, the electronic device can include a conductive structure within a relatively narrower portion of the trench, and a conductive electrode within a relatively wider portion of the trench. In another embodiment, a process of forming the electronic device can include forming a sacrificial plug and may allow insulating layers of different thicknesses to be formed within the trench. | 2013-06-20 |
20130153993 | HYBRID CMOS NANOWIRE MESH DEVICE AND FINFET DEVICE - A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a FINFET device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the FINFET device on the same SOI substrate. | 2013-06-20 |
20130153994 | TRENCH TYPE POWER TRANSISTOR DEVICE WITH SUPER JUNCTION AND MANUFACTURING METHOD THEREOF - The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate. | 2013-06-20 |
20130153995 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first region with second conductivity type formed over a semiconductor layer with first conductivity type. On this first region, the second region of the first conductivity type is selectively provided. On the same first region, a third region of second conductivity type is also selectively provided and is adjoined to the second region. The first control electrode is provided within a trench located deeper than the first side of the second region compared to the first region. The first control electrode includes a part opposed to the first and second regions separated by a first insulator, and a second part opposed to the semiconductor layer separated by a thicker second insulator. Inside the trench, the second control electrode is provided between the trench bottom and the first control electrode. The second control electrode is opposed to the semiconductor layer through a third insulator. | 2013-06-20 |
20130153996 | HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE - A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate. | 2013-06-20 |
20130153997 | HYBRID CMOS NANOWIRE MESH DEVICE AND BULK CMOS DEVICE - A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a bulk CMOS device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the bulk CMOS device on the same SOI substrate. | 2013-06-20 |
20130153998 | DATA STORAGE DEVICE AND METHODS OF MANUFACTURING THE SAME - Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a plate conductive pattern covering the cell selection parts and electrically connected to first terminals of the cell selection parts, a plurality of through-pillars penetrating the plate conductive pattern and insulated from the plate conductive pattern, and a plurality of data storage parts directly connected to the plurality of through-pillars, respectively. The data storage parts may be electrically connected to second terminals of the cell selection parts, respectively. | 2013-06-20 |
20130153999 | TRENCH GATE MOSFET DEVICE - A trench gate MOSFET device has a drain region, a drift region, a trench gate having a gate electrode and a poly-silicon region, a super junction pillar juxtaposing the trench gate, a body region and a source region. By the interaction among the trench gate, the drift region and the super junction pillar, the break down voltage of the trench gate MOSFET device may be relatively high while the on-state resistance of the trench gate MOSFET device may be maintained relatively small. | 2013-06-20 |
20130154000 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate. | 2013-06-20 |
20130154001 | EMBEDDED STRESSORS FOR MULTIGATE TRANSISTOR DEVICES - Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region. | 2013-06-20 |
20130154002 | FinFETs with Multiple Threshold Voltages - A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function. | 2013-06-20 |
20130154003 | ASYMMETRIC ANTI-HALO FIELD EFFECT TRANSISTOR - A method of forming an integrated circuit structure implants a first compensating implant into a substrate. The method patterns a mask on the first compensating implant in the substrate. The mask includes an opening exposing a channel location of the substrate. The method implants a second compensating implant into the channel location of the substrate. The second compensating implant is made through the opening in the mask and at an angle that is offset from perpendicular to the top surface of the substrate. The second compensating implant is positioned closer to a first side of the channel location relative to an opposite second side of the channel location and the second compensating implant comprises a material having the same doping polarity as the semiconductor channel implant. Then, the method forms a gate conductor above the channel location of the substrate in the opening of the mask. | 2013-06-20 |
20130154004 | SEMICONDUCTOR DEVICE WITH BIASED FEATURE - A method of fabricating a semiconductor device includes forming a plurality of line element on a provided substrate. The plurality of line elements includes a first line element having a first region having a first width and a biased region having a second width. The second width different than the first width. Spacer elements are then formed abutting sidewalls of each of the plurality of line elements including the biased region where the spacer elements may be shifted. After forming the spacer elements, the plurality of line elements from the substrate are removed from the substrate. An underlying layer is etched using the spacer elements after removing the plurality of line elements. | 2013-06-20 |
20130154005 | SOI FINFET WITH RECESSED MERGED FINS AND LINER FOR ENHANCED STRESS COUPLING - FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SW substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance. | 2013-06-20 |
20130154006 | FINFET WITH VERTICAL SILICIDE STRUCTURE - FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls. | 2013-06-20 |
20130154007 | RARE-EARTH OXIDE ISOLATED SEMICONDUCTOR FIN - A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion. | 2013-06-20 |
20130154008 | ISOLATED EPITAXIAL MODULATION DEVICE - An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage. | 2013-06-20 |
20130154009 | SEMICONDUCTOR DEVICE - A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode. | 2013-06-20 |
20130154010 | Integrated Circuit Device, System, and Method of Fabrication - A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portion that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion. | 2013-06-20 |
20130154011 | Methods and Apparatus for Reduced Gate Resistance FinFET - Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed. | 2013-06-20 |
20130154012 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE - A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench. | 2013-06-20 |
20130154013 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided, which includes a circuit including a first MOS transistor having a gate connected to a first signal line, a second MOS transistor having a gate connected to a second signal line, and the circuit outputting an output signal according to a difference in potential between the first signal line and the second signal line, wherein channel regions of the first and second MOS transistors include no maximum impurity concentration at an area, which is shallower than a depth indicating a maximum concentration of one conduction type impurity that forms source and drain regions of the MOS transistors. | 2013-06-20 |
20130154014 | Semiconductor Device and Method for Fabricating the Same - A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes forming an shallow trench isolation (STI) in a substrate, sequentially forming an oxide layer and a nitride layer over the substrate, patterning the nitride layer and the oxide layer to expose a portion of the substrate adjacent to the STI layer, forming a field oxide layer contacting the STI layer in the exposed portion of the substrate, removing the nitride layer, etching a portion of the patterned oxide layer to form a first gate oxide layer contacting the field oxide layer, forming a second gate oxide layer over the substrate, and forming a gate pattern over the field oxide layer, the first gate oxide layer, and the second gate oxide layer. | 2013-06-20 |
20130154015 | THREE-DIMENSION CIRCUIT STRUCTURE AND SEMICONDUCTOR DEVICE - A three-dimension circuit structure includes a substrate, a first conductive layer, a filled material and a second conductive layer. The substrate has an upper surface and a cavity located at the upper surface. The first conductive layer covers the inside walls of the cavity and protrudes out the upper surface. The filled material fills the cavity and covers the first conductive layer. The second conductive layer covers the filled material and a portion of the first conductive layer, and the first conductive layer and the second conductive layer encapsulate the filled material. The material of the filled material is different from that of the first conductive layer and the second conductive layer. | 2013-06-20 |
20130154016 | TIN DOPED III-V MATERIAL CONTACTS - Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstained channel structures. | 2013-06-20 |
20130154017 | Self-Aligned Gate Structure for Field Effect Transistor - A field effect transistor has a substrate with an epitaxial layer, base regions extending from a top of the epitaxial layer into the epitaxial layer, an insulation region having side walls and extending between two base regions on top of the substrate; and a polysilicon gate structure covering the insulation region including the side walls, wherein effective gates are formed by a portion of the polysilicon covering side walls above the base region. | 2013-06-20 |
20130154018 | SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT BARS AND METAL LINES WITH INCREASED VIA LANDING REGIONS - Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material. | 2013-06-20 |
20130154019 | LOW THRESHOLD VOLTAGE CMOS DEVICE - A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process. | 2013-06-20 |
20130154020 | SYSTEM, METHOD AND APPARATUS FOR SEEDLESS ELECTROPLATED STRUCTURE ON A SEMICONDUCTOR SUBSTRATE - An integrated circuit has a doped silicon semiconductor with regions of insulators and bare silicon. The bare silicon regions are isolated from other bare silicon regions. A semiconductor device on the doped silicon semiconductor has at least two electrical connections to form regions of patterned metal. A metal is electroplated directly on each of the regions of patterned metal to form plated connections without a seed layer. A self-aligned silicide is located under each plated connection, formed by annealing, for the regions of plated metal on bare silicon. | 2013-06-20 |
20130154021 | ENHANCED GATE REPLACEMENT PROCESS FOR HIGH-K METAL GATE TECHNOLOGY - The present disclosure provides a method of fabricating a semiconductor device. A high-k dielectric layer is formed over a substrate. A first capping layer is formed over a portion of the high-k dielectric layer. A second capping layer is formed over the first capping layer and the high-k dielectric layer. A dummy gate electrode layer is formed over the second capping layer. The dummy gate electrode layer, the second capping layer, the first capping layer, and the high-k dielectric layer are patterned to form an NMOS gate and a PMOS gate. The NMOS gate includes the first capping layer, and the PMOS gate is free of the first capping layer. The dummy gate electrode layer of the PMOS gate is removed, thereby exposing the second capping layer of the PMOS gate. The second capping layer of the PMOS gate is transformed into a third capping layer. | 2013-06-20 |
20130154022 | CMOS Devices with Metal Gates and Methods for Forming the Same - A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device. | 2013-06-20 |
20130154023 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, SRAM, AND METHOD FOR PRODUCING Dt-MOS TRANSISTOR - A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well. | 2013-06-20 |
20130154024 | STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY - A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material. | 2013-06-20 |
20130154025 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR STABILIZING VARIATION OF POWER SUPPLY VOLTAGE - Disclosed herein is a semiconductor device that includes a first line supplied with a first voltage, a second line supplied with a second voltage, a first node, at least one first capacitor connected between the first line and the first node, at least one second capacitor connected between the node and the second line, and a protective element connected between the first node and the second line in parallel to the second capacitor. | 2013-06-20 |
20130154026 | CONTACT STRUCTURES FOR SEMICONDUCTOR TRANSISTORS - Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors. | 2013-06-20 |
20130154027 | Memory Cell - A memory cell and array and a method of forming a memory cell and array are disclosed. An embodiment is a memory cell comprising first and second pull-up transistors, first and second pull-down transistors, first and second pass-gate transistors, and first and second isolation transistors. Drains of the first pull-up and first pull-down transistors are electrically coupled together at a first node. Drains of the second pull-up and second pull-down transistors are electrically coupled together at a second node. Gates of the second pull-up and second pull-down transistors are electrically coupled to the first node, and gates of the first pull-up and first pull-down transistors are electrically coupled to the second node. The first and second pass-gate transistors are electrically coupled to the first and second nodes, respectively. The first and second isolation transistors are electrically coupled to the first and second nodes, respectively. | 2013-06-20 |
20130154028 | FIN-TYPE FIELD EFFECT TRANSISTOR - A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure. | 2013-06-20 |
20130154029 | EMBEDDED STRESSORS FOR MULTIGATE TRANSISTOR DEVICES - Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region. | 2013-06-20 |
20130154030 | Semiconductor Device with Self-Charging Field Electrodes and Compensation Regions - A semiconductor device includes a drift region of a first doping type, a junction between the drift region and a device region, a compensation region of a second doping type, and at least one field electrode structure arranged between the drift region and the compensation region. The at least one field electrode includes a field electrode and a field electrode dielectric adjoining the field electrode. The field electrode dielectric is arranged between the field electrode and the drift region and between the field electrode and the compensation. The field electrode dielectric includes a first opening through which the field electrode is coupled to drift region and a second opening through which the field electrode is coupled to the compensation region. | 2013-06-20 |
20130154031 | INTEGRALLY MOLDED DIE AND BEZEL STRUCTURE FOR FINGERPRINT SENSORS AND THE LIKE - A biometric sensor device, such as a fingerprint sensor, comprises a substrate to which is mounted a die on which is formed a sensor array and at least one conductive bezel. The die and the bezel are encased in a unitary encapsulation structure to protect those elements from mechanical, electrical, and environmental damage, yet with a portion of the sensor array and the bezel exposed or at most thinly covered by the encapsulation or other coating material structure. | 2013-06-20 |
20130154032 | System With Recessed Sensing Or Processing Elements - Backside recesses in a base member host components, such as sensors or circuits, to allow closer proximity and efficient use of the surface space and internal volume of the base member. Recesses may include covers, caps, filters and lenses, and may be in communication with circuits on the frontside of the base member, or with circuits on an active backside cap. An array of recessed components may a form complete, compact sensor system. | 2013-06-20 |
20130154033 | MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES - Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes layering metal and insulator materials on a sacrificial material formed on a substrate. The method further includes masking the layered metal and insulator materials. The method further includes forming an opening in the masking which overlaps with the sacrificial material. The method further includes etching the layered metal and insulator materials in a single etching process to form the beam structure, such that edges of the layered metal and insulator material are aligned. The method further includes forming a cavity about the beam structure through a venting. | 2013-06-20 |
20130154034 | METHOD AND SYSTEM FOR SETTING A PINNED LAYER IN A MAGNETIC TUNNELING JUNCTION - A method and system for setting the direction of pinned layers in a magnetic junction are described. In one aspect, a magnetic field greater than the coercivity of the layers in a pinned layer but less than the coupling field between the layers is applied. In another aspect the pinned layers are switched from an anti-dual state to a dual state using a spin transfer torque current. In another aspect, a magnetic junction having a partial perpendicular anisotropy (PPMA) layer in the pinned layer is provided. In some aspects, the PPMA layer is part of a synthetic antiferromagnetic structure. In some embodiments, a decoupling layer is provided between the PPMA layer and another ferromagnetic layer in the pinned layer. | 2013-06-20 |
20130154035 | METHOD AND SYSTEM FOR PROVIDING A MAGNETIC TUNNELING JUNCTION USING THERMALLY ASSISTED SWITCHING - A magnetic junction is described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The magnetic junction may also include an additional nonmagnetic spacer layer and an additional pinned layer opposing the nonmagnetic spacer layer and the pinned layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer is configured to be switchable using a write current passed through the magnetic junction. The free layer is also configured to be thermally stable in a quiescent state and have a reduced thermal stability due to heating from the write current being passed through the magnetic junction. In some aspects, the free layer includes at least one of a pinning layer(s) interleaved with ferromagnetic layer(s), two sets of interleaved ferromagnetic layers having different Curie temperatures, and a ferrimagnet having a saturation magnetization that increases with temperature between ferromagnetic layers. | 2013-06-20 |
20130154036 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS HAVING IMPROVED CHARACTERISTICS - A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, a free layer, at least one insulating layer, and at least one magnetic insertion layer adjoining the at least one insulating layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The at least one insulating layer is adjacent to at least one of the free layer and the pinned layer. The at least one magnetic insertion layer adjoins the at least one insulating layer. In some aspects, the insulating layer(s) include at least one of magnesium oxide, aluminum oxide, tantalum oxide, ruthenium oxide, titanium oxide, and nickel oxide The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 2013-06-20 |
20130154037 | METHOD OF MAKING DEVICE - A method for forming MRAM (magnetoresistive random access memory) devices is provided. A bottom electrode assembly is formed. A magnetic junction assembly is formed, comprising, depositing a magnetic junction assembly layer over the bottom electrode assembly, forming a patterned mask over the magnetic junction assembly layer, etching the magnetic junction assembly layer to form the magnetic junction assembly with gaps, gap filling the magnetic junction assembly, and planarizing the magnetic junction assembly. A top electrode assembly is formed. | 2013-06-20 |
20130154038 | High Performance MTJ Element for Conventional MRAM and for STT-RAM and a Method for Making the Same - A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) is disclosed. The MTJ has a MgO tunnel barrier layer formed with a natural oxidation process to achieve a low RA (10 ohm-um | 2013-06-20 |
20130154039 | PRODUCTION METHOD OF RADIATION IMAGE DETECTOR AND RADIATION IMAGE DETECTOR - The present invention provides a production method of a radiation image detector, comprising a scintillator panel preparation step, a composite rigid plate preparation step of bonding a flexible polymer film to a rigid plate with an adhesive to prepare the composite rigid plate, a preparation step of a scintillator panel provided with a composite rigid plate of bonding the composite rigid plate to a scintillator panel to prepare the scintillator panel provided with a composite rigid plate, and a preparation step of a radiation image detection member of opposing the surface of the photoelectric conversion base plate in which the photoelectric conversion elements are disposed to the surface of the side of the scintillator layer of the scintillator panel provided with the composite rigid plate and bonding the photoelectric conversion base plate to the scintillator panel to prepare a radiation image detection member; whereby there arc provided a production method of a radiation image detector which can he easily produced and results in superior image uniformity, and a radiation image detector obtained by the method. | 2013-06-20 |
20130154040 | PHOTO DETECTORS - Photo detectors are provided. The photo detector includes a photoelectric conversion layer between a lower carrier transportation layer and an upper carrier transportation layer, and a common electrode on the upper carrier transportation layer opposite to the photoelectric conversion layer. The photoelectric conversion layer includes a plurality of light absorption layers and each of the light absorption layers contains silicon nanocrystals. The silicon nanocrystals in respective ones of the light absorption layers have different sizes from each other. | 2013-06-20 |
20130154041 | SOLID-STATE IMAGE SENSOR - According to one embodiment, there is provided a solid-state image sensor including a photoelectric conversion layer, and a multilayer interference filter. The multilayer interference filter is arranged to conduct light of a particular color, of incident light, selectively to the photoelectric conversion layer. The multilayer interference filter has a laminate structure in which a first layer having a first refraction index and a second layer having a second refraction index are repeatedly laminated, and a third layer which is in contact with a lower surface of the laminate structure and has a third refraction index. A lowermost layer of the laminate structure is the second layer. The third refraction index is not equal to the first refraction index and is higher than the second refraction index. | 2013-06-20 |
20130154042 | Photonic Systems and Methods of Forming Photonic Systems - Some embodiments include photonic systems. The systems may include a silicon-containing waveguide configured to direct light along a path, and a detector proximate the silicon-containing waveguide. The detector may comprise a detector material which has a lower region and an upper region, with the lower region having a higher concentration of defects than the upper region. The detector material may comprise germanium in some embodiments. Some embodiments include methods of forming photonic systems. | 2013-06-20 |
20130154043 | FILM-FORMING COMPOSITION - A film-forming composition including a triazine ring-containing hyperbranched polymer with a repeating unit structure indicated by formula (1), and inorganic micro particles is provided. This enables the provision of a film-forming composition capable of hybridizing without reducing dispersion of the inorganic micro particles in a dispersion fluid, capable of depositing a coating film with a high refractive index, and suitable for electronic device film formation. | 2013-06-20 |
20130154044 | Single-Photon Avalanche Diode Assembly - A single-photon avalanche diode assembly, the diode including a central terminal and a peripheral terminal, the peripheral terminal being connected to an input of a comparator and to a first power supply terminal by a first resistor, the central terminal being connected by a conductive track to a second power supply terminal, a second resistor being arranged in series on said conductive track. | 2013-06-20 |
20130154045 | AVALANCHE PHOTODIODE - An APD is provided with a semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side of the first mesa, and in the APD, a total donor concentration of the n-type electric field control layer is lower than a total acceptor concentration of the p-type electric field control layer in a range of 2×10 | 2013-06-20 |
20130154046 | IMAGE SENSOR - An image sensor includes a plurality of unit pixels. Each unit pixel has a photo diode for sensing external light to generate photo charges. A transfer transistor is connected to the photo diode for storing the photo charges generated in the photo diode into a floating diffusion region when being turned-on. An amplification transistor amplifies the photo charges stored into the floating diffusion region. A select transistor, connected to the amplification transistor, performs a switching operation. An output line, extended in a column direction, outputs the photo charges in accordance with the switching operation of the select transistor. The photo diode may be formed in such a manner to share the output line with its adjacent photo diode in a horizontal direction, so that the photo charges generated in the photo diode and its adjacent photo diode are outputted through the output line. | 2013-06-20 |
20130154047 | PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR FABRICATING THE PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device includes a substrate, a plurality of photoelectric conversion cells formed on the main surface of the substrate, a current-collecting wiring formed on the plurality of photoelectric conversion cells, an output wiring connected to the current-collecting wiring, and a back-side protective member bonded to the plurality of photoelectric conversion cells via a sealing member in a manner such that the plurality of photoelectric conversion cells formed on the main surface of the substrate are interposed between the substrate and the back-side protective member via the sealing member. The current-collecting wiring and the output wiring are positioned such that the current-collecting wiring and the output wiring do not overlap with each other above the main surface of the substrate. | 2013-06-20 |
20130154048 | Guard Ring for Through Vias - A guard ring for a through via, and a method of manufacture thereof, is provided. The guard ring comprises one or more rings around a through via, wherein the rings may be, for example, circular, rectangular, octagon, elliptical, square, or the like. The guard ring may be formed from a contact through an inter-layer dielectric layer and interconnect structures (e.g., vias and lines) extending through the inter-metal dielectric layers. The guard ring may contact a well formed in the substrate. | 2013-06-20 |
20130154049 | Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology - Novel integrated circuits (ICs) on ceramic wafers and methods of fabricating ICs on ceramic wafers are disclosed. In one embodiment, an active layer comprising IC circuit components is coupled to a selected wafer comprising a ceramic. A surface of the ceramic is processed to enable direct bonding between the selected wafer and the active layer. Another embodiment comprises an active layer comprising IC circuit components and a selected wafer comprising a ceramic and an intermediate layer. A surface of the intermediate layer is processed to enable direct bonding. In some embodiments the intermediate layer comprises a material selected from the following: silicon carbide, silicon dioxide, silicon nitride and diamond. Methods of fabrication are described, wherein layer transfer technology is employed to form active layers and to couple the active layers to the selected wafers. | 2013-06-20 |
20130154050 | Integrated Circuit and IC Manufacturing Method - Disclosed is an integrated circuit die comprising an active substrate including a plurality of components laterally separated from each other by respective isolation structures, at least some of the isolation structures carrying a further component, wherein the respective portions of the active substrate underneath the isolation structures carrying said further components are electrically insulated from said components. A method of manufacturing such an IC die is also disclosed. | 2013-06-20 |
20130154051 | METHOD FOR FORMING A DEEP TRENCH IN A MICROELECTRONIC COMPONENT SUBSTRATE - A trench is formed in a semiconductor substrate by depositing an etch mask on the substrate having an opening, etching of the trench through the opening, and doping the walls of the trench. The etching step includes a first phase having an etch power set to etch the substrate under the etch mask, and a second phase having an etch power set smaller than the power of the first phase. Further, the doping of the walls of the trench is applied through the opening of the etch mask. | 2013-06-20 |
20130154052 | SEMICONDUCTOR DEVICE ISOLATION STRUCTURES - Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a second integrated device region on a substrate that is spaced apart from a first integrated device region. An isolation region may be interposed between the first integrated device region and the second integrated device region. The isolation region may include an isolation recess that projects into the substrate to a first predetermined depth, and that may be extended to a second predetermined depth. | 2013-06-20 |
20130154053 | INDUCTORS WITH THROUGH VIAS - A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend through one or more dielectric layers interposed between a substrate and the inductors. Additionally, the through vias may extend completely or partially through the substrate. | 2013-06-20 |
20130154054 | MICRO-ELECTRO-MECHANICAL STRUCTURE (MEMS) CAPACITOR DEVICES, CAPACITOR TRIMMING THEREOF AND DESIGN STRUCTURES - Micro-electro-mechanical structure (MEMS) capacitor devices, capacitor trimming for MEMS capacitor devices, and design structures are disclosed. The method includes identifying a process variation related to a formation of micro-electro-mechanical structure (MEMS) capacitor devices across a substrate. The method further includes providing design offsets or process offsets in electrode areas of the MEMS capacitor devices across the substrate, based on the identified process variation. | 2013-06-20 |
20130154055 | CAPACITOR AND REGISTER OF SEMICONDUCTOR DEVICE, MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers. | 2013-06-20 |
20130154056 | SEMICONDUCTOR DEVICE - In a semiconductor device including a capacitor which has an upper electrode, a polycrystalline silicon layer on the upper electrode, and a metallic member on the polycrystalline silicon layer, the polycrystalline silicon layer includes germanium so that an upper portion of the polycrystalline silicon layer is lower than a lower portion thereof in a concentration of germanium. | 2013-06-20 |
20130154057 | Method for Fabricating a DRAM Capacitor - A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO | 2013-06-20 |
20130154058 | HIGH SURFACE AREA FILLER FOR USE IN CONFORMAL COATING COMPOSITIONS - A high surface area filler, a conformal coating composition, and an apparatus. The high surface area filler comprises an amorphous silicon dioxide powder and a phosphine compound bonded to the amorphous silicon dioxide powder. The conformal coating composition comprises a conformal coating and the high surface area filler. The apparatus includes an electronic component mounted on a substrate and metal conductors electrically connecting the electronic component. The conformal coating composition overlies the metal conductors and comprises a conformal coating and the high surface area filler. Accordingly, the conformal coating composition is able to protect the metal conductors from corrosion caused by sulfur components (e.g., elemental sulfur, hydrogen sulfide, and/or sulfur oxides) in the air. | 2013-06-20 |
20130154059 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes exciting plasma, applying RF power onto a target substrate to generate substrate bias and performing an ion implantation plural times by applying the RF power in the form of pulses. | 2013-06-20 |
20130154060 | WAFER AND METHOD OF PROCESSING WAFER - A wafer including a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer is disclosed. The substrate has a main portion. A periphery of the dielectric layer and the periphery of the main portion of the substrate are separated by a first distance. A periphery of the conductive layer and the periphery of the main portion of the substrate are separated by a second distance. The second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter greater than the first distance. | 2013-06-20 |
20130154061 | ANODIZING APPARATUS, AN ANODIZING SYSTEM HAVING THE SAME, AND A SEMICONDUCTOR WAFER - An anodizing apparatus for causing an anodizing reaction to substrates immersed in an electrolyte solution. The apparatus includes a storage tank for storing the electrolyte solution, a holder for holding a plurality of substrates in liquid-tight contact with circumferential surfaces of the substrates, a moving mechanism for moving the holder between a transfer position outside the storage tank and a treating position inside the storage tank, and a closing device disposed in the storage tank for cooperating with the holder to complete a liquid-tight closure of the circumferential surfaces of the substrates held by the holder. Chemical reaction treatment is carried out with the circumferential surfaces of the substrates placed in a liquid-tight state. After the chemical reaction treatment is completed, the closing device is made inoperative and the holder is moved away from the treating position to unload the substrates from the storage tank. | 2013-06-20 |
20130154062 | Die Structure and Method of Fabrication Thereof - A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate. | 2013-06-20 |
20130154063 | DRIVING SUBSTRATE, DISPLAY DEVICE, PLANARIZING METHOD, AND METHOD OF MANUFACTURING DRIVING SUBSTRATE - A driving substrate includes: a protective layer including an etching surface; and a film layer including one or more convex portions on a surface thereof, the film layer being in contact with a rear surface of the protective layer, the one or more convex portions each having a surface being flush with the etching surface. | 2013-06-20 |