| 25th week of 2009 patent applcation highlights part 66 |
| Patent application number | Title | Published |
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| 20090157984 | Avoiding use of an inter-unit network in a storage system having multiple storage control units - A storage system provides virtual ports, and is able to transfer the virtual ports among physical ports located on multiple storage control units making up the storage system. The storage system is able to manage logical volumes and/or virtual volumes and virtual ports as a group when considering whether to move logical/virtual volumes and/or virtual ports to another storage control unit in the storage system. When the storage system is instructed to transfer volumes, virtual ports, or a group of volumes and virtual ports among the storage control units, the storage system determines whether an inter-unit network will be required to be used following the transfer. When the storage system determines that the inter-unit network will be required if the transfer takes place, the storage system determines and presents an alternate storage control unit for the transfer to avoid use of the inter-unit network, thereby avoiding degraded performance. | 2009-06-18 |
| 20090157985 | Accessing memory arrays - A memory controller for controlling access to a memory, said memory comprising at least one memory array, said at least one memory array comprising a plurality of rows and a plurality of columns, access to an element within said memory array being performed by opening a row comprising said element and then accessing a column comprising said element, said at least one memory array being adapted to have no more than one row in said at least one memory array open at a time; said memory controller being responsive to a memory access request to access an element within said memory and following said access to determine if said row comprising said accessed element should be closed or should remain open in dependence upon a property of said memory access request. | 2009-06-18 |
| 20090157986 | MEMORY CONTROLLER - A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal. | 2009-06-18 |
| 20090157987 | System and Method for Creating Self-Authenticating Documents Including Unique Content Identifiers - One embodiment of a method for creating a self-authenticating document includes receiving a request to retrieve a data element identified by a content identifier, identifying a storage location associated with the content identifier, retrieving a data element stored at the storage location, calculating a second content identifier of the retrieved data element, comparing the content identifier and the second content identifier, if the content identifier and the second content identifier match, creating an image of the retrieved data element, creating a representation of the stored content identifier, creating a representation of metadata associated with the retrieved data element, and creating a document that includes the image of the retrieved data element, the representation of the stored content identifier, and the representation of metadata. The representation of the stored content identifier may be an alphanumeric string or a graphical representation derived from the stored content identifier. | 2009-06-18 |
| 20090157988 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - Disclosed is a data processing apparatus that includes a plurality of ports inputting and outputting a clip including a plurality of types of essence, a memory storing the clip when recording or playing back of the clip from a recording medium, and a generator storing types of essence in separate regions of the memory, and generate identification information identifying the types of essence, while generating linking information indicating an association between regions of the memory storing one of the types of essence as a master essence and regions of the memory storing the remaining types of essence. The apparatus further includes a control unit outputting the master essence in the regions and the remaining essence in the regions associated therewith via linking information from the designated ports when the master essence in the clip of the video data subjected to playback request designating the ports is stored in the memory. | 2009-06-18 |
| 20090157989 | Distributing Metadata Across Multiple Different Disruption Regions Within an Asymmetric Memory System - Metadata that corresponds to application data is distributed across different disruption regions of an asymmetric memory component such that metadata is written in the same disruption region as the application data to which it corresponds. A first block of application data is written to a first disruption region and a second block of application data is written to a second disruption region. A first block of metadata corresponding to the first block of application data and a second block of metadata corresponding to the second block of application data both are generated. The first block of metadata is written to the first disruption region and the second block of metadata is written to the second disruption region such that the first and second blocks of metadata are written to the same disruption regions as the blocks of application data to which they correspond. | 2009-06-18 |
| 20090157990 | Backing-up apparatus, backing-up method, and backing-up program - A backing-up apparatus, upon receiving an instruction to execute backing up, allocates a storage area to store a snapshot to be produced to each time point indicated by the instruction. When the original data is updated after the time point indicated by the instruction, it is checked that the original data corresponding to the place to which the updating has been executed at a time point immediately before the time point indicated by the instruction is stored in the storage area allocated as the storage area to store the latest snapshot produced for the immediately previous time point. When it has been confirmed that the original data is not stored, the original data immediately before the updating corresponding to the place to which the updating has been executed is stored in only the storage area to store the latest snapshot. | 2009-06-18 |
| 20090157991 | Reliable storage of data in a distributed storage system - The present invention relates to the reliable storage of data within a distributed storage system. A method and system for storing a data unit within a distributed storage system is disclosed, wherein the distributed storage system comprises a plurality of storage elements of unspecified system reliability, a public network interconnecting the plurality of storage elements and a reliability index control unit measuring a plurality of storage element reliability indexes associated with the plurality of storage elements. The data unit is stored following the steps of receiving a request to store the data unit according to a data unit reliability index and storing replicated copies of the data unit in at least one storage element, such that the data unit reliability index is achieved. | 2009-06-18 |
| 20090157992 | Docbase management system and implementing method thereof - The present invention discloses a docbase management system, including a first module, adapted to parse a received invocation from an application and generate an execution plan which comprises operations on physical storage; a second module, adapted to execute the execution plan to schedule a third module to execute the operations on physical storage in the execution plan; and the third module, adapted to execute the operations on physical storage in the execution plan under the scheduling of the second module. Since the implementation of the docbase management system is divided into hierarchies, and the hierarchies are independent of each other, the docbase management system is well extendable, scalable and maintainable. | 2009-06-18 |
| 20090157993 | MECHANISM FOR ENABLING FULL DATA BUS UTILIZATION WITHOUT INCREASING DATA GRANULARITY - A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity. | 2009-06-18 |
| 20090157994 | MEMORY MODULE WITH REDUCED ACCESS GRANULARITY - A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands. | 2009-06-18 |
| 20090157995 | DYNAMIC MEMORY MANAGEMENT IN AN RDMA CONTEXT - A method for dynamically managing memory to support one or more processes executing in a remote direct memory access (RDMA) environment is provided. The method includes inserting a descriptor in a shared descriptor table, the descriptor corresponding to a block of memory allocated to a heap by an operating system. The method further includes, in response to allocating a portion of the block of memory from the heap to a process, determining whether the process has an existing registration with an application program interface for the block of memory. If the process has no existing registration, registering the process the process is registered with the application program interface and a registration corresponding to the block of memory is stored in a private registration table of the process. Additionally, the method includes, in response to the process releasing the allocated portion of the block of memory to the operating system, de-registering with the application program interface and removing the registration from the registration table. When the block of memory is released to the operating system, other registrations corresponding to the block of memory in other private registration tables of other processes remain in the other registration tables. | 2009-06-18 |
| 20090157996 | Method, System and Program Product for Allocating a Global Shared Memory - A method of operating a data processing system includes each of multiple tasks within a parallel job executing on multiple nodes of the data processing system issuing a system call to request allocation of backing storage in physical memory for global shared memory accessible to all of the multiple tasks within the parallel job, where the global shared memory is in a global address space defined by a range of effective addresses. Each task among the multiple tasks receives an indication that the allocation requested by the system call was successful only if the global address space for that task was previously reserved and backing storage for the global shared memory has not already been allocated. | 2009-06-18 |
| 20090157997 | USING IN-LEAF MULTIPLE TRIANGLE PACKING FOR KD-TREES SIZE REDUCTION - Embodiments of a binary layout and packing scheme are disclosed for storing kd-tree information. Information about triangles belonging to the tree leaf may be stored inside the leaf structure itself. Multiple triangles in a corresponding leaf may be stored in the leaf of the kd-tree structure. | 2009-06-18 |
| 20090157998 | Policy based storage appliance virtualization - An embodiment of the invention provides an apparatus and method for a policy-based storage appliance virtualization that identifies the storage space based on a desired storage management operation type. One example of a storage management operation type is the allocation of storage space from a storage appliance(s) to a host(s). The requested storage space amount to be allocated to a host is first specified in a management console. The management console checks one or more policies and compares the policies with the requested storage space amount and identity of the host, so that the management console identifies the storage space(s) that are available for allocation from a storage appliance(s) to the host. The management console may generate a candidate virtualized storage pool identification that identifies the storage space(s) that are available for allocation from the storage appliance(s) to the host. The server administrator then selects the storage space(s) to be allocated to the host. The policies may also be used as constraints to other storage management operation types besides the above-mentioned storage allocation to hosts. | 2009-06-18 |
| 20090157999 | Control Mechanism For Multi-Functional Chips - A control mechanism for multi-functional chips is provided. By receiving operation signals from the predefined pins of the different operation functions, the present invention accesses the corresponding storage area in the memory module according to the operation signals without using different memory modules and memory controllers corresponding to different operation functions so as to save power and reduce the hardware size. For example, the MegaSIM™ multi-functional chip includes the integration of a plurality of operation functions, such as SD/MMC and ISO 7816. Each operation function uses different communication protocol to provide operation signals through individual to shared predefined pins. For example, MegaSIM™ I/O, Vpp/CLK, GND, CLK RST, and Vcc pins are used by ISO 7816, and Cmd, Data0, and Vpp/CLK pins are used by SD/MMC. | 2009-06-18 |
| 20090158000 | Computer System, Memory Management Method and Program Thereof - A computer system, having a non-volatile storage unit ( | 2009-06-18 |
| 20090158001 | ACCESSING CONTROL AND STATUS REGISTER (CSR) - A system may comprise one or more source agents, target agents, and a plurality of directory agents, which may determine the target agent to which one or more transactions generated by the source agents is to be sent. A controller may identify one of a plurality of directory agents to process the transactions. The directory agent may determine the control and status registers of the target agents to which the transaction is to be sent. The target agent may complete the transaction after receiving the transaction from the directory agent. The directory agents may store a memory map to resolve the target agent to which the transactions is to be sent. The directory based distributed CSR access may provide scalability to ever increasing number of heterogeneous agents in the system. | 2009-06-18 |
| 20090158002 | NETWORK STORAGE DEVICE AND DATA READ-WRITE CONTROL METHOD - An embodiment of the present invention discloses a network storage device including a physical storage medium. The network storage device further includes: a storage controller, configured to map the physical storage medium to sub-logical units and map the sub-logical units to logical units, so as to implement data storing, reading, and writing, wherein the sub-logical units are identified by sub-logical unit numbers and the logical units are identified by logical unit numbers. In addition, an embodiment of the present invention further discloses a data read-write control method. The present invention can enlarge valid storage capacity of the logical units, and is compatible with existing logical unit data read-write manners. | 2009-06-18 |
| 20090158003 | STRUCTURE FOR A MEMORY-CENTRIC PAGE TABLE WALKER - A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a page table walker. The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor. | 2009-06-18 |
| 20090158004 | TLB Virtualization Method of Machine Virtualization Device, and Machine Virtualization Program - A TLB virtualization method of a machine virtualization device which, in the case where a TLB is shadowed in a virtualization environment, avoids TLB entry conflicts and is capable of improving the performance of a virtualization environment; wherein a hypervisor is executed on a real machine, an OS is operated on a plurality of virtual machines generated by means of processing based on the hypervisor, TLB entry calculations are carried out using RID values in the virtual machines by means of hypervisor processing, the RID values in the virtual machines used in the TLB entry calculations in the real machine are translated into different values in said plurality of virtual machines, and, further, the values of the bit strings of translated RID values are modified. | 2009-06-18 |
| 20090158005 | CLOCK ENCODED PRE-FETCH TO ACCESS MEMORY DATA IN CLUSTERING NETWORK ENVIRONMENT - Systems and/or methods that facilitate reading data from a memory component associated with a network are presented. A pre-fetch generation component generates a pre-fetch request based in part on a received read command. To facilitate a reduction in latency associated with transmitting the read command via an interconnect network component to which the memory component is connected, the pre-fetch request is transmitted directly to the memory component bypassing a portion of the interconnect network component. The memory component specified in the pre-fetch request receives the pre-fetch request and reads the data stored therein, and can store the read data in a buffer and/or transmit the read data to the requester via the interconnect network component, even though the read command has not yet reached the memory component. The read data is verified by comparison with the read command at a convergence point. | 2009-06-18 |
| 20090158006 | Facilitating management of layer 2 hardware address table based on packet priority information - A network switching device comprises hardware address table storage space, a priority comparison mechanism, and an address table management mechanism. The hardware address table storage space having a number of entries therein. Each one of the entries within the hardware address table storage space includes respective information designating a priority of a respective source network address. The priority comparison mechanism is configured for comparing the priority designating information of the received packet with the priority designating information of at least a portion of the entries within the hardware address table storage space in response to determining that a number of entries within the hardware address table storage space is equal to a capacity of the hardware address table storage space. The address table management mechanism is configured for replacing an entry within the hardware address table storage space with an entry having contents corresponding to the received packet in response to determining that a priority level corresponding to the priority designating information of the received packet is higher than a priority level corresponding to the priority designating information of the replaced entry. | 2009-06-18 |
| 20090158007 | SCALEABLE ARRAY OF MICRO-ENGINES FOR WAVEFORM PROCESSING - A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting to each other in the two dimensional topology. One micro-engine communicates with another adjacent micro-engine by way of the respective FIFOs. The micro-engines are dedicated to predetermined algorithms. The two dimensional topology includes an array of N×M micro-engines interconnected by the multiple FIFOs. The N×M are integer numbers of rows and columns, respectively, in the array of micro-engines. The micro-engines are dedicated to baseband processing of data for RF transmission or RF reception. | 2009-06-18 |
| 20090158008 | SOFTWARE PARAMETERIZABLE CONTROL BLOCKS FOR USE IN PHYSICAL LAYER PROCESSING - A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode. | 2009-06-18 |
| 20090158009 | ELECTRONIC EQUIPMENT AND CONTROL METHOD - Plural CPUs are provided, and when a first CPU of the plural CPUs is a master, the other CPU operates as a slave. Also, plural memories are provided including a memory that operates and is used for first processing when the master CPU operates and a memory that operates and is used for second processing when the slave CPU operates. Every time an OS (Operating System) starts, the CPU to serve as a master is sequentially switched, then the remaining CPU is caused to serve as a slave, and the memories used for the first processing and the second processing are sequentially switched. | 2009-06-18 |
| 20090158010 | Command Protocol for Integrated Circuits - A method of operating an integrated circuit involves supplying an instruction portion of a command to the integrated circuit to specify an operation to be performed by the integrated circuit. At least some types of commands also include an attributes portion that provides additional information about the operation to be performed. The attributes portion of the command is supplied to the integrated circuit with a delay relative to the instruction portion of the command. The integrated circuit selectively enables circuitry for processing the attributes portion if the integrated circuit determines from the received instruction portion that the command also includes an attributes portion. The delay between the two portions of the command provides sufficient time for the integrated circuit to enable the attributes processing circuitry, which, in a default state, can be disabled during an active mode of the integrated circuit to save power. | 2009-06-18 |
| 20090158011 | DATA PROCESSING SYSTEM - A data processing system comprising a computer chip having a processing circuit and a chip-internal first memory and a chip-external second memory being coupled to the computer chip, wherein the processing circuit is configured to allow execution of computer programs stored in the first memory and to prevent execution of computer programs stored in the second memory when the data processing system is in a first state, and to allow execution of computer programs stored in the second memory when the data processing system is in a second state. | 2009-06-18 |
| 20090158012 | Method and Apparatus for Performing Improved Group Instructions - Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions. | 2009-06-18 |
| 20090158013 | Method and Apparatus Implementing a Minimal Area Consumption Multiple Addend Floating Point Summation Function in a Vector Microprocessor - Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises transferring more than two operands to a vector unit, each operand being transferred to a respective one of a plurality of processing lanes of the vector unit. The operands may be transferred from the vector unit to a dot product unit wherein an arithmetic operation using the more than two operands may be performed. | 2009-06-18 |
| 20090158014 | System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor - An apparatus and method for executing instructions having a program order. The apparatus comprising a temporary buffer, tag assignment logic, a plurality of functional units, a plurality of data paths, a register array, a retirement control block, and a superscalar instruction retirement unit. The temporary buffer includes a plurality of temporary buffer locations to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations. The tag assignment logic is configured to concurrently assign a tag to each instruction in a first set of instructions, wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations. | 2009-06-18 |
| 20090158015 | Uses of Known Good Code for Implementing Processor Architectural Modifications - In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC. | 2009-06-18 |
| 20090158016 | USE OF MODES FOR COMPUTER CLUSTER MANAGEMENT - A system, method and computer program product for managing a plurality of applications in a computer cluster. Each application is able to run on a particular node in the cluster. In one embodiment, associations are maintained among a plurality of modes and the plurality of applications, with each application being associated with at least one mode. Responsive to designation of at least one mode as active for the cluster, each application that is associated with an active mode is flagged as eligible for activation, each inactive application that is not associated with any active mode is flagged as ineligible for activation, and each active application that is not associated with any active mode is flagged as ineligible for activation and inactivated. Flagging as eligible, flagging as ineligible and flagging as ineligible and inactivating may be performed in any order, and inactivating is sequenced according to dependencies among the applications. | 2009-06-18 |
| 20090158017 | TARGET-FREQUENCY BASED INDIRECT JUMP PREDICTION FOR HIGH-PERFORMANCE PROCESSORS - A frequency-based prediction of indirect jumps executing in a computing environment is provided. Illustratively, a computing environment comprises a prediction engine that processes data representative of indirect jumps performed by the exemplary computing environment according to a selected frequency-based prediction paradigm. Operatively, the exemplary prediction engine can keep track of targets, in a table, taken for each indirect jump and program context (e.g., branch history and/or path information) of an exemplary computing program. Further, the prediction engine can also store a frequency counter associated with each target in the exemplary table. Illustratively, the frequency counter can record the number of times a target was taken in the recent past executions of an observed one or more indirect jump. The prediction engine can supply the target address of an indirect jump based on the values of the frequency counters of each stored target address. | 2009-06-18 |
| 20090158018 | Method and System for Auto Parallelization of Zero-Trip Loops Through the Induction Variable Substitution - A method and system of auto parallelization of zero-trip loops that substitutes a nested basic linear induction variable by exploiting a parallelizing compiler is provided. Provided is a use of a max{0,N} variable for loop iterations in case of no information is known about the value of N, for a typical loop iterating from 1 to N, in which N is the loop invariant. For the nested basic induction variables, an induction variable substitution process is applied to the nested loops starting from the innermost loop to the outermost one. Then a removal of the max operator afterwards through a copy propagation pass of the IBM compiler is provided. In doing so, the loop dependency on the induction variable is eliminated and an opportunity for a parallelizing compiler to parallel the outermost loop is provided. | 2009-06-18 |
| 20090158019 | Computer Program Code Size Partitioning System for Multiple Memory Multi-Processing Systems - The present invention provides for a system for computer program code size partitioning for multiple memory multi-processor systems. At least one system parameter of a computer system comprising one or more disparate processing nodes is identified. Computer program code comprising a program to be run on the computer system is received. A program representation based on received computer program code is generated. At least one single-entry-single-exit (SESE) region is identified based on the whole program representation. At least one SESE region of less than a certain size (store-size-specific) is identified based on identified SESE regions and the at least one system parameter. Each store-size-specific SESE region is grouped into a node-specific subroutine. The non node-specific parts of the computer program code are modified based on the partitioning into node-specific subroutines. The modified computer program code including each node-specific subroutine is compiled based on a specified node characteristic. | 2009-06-18 |
| 20090158020 | System Backup And Recovery Solution Based On BIOS - A system performs system initialization for a computing device, comprising a module to back up one or more files of the computing device in response to a backup request and to restore one or more files of the computing device in response to a recovery request; and a point managing module to set up a backup point that comprises information based on the backup request and locate one or more backup points for the restoration operation. | 2009-06-18 |
| 20090158021 | METHODS OF USING BIOS INFORMATION WHEN BOOTING INFORMATION HANDLING SYSTEMS AND MACHINE-EXECUTABLE CODE FOR CARRYING OUT THE METHODS - A method of using BIOS information can include exporting first BIOS information from a first information handling system. The method can further include initiating a boot sequence for the second information handling system and importing second BIOS information into a second information handling system after initiating the boot sequence and before initiating an operating system, wherein the second BIOS information is associated with the first BIOS information. The method can further include initiating an operating system of the second information handling system after importing the second BIOS information. The first and second BIOS information may be the same, or the second BIOS information may be derived from the first BIOS information. The first and second information handling systems may be the same or different. In one embodiment, the first BIOS information can be translated into a text file for editing before using the second BIOS information during a boot sequence. | 2009-06-18 |
| 20090158022 | SNOOP FILTER OPTIMIZATION - A snoop filter optimization system includes one or more subsystems to operate a snoop filter, determine information that that affects operation of the snoop filter, and adjust operation of the snoop filter relative to the information that affects operation of the snoop filter. | 2009-06-18 |
| 20090158023 | ADAPTIVE SYSTEM BOOT ACCELERATOR FOR COMPUTING SYSTEMS - An acceleration mechanism for boot-up processing in a computing system is provided. The acceleration mechanism relies on recording most, if not all, of the read transactions, associated with requests and retrievals made during a boot-up and, in some aspects most, if not all, of the write transactions, associated with requests and stores made during a shutdown process. Prior to executing the boot-up process, data associated with the transactions is pre-fetched based on the recorded information and used to make the requests or information retrievals during the ensuing boot-up process. Additionally, since the mechanism of the present innovation provides for continual recording and the transaction data, the acceleration of the boot-up process can be adaptive even if hardware additions/changes or any other changes that affect the boot-up or shutdown process occur. | 2009-06-18 |
| 20090158024 | DUAL BIOS CIRCUIT - A dual BIOS circuit includes a first BIOS chip, a second BIOS chip, and a transistor. The first and the second BIOS chip include a setup program configured for setting the voltage of a GPIO pin of a Southbridge chip. The first and the second BIOS chip are connected to the Southbridge chip. The gate of the transistor is connected to the GPIO pin of the Southbridge chip. The drain of the transistor is connected to a power supply via a resistor, and connected to a detecting pin of the Southbridge chip. The source of the transistor is grounded. The power supply is connected to a signal pin of the Southbridge chip. The first or second BIOS chip is selected to operate according to the voltage level at the detecting pin of the Southbridge chip. | 2009-06-18 |
| 20090158025 | DUAL BIOS CIRCUIT - A dual BIOS circuit includes a first BIOS chip, a second BIOS chip, a power supply, and a switch. The first BIOS chip is connected to a Southbridge chip of a motherboard via a bus. The second BIOS chip is connected to the Southbridge chip of a motherboard via another bus. The power supply is connected to signal pin of the Southbridge chip. The switch includes a handle. The first terminal of the switch is connected to the a detecting pin of the Southbridge chip. The second terminal of the switch is connected to the power supply. The third terminal of the switch is grounded. The first or second BIOS chip is selected to operate according to the voltage level at the detecting pin of the Southbridge chip. | 2009-06-18 |
| 20090158026 | METHOD AND DEVICE FOR SECURELY CONFIGURING A TERMINAL BY MEANS OF A STARTUP DATA STORAGE DEVICE - Method of configuring a terminal ( | 2009-06-18 |
| 20090158027 | ELECTRONIC DEVICE HAVING AN ALTERABLE CONFIGURATION AND METHODS OF MANUFACTURING AND CONFIGURING THE SAME - An electronic device having an alterable configuration includes a non-volatile memory configurable to include at least a first partition and a second partition, the non-volatile memory storing a boot ROM. The boot ROM is operable when executed by a processor of said electronic device to, in the event that a third partition is available, boot an operating system in the third partition, the operating system operable when booted to cause the third partition to be deleted and the second partition to be expanded to encompass memory freed by the deletion; and otherwise boot an operating system in the first partition. | 2009-06-18 |
| 20090158028 | DRM METHOD AND DRM SYSTEM USING TRUSTED PLATFORM MODULE - The present invention relates to a terminal apparatus including a trusted platform module (TPM) and a DRM method using the same. The terminal apparatus receives information on a validity period from a server, uses the TPM generates a public key including the information on the validity period, transmits the public key to the server, receives encoded digital contents from the server, and uses the TPM to decode the received digital contents. | 2009-06-18 |
| 20090158029 | MANUFACTURING UNIQUE DEVICES THAT GENERATE DIGITAL SIGNATURES - A method of manufacturing devices that generate digital signatures such that each device may be reliably and uniquely identified includes creating a public-private key pair within each device during manufacture; exporting only the public key from the device; retaining the private key within the device against the possibility of divulgement thereof by the device; and securely linking said exported public key with other information within the environment of the manufacture of the device, whereby each device is securely bound with its respective public key. A database of PuK-linked account information of users is maintained. The PuK-linked account information for each user includes a public key of such a device; information securely linked with the public key during manufacture; and third-party account identifiers, each of which identifies an account to a third-party of the user maintained with the third-party that has been associated with the user's public key by the third-party. | 2009-06-18 |
| 20090158030 | Doing business without SSN, EIN, and charge card numbers - This invention introduces encrypted identifiers to be used when the owner of an identifier wants to hide the original identifier away from public exposure but still be able to be uniquely identified through the encrypted form of the identifier. The logical requirement for such an encrypted identity is that it needs to be different for each user in order for it not to become public knowledge. The inventor refers to such changeable, proxy identifiers as “Pxy” identifiers. Pxy identifiers are generated using a Rule Number that references a user-specific algorithm and encryption key that is different for every user. To further privatize and facilitate tracing the ownership of a Pxy identifier to its owner, one or more identity-owner-specific passwords are also utilized. Pxy identity-identifiers examples include: PxySsn, PxyId, PxyEIN; and non-identity-identifier examples are: user-specific-encrypted-door-opener-codes, coded charge numbers, Pxy Software Keys, and so on. | 2009-06-18 |
| 20090158031 | Secure Certificate Installation on IP Clients - According to one embodiment of the invention, a method is deployed for loading a user CA certificate into the trusted certificate storage of a network device The method comprises a number of operations. A first operation involves a downloading of addressing information. Thereafter, a communication session is established using the addressing information for retrieval of a bootstrapping digital certificate that can be digitally verified by the network device using its factory settings. Keying information is extracted from the bootstrapping digital certificate and the keying information can be used to verify that the communication session is between the network device and a certificate server being different than a source for the addressing information. Upon verification that the network device is in communication with the certificate server, the user CA certificate is downloaded from the certificate server using a secure channel that is established based on the bootstrapping digital certificate. | 2009-06-18 |
| 20090158032 | Method and System for Automated and Secure Provisioning of Service Access Credentials for On-Line Services to Users of Mobile Communication Terminals - In a communications network including at least one authentication entity adapted to authenticating a network access requestor in order to conditionally grant thereto access to the communications network, wherein the authenticating is based on public key cryptography, a method for automatically provisioning the network access requestor with service access credentials for accessing an on-line service offered by an on-line service provider accessible through the communications network. The method includes: during the authenticating the network access requestor, having an authentication entity request to the on-line service provider the generation of the service access credentials; at the on-line service provider, generating the service access credentials, encrypting the service access credentials by exploiting a public encryption key of the network access requestor and providing the encrypted service access credentials to the authentication entity; and having the authentication entity cause the network access requestor to be provided with the encrypted service access credentials. | 2009-06-18 |
| 20090158033 | METHOD AND APPARATUS FOR PERFORMING SECURE COMMUNICATION USING ONE TIME PASSWORD - The invention relates to a communication method and system using a one time password (OTP). The communication system includes: a user computer that has an OTP generator for generating the OTP provided therein; a service server that performs user authentication using user information and an OTP value input from the user computer, and communicates with the user computer using the encoded data that is associated with the OTP value, when the user authentication succeeds; and an OTP integrated authentication server that verifies the OTP value between the user computer and the service server. | 2009-06-18 |
| 20090158034 | AUTHENTICATION GATEWAY APPARATUS FOR ACCESSING UBIQUITOUS SERVICE AND METHOD THEREOF - An authentication gateway apparatus for accessing a ubiquitous service includes: an authentication server of a service provider that receives an authentication data request message from a portable apparatus, and provides an authentication token; a first authentication device of the portable apparatus that transmits the authentication data request message to the authentication server, receives and stores an authentication token from the authentication server, and is used as a representative authentication device; and second authentication devices of ubiquitous apparatuses that are connected to the first authentication device of the portable apparatus by a wireless communication system, and have individual unique values. | 2009-06-18 |
| 20090158035 | Public Key Encryption For Web Browsers - A method, apparatus, and article are provided to support encryption of web service applications on a remote server. In a computer system with a remote server and a local client machine, a browser is provided on the local client machine to access applications on the server. Web server applications are stored on one or more remote servers, with access provided through the browser local to the client machine. A user of one or more web services may encrypt data entered with a public key, and may view received data with a private key. The public key and private key are local to the client machine and are employed to encrypt the data stored on the server. | 2009-06-18 |
| 20090158036 | PROTECTED COMPUTING ENVIRONMENT - A method of establishing a protected environment within a computing device including validating a kernel component loaded into a kernel of the computing device, establishing a security state for the kernel based on the validation, creating a secure process and loading a software component into the secure process, periodically checking the security state of the kernel, and notifying the secure process when the security state of the kernel has changed. | 2009-06-18 |
| 20090158037 | SYSTEM AND METHOD FOR PROTECTING AN ELECTRONIC FILE - A method for protecting an electronic file is provided. The method symmetrically encrypts the electronic file with a symmetric key, and asymmetrically encrypts the symmetric key. In addition, the method calculates a message digest for the encrypted electronic file, and obtains a trusted timestamp for the message digest. The method may provide security and authenticity for the electronic file. | 2009-06-18 |
| 20090158038 | UNIVERSAL AUTHENTICATION METHOD - The present invention is directed to a universal authentication method that is more secure than conventional methods found on most electronic systems. The universal authentication method does not send passwords over hard wires or wireless systems. Consequently, it is difficult for would be password thief to intersect password data. It can also provide a further layer of security by providing rotating passwords. | 2009-06-18 |
| 20090158039 | DEVICE PAIRING USING "HUMAN-COMPARABLE" SYNCHRONIZED AUDIBLE AND/OR VISUAL PATTERNS - A first device may authenticate a key of a second device (after discovering the second device, and executing a pairing protocol with the second device, wherein a result of the pairing protocol is a bit string) by encoding the bit string, transmitting a human-perceptible representation of the encoded bit string, transmitting a human-perceptible distinctive end of string indicator, receiving human feedback and determining whether or not a key of the second device is authentic based on the received human feedback. At the first device, wireless communications with the second device may be controlled based on the determination of whether or not the key of the second device is authentic. | 2009-06-18 |
| 20090158040 | METHOD AND SYSTEM FOR SECURE EXCHANGE OF DATA IN A NETWORK - A first network device implements a method for the secure exchange of data in a network. The network also includes a second network device and a remote device. The method includes establishing an indirect path to the remote device and pre-negotiating first security parameters with the remote device over the indirect path using a network layer protocol, when the second network device has an active first data link. The method further includes establishing an active second data link with the remote device and exchanging first data with the remote device over the active second data link using the first security parameters, when the first data link becomes inactive. | 2009-06-18 |
| 20090158041 | METHODS AND DEVICES FOR CREATING SECURITY GROUP AND AUTHENTICATION OVER P2P NETWORK - A method of creating a security group over a Peer-To-Peer (P2P) network is disclosed. An invitee terminal attaches a public key to a peer advertisement in which its own identification information is encrypted using its own private key, and then sends a resulting peer advertisement over the P2P network. An inviter terminal, which has found the peer advertisement, encrypts a group advertisement, including group information about the security group, using public keys of the corresponding invitee terminal, and then sends a resulting group advertisement to the invitee terminal desired to be invited to the security group. The invitee terminal decrypts the group advertisement using its own private key, and participates in the security group using the group information. | 2009-06-18 |
| 20090158042 | Managed Access Point Protocol - Methods, apparatuses and systems facilitating deployment and configuration of managed access points in hierarchical wireless network systems. An embodiment of the invention facilitates deployment and configuration of conventional, substantially autonomous access points operating in connection with a central management node, such as a server or appliance. In another embodiment, the present invention facilitates deployment and configuration of light-weight access points in a hierarchical wireless network system. In one embodiment, the present invention also provides a streamlined encryption key exchange protocol adapted to hierarchical wireless network system architectures. | 2009-06-18 |
| 20090158043 | SECURE DIGITAL SIGNATURE SYSTEM - The illustrative embodiments provide a computer implemented method, apparatus, and computer program product for receiving a request from a client to instantiate an electronic document. After successful completion of mutual authentication between a web application server and the client, the web application server provides the electronic document to the client. The web application server may then receive a set of changes associated with the electronic document to form a modified document. After receiving a request from the client for a digital signature to be generated for the modified document, the web application server generates a digital signature using a private key of the web application server and an identity of an end-user associated with the client. The web application server then signs the modified document with the digital signature. | 2009-06-18 |
| 20090158044 | OPTICAL DNA BASED ON NON-DETERMINISTIC ERRORS - The claimed subject matter relates to architectures and/or mechanisms that can facilitate issuing, embedding and verification of an optical DNA (o-DNA) signature. A first mechanism is provided for obtaining a set of manufacturing errors inherent in an optical media instance. These errors can be non-deterministic and can be encoded into the o-DNA that can be cryptographically signed with a private key, and then embedded into the source optical media instance. A second mechanism is provided that can decrypt the o-DNA with a public key and compare the authenticated errors to the observed errors to ascertain whether the optical media instance is authentic as opposed to a forgery or counterfeit. | 2009-06-18 |
| 20090158045 | LIGHT-OVERHEAD AND FLEXIBLE WIRELESS SENSOR MESSAGE AUTHENTICATION METHOD - The present invention relates to a wireless sensor message authentication method, which is characterized by an authentication scheme of any message authentication code applied to any secure message authentication code (MAC); an authentication scheme using the concept of error correcting code (ECC) and applied to any binary ECC to provide different feature; flexible technique tuning required throughput and faulty data detection capability by adjusting the ECC in use; end-to-end authentication; and XOR operation conducted to original MAC to secure light overhead. | 2009-06-18 |
| 20090158046 | HASH-BASED SYSTEMS AND METHODS FOR DETECTING AND PREVENTING TRANSMISSION OF POLYMORPHIC NETWORK WORMS AND VIRUSES | 2009-06-18 |
| 20090158047 | HIGH PERFORMANCE SECURE CACHING IN THE MID-TIER - In a multi-tier data server system, data from the first tier is cached in a mid-tier cache of the middle tier. Access control information from the first tier for the data is also cached within the mid-tier cache. Caching the security information in the middle tier allows the middle tier to make access control decisions regarding requests for data made by clients in the outer tier. | 2009-06-18 |
| 20090158048 | METHOD, CLIENT AND SYSTEM FOR REVERSED ACCESS TO MANAGEMENT SERVER USING ONE-TIME PASSWORD - Provided are a method, client and system for reservation access to a management server using a one-time password. A generated personal identification number (PIN) is transmitted to the management server when a reservation time comes. The management server generates a random number encrypted using the PIN and transmits the random number to the client. The random number encrypted using the PIN is received, the received random number is encrypted by a symmetric-key algorithm using a client secret key and is transmitted to the management server. The management server receives the random number encrypted using the client secret key, and decrypts the received random number using a server secret key and the PIN. A random number before the encryption using the PIN is compared with a decrypted random number, and access of the client is accepted if the two numbers are identical. Automatic access to a system employing a one-time password authentication method can be made through an arbitrary route according to previously reserved settings to perform information collection and to process specific functions in the case where a system manager is unable to directly access the system through a determined route because of temporal and spatial limitations. | 2009-06-18 |
| 20090158049 | Building a security access system - In an embodiment, a secure module is provided that provides access keys to an unsecured system. In an embodiment, the secure module may generate passcodes and supply the passcodes to the unsecured system. In an embodiment, the access keys are sent to the unsecured system after receiving the passcode from the unsecured system. In an embodiment, after authenticating the passcode, the secure module does not store the passcode in its memory. In an embodiment, the unsecured module requires the access key to execute a set of instructions or another entity. In an embodiment, the unsecured system does not store access keys. In an embodiment, the unsecured system erases the access key once the unsecured system no longer requires the access key. In an embodiment, the unsecured system receives a new passcode to replace the stored passcode after using the stored passcode. Each of these embodiments may be used separately. | 2009-06-18 |
| 20090158050 | Trusted Labeler - A cryptographic device and method are disclosed for processing different levels of classified information. Input and output ports are physically isolated on the cryptographic device. Within the cryptographic device, each port has its packets labeled in such a way that it can be processed differently from other packets by a cryptographic module. High-assurance techniques are used to assure labeling and proper processing of the packets. These labeled packets are intermixed on common pathways regardless of level of classification. Despite intermixing, separation of the packets is assured through the process. | 2009-06-18 |
| 20090158051 | METHOD AND SYSTEM FOR OBFUSCATING A CRYPTOGRAPHIC FUNCTION - A method of protecting an integrity of a data processing system. The method comprises determining ( | 2009-06-18 |
| 20090158052 | IMAGE PROCESSING APPARATUS FOR CHECKING UNAUTHORIZED ACCESS TO INFORMATION AND METHOD OF PERFORMING THE SAME - Information is prevented from being retrieved by an unauthorized person when an information processing apparatus is stolen or lost. There is provided an information processing apparatus including: a storage; dividing logic/utility that divides data stored on the storage into a predetermined first number of pieces of partial data; transmitting logic/utility that transmits one or more of the first number of pieces of divided partial data to one or more different information processing apparatuses, and deletes the one or more of the first number of pieces of partial data from the storage; retrieving logic/utility that retrieves the one or more pieces of partial data from the one or more different information processing apparatuses, and stores the retrieved pieces of partial data onto the storage; and restoring logic/utility that restores the data from the minimum number of pieces of partial data. | 2009-06-18 |
| 20090158053 | Battery Pack and Electronic Apparatus - A battery pack includes at least one rechargeable battery configured to output power; a remaining battery capacity detection unit configured to detect a remaining battery capacity of the at least one rechargeable battery; and a cryptographic unit configured to output a response word in response to an external request word by encrypting the external request word based on a cryptographic algorithm with a common code key. | 2009-06-18 |
| 20090158054 | PRIVATE DATA PROCESSING - A method for processing one or more terms includes, at a first computation facility, computing an obfuscated numerical representation for each of the terms. The computed obfuscated representations are provided from the first facility to a second computation facility. A result of an arithmetic computation based on the provided obfuscated values is received at the first facility. This received result represents an obfuscation of a result of application of a first function to the terms. The received result is processed to determine the result of application of the first function to the terms. | 2009-06-18 |
| 20090158055 | METHOD FOR CRYPTOGRAPHIC AUTHENTICATION - The invention relates to a method for cryptographic authentication in access security systems. The aim of the invention is to provide a software solution. To this end, the method for secured storage of counter states in a non-volatile memory (EEPROM) ( | 2009-06-18 |
| 20090158056 | Battery Load Allocation in Parallel-Connected Uninterruptible Power Supply Systems - An uninterruptible power supply (UPS) of a UPS system including a plurality of UPSs connected in parallel at a load bus and configured to provide power thereto from respective batteries of a plurality of batteries is operated such that a difference between a variable, for example, battery voltage, indicative of battery capacity for a battery associated with the subject UPS and an average value of the variable for the plurality of batteries is determined and a power flow between the subject UPS and the load bus is controlled responsive to the determined difference. Controlling a power flow between the subject UPS and the load bus responsive to the determined difference may include, for example, controlling a phase of an inverter of the subject I 0 UPS responsive to the determined difference. | 2009-06-18 |
| 20090158057 | SYSTEM AND METHOD FOR INTERCHANGEABLY POWERING SINGLE OR MULTIPLE MOTHERBOARDS - In one embodiment, a single electrical power supply is used to interchangeably power either a single motherboard or dual motherboards. Switchable output power and individual sequencing may be provided to each motherboard using FETs, such that the power supply may respond to the sequencing of each motherboard as if it were dedicated to that motherboard. In a two motherboard system, power to the first motherboard is reduced by removing some output voltages from the first motherboard. Fault circuitry may also be provided so that a power related fault on one domain does not affect operation of the other motherboard. | 2009-06-18 |
| 20090158058 | ASSEMBLY OF A POWER SUPPLY TO A DATA ACCESS DEVICE - An assembly of a power supply to a data access device inside which a 3.5-inch hard disk and a circuit are provided. The hard disk is electrically connected to a signal and power conversion unit to obtain a required voltage and signal supplied by the signal and power conversion unit. Two connection terminals arranged on the signal and power conversion unit are respectively may transmit a signal and meanwhile carry a first voltage to supply power to a circuit and its electronic parts and may receive only a second voltage or convert the second voltage into a third voltage. Alternatively, dual sets of second and third voltage are optionally received as the power supplied to the 3.5-inch hard disk and the circuit and its electronic parts for a solution to a dual-channel multi-power and signal transmission. | 2009-06-18 |
| 20090158059 | VOLTAGE REGULATING CIRCUIT FOR MOTHERBOARD - An exemplary voltage regulating circuit for a motherboard includes a selecting switch and a first switch module, the selecting switch comprising a first input terminal arranged to receive a standby power provided by a power supply, a first control terminal arranged to receive a state signal from the motherboard via a first switch module controlled by a power good signal generated by the power supply, and an output terminal, wherein, when the motherboard is turned off, the state signal is at a high level and the first switch module is turned on by the power good signal for turning off the selecting switch to stop outputting the standby power. | 2009-06-18 |
| 20090158060 | Runtime control of system performance - An apparatus includes a hardware unit having an interface to a clock generator, an interface to a power supply and an interface to a software unit. The interface to the software unit is configurable to receive a request from the software unit that identifies at least one operating point for the apparatus. The hardware unit is operable to control at least one of the clock generator and the power supply so as to achieve the requested operating point. | 2009-06-18 |
| 20090158061 | Method and apparatus for on-demand power management - Embodiments of a method and an apparatus for on-demand power management of a processing system have been presented. In some embodiments, the apparatus includes a power management unit (PMU) to provide power to an electronic system. The apparatus further includes a power management controller (PMC) coupled to the power management unit, to control values of one or more parameters of an operating state of the PMU in response to the operating conditions of the electronic system. The PMC may execute a power management algorithm (PMA) to determine the values of the parameters. Further, the PMU and the PMC may reside on different integrated circuit substrates. | 2009-06-18 |
| 20090158062 | PERIPHERAL TELECOMMUNICATIONS DEVICE HAVING MOVABLE COVER WITH INTEGRATED ANTENNA - A computer peripheral telecommunications device having an electronic interface for connection to a computer and being configured for adding wireless telecommunication functionality to the computer, the device comprising a movable cover portion for covering the electronic interface while not in use and an antenna integrated in the movable cover portion. | 2009-06-18 |
| 20090158063 | METHOD AND DEVICE FOR DYNAMICALLY CONTROLLING POWER CONSUMPTION AND CONNECTION MODE OF NETWORK CARD - The invention provides a method and a device for dynamically control power consumption and a connection mode of a network card, which relates to a power saving technique for the network card. The method comprises steps of: monitoring a data transmission state in a network in real time, and obtaining a statistic value for the data transmission state in a current or a predetermined period; obtaining a target connection mode matching with the current data transmission based on the statistic value, and switching the connection mode of the network card to the target connection mode. In the embodiments of the present invention, when a network connection is established, it is not forced to a certain connection mode. The connection mode may be dynamically varied according to a load task by monitoring the data transmission state in the network and comparing with a switching condition. The connection mode may be dynamically switched among respective modes, so as to improve efficiency of the transmission bandwidth and implement an optimal dynamic match of the bandwidth/power consumption. | 2009-06-18 |
| 20090158064 | Home network client and server including energy-away control element and control method thereof - Provided are a home network client and server including an energy-away control element (ECE), and a control method thereof. A client advertises an ECE serving as a functional block of each service unit. The advertisement is recognized and the ECE is registered by a plug and play method. An ECE to be controlled is searched and selected among registered ECEs. State checking and management are performed on the selected ECE. The ECE is defined by each service unit in the home network server and client, and energy is controlled for each ECE, so that the energy consumption can be reduced. | 2009-06-18 |
| 20090158065 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING SYSTEM AND POWER CONTROL METHOD THEREOF - Provided is an image processing apparatus including a microcomputer, a standby power supply unit to supply standby power to the microcomputer, a power control port to receive an external control signal, and a power controller to supply the standby power or to cut off the standby power supplied to the microcomputer according to an external control signal if the external power control signal is supplied. | 2009-06-18 |
| 20090158066 | Power management using automatic load/unload detection of DAC - An automatic load detection system. A first reference signal that may be known apriori can be used for load detection. For example, the first reference signal may be used for invisible portion of a frame. The DAC receives the first reference signal and outputs a signal that is based on the first reference signal. The output of the DAC may have two known values depending on whether the load is coupled to the DAC, e.g., by having a different impedance. Thus, the output signal may be used for detecting whether the load is uncoupled from the DAC. If it is determined that the load is uncoupled from the DAC, the clocking signal to the DAC may be turned off. Thus, DAC no longer consumes power when the load is uncoupled, thereby saving power. | 2009-06-18 |
| 20090158067 | SAVING POWER IN A COMPUTER SYSTEM - A power management unit (PMU) may promote a processing core from a working state to a first non-working power saving state after receiving a signal from an automatic core C-state promotion (ACCP) unit. An OS component may detect the idling of the processing core and may initiate the ACCP. The ACCP may initiate the PMU to promote the processing core to a first non-working power saving state. The ACCP may track the residency time of the processing core in the first non-working power saving state and may initiate the PMU to promote the processing core to a next non-working power saving state if residency time of the processing core in the first non-working power saving state exceeds a first value. The ACCP may initiate the PMU to demote the processing core back to the working state if a break event occurs during the residency time. | 2009-06-18 |
| 20090158068 | REDUCING CORE WAKE-UP LATENCY IN A COMPUTER SYSTEM - A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect arrival of a first, second, and a third interrupt directed at a first, second, and a third core. The power control unit may check whether the second interrupt occurs within a first period, wherein the first period is counted after waking-up of the first core is complete. The power control unit may then wake-up the second and the third core concurrently if the second interrupt occurs within the first period after the wake-up activity of the first core is complete. The first period may at least equal twice the time required for a first credit to be returned and next credit to be accepted. | 2009-06-18 |
| 20090158069 | APPARATUS AND METHOD FOR POWER MANAGEMENT CONTROL - A power management control apparatus including a memory unit configured to store a program for disabling a previously determined Link power management state when a system enters a specific operating state and for enabling the disabled Link power management state when the system is resumed, a processor configured to access the memory unit and to execute the program, and a control unit connected to the processor and the memory unit and configured to manage Link power based on a result of executing the program. | 2009-06-18 |
| 20090158070 | Selecting Between High Availability Redundant Power Supply Modes For Powering A Computer System - Methods, apparatus, and products for selecting a redundant power supply mode for powering a computer system are disclosed that include detecting, by a voltage monitoring module, an input voltage level of a power supply; determining, by the voltage monitoring module, whether the input voltage level of the power supply is greater than a predetermined threshold value; if the input voltage level of the power supply is greater than the predetermined threshold value, configuring, by the voltage monitoring module, the power supply for an N+N redundant power supply mode having N primary power supplies and N redundant power supplies; and if the input voltage level of the power supply is not greater than the predetermined threshold value, configuring, by the voltage monitoring module, the power supply for an N+M redundant power supply mode having N primary power supplies and M redundant power supplies, where N is greater than M. | 2009-06-18 |
| 20090158071 | INTEGRATED POWER MANAGEMENT LOGIC - A device and system are disclosed. In one embodiment the device includes a programmable power supply management logic. The programmable power supply management logic is capable of managing a plurality of voltage regulators present in a computer system. Additionally, the power supply management logic is integrated into an input/output complex in the computer system. | 2009-06-18 |
| 20090158072 | System and Method to Identify Power Savings - A device includes an estimation module, a ratio module, and a recommendation module. The estimation module is adapted to receive a first performance level and a first power consumption level associated with a current server, and adapted to estimate a second performance level and a second power consumption level associated with a first target server based on the first performance level and the first power consumption level. The ratio module is adapted to determine a first performance ratio between the first performance level and the second performance level, and adapted to determine a first power consumption ratio between the first power consumption level and the second power consumption level. The recommendation module is adapted to determine whether to suggest a migration from the current server to the first target server based on the first performance ratio and the first power consumption ratio and adapted to output a first migration determination. | 2009-06-18 |
| 20090158073 | SELF-AWARE ADAPTIVE POWER CONTROL SYSTEM AND A METHOD FOR DETERMINING THE CIRCUIT STATE - The present invention provides a self-aware power control system and a method for determining the circuit state. The self-aware adaptive power control architecture comprises of a multi-mode power gating network, a current monitoring translator, a variable threshold comparator, a slack detector, and a bi-directional shift register. The multi-mode power gating network controls the amount of supply current and hence the circuit speed. The power gating network can be composed of either N-type MOSFETs for virtual ground insertion or P-type MOSFETs for virtual supply insertion. The number of MOSFETs in the multi-mode power gating network can be configured according to the supply range and step difference of the supply current. Then, by monitoring the current characteristics drained by target circuit, the circuit state can be determined. No delay matching circuit is required. Together with other peripherals, the supply current can be down controlled to a minimum acceptable level. The circuit will use up all available slack. The smaller current implies lower power consumption as well. Furthermore, the present invention is capable of self adaptation to frequency change. To summarize, the present invention can make the circuit consume least power under various frequency achieving best power efficiency. | 2009-06-18 |
| 20090158074 | CLUSTER SYSTEM WITH REDUCED POWER CONSUMPTION AND POWER MANAGEMENT METHOD THEREOF - Provided are a cluster system, which can reduce power consumption by controlling power at a cluster level according to loads, and a power management method of the cluster system. The cluster system includes a plurality of management target nodes for performing an actual task which the cluster system is supposed to perform, a load balancer/switch for distributing a user's request received through an external network into the management target nodes, and a power management master for monitoring a load of an entire system and performing a power management by controlling the load balancer/switch. The power management master classifies the management target nodes into a power on group and a power off group. | 2009-06-18 |
| 20090158075 | SYNCHRONIZATION OF INDEPENDENT CLOCKS - A system and method to synchronize independent local clocks in multi-core processing system are disclosed. A shared counter or a shared memory/file is provided to establish a partial happened-before relationship (e | 2009-06-18 |
| 20090158076 | TECHNIQUE TO IMPLEMENT CLOCK-GATING - A system and method for providing clock gating while reducing area and power on an integrated circuit (IC) chip. An array of registers or memory cells may have a single clock gating circuit, rather than multiple circuits such as one clock gating circuit for each bit of storage. The single clock gating circuit may be larger in size than each of the multiple clock gating circuits, but the single clock gating circuit may still have less capacitive loading. A reduction in overall allocated area allows floorplanning to offer less congested signal routing. Clock generation circuitry may be configured to provide a clock signal from a last ungated stage to clock enabling circuitry. A power reduction control unit may be configured to determine when the last ungated stage clock waveform is enabled/disabled within the clock gating circuitry. | 2009-06-18 |
| 20090158077 | Circuit and method for generation of duty cycle independent core clock - A disclosed embodiment is a circuit for producing a core clock from a system clock so that a core clock cycle is independent of a duty cycle of the system clock. The circuit comprises a system clock receiving sub-circuit for generating a first rising edge of the core clock, a core clock falling edge generation sub-circuit responsive to every rising edge of the core clock, and a self-triggering sub-circuit to trigger a second rising edge of the core clock so as to cause the core clock cycle to be independent of the system clock duty cycle. In one embodiment, the first core clock rising edge may be triggered in response to an initial system clock rising edge. In another embodiment, the first core clock rising edge may be triggered in response to an initial system clock falling edge. The core clock frequency may be twice the frequency of the system clock. | 2009-06-18 |
| 20090158078 | Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof - The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that includes a first digital circuit that operates at a first rate determined by a first clock signal and a second digital circuit that operates at a second rate determined by a second clock signal. The first digital circuit is coupled to the second digital circuit by a bus that is used for communications between the first digital circuit and the second digital circuit. A clock ratio controller is used to adjust the frequency of the first clock signal and/or the second clock signal in response to a power management signal without causing a loss of synchronization between the first digital circuit and the second digital circuit. | 2009-06-18 |
| 20090158079 | Fault information processing system and method for vehicle - The present invention relates to a fault information processing system and method for a vehicle, which can satisfy a short control cycle to thereby reduce the burden applied to the CPU and enables significant fault information (freeze frame) to be frozen. To this end, this invention features that the fault detection unit, the fault processing unit, the fault management unit having independent control cycles process all the faults occurred depending on a priority in such a fashion that fault-related data (freeze frame) is frozen immediately after the occurrence of a fault irrespective of the type of the occurred fault and the priority. Also, the fault management unit retrieves the occurred fault at an independent control cycle, combines the previously frozen fault-related data and the occurred fault, and stores corresponding fault information in a buffer unit. | 2009-06-18 |
| 20090158080 | STORAGE DEVICE AND DATA BACKUP METHOD - A storage device includes: a storage unit for storing data; a memory for storing management information; a local storage unit for storing differential data; a controller for controlling the storage device in accordance with a process comprising the steps of: updating data; updating management information; transmitting differential data to the another storage device, the differential data being the updated portions of the data which have been updated after preceding backing up of data until current backing up of data; resetting the management information after transmitting the differential data; storing, when the storage device fails transmission of the differential data to the another storage device, the differential data and the associated management information in the local storage unit; and transmitting the differential data to the another storage device at a later time after resetting of the management information. | 2009-06-18 |
| 20090158081 | Failover Of Blade Servers In A Data Center - Failover of blade servers in a data center including powering off a failing blade server by a system management server through a blade server management module (‘BSMM’) managing the failing blade server, the failing blade server characterized by a machine type, one or more network addresses, and one or more storage addresses, the addresses being virtual addresses; identifying, by the system management server from a pool of standby blade servers, a replacement blade server, the replacement blade server managed by a BSMM; assigning, by the system management server through the BSMM managing the replacement blade server, the one or more network addresses and the one or more storage addresses of the failing blade server to the replacement blade server, including enabling in the replacement blade server the assigned addresses; and powering on the replacement blade server by the system management server through the BSMM managing the replacement blade server. | 2009-06-18 |
| 20090158082 | FAILOVER IN A HOST CONCURRENTLY SUPPORTING MULTIPLE VIRTUAL IP ADDRESSES ACROSS MULTIPLE ADAPTERS - A host enables any adapter of multiple adapters of the host to concurrently support any VIPA of the multiple VIPAs assigned to the host. Responsive to a failure of at least one particular adapter from among the multiple adapters, the host triggers the remaining, functioning adapters to broadcast a separate hardware address update for each VIPA over the network, such that for a failover in the host supporting the multiple VIPAs the host directs at least one other host accessible via the network to address any new packets for the multiple VIPAs to one of the separate hardware addresses of one of the remaining adapters. | 2009-06-18 |
| 20090158083 | CLUSTER SYSTEM AND METHOD FOR OPERATING THE SAME - Provided are a cluster system, which makes general nodes appear as if they provide seamless services without failure when seen from the outside, and a method for operating the cluster system. The cluster system for operating individual nodes in a distributed management manner includes a board server having a task board registered with a task list, an agent server for managing the task board, and a plurality of general server nodes for performing a corresponding task on the basis of the task list, among which a failed general server node is replaced with another normal general server node. | 2009-06-18 |
