25th week of 2009 patent applcation highlights part 12 |
Patent application number | Title | Published |
20090152586 | LIGHT EMITTING DIODE HAVING ACTIVE REGION OF MULTI QUANTUM WELL STRUCTURE - Disclosed is a light emitting diode having an active region of a multi quantum well structure. The active region is positioned between GaN-based N-type and P-type compound semiconductor layers. At least one of barrier layers in the active region includes an undoped InGaN layer and a Si-doped GaN layer, and the Si-doped GaN layer is in contact with a well layer positioned at a side of the P-type compound semiconductor layer therefrom. Accordingly, carrier overflow and a quantum confined stark effect can be reduced, thereby improving an electron-hole recombination rate. Further, disclosed is an active region of a multi quantum well structure including relatively thick barrier layers and relatively thin barrier layers. | 2009-06-18 |
20090152587 | DEEP GUARD REGIONS FOR REDUCING LATCH-UP IN ELECTRONICS DEVICES - An embodiment of an integrated circuit includes a semiconductor layer, a well, first and second source/drain regions, and a guard region. The semiconductor layer has a first conductivity, and the well is disposed in the layer and has a second conductivity. The first source/drain region is formed in the well and has the first conductivity, and the second source/drain region is formed in the layer outside of the well and has the second conductivity. The guard region is disposed in the layer between the well and the second source/drain region and has the second conductivity. The guard region may prevent latch up by inhibiting the triggering of a silicon-controlled rectifier (SCR) having one of the first and second source/drain regions as an anode and the other of the first and second source/drain regions as a cathode. | 2009-06-18 |
20090152588 | ESD PROTECTION DEVICE IN HIGH VOLTAGE AND MANUFACTURING METHOD FOR THE SAME - An ESD protection device comprises a substrate of a first conductive type; a transistor formed in the substrate having an input terminal of the first conductive type, a control terminal of a second conductive type, and a ground terminal of the first conductive type; and a diode formed in the substrate having a first terminal of the first conductive type and a second terminal of the second conductive type, wherein the input terminal and the second terminal are coupled to an input, and the ground terminal and the first terminal are coupled to a ground. | 2009-06-18 |
20090152589 | Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors - A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the semiconductor bodies, wherein the common source region is coupled to all of the at least two semiconductor bodies, a common drain region formed on another end of the semiconductor bodies, wherein the common drain region is coupled to all of the at least two semiconductor bodies, and a common gate electrode formed over the at least two semiconductor bodies, wherein the common gate electrode provides a gate electrode for each of the at least two semiconductor bodies and wherein the common gate electrode has a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies. | 2009-06-18 |
20090152590 | METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM DEPOSITS - A method of forming a semiconductor device including forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium, and the second deposit having a second percentage of germanium that is less than the first percentage and supports forming a silicide deposit on the second deposit. A structure is also provided. | 2009-06-18 |
20090152591 | Design Structure for an On-Demand Power Supply Current Modification System for an Integrated Circuit - A design structure for a circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes and input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line. | 2009-06-18 |
20090152592 | STRUCTURE FOR A LATCHUP ROBUST ARRAY I/O USING THROUGH WAFER VIA - A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits. | 2009-06-18 |
20090152593 | STRUCTURE FOR A LATCHUP ROBUST GATE ARRAY USING THROUGH WAFER VIA - A structure, method and a design structure for preventing latchup in a gate array. The design structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well. | 2009-06-18 |
20090152594 | On-Demand Power Supply Current Modification System and Method for an Integrated Circuit - A circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes an input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line. | 2009-06-18 |
20090152595 | SEMICONDUCTOR DEVICES AND METHOD OF TESTING SAME - There are provided a semiconductor device having a pattern which allows electric failures to be sensitively detected at high speeds, and a method of testing the same. In one embodiment, the semiconductor device comprises a pair of row wires including a plurality of first wires arranged in a first layer at predetermined intervals in a row direction, where the first wires have ends connected to second wires arranged in a second layer at a predetermined intervals through vias, and the first wire and second wire are at the same potential. In the pair of row wires, a first wire positioned at a right end of one row wire is connected to a first conductor, and a first wire positioned at a left end in the other row wire is connected to a second conductor. By sequentially scanning the first conductor and second conductor using an electron beam, a change in the amount of emitted secondary electrons due to a difference in potential between these conductors is detected to detect electric anomalies. | 2009-06-18 |
20090152596 | SEMICONDUCTOR FET SENSOR AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor Field-Effect Transistor (FET) sensor and a method of fabricating the same. The method includes providing a semiconductor substrate, forming a sensor structure having a fin-shaped structure on the semiconductor substrate, injecting ions for electrical ohmic contact into the sensor structure, and depositing a metal electrode on the sensor structure, immobilizing a sensing material to be specifically combined with a target material onto both sidewall surfaces of the fin-shaped structure, and forming a passage on the sensor structure such that the target material passes through the fin-shaped structure. | 2009-06-18 |
20090152597 | BIOSENSOR AND METHOD OF MANUFACTURING THE SAME - Provided are a biosensor with a silicon nanowire and a method of manufacturing the same, and more particularly, a biosensor with a silicon nanowire including a defect region formed by irradiation of an electron beam, and a method of manufacturing the same. The biosensor includes: a silicon substrate; a source region disposed on the silicon substrate; a drain region disposed on the silicon substrate; and a silicon nanowire disposed on the source region and the drain region, and having a defect region formed by irradiation of an electron beam. Therefore, by irradiating a certain region of a high-concentration doped silicon nanowire with an electron beam to lower electron mobility in the certain region, it is possible to maintain a low contact resistance between the silicon nanowire and a metal electrode and to lower operation current of a biomaterial detection part, thereby improving sensitivity of the biosensor. | 2009-06-18 |
20090152598 | BIOSENSOR USING SILICON NANOWIRE AND METHOD OF MANUFACTURING THE SAME - Provided are a biosensor using a silicon nanowire and a method of manufacturing the same. The silicon nanowire can be formed to have a shape, in which identical patterns are continuously repeated, to enlarge an area in which probe molecules are fixed to the silicon nanowire, thereby increasing detection sensitivity. In addition, the detection sensitivity can be easily adjusted by adjusting a gap between the identical patterns of the silicon nanowire depending on characteristics of target molecules, without adjusting a line width of the silicon nanowire in the conventional art. Further, the gap between the identical patterns of the silicon nanowire can be adjusted depending on characteristics of the target molecule to differentiate detection sensitivities, thereby simultaneously detecting various detection sensitivities. | 2009-06-18 |
20090152599 | Silicon Germanium and Polysilicon Gate Structure for Strained Silicon Transistors - An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region. Depending upon the embodiment, the fill material can be any suitable species such as silicon germanium, silicon carbide, and others. | 2009-06-18 |
20090152600 | PROCESS FOR REMOVING ION-IMPLANTED PHOTORESIST - A method of manufacturing an IC that comprises fabricating a semiconductor device. Fabricating the device includes depositing a photoresist layer on a substrate surface and implanting one or more dopant species through openings in the photoresist layer into the substrate, and, into the photoresist layer, thereby forming an implanted photoresist layer. Fabricating the device also includes removing the implanted photoresist layer. Removing the implanted photoresist layer includes exposing the implanted photoresist layer to a mixture that includes sulfuric acid, hydrogen peroxide and ozone. The mixture is at a temperature of at least about 130°. | 2009-06-18 |
20090152601 | Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain - Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels. | 2009-06-18 |
20090152602 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a semiconductor device having a low-k film including an interconnect layer and a highly-reliable through-substrate contact plug. The semiconductor device includes:
| 2009-06-18 |
20090152603 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to an image sensor that may include transistors, a first dielectric, a crystalline semiconductor layer on and/or over the first dielectric, a photodiode, a dummy region, via contacts, and a second dielectric. A photodiode may be formed by implanting impurity ions into a crystalline semiconductor layer to correspond the pixel region. A dummy region may be formed in the crystalline semiconductor layer excepting a region for the photodiode. Via contacts may penetrate the dummy region, and may be connected to the first metal interconnections. A second dielectric may include a plurality of second metal interconnections on and/or over the crystalline semiconductor layer. The plurality of second metal interconnections may electrically connect the via contacts to the photodiode. | 2009-06-18 |
20090152604 | System and method for sensing image on CMOS - A system and method for sensing image on CMOS. According to an embodiment, the present invention provide a CMOS image sensing pixel. The pixel includes an n-type substrate, which includes a first width and a first thickness. The pixel also includes a p-type epitaxy layer overlying the n-type substrate. The p-type epitaxy layer includes a second width and a second thickness. The second width is associated with one or more characteristics of a colored light. The pixel additionally includes an n-type layer overlying the p-type epitaxy layer. The n-type layer is associated with a third width and a third thickness. Additionally, the pixel includes an pn junction formed between the p-type epitaxy layer and the n-type layer. Moreover, the pixel includes a control circuit being coupled to the CMOS image sensing pixel. | 2009-06-18 |
20090152605 | IMAGE SENSOR AND CMOS IMAGE SENSOR - An image sensor includes a carrier generating portion having a photoelectric conversion function, a voltage conversion portion for converting signal charges to a voltage, a charge increasing portion for increasing carriers generated by the carrier generating portion and a light shielding film formed to cover at least one part of the charge increasing portion. | 2009-06-18 |
20090152606 | Spin Transistor Using Epitaxial Ferromagnet-Semiconductor Junction - A spin transistor conducive to the miniaturization and large scale integration of devices, because a magnetization direction of a source and a drain is determined by a direction of the epitaxial growth of a ferromagnet. The spin transistor includes a semiconductor substrate having a channel layer formed thereinside; ferromagnetic source and drain epitaxially grown on the semiconductor substrate and magnetized in a longitudinal direction of the channel layer due to magnetocrystalline anisotropy—the source and drain being disposed spaced apart from each other in a channel direction and magnetized in the same direction—; and a gate disposed between the source and the drain to be insulated with the semiconductor substrate and formed on the semiconductor substrate to control the spin of electrons that are passed through the channel layer. | 2009-06-18 |
20090152607 | FERROELECTRIC STACKED-LAYER STRUCTURE, FIELD EFFECT TRANSISTOR, AND FERROELECTRIC CAPACITOR AND FABRICATION METHODS THEREOF - A ferroelectric stacked-layer structure is fabricated by forming a first polycrystalline ferroelectric film on a polycrystalline or amorphous substrate, and after planarizing a surface of the first ferroelectric film, laminating on the first ferroelectric film a second thin ferroelectric film having the same crystalline structure as the first ferroelectric film. A field effect transistor or a ferroelectric capacitor includes the ferroelectric stacked-layer structure as a gate insulating film or a capacitor film. | 2009-06-18 |
20090152608 | DRAM Cell Transistor Device and Method - A method for forming a memory device. The method provides a protective layer overlying a surface region of a substrate before threshold voltage implant. The method then includes depositing a photo resist layer and patterning the photo resist by selectively removing a portion of the photo resist to expose the protective layer overlying a first region while maintaining the photo resist overlying a second region. The method includes implanting impurities for threshold voltage adjustment into the first region while the second region is substantially free of the impurities for threshold voltage adjustment. The method also includes forming a source region and a drain region. The method further includes providing a conductive structure over the source region. A junction between the conductive structure and the source region is substantially within the second region. The method then provides a storage capacitor in electrical contact with the source region via the conductive structure. | 2009-06-18 |
20090152609 | Semiconductor integrated circuit device - A semiconductor integrated circuit device which is formed on an area comprises a first storage node which is formed on a first area having a first conductive type of the area, the first storage node having a first level, a second storage node which is formed on a second area having second conductive type of the area, the second storage node having a second level opposite to the first level and a well boundary which is sandwiched between the first area and the second area, wherein the second storage node has two diagonal lines, thereby, the first area having a first part sandwiched between the diagonal lines extended from the second storage node through the well boundary, and a second part which is the other part of the first part, wherein the first storage node is placed outside a region between the extended lines of two diagonal lines extending from the second storage node to the well boundary direction, and wherein the second storage node is placed outside a region between the extended lines of two diagonal lines extending from the first storage node to the well boundary direction. | 2009-06-18 |
20090152610 | SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data. | 2009-06-18 |
20090152611 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a first contact plug, a first structure and a second insulating layer, or comprises a first contact plug, a first structure, a protruding region and a second insulating layer. The first contact plug extends in a predetermined direction and including a step converting a cross section area of the first contact plug perpendicular to the predetermined direction discontinuously via the step in one end side. The second insulating layer is formed on side surface of a part of the first contact plug closer to the first structure than the step, or on side surfaces of the protruding region and a part of the first contact plug closer to the first structure than the step. | 2009-06-18 |
20090152612 | HIGH YIELD, HIGH DENSITY ON-CHIP CAPACITOR DESIGN - A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance. | 2009-06-18 |
20090152613 | SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING BODY CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked, a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region, and a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven. | 2009-06-18 |
20090152614 | NAND flash memory device having a contact for controlling a well potential - A NAND flash memory device includes a plurality of active regions extending in a first direction on a substrate, the active regions including a first well of a first conductivity, a plurality of word lines extending on the first well in a second direction perpendicular to the first direction, first and second dummy word lines extending in a second direction on the first well, the first and second dummy word lines being separated from each other to define an intermediate region therebetween, the first and second dummy word lines being adapted to receive a substantially constant bias voltage of about 0 V, and at least one contact in an active region in the intermediate region between the first and second dummy word lines. | 2009-06-18 |
20090152615 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to a semiconductor device that may include a floating gate, an inter poly dielectric formed on and/or over both sides of the floating gate in a bit line direction and on and/or over both side of the floating gate in a word line direction, and a control gate formed on and/or over the IPD. According to embodiments, an IPD may be formed on and/or over a top and four sides of a floating gate. This may increase a coupling ratio of a semiconductor device. | 2009-06-18 |
20090152616 | Semiconductor Device and Method for Manufacturing the Same - Disclosed are a semiconductor device and a method for manufacturing the same. The method includes forming a gate layer on a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; forming a second oxide layer on the first oxide layer; exposing the first oxide layer by removing the second oxide layer other than on side surfaces of the gate layer by etching using a photoresist as a mask; and forming junctions in source/drain regions by implanting a high concentration of N-type ions and/or a high concentration of P-type ions using the second oxide layer as a sidewall mask. | 2009-06-18 |
20090152617 | HETERO-STRUCTURE VARIABLE SILICON RICHNESS NITRIDE FOR MLC FLASH MEMORY DEVICE - Charge storage stacks containing hetero-structure variable silicon richness nitride for memory cells and methods for making the charge storage stacks are provided. The charge storage stack can contain a first insulating layer on a semiconductor substrate; n charge storage layers comprising silicon-rich silicon nitride on the first insulating layer, wherein numbers of the charge storage layers increase from the bottom to the top and a k-value of an n-1th charge storage layer is higher than a k-value of an nth charge storage layer; n-1 dielectric layers comprising substantially stoichiometric silicon nitride between each of the n charge storage layers; and a second insulating layer on the nth charge storage layers. | 2009-06-18 |
20090152618 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film, an intermediate insulating film formed on the first silicon oxide film and having a relative permittivity of not less than 7, and a second silicon oxide film formed on the intermediate insulating film. A charge trap layer is formed at least in either first or second silicon oxide film or a boundary between the first silicon oxide film and the intermediate insulating film or a boundary between the second silicon oxide film and the intermediate insulating film. | 2009-06-18 |
20090152619 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down. | 2009-06-18 |
20090152620 | ATOMIC LAYER DEPOSITION OF GdScO3 FILMS AS GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd | 2009-06-18 |
20090152621 | NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION - A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. The gate stack includes a high dielectric constant blocking region. | 2009-06-18 |
20090152622 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region having a channel region, and containing silicon as a main component, second semiconductor regions sandwiching the first semiconductor region, formed of SiGe, and applying stress to the first semiconductor region, cap layers provided on the second semiconductor regions, and formed of silicon containing carbon or SiGe containing carbon, and silicide layers provided on the cap layers, and formed of nickel silicide or nickel-platinum alloy silicide. | 2009-06-18 |
20090152623 | FIN TRANSISTOR - A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode. | 2009-06-18 |
20090152624 | INTEGRATED CIRCUIT DEVICE WITH A SEMICONDUCTOR BODY AND METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT DEVICE - An integrated circuit device with a semiconductor body and a method for the production of a semiconductor device a provided. The semiconductor body comprises a cell field with a drift zone of a first conduction type. In addition, the semiconductor device comprises an edge region surrounding the cell field. Field plates with a trench gate structure are arranged in the cell field, and an edge trench surrounding the cell field is provided in the edge region. The front side of the semiconductor body is in the edge region provided with an edge zone of a conduction type complementing the first conduction type with doping materials of body zones of the cell field. The edge zone of the complementary conduction type extends both within and outside the edge trench. | 2009-06-18 |
20090152625 | Recessed channel transistor - A recessed channel transistor includes a single crystalline silicon substrate having a recessed portion, a bottom surface of the recessed portion including an elevated central portion, a channel doping region in the single crystalline silicon substrate, the channel doping region being under the bottom surface of the recessed portion, a gate structure in the recessed portion, and source/drain regions in the single crystalline silicon substrate at both sides of the recessed portion, the source/drain regions being spaced apart from the bottom surface of the recessed portion. | 2009-06-18 |
20090152626 | Super Halo Formation Using a Reverse Flow for Halo Implants - Shrinking dimensions of MOS transistors in integrated circuits requires tighter distributions of dopants in pocket regions from halo ion implant processes. In conventional fabrication process sequences, halo dopant distributions spread during source/drain anneals. The instant invention is a method of fabricating MOS transistors in an integrated circuit in which halo ion are performed after source/drain anneals. In the inventive method, source/drain spacers on MOS gate sidewalls are removed prior to halo ion implant processes. Spacers to offset metal silicide are formed after halo implants and may be of low-k dielectric material to reduce gate to drain capacitance. A compressive stress layer may be deposited on MOS gates after source/drain spacers are removed for greater stress transfer efficiency to the MOS gates. An integrated circuit embodying the inventive method is also disclosed. | 2009-06-18 |
20090152627 | SEMICONDUCTOR DEVICE - This invention is directed to offer a MOS transistor that has a high source-drain breakdown BVds, a low on resistance and a high electric current driving capacity. On resistance is lowered by forming an N well layer for lowering on resistance in the drift region. The N well layer is disposed beneath the gate electrode and away from the N well layer with a certain space between them. This space ensures the withstand voltage at the edge of the gate electrode of the drain layer side. Also, the N well layer is formed on the surface of an epitaxial layer in the region that includes a P+L layer. The edge of the N well layer of the drain layer side is located near the edge of the P+L layer of the drain layer side and away from the N well layer. This space makes the expansion of depletion layer from the P+L layer easier, further improving the withstand voltage. | 2009-06-18 |
20090152628 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - It is desirable to reduce chip area, lower on resistance and improve electric current driving capacity of a DMOS transistor in a semiconductor device with a DMOS transistor. On the surface of an N type epitaxial layer, a P+W layer of the opposite conductivity type (P type) is disposed and a DMOS transistor is formed in the P+W layer. The epitaxial layer and a drain region are insulated by the P+W layer. Therefore, it is possible to form both the DMOS transistor and other device element in a single confined region surrounded by an isolation layer. An N type FN layer is disposed on the surface region of the P+W layer beneath the gate electrode. An N+D layer, which is adjacent to the edge of the gate electrode of the drain layer side, is also formed. P type impurity layers (a P+D layer and a FP layer), which are located below the drain layer, are disposed beneath the contact region of the drain layer. | 2009-06-18 |
20090152629 | METHODS OF SELECTIVELY OXIDIZING SEMICONDUCTOR STRUCTURES, AND STRUCTURES RESULTING THEREFROM - Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed. | 2009-06-18 |
20090152630 | SEMICONDUCTOR DEVICE USING SOI-SUBSTRATE - According to a feature of the present invention, a semiconductor device includes a SOI substrate, including a semiconductor substrate; an insulating layer formed on the semiconductor substrate and a silicon layer formed on the insulating layer. A drain region and a source region are formed in the silicon layer so that the source region is in contact with the insulating layer but the drain region is not in contact with the insulating layer. | 2009-06-18 |
20090152631 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal, and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 μm or less in width, and allowing the metal to react with silicon. | 2009-06-18 |
20090152632 | LATCHUP ROBUST ARRAY I/O USING THROUGH WAFER VIA - A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits. | 2009-06-18 |
20090152633 | Semiconductor device - In a semiconductor device including, between an external connection terminal and an internal circuit region, an NMOS transistor for ESD protection having a gate potential fixed to a ground potential, the external connection terminal is formed above a drain region of the NMOS transistor for ESD protection, and the drain region is surrounded by a source region through a channel region. Further, the drain region has a shape with rounded corners in plan view. | 2009-06-18 |
20090152634 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of forming a semiconductor device comprises forming a control electrode over a portion of a semiconductor layer, forming recesses extending into the semiconductor layer on opposing sides of the control electrode, and forming doped regions in the semiconductor layer through the recesses. The doped regions form current electrode regions of the semiconductor device and each doped region extends into the semiconductor layer from at least a base of a recess. The method further comprises forming, after forming the doped regions, strained semiconductor regions in the recesses, wherein a junction between each doped region and the semiconductor layer is formed below an interface between a strained semiconductor region and the semiconductor layer. | 2009-06-18 |
20090152635 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING A DISPLAY PANEL - Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved. | 2009-06-18 |
20090152636 | HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS - Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal. | 2009-06-18 |
20090152637 | PFET WITH TAILORED DIELECTRIC AND RELATED METHODS AND INTEGRATED CIRCUIT - A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer. | 2009-06-18 |
20090152638 | DUAL OXIDE STRESS LINER - A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor. | 2009-06-18 |
20090152639 | Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement - Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instabilty (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed. | 2009-06-18 |
20090152640 | Semiconductor Device and Manufacturing Process Therefor - This invention provides a semiconductor device that can prevent a deviation of work function by adopting a gate electrode having a uniform composition and exhibits excellent operating characteristics by virtue of effective control of a V | 2009-06-18 |
20090152641 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING - A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type transistor and a drain of the first p-type transistor; and a second wiring layer having a first conductive portion electrically connected to the first interconnecting portion. | 2009-06-18 |
20090152642 | SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-k DIELECTRICS - The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric. | 2009-06-18 |
20090152643 | Semiconductor structures - A semiconductor structure is provided. The semiconductor structure comprises a substrate, a first metal-oxide-semiconductor (MOS), a second MOS, a first semiconductor region, and a second semiconductor region. The first and the second MOSs are formed on the substrate. The first semiconductor region is formed between the substrate and the first MOS. The second semiconductor region is formed between the substrate and the second MOS. The first semiconductor region and the second semiconductor region isolate the first MOS from the second MOS. | 2009-06-18 |
20090152644 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n | 2009-06-18 |
20090152645 | METHODS FOR ISOLATING PORTIONS OF A LOOP OF PITCH-MULTIPLIED MATERIAL AND RELATED STRUCTURES - Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other. | 2009-06-18 |
20090152646 | Structure and method for manufacturing device with planar halo profile - A semiconductor device and method for manufacturing the device with a planar halo profile is provided. The semiconductor device can be a MOSFET. The method of forming the structure includes forming an angled spacer adjacent a gate structure and implanting a halo implant at an angle to form a halo profile having low dopant concentration near a gate dielectric under the gate structure. The structure includes an underlying wafer or substrate and an angled gate spacer having an upper portion and an angled lower portion. The upper portion is structured to prevent halo dopants from penetrating an inversion layer of the structure. The structure further includes a low concentration halo dopant within a channel of a gate structure. | 2009-06-18 |
20090152647 | FIELD-EFFECT TRANSISTOR INCLUDING LOCALIZED HALO ION REGIONS, AND SEMICONDUCTOR MEMORY, MEMORY CARD, AND SYSTEM INCLUDING THE SAME - A field-effect transistor including localized halo ion regions that can optimize HEIP characteristics and GIDL characteristics. The field-effect transistor includes a substrate, an active region, a gate structure, and halo ion regions. The active region includes source/drain regions and a channel region formed at a partial region in the substrate. The gate structure electrically contacts the active region. The halo ion regions are locally formed adjacent to both end portions of the source/drain regions in the substrate. | 2009-06-18 |
20090152648 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a gate electrode that includes a body part disposed on the semiconductor substrate and a projecting part projecting downward from the body part; and source/drain regions at opposite sides of the gate electrode. | 2009-06-18 |
20090152649 | Semiconductor Device of Multi-Finger Type - Provided is a semiconductor device of a multi-finger type. The semiconductor device comprises an active region, a guard ring, a source electrode, at least one gate electrode, and at least one drain electrode. The active region includes a source region, a drain region, and a channel region. The guard ring surrounds the active region. The source electrode is connected to the guard ring and a bulk region. The source electrode includes electrode bodies disposed on a first side of the active region and a second side of the active region opposite the first side, and fingers connecting the two electrode bodies to branch through the source region. The gate electrode can be provided in plurality as fingers on the channel region. One or more gate electrode fingers can be connected to each other through a set of vias. The drain electrode can be provided in plurality as fingers branching on the drain region. | 2009-06-18 |
20090152650 | HIGH-K DIELECTRIC AND METAL GATE STACK WITH MINIMAL OVERLAP WITH ISOLATION REGION AND RELATED METHODS - A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions. | 2009-06-18 |
20090152651 | GATE STACK STRUCTURE WITH OXYGEN GETTERING LAYER - A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate, and a high-k dielectric layer (having a dielectric constant above 4.0) contacting (on) the interface layer. A Nitrogen rich first metal Nitride layer contacts (is on) the dielectric layer, and a metal rich second metal Nitride layer contacts (is on) the first metal Nitride layer. Finally, a Polysilicon cap contacts (is on) the second metal Nitride layer. | 2009-06-18 |
20090152652 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment. | 2009-06-18 |
20090152653 | Surface mount multi-axis electronics package for micro-electrical mechanical systems(MEMS) devices - A surface mount multi-axis cavity package for micro-electrical mechanical systems (MEMS) devices includes a substantially cubical housing having a plurality of sides and at least one internal cavity. A first plurality of solder pads are positioned on at least one side of the housing and a second plurality of solder pads are positioned on a bottom of the housing. A MEMS sensor is then mounted within the at least one internal cavity in any axis for increasing the versatility of the MEMS device. | 2009-06-18 |
20090152654 | MICROMECHANICAL SYSTEM - A micromechanical system includes a substrate, a first planar electrode, a second planar electrode, and a third planar electrode. The second planar electrode is movably positioned at a distance above the first planar electrode and the third planar electrode is positioned at a distance above the second electrode. | 2009-06-18 |
20090152655 | MEMS DEVICE - A method of fabricating a micro-electrical-mechanical system (MEMS) apparatus on a substrate ( | 2009-06-18 |
20090152656 | SENSOR DEVICE AND PRODUCTION METHOD THEREFOR - A compact sensor device having stable sensor characteristics and the production method are provided. The sensor device is formed with a sensor substrate and a pair of package substrates bonded to both surface of the sensor substrate. The sensor substrate has a frame with an opening, a movable portion held in the opening to be movable relative to the frame, and a detecting portion for outputting an electric signal according to a positional displacement of the movable portion. Surface-activated regions are formed on the frame of the sensor substrate and the package substrates by use of an atomic beam, an ion beam or a plasma of an inert gas. By forming a direct bonding between the surface-activated regions of the sensor substrate and each of the package substrates at room temperature, it is possible to avoid inconvenience resulting from residual stress at the bonding portion. | 2009-06-18 |
20090152657 | MAGNETIC FIELD DETECTOR - Disclosed is a magnetic field detector having various structures that can be used as a high-density magnetic biosensor. An embodiment of the invention provides a magnetic field detector using a thin film for detecting magnetic beads. The magnetic field detector includes: a substrate; a magnetoresistive element that is formed on an upper surface of the substrate in a ring shape using the thin film; electrodes that are formed on the upper surface of the substrate to be connected to the magnetoresistive element; a protective layer that is formed on the magnetoresistive element and the electrodes; and a magnetic bead limiting layer that is formed on an upper surface of the protective layer to cover the entire surface of the magnetoresistive element and portions of the electrodes. | 2009-06-18 |
20090152658 | METHODS OF PACKAGING IMAGER DEVICES AND OPTICS MODULES, AND RESULTING ASSEMBLIES - A method of packaging imager devices and optics modules is disclosed which includes positioning an imager device and an optics module in each of a plurality of openings in a carrier body, introducing an encapsulant material into each of the openings in the carrier body and cutting the carrier body to singulate the plurality of imager devices and optics modules into individual units, each of which comprise an imager device and an optics module. A device is also disclosed which includes an imager device comprising a plurality of photosensitive elements and an optics module coupled to the imager device, the optics module comprising at least one lens that, when the optics module is coupled to the imager device, is positioned a fixed, non-adjustable distance from the plurality of photosensitive elements. | 2009-06-18 |
20090152659 | REFLOWABLE CAMERA MODULE WITH IMPROVED RELIABILITY OF SOLDER CONNECTIONS - A reflowable camera module has a set of solder joints formed on a bottom surface of the camera module that provide electrical signal and power connections between the camera module and a printed circuit substrate. The solder joints are susceptible to failure caused by shear forces, particularly in corner regions. Additional localized mechanical supports are provided to protect those solder joints carrying power and electrical signals for the camera module. The localized mechanical supports are formed outside of a region containing the solder joints carrying power and electrical signals. The localized mechanical supports may include dummy solder joints formed in corner regions and/or dummy leads used to support the camera module. Solder joint reliability is enhanced without requiring the use of an underfill encapsulant. | 2009-06-18 |
20090152660 | Photomask, Image Sensor, and Method of Manufacturing the Image Sensor - Provided are a photomask, an image sensor, and a method of manufacturing the image sensor. The image sensor can include photodiode structures, color filters, a planarization layer, and microlenses. The photodiode structures can be disposed on a semiconductor substrate according to unit pixel. The color filters can be disposed on the semiconductor substrate in a matrix arrangement above the photodiode structures. The planarization layer can cover the entire semiconductor substrate and includes cavities in regions of the planarization layer corresponding to boundaries between the color filters. The cavities may be arranged at boundaries between unit pixels. The microlenses can be disposed on the planarization layer such that portions of the microlenses are arranged in the cavities of the planarization layer. | 2009-06-18 |
20090152661 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing the image sensor includes: forming a photoresist layer on a surface of an image sensor; exposing and developing the photoresist layer using a mask used for fabricating a plurality of micro-lenses, which has a number of first light shielding patterns aligned apart from one another and a number of second light shielding patterns, each being formed at a part, on which four adjacent edges of the first light shielding patterns are centered, so that a photoresist pattern is formed; and reflowing the photoresist pattern to fabricate a plurality of micro-lenses and a concave lens at each part, on which four adjacent edges of the micro-lenses are centered. | 2009-06-18 |
20090152662 | MICRO-SENSOR AND MANUFACTURING METHOD THEREOF - The micro-sensor for a micro image pick-up device includes a flexible circuit board and a circuit substrate. The flexible circuit board has an opening exposing an end of a plurality of metal wires. An image sensing device that electrically connected to a plurality of printed wires disposed on the circuit substrate. The circuit substrate is disposed at the opening of the flexible circuit board. The plurality of printed wires on the circuit substrate corresponds to and contacts the end of the plurality of metal wires exposed out of the flexible circuit board. With the design of the flexible circuit board, the steps of forming a plurality of wiring ducts on the circuit substrate and electrically connecting the printed wires of the circuit substrate by a plurality of connecting lines for transferring signals can be omitted. | 2009-06-18 |
20090152663 | Perforated silicon plate assembly for forming and transferring of silicon thin film solar cells - A perforated monocrystalline silicon plate assembly is provided for forming and transferring of monocrystalline silicon thin film solar cells. The assembly comprises a perforated monocrystalline silicon plate with a plurality of through holes and obstructive holes. The assembly is allowed to grow a first p-type epitaxial layer with an inverted pyramid surface on the surface of the silicon plate, which is then selectively converted into a porous silicon layer with an inverted pyramid surface. The assembly is further allowed to grow a second p-type epitaxial layer with an inverted pyramid surface on the surface of the porous silicon layer, which is then used to fabricate a monocrystalline silicon thin film solar cell with an inverted pyramid surface. The assembly further comprises a transferring means for chemically etching of the porous silicon layer so as to transfer the silicon solar cell onto a transparent plate and reuse the assembly for next forming and transferring of a monocrystalline silicon thin film solar cell. The perforated silicon plate assembly can be reused for forming and transferring of a monocrystalline silicon thin film solar cell infinite times. A method for fabricating the assembly mainly comprises steps: performing deep reactive ion etching of a monocrystalline silicon plate to form a plurality of through holes and obstructive holes; growing a first p-type silicon epitaxial layer with an inverted pyramid surface; performing anodization for selectively converting the epitaxial layer into a porous silicon layer with an inverted pyramid surface; growing a second p-type epitaxial layer with an inverted pyramid surface on the surface of the porous silicon layer, fabricating a monocrystalline silicon thin film solar cell with an inverted pyramid surface using the second monocrystalline silicon epitaxial layer; and chemically etching the porous silicon layer for transferring the silicon solar cell onto a transparent plate. | 2009-06-18 |
20090152664 | Materials, Systems and Methods for Optoelectronic Devices - A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer. | 2009-06-18 |
20090152665 | FABRICATING METHODS OF PHOTOELECTRIC DEVICES AND PACKAGE STRUCTURES THEREOF - The invention discloses a method for fabricating a photoelectric device. A ceramic substrate is first provided, and then a first patterned electrode and a second patterned electrode are formed on and underneath the surface of the ceramic substrate. A plurality of photoelectric devices is sequentially connected to the first electrode layer with a wire solder or a eutectic joint method. The encapsulation materials cover the each photoelectric die to prevent damaged from the external force or environment. Cutting the ceramic substrate along the spaces between the photoelectric dies forms a plurality of independent package units. | 2009-06-18 |
20090152666 | THERMOELECTRIC SEMICONDUCTOR DEVICE - A thermoelectric semiconductor device includes a plurality of alternating P-type and N-type semiconductor elements disposed between first and second ceramic layers, first conductor elements attached to the first ceramic layer and interconnecting cold junctions of the P-type and N-type semiconductor elements, and second conductor elements attached to the second ceramic layer and interconnecting hot junctions of the P-type and N-type semiconductor elements. A thermal insulation material made from ammonium phosphate is filled in gaps between the first and second ceramic layers and the P-type and N-type semiconductor elements so that the temperature difference between the hot and cold junctions can be maximized | 2009-06-18 |
20090152667 | Semiconductor with active component and method for manufacture - A semiconductor with active component and method for manufacture. One embodiment provides a semiconductor component arrangement having an active semiconductor component and a semiconductor body having a first semiconductor zone, a third semiconductor zone, and also a drift zone arranged between the first semiconductor zone and the third semiconductor zone. A patterned fourth semiconductor zone doped complementarily to the drift zone is arranged in the drift zone. A potential control structure is provided, which is connected to the patterned fourth semiconductor zone. The potential control structure is designed to connect the patterned fourth semiconductor zone, in the off state of the semiconductor component, to an electrical potential lying between the electrical potential of the first semiconductor zone and the electrical potential of the third semiconductor zone. | 2009-06-18 |
20090152668 | Semiconductor apparatus - A semiconductor apparatus is disclosed. The semiconductor apparatus includes an SOI substrate including an active layer, a buried insulation film and a support substrate; a low potential reference circuit part located in the active layer and operable at a first reference potential; a high potential reference circuit part located in the active layer and operable at a second reference potential; a level-shifting element forming part located in the active layer and for providing a level-shift between the first and second reference potentials; and an insulation member insulating first and second portions of the support substrate from each other, wherein locations of the first and second portions respectively correspond to the low and high potential reference circuit parts. | 2009-06-18 |
20090152669 | SI TRENCH BETWEEN BITLINE HDP FOR BVDSS IMPROVEMENT - Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss. | 2009-06-18 |
20090152670 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same includes a semiconductor substrate including a first trench; an epitaxial layer disposed on and/or over the semiconductor substrate and including a second trench connected to the first trench; a first insulator disposed in the first trench; and a second insulator disposed in the second trench. | 2009-06-18 |
20090152671 | METHOD FOR MANUFACTURING SIMOX WAFER AND SIMOX WAFER - This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and an implanting of oxygen ions so as to form an amorphous layer; and subjecting the silicon wafer to a heat-treating in a mixed gas atmosphere containing oxygen so as to form a buried oxide layer. In the forming of the buried oxide layer, a starting temperature is less than 1350° C. and a maximum temperature is 1350° C. or more. This SIMOX wafer is manufactured by the above method and includes a BOX layer and a SOI layer on the BOX layer. The BOX layer has a thickness of 1300 Å or more and a breakdown voltage of 7 MV/cm or more, and the surface of the SOI layer and the interface between the SOI layer and the BOX layer have a roughness over a 10-μm square area of 4 Å rms or less. | 2009-06-18 |
20090152672 | Semiconductor Devices and Methods of Manufacture Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner. | 2009-06-18 |
20090152673 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is formed on the buried insulating layer. A first insulating layer is formed to enclose the silicon pattern. | 2009-06-18 |
20090152674 | Semiconductor device - A semiconductor device contains a semiconductor substrate, an insulating film formed on the semiconductor substrate, an inductor formed over the semiconductor substrate while placing a portion of the insulating film in between, and a guard ring surrounding the inductor in a plan view, and isolating the inductor from other regions, wherein the guard ring contains an annular impurity diffused layer provided in the surficial portion of the semiconductor substrate, and an annular electro-conductor connected to the impurity diffused layer, and extended across a plurality of interconnect layers, up to a layer having a level of height not lower than the layer having the inductor provided therein. | 2009-06-18 |
20090152675 | INDUCTOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device having a first region formed with the inductor and a second region formed with transistors, the inductor includes a deep well region formed in the silicon substrate beneath the first and second regions, a well region formed on the deep well region in the second region, N type shield regions formed to have the same depth as the well region, and P type shield regions arranged to alternate with the N type shield regions, the transistors formed on the silicon substrate in the second region, an insulating film formed over an entire surface of the silicon substrate such that the insulating film covers the transistors, and a metal line formed on the insulating film in the first region such that the metal line corresponds to the N and P type shield regions. | 2009-06-18 |
20090152676 | ELECTRONIC DEVICE INCLUDING AN INDUCTOR - An electronic device can include an inductor overlying a shock-absorbing layer. In one aspect, the electronic device can include a substrate, an interconnect level overlying the substrate, and the shock-absorbing layer overlying the interconnect level. The inductor can include conductive traces and looped wires. The conductive traces can be attached to the conductive traces over the shock-absorbing layer. In another aspect, a process can be used to form the electronic device including the inductor. In still another aspect, an electronic device can a toroidal-shaped inductor that includes linear inductor segments that are connected in series. | 2009-06-18 |
20090152677 | Semiconductor device and method for manufacturing semiconductor device - A semiconductor device including: a conducting plug provided in an interlayer insulating film over a semiconductor substrate; and a capacitor including a lower electrode provided over the conducting plug, the lower electrode being connected to the conducting plug, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film. The lower electrode includes a conducting pillar and a conducting outer layer provided over at least a circumferential side surface of the conducting pillar. The dielectric film covers at least a circumferential side surface of the lower electrode, and is contact with the conducting outer layer. | 2009-06-18 |
20090152678 | CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A capacitor includes a first lower metal layer and an insulating layer on a lower interlayer dielectric layer of a semiconductor substrate; a first upper metal layer aligned on the insulating layer to partially expose it; a first capping layer and an upper interlayer dielectric layer on the insulating layer including the first upper metal layer; a second lower metal layer connected to the first upper metal layer through the upper interlayer dielectric layer and the first capping layer; a second capping layer aligned on the upper interlayer dielectric layer including the second lower metal layer and formed with a hole for partially exposing the second lower metal layer; a pad aligned on the second capping layer and connected to the second lower metal layer; a protective layer on the second capping layer; and a second upper metal layer aligned on the second capping layer. | 2009-06-18 |
20090152679 | SEMICONDUCTOR DEVICE - A metal electrode is disposed on each of a plurality of resistor groups which are made of polycrystalline silicon resistors and constitute a resistor circuit. The metal electrode is connected to an end of the resistor via another interconnecting layer. Accordingly, the external influence which the metal electrode receives during a semiconductor manufacturing process is prevented from directly acting on the resistor, whereby resistance variation is suppressed. | 2009-06-18 |
20090152680 | ELECTROSTATIC DISCHARGE PROTECTION FOR BIPOLAR SEMICONDUCTOR CIRCUITRY - Multiple emitter-base regions arc formed on a single contiguous collector. The multiple emitter-base regions are cascoded such that the base of one emitter-base region is directly wired to the emitter of an adjacent emitter-base region. An electrostatic discharge (ESD) protection unit, comprising a single collector and multiple emitter-base regions, provides protection against an ESD event of one type, i.e., a positive or negative voltage surge. The inventive ESD protection structure comprises a parallel connection of two ESD protection units, each providing a discharge path for electrical charges of opposite types, and provides ESD protection for both types of voltage swing in the circuit. | 2009-06-18 |
20090152681 | NANO-MULTIPLICATION REGION AVALANCHE PHOTODIODES AND ARRAYS - An avalanche photodiode with a nano-scale reach-through structure comprising n-doped and p-doped regions, formed on a silicon island on an insulator, so that the avalanche photodiode may be electrically isolated from other circuitry on other silicon islands on the same silicon chip as the avalanche photodiode. For some embodiments, multiplied holes generated by an avalanche reduces the electric field in the depletion region of the n-doped and p-doped regions to bring about self-quenching of the avalanche photodiode. Other embodiments are described and claimed. | 2009-06-18 |
20090152682 | LINE ELEMENT AND METHOD OF MANUFACTURING LINE ELEMENT - An element capable of manufacturing various devices of any shape having plasticity or flexibility without being limited by shape and a method for manufacturing thereof are provided. An element characterized by that a circuit element is formed continuously or intermittently in the longitudinal direction. An element characterized by that a cross section having a plurality of areas forming a circuit is formed continuously or intermittently in the longitudinal direction. | 2009-06-18 |
20090152683 | ROUNDED DIE CONFIGURATION FOR STRESS MINIMIZATION AND ENHANCED THERMO-MECHANICAL RELIABILITY - One aspect of the invention pertains to a semiconductor die with rounded sidewall junction edge corners. Such rounding reduces stress accumulations at those corners. In other embodiments of the invention, the sharpness of other corners and edges in the die are reduced. For example, reducing the sharpness of the bottom edge corners formed by the intersection of a sidewall and the back surface of a die can further diminish stress accumulations. One embodiment pertains to a wafer carried on a wafer support, where the wafer includes a multiplicity of such dice. Another embodiment involves a semiconductor package containing such dice. Methods of fabricating the dice are also described. | 2009-06-18 |
20090152684 | MANUFACTURE-FRIENDLY BUFFER LAYER FOR FERROELECTRIC MEDIA - The present invention describes a method including: providing a substrate; forming a buffer layer epitaxially over the substrate with a manufacture-friendly process; forming a bottom electrode epitaxially over the buffer layer; and forming a ferroelectric layer epitaxially over the bottom electrode. | 2009-06-18 |
20090152685 | EPITAXIAL WAFER AND METHOD OF PRODUCING THE SAME - An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon lattices. | 2009-06-18 |