24th week of 2010 patent applcation highlights part 22 |
Patent application number | Title | Published |
20100148780 | SYSTEM AND METHOD FOR QUALITATIVE AND QUANTITATIVE ANALYSIS OF GASEOUS COMPONENTS OF MULTIPHASE HYDROCARBON MIXTURES - Embodiments of the present invention provide systems and methods for detection and/or measurement of gaseous components of multiphase mixtures containing one or more hydrocarbons that may be retrieved down a wellbore or may be being transported in a pipeline. More specifically, but not by way of limitation, embodiments of the present invention may provide for separation of the gaseous components from the multiphase mixtures and detection and/or measurement of the separated gaseous components by direct oxidation or reduction. | 2010-06-17 |
20100148781 | RECTANGULAR-WAVE TRANSMITTING METAL DETECTOR - A metal detector including transmit electronics having a plurality of switches for generating a repeating transmit signal cycle for transmission by a transmit coil. The repeating transmit signal cycle includes at least a high voltage period, and at least a low voltage period, the low voltage period followed by a substantially zero voltage period. The output impedance of the transmit electronics is less than three times the equivalent series resistance of the transmit coil during the low voltage period and the substantially zero voltage period. | 2010-06-17 |
20100148782 | RUGGED QUARTZ CLOCK - A resonator clock suitable for use in downhole conditions is described. The resonator clock includes a resonator portion of piezoelectric material; two electrodes in electrical communication with the resonator portion such that the resonator portion resonates when voltage is applied between the two electrodes; and four supports to support the resonator portion. The supports are dimensioned and positioned to support the resonator portion under shock and vibration encountered in downhole use. The supports and the resonator portion are formed from the same continuous piece of piezoelectric material. | 2010-06-17 |
20100148783 | MULTI-COMPONENT MARINE ELECTROMAGNETIC SIGNAL AQUISITION CABLE AND SYSTEM - A marine electromagnetic sensor cable includes a plurality of sensor modules disposed at spaced apart locations along a cable. Each module includes at least one pair of electrodes associated therewith. The electrodes are arranged to measure electric field in a direction along the direction of the cable. A plurality of spaced apart magnetic field sensors is associated with each module and arranged to enable determining an electric field amplitude in a direction transverse to the direction of the cable from magnetic field gradient. | 2010-06-17 |
20100148784 | METHOD OF PROCESSING MARINE CSEM DATA - A method is provided for processing marine controlled source electromagnetic data. Inline and broadside marine controlled source electromagnetic data are provided, for example by means of one or more horizontal electric dipoles and one or more receivers disposed in a water column above a subsurface to be surveyed. A linear combination of the inline and broadside data is formed so as to reduce the airwave content. | 2010-06-17 |
20100148785 | APPARATUS AND METHOD FOR EVALUATING DOWNHOLE FLUIDS - An apparatus for evaluating downhole fluids is disclosed. The apparatus includes: an optical block having an adjustable opening that receives electromagnetic energy emitted by an electromagnetic energy source; a controller operatively associated with the optical block for adjusting the opening size, wherein the opening size is adjusted at least in part based on one or more estimated downhole parameters; and a sensor that receives the electromagnetic energy emitted by the electromagnetic energy source after the emitted electromagnetic energy interacts with a downhole fluid. A method for evaluating downhole fluids is also disclosed. | 2010-06-17 |
20100148786 | METHOD AND DEVICE FOR CARRYING OUT MARINE ELECTRICAL EXPLORATION DURING A SHIP TRAVEL - The inventive method for reducing a noise effect during a ship travel consists in generating direct current pulses, the parameters of which are set up according to a section conductivity and the depth of a formation, in simultaneously measuring the electric field on pairs of receiving electrodes on the basis of the space average of a double electric layer potential originated at the electrode-water interface during the pulses and intervals therebetween and in determining geoelectrical parameters. The inventive device comprises a unit for forming an exciting field, in which a switchboard generates pulses on feeding electrodes and a generator consists of two mutually parallel cable lines with emitting electrodes, a nonradiative dummy device in the form of a pair of opposite electric dipoles having equal moments and a measuring unit with pairs of sectional receiving electrodes, wherein the total length of the electrode section is equal to or less than 5% the interelectode distance and the communication between the electrode elements connected to a receiving line via a common input/output makes it possible to add electromotive forces generated therein. | 2010-06-17 |
20100148787 | High Frequency or Multifrequency Resistivity Tool - A system and method for determining material resistivity. A current of one or more frequencies is generated using a circuitry ( | 2010-06-17 |
20100148788 | High Resolution Voltage Sensing Array - An apparatus and method for performing high transverse resolution voltage measurements in downhole logging tools utilized to determine the resistivity of an adjacent portion of a borehole wall Two current electrodes | 2010-06-17 |
20100148789 | System for Measuring the Electric Potential of a Voltage Source - A non-invasive measurement system ( | 2010-06-17 |
20100148790 | METHOD AND DEVICE FOR CHARACTERISING SENSITIVITY TO ENERGY INTERACTIONS IN AN ELECTRONIC COMPONENT - To analyse an electric component in depth, provision is made to submit said component to focused laser radiation. It is shown that by modifying the altitude of the focus in the component, some internal parts of said component can be characterized more easily. | 2010-06-17 |
20100148791 | WIRE FAULT LOCATING IN DISTRIBUTED POWER SYSTEMS - An electrical fault locating system for distributing power from an input to a plurality of output channels provides fault detection and locating for each of the plurality of output channels. Each of the plurality of output channels is monitored by a fault detection circuit to detect the presence of an electrical fault. In response to a detected fault condition, the fault detection circuit isolates the output channel from the input and generates an output identifying the output channel on which the fault was detected. A fault locating device injects a high-frequency (HF) signal onto the input of the electrical system, the HF signal is distributed to each of the plurality of output channels, and the monitored reflection of the HF signal is monitored by the fault locating device to calculate a distance to the detected fault. The distance calculated by the fault locating device is combined with the channel identification provided by the fault detection circuit to generate a specific location associated with the detected fault. | 2010-06-17 |
20100148792 | HEAT SINK STRUCTURE AND TEST HEAD WITH SAME - To provide a heat sink structure able to improve the heat radiation efficiency without thickening of the heat sink. | 2010-06-17 |
20100148793 | ELECTRONIC DEVICE TEST APPARATUS FOR SUCCESSIVELY TESTING ELECTRONIC DEVICES - An electronic device test apparatus includes a plurality of testers on which are mounted test heads that are connected to test outputters for outputting test signals to the electronic devices and for receiving response signals from the electronic devices. A loading transporter is provided at a frontmost stage of the testers that transports the electronic devices from a previous process conveyance medium to a test tray before loading the electronic devices into the testers. An unloading transporter is provided at a rearmost stage of the testers that unloads the electronic devices from the test tray to a later process conveyance medium corresponding to the response signals. A transporter is provided between the testers that transports the test tray from a previous process tester to a later process tester. The transporter includes a buffer that holds test trays to absorb a waiting time due to differences in processing capacities between test trays. | 2010-06-17 |
20100148794 | INDICATOR ARRANGEMENT - An indicator arrangement according to the invention also comprises a resistor ( | 2010-06-17 |
20100148795 | METHODS AND APPARATUS FOR SELECTING SETTINGS FOR CIRCUITS - Methods and apparatus selecting settings for circuits according to various aspects of the present invention may operate in conjunction with a measurement element connected to the circuit. The circuit may include a voltage source adapted to supply a voltage to the measurement element. The voltage may be substantially independent of the characteristics of the measurement element. The circuit may further include a measurement sensor responsive to a current in the measurement element. The measurement sensor may generate a control signal according to the current in the measurement element. | 2010-06-17 |
20100148796 | DEVICE FOR CHECKING THE ATTACHMENT OF A CIRCUIT BOARD ON A CARRIER - A device for checking the attachment of a circuit board on a carrier, in particular a housing, has on each attachment point a pair of mutually associated electrically conductive contact surfaces and an electrically conductive connecting arrangement, which connects the circuit board mechanically to the carrier and at the same time connects the electrically conductive contact surfaces of the respective pair electrically to each other. At least one of the electrically conductive contact surfaces of a pair is situated on the circuit board. The other contact surface may likewise be situated on the circuit board or, for an electrically conductive carrier, even on the carrier. The respective pairs of conductive contact surfaces and the electrically conductive connecting arrangement form an electric circuit, which may be connected in a series circuit or a parallel circuit. An evaluation circuit checks whether the electric circuit thus formed is closed. | 2010-06-17 |
20100148797 | ESD DETECTION CIRCUIT AND RELATED METHOD THEREOF - An electro-static discharge (ESD) detection circuit is provided. The ESD detection circuit includes: a first power pad for receiving a first supply voltage; a second power pad for receiving a second supply voltage; an RC circuit having an impedance component coupled between the first power pad and a first terminal and having an capacitive component coupled between the first terminal and a second terminal, wherein the second terminal is not directly connected to the second supply voltage; a trigger circuit couples to the first power pad, the second power pad, and the RC circuit, for generating an ESD trigger signal according to a voltage level at the first terminal and a voltage level at the second terminal, and a bias circuit coupled between the first power pad and the second power pad for providing a bias voltage to the second terminal. | 2010-06-17 |
20100148798 | Apparatus and Method for Electrical Impedance Imaging - An apparatus | 2010-06-17 |
20100148799 | INDUCTIVE PROXIMITY SENSOR AND RELATED METHODS - An inductive proximity sensor or switch and a method of using same. The sensor or switch includes an Application Specific Integrated Circuit (“ASIC”) and a plurality of external components. The ASIC is implemented in CMOS technology and has an oscillator. A switch point of the sensor or switch is predetermined by selection of a bias voltage to a potential node of the oscillator. | 2010-06-17 |
20100148800 | INDUCTIVE SWITCH FOR ADJUSTMENT AND SWITCHING FOR APPLICATIONS IN SPECIAL ENVIRONMENTS - An inductive programming switch for applications in special environments, comprising an inductive component and a container in which the inductive component is accommodated proximate to a wall of the container, the inductive component being connected to an electronic evaluation circuit, which is adapted to detect variations of parameters of the inductive component caused by the approach of a metallic object to the wall, the evaluation circuit being adapted to detect and identify a sequence of approach/spacing of the metallic object with respect to the wall and for modifying its functional parameters according to the sequence. | 2010-06-17 |
20100148801 | CAPACITANCE-TYPE ENCODER - A capacitance-type encoder capable of obtaining position data of a movable element with low power-consumption. The capacitance-type encoder comprises a stator, a movable element arranged to confront the stator, an excitation device and a signal processing device. The stator has at least three excitation-electrode sets electrically independent from each other, each set constituted of excitation electrodes arranged cyclically and electrically connected with each other so that a predetermined number of excitation-electrode groups are formed. The movable element has connection electrodes having the same number as the excitation-electrode groups. The excitation device applies excitation signals to the excitation-electrode sets periodically in a predetermined sequence. The signal processing device determines which one of divided regions of one cycle of arrangement of the excitation electrodes the movable element is positioned in based on a combination pattern of detection signals generated in the connection electrodes. | 2010-06-17 |
20100148802 | CAPACITANCE-TYPE ENCODER - A capacitance-type encoder comprising a stator, a movable element, an excitation device and a signal processing device to obtain position data with low power-consumption. The stator has excitation-electrode sets electrically independent and displaced to have phase differences from each other to form a predetermined number of excitation-electrode groups. The movable element has connection electrodes having the same number as the excitation-electrode groups. The excitation device simultaneously applies a first pair of positive and negative pulse voltages respectively to two of the excitation-electrode sets having a phase difference of 180 degrees, and then simultaneously applies a second set of positive and negative pulse voltages respectively to the rest of the excitation-electrode sets. The signal processing device determines which one of four divided regions the movable element is positioned in based on a combination of detection signals when the first and second pairs of pulse voltages are applied respectively. | 2010-06-17 |
20100148803 | PASSAGE DETECTION APPARATUS OF OBJECT - A passage detection apparatus is configured to detect the change in the properties (propagation state of sound wave, dielectric constant, etc.) of a specific space, which changes according to the passage of an object in the specific space and the size of the object. The passage detection apparatus includes a pair of detection units and configured to transmit and receive signals to and from an external device. The specific space is formed by the space between the detection unit and the detection unit. The detection unit is supported by a first substrate. The detection unit is supported by a second substrate that is parallel to the first substrate, and arranged at the position corresponding to the detection unit supported by the first substrate. | 2010-06-17 |
20100148804 | DEVICE AND METHOD FOR DETERMINING AT LEAST ONE PARAMETER OF A MEDIUM - The invention relates to a device for determining at least one parameter of at least one medium, said medium being introducible into at least one measuring path. An electric and/or electromagnetic field can be partially coupled into or out of the medium by passing at least one electric and/or electromagnetic signal into the measuring path. The measuring path comprises at least one line arrangement having at least two elementary cells arranged along the measuring path, said elementary cells comprising at least one electric path from at least one input to at least one output and comprising at least one respective capacitative element. The electrical properties of the capacitative element can by be modified by the medium. The electric and/or the electromagnetic signal can be applied to the input of a first elementary cell and the output of the first elementary cell can be connected to the input of a second elementary cell. The capacitative element of the respective elementary cell is arranged in the electric path of the first and second elementary cell. At least one inductive element connects the first elementary cell and the second elementary cell to a ground. The invention also relates to a method for determining a parameter of a medium. | 2010-06-17 |
20100148805 | Fail-Safe System and Test Module, Notably For Use In A Railroad Signaling System - A fail-safe system, notably for use in a railroad signaling system, comprising a test module with a photovoltaic coupler able to charge a capacitor. The energy stored in the capacitor provides power supply to a circuit under test. Advantageously, means of measuring a state of charge of the capacitor make it possible to quantify current leaks from the circuit under test. | 2010-06-17 |
20100148806 | METHODS AND SYSTEMS FOR DETECTING A CAPACITANCE USING SIGMA-DELTA MEASUREMENT TECHNIQUES - Methods, systems and devices are described for detecting a measurable capacitance using sigma-delta measurement techniques. According to various embodiments, a voltage is applied to the measurable capacitance using a first switch. The measurable capacitance is allowed to share charge with a passive network. If the charge on the passive network is past a threshold value, then the charge on the passive network is changed by a known amount for a sufficient number of repetitions until the measurable capacitance can be detected. Such a detection scheme may be readily implemented using conventional components, and can be particularly useful in sensing the position of a finger, stylus or other object with respect to a button, slider, touchpad or other input sensor. | 2010-06-17 |
20100148807 | ORIENTATION DETECTION CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - An orientation detection circuit is provided. The circuit includes a processor, a first resistor, a second resistor, a third resistor, and a vibration switch. The processor comprises a first input pin and a second input pin. The second resistor has a resistance value greater than that of the first resistor. The third resistor has a resistance value greater than that of the second resistor. The switch comprises a first terminal connected to a power source and a second terminal connected to the second input pin and connected to ground via the third resistor. The switch includes a third terminal connected to the first terminal via the second resistor, and a fourth terminal connected to the first input pin and connected to ground via the first resistor. The switch also includes a fifth terminal connected to the fourth terminal, and a conductive ball for contacting two or three of the terminals. | 2010-06-17 |
20100148808 | METHODS AND APPARATUS TO ANALYZE ON-CHIP CONTROLLED INTEGRATED CIRCUITS - Methods and apparatus for analyzing an integrated circuit are disclosed. An example method includes supplying power to an on-chip supply power regulator of integrated circuit, instructing the on-chip supply power regulator to output a circuit supply signal having a desired minimum voltage level for the integrated circuit, instructing the integrated circuit to initiate an on-chip self-test process, analyzing the results of the on-chip self-test process, and repeating the process after stepping down the voltage of the circuit supply signal level. | 2010-06-17 |
20100148809 | PROBE CARD FOR TESTING SEMICONDUCTOR DEVICE, PROBE CARD BUILT-IN PROBE SYSTEM, AND METHOD FOR MANUFACTURING PROBE CARD - A probe card is includes a wafer and a plurality of needle patterns penetrating the wafer. The needle patterns are configured to supply an electrical signal for testing a separate wafer. The probe card may be mounted to a printed circuit board in a manner in which conductive patterns of the probe card are electrically connected to conductive terminals of the printed circuit board. The needle patterns may protrude from a lower end of the wafer and be formed so that an interval between needle patterns is the same as an interval between pads of a wafer to be tested. | 2010-06-17 |
20100148810 | PROBE DEVICE, PROCESSING DEVICE, AND PROBE TESTING METHOD - Provision of a probe device, a processing device and a probe test capable of performing an efficient wafer probe test. A probe device, comprising a plurality of measuring stages to which a plurality of probe cards for inspecting semiconductor wafers are connected, respectively; a first conveying portion for conveying a semiconductor wafer to a first measuring stage to which a first probe card is connected; a first inspection control portion for controlling the inspection of the semiconductor wafer by the first probe card; a receiving portion for receiving stage information including information showing nonuse of the first measuring stage from a processing device; a second conveying portion for conveying the semiconductor wafer to a second measuring stage, to which a second probe card different from the first probe card is connected, according to the received stage information; and a second inspection control portion for controlling the inspection of the semiconductor wafer by the second probe card. | 2010-06-17 |
20100148811 | Probe card, and apparatus and method for testing semiconductor device using the probe card - A probe card transmitting electrical test signals between a tester and a semiconductor device includes a main circuit board configured to receive and transmit electrical signals from the tester, an interface unit electrically connected to the main circuit board, the interface unit including a signal line and a signal connection terminal, and at least one probe unit connected to the interface unit, the probe unit being detachable and including a plurality of probe needles arranged in a pattern corresponding to a pattern of electrode pads of the semiconductor device. | 2010-06-17 |
20100148812 | SEMICONDUCTOR DEVICE INCLUDING CHIP - A semiconductor device in which a chip | 2010-06-17 |
20100148813 | APPARATUS AND METHOD FOR COMBINED MICRO-SCALE AND NANO-SCALE C-V, Q-V, AND I-V TESTING OF SEMICONDUCTOR MATERIALS - Current Voltage and Capacitance Voltage (IV and CV) measurements are critical in measurement of properties of electronic materials especially semiconductors. A semiconductor testing device to accomplish IV and CV measurement supports a semiconductor wafer and provides a probe for contacting a surface on the wafer under control of an atomic Force Microscope or similar probing device for positioning the probe to a desired measurement point on the wafer surface. Detection of contact by the probe on the surface is accomplished and test voltage is supplied to the semiconductor wafer. A first circuit for measuring capacitance sensed by the probe based on the test voltage and a complimentary circuit for measuring Fowler Nordheim current sensed by the probe based on the test voltage are employed with the probe allowing the calculation of characteristics of the semiconductor wafer based on the measured capacitance and Fowler Nordheim current. | 2010-06-17 |
20100148814 | COMPLIANCE CONTROL METHODS AND APPARATUSES - Methods and apparatuses for modifying a stage position and measuring at least one parameter of a motor connected with a stage during a commanded stage position are described. In one embodiment of one aspect of the invention, the motor is configured to move the stage in a first direction in response to the at least one parameter and determine whether the at least one parameter is within a threshold range. | 2010-06-17 |
20100148815 | TEST APPARATUS - Provided is a test apparatus that tests a device under test having a test function for sequentially outputting, from a single test terminal, signals that would be output from a plurality of terminals, the test apparatus comprising: a test section that supplies the device under test with a test signal and receives signals that are sequentially output from the test terminal in response to the test signal; an identifying section that identifies a correspondence between each signal sequentially received by the test section and a signal that would be output from one of the terminals of the device under test; and a counting section that counts a number of signals judged to be unacceptable from among the signals sequentially received by the test section for each terminal of the device under test, based on the correspondence identified by the identifying section. | 2010-06-17 |
20100148816 | Semiconductor integrated circuit device and testing method of the same - A disclosed semiconductor integrated circuit device includes a logic circuit, a memory circuit to which data are written by the logic circuit and from which the data are read by the logic circuit, a register circuit holding the data when the logic circuit writes the data to the memory circuit, and a selector circuit selecting one of data output from the register circuit and data output from the memory circuit, and outputting the selected data to the logic circuit. Further in the semiconductor integrated circuit device, in an operational test of the logic circuit, the selector circuit selects the data output from the register circuit and outputs the selected data to the logic circuit. | 2010-06-17 |
20100148817 | Reduced power output buffer - A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor. | 2010-06-17 |
20100148818 | HIGH SPEED CONDITIONAL BACK BIAS VIRTUAL GROUND RESTORATION CIRCUIT - A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground, V | 2010-06-17 |
20100148819 | Majority voter circuits and semiconductor device including the same - A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority. | 2010-06-17 |
20100148820 | PROGRAMMABLE DEVICE, CONTROL METHOD OF DEVICE AND INFORMATION PROCESSING SYSTEM - A programmable device can operate at high speed while reducing power consumption. The programmable device ( | 2010-06-17 |
20100148821 | PROGRAMMABLE LOGIC BLOCK OF FPGA USING PHASE-CHANGE MEMORY DEVICE - Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed. | 2010-06-17 |
20100148822 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING DEDICATED MEMORY STACKS IN A VERTICAL LAYER FORMAT - A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips. | 2010-06-17 |
20100148823 | SEMICONDUCTOR DEVICE - An RESURF region is formed so as to surround a high-potential logic region with an isolation region interposed therebetween, in which a sense resistance and a first logic circuit which are applied with a high potential are formed in high-potential logic region. On the outside of RESURF region, a second logic circuit region is formed, which is applied with the driving voltage level required for driving a second logic circuit with respect to the ground potential. In RESURF region, a drain electrode of a field-effect transistor is formed along the inner periphery, and a source electrode is formed along the outer periphery. Furthermore, a polysilicon resistance connected to sense resistance is formed in the shape of a spiral from the inner peripheral side toward the outer peripheral side. | 2010-06-17 |
20100148824 | CIRCUIT ARRANGEMENT FOR PRODUCING SHORT ELECTRICAL PULSES - A circuit arrangement for producing short electrical pulses, including a logic gate ( | 2010-06-17 |
20100148825 | Semiconductor devices and methods of fabricating the same - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter, a NAND device, or a NOR device. | 2010-06-17 |
20100148826 | DIFFERENTIAL COMPARATOR WITH SKEW COMPENSATION FUNCTION AND TEST APPARATUS USING THE SAME - One of differential signals is inputted to a first input terminal. The other of the differential signals is inputted to a second input terminal. A first sample hold circuit samples the signal inputted to the first input terminal and hold it thereafter. A second sample hold circuit samples the signal inputted to the second input terminal and holds it thereafter. A comparison unit compares a signal corresponding to a difference between respective output signals from the first and the second sample hold circuits, with a predetermined threshold value. A latch circuit latches an output from the comparison unit. Sample timings of the first and the second sample hold circuits and a latch timing of the latch circuit can be adjusted independently. | 2010-06-17 |
20100148827 | Radio Frequency (RF) Signal Generator and Method for Providing Test Signals for Testing Multiple RF Signal Receivers - A test signal interface and method for allowing sharing of multiple test signal generators among multiple devices under test (DUTs). Digital baseband test signals generated by the multiple test signal generators are combined and converted to a baseband analog signal for conversion to a radio frequency (RF) signal for testing the multiple DUTs. | 2010-06-17 |
20100148828 | PEAK POWER REDUCTION METHOD - A technique wherein when signals, the modulation schemes of which are different, are to be combined, performing the peak suppression using amounts of the respective modulation schemes can effectively reduce the PAPR of a resulting combined signal. A peak suppressing method for use in a peak suppressing circuit, which combines input signals of different modulation schemes in a time domain to provide a combined signal, comprises detecting, as a peak, that portion of the combined signal which excesses a threshold value to generate a peak signal in accordance with the peak; converting the peak signal into a frequency domain signal and then dividing it into signals originating from the input signals to use these input-signal-originated signals as respective suppression signals; and adding, to the input signals, the suppression signals having different suppression amounts for the respective modulation schemes, thereby performing the peak suppression. | 2010-06-17 |
20100148829 | LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME - A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, a feedback check line that connects a last source drive IC of the N source drive ICs to the timing controller. | 2010-06-17 |
20100148830 | GATE DRIVER CIRCUIT, SWITCH ASSEMBLY AND SWITCH SYSTEM - It is presented a gate driver circuit for driving an electric switch, the switch being arranged to control a main current using a gate signal. The gate driver circuit comprises: a non-linear capacitor means having a lower capacitance when an applied voltage is under a threshold voltage and a higher capacitance when an applied voltage is over the threshold voltage, wherein the non-linear capacitor is arranged to be connected between a high voltage connection point of the switch and a connection point for the gate signal; a current change rate sensor, the current change rate sensor being configured to detect changes in a main current of the electric switch and to control a gate signal of the electric switch depending on the current change; a gate buffer; and at least one current source, arranged to drive the gate buffer. The current change rate sensor is connected to control the current source to thereby control the gate signal of the electric switch. | 2010-06-17 |
20100148831 | BUFFER WITH REMOTE CASCODE TOPOLOGY - A buffer circuit is described for buffering signals between a circuit element and a load. The buffer includes a main transistor and a cascode transistor, as well as a distribution line for transferring signals over a distance between the circuit element and the load. The buffer is arranged in a remote cascode topology such that the cascode transistor is located substantially adjacent to the load and remote from the main transistor. The distribution line transfers signals over the distance from the main transistor to the cascode transistor. This remote cascode topology makes it possible to significantly reduce the power consumption of the buffer—as compared to conventional buffers—while maintaining the maximum bandwidth possible. | 2010-06-17 |
20100148832 | Clock data recovery circuit - A simple circuit that supports high and low data rates is provided. The circuit includes: a detection circuit | 2010-06-17 |
20100148833 | DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS - The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal. | 2010-06-17 |
20100148834 | ENHANCED PREDISTORTION FOR SLEWING CORRECTION - The present invention relates to a circuit arrangement and method of applying predistortion to a baseband signal used for modulating a pulse-shaped signal, wherein an envelope information of the baseband signal is detected and slewing distortions of the pulse-shaped signal are reduced by applying at least one of a phase modulation and a duty cycle | 2010-06-17 |
20100148835 | Duty control buffer circuit and duty correction circuit - The circuit includes a duty control buffer and a duty control voltage generator that receives outputs of the duty control buffer, detects a duty error, and generates control signals. The duty control buffer includes a differential stage including unbalanced first and second differential pairs each differentially receiving input signals, a load element pair connected between output pairs of the first and second differential pairs and a power supply, and a current source stage that supplies respective driving currents to the first and second differential pairs. | 2010-06-17 |
20100148836 | Contention-Free Level Converting Flip-Flops for Low-Swing Clocking - The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. Additionally, the presented flip-flops are contention-free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function. | 2010-06-17 |
20100148837 | LATCH CIRCUIT WITH SINGLE NODE SINGLE-EVENT-UPSET IMMUNITY - A latch circuit, such as a memory cell or a flip-flop, that is immune to single-event upset at any single node. The latch circuit includes two banks of four logic gates each. The output of each logic gate in the first bank is connected to inputs of two logic gates in the second bank, and the output of each logic gate in the second bank is connected to inputs of two logic gates in the first bank. Each logic gate includes a logic function receiving an input node and an enable signal, such as a load signal. The interconnection of the logic gates corrects single-event upset at any one of the nodes. In the memory cell arrangement, redundant data paths are used to produce two input nodes provides single-event upset immunity at those input nodes. A layout of the latch circuit that ensures that random ionization affects only a single node is also disclosed. | 2010-06-17 |
20100148838 | WIDE RANGE DELAY CELL - A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell, while a control circuit (which is generally a current source that is controlled by a control voltage) provides additional delay. Thus, the delay cell provided here can be used to improve the performance of delay locked loops (DLLs) and other circuits. | 2010-06-17 |
20100148839 | Self-Tuning Of Signal Path Delay In Circuit Employing Multiple Voltage Domains - Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation. | 2010-06-17 |
20100148840 | PULSE MODULATED CHARGE PUMP CIRCUIT - A circuit for increasing a gate voltage of a transmission gate in a high-speed switch to a level higher than a level of a supply voltage is provided. The circuit includes an oscillator generating a clock signal and a charge pump circuit operatively coupled to the oscillator. The charge pump circuit receives the supply voltage and the clock signal as inputs, and outputs the gate voltage. The circuit also includes a comparator circuit coupled to the oscillator circuit and the charge pump circuit and a pulse signal generator circuit operatively coupled to the oscillator, the pulse signal generator circuit generating a pulse signal which enables the oscillator. | 2010-06-17 |
20100148841 | Multiphase clock for superconducting electronics - A multiphase clock circuit in which bit errors are propagated only for the duration of the clock cycle in which a bit error occurs. The circuit recovers automatically from bit errors and is capable of operating at high frequency with high clock precision. The multiphase clock circuit can generate a plurality of clock pulse streams, each pulse stream at the same clock frequency, with fixed phase relationships among the streams. The multiphase clock circuit includes a master clock signal of frequency fc which is applied to a divide by N frequency divider circuit for producing a base clock signal of fc/N. The base clock signal is sequentially applied to the data input of a series chain of N clocked data flip-flops (DFFs) each of which is simultaneously clocked by a clock signal of frequency fc to produce N clock signals of base frequency fc/N separated from each other by a constant time delay T=1/fc. | 2010-06-17 |
20100148842 | MULTI-PHASE CLOCK SIGNAL GENERATING CIRCUIT HAVING IMPROVED PHASE DIFFERENCE AND A CONTROLLING METHOD THEREOF - A multi-phase clock signal generating circuit includes a phase correction block configured to receive multi-phase clock signals and produce a plurality of interpolated phase clock signal groups in which the phases of the multi-phase clock signals are differently controlled. The multi-phase clock signals are out of phase with each other. A clock control block is configured to produce output multi-clock signals by selectively outputting one among the interpolated phase clock signal groups using a digital control signal having a plurality of bits which are produced based on phase differences of the multi-phase clock signals. | 2010-06-17 |
20100148843 | BOW TIE CLOCK DISTRIBUTION - A clock distribution network includes: a primary clock signal and a distribution tree coupled to the primary clock signal. The distribution tree derives a plurality of separate clock signals from the primary clock signal and provides each of the plurality of separate clock signals to each of a plurality of loads. The distribution tree comprises a plurality of bow tie elements. | 2010-06-17 |
20100148844 | System And Method For Common Mode Translation - System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels. | 2010-06-17 |
20100148845 | LIMITER AND SEMICONDUCTOR DEVICE USING THE SAME - The limiter of the invention uses as a diode a stacked gate thin film transistor (TFT) including a floating gate. When the TFT including a floating gate is used, the threshold voltage Vth may be corrected by controlling the amount of charge accumulated in the floating gate even in the case where there are variations in the threshold voltages Vth of the TFT. | 2010-06-17 |
20100148846 | GATE DRIVE CIRCUIT - A gate drive circuit includes a turn-on side circuit for turning on a gate of a power switching device, the turn-on side circuit including a first turn-on side power supply circuit and a second turn-on side power supply circuit, the first turn-on side power supply circuit including: a first turn-on voltage source for supplying a first turn-on voltage; first turn-on wiring; and a first turn-on switch connected in the first turn-on wiring and controlled by a gate drive signal; and the second turn-on side power supply circuit including: a second turn-on voltage source for supplying a second turn-on voltage applied to the gate of the power switching device to set the power switching device in a steady (on) state; second turn-on wiring; a second turn-on switch connected in the second turn-on wiring; and a turn-on side delay circuit for delaying the gate drive signal and passing it to the second turn-on switch. | 2010-06-17 |
20100148847 | HIGH-POWER SWITCHING MODULE AND METHOD FOR THE GENERATION OF SWITCHING SYNCHRONISM IN A HIGH-POWER SWITCHING MODULE - A high-power switching module for directly feeding pulse energy to a load includes a plurality of series-connected switching stages. Each switching stage includes a semiconductor switch; a snubber capacitor and a synchronizing resistor; and a control network configured to act on the semiconductor switch and to be supplied with auxiliary power and switching pulses from a pulse driver so as to influence a switching of the semiconductor switch. The control network includes at least one control resistor, a control diode, an auxiliary diode, an auxiliary capacitor configured to decouple and store the auxiliary power so as to maintain an offset voltage at the semiconductor switch, and an adjustable time-delay element series connected to the control diode and connected in parallel with the control resistor. The adjustable time-delay element is configured to variably set the offset voltage for the semiconductor switch that determines the switching of the semiconductor switch. | 2010-06-17 |
20100148848 | High speed four-to-one multiplexer - According to one embodiment, a high speed multiplexer includes a number of data inputs, a number of hot code select inputs, and a final data output. In one embodiment, the high speed multiplexer utilizes a number of intermediate multiplexers, each receiving respective hot code select inputs and providing an intermediate data output. In one embodiment, each intermediate multiplexer has a critical delay path comprising a first NAND gate and a second NAND gate. In one implementation a four-to-one intermediate multiplexer comprises a first two-input NAND gate and a second four-input NAND gate. In one embodiment, a 32-to-1 high speed multiplexer comprises four four-to-one intermediate multiplexers. According to one implementation of this embodiment, the 32-to-1 multiplexer has a critical delay path from any of the data inputs to the final data output comprising a first NAND gate, a second NAND gate, a NOR gate, and a third NAND gate. | 2010-06-17 |
20100148849 | SIGNAL CONVERTER FOR WIRELESS COMMUNICATION AND RECEIVING DEVICE USING THE SAME - The present invention relates to a signal converting device and receiving device in a wireless communication system. The receiving device of the wireless communication system includes a differential signal converter for receiving a single ended radio frequency signal and converting it into a differential radio frequency signal, and a frequency down converter for down converting the differential radio frequency signal to down frequency signal. | 2010-06-17 |
20100148850 | System And Method For Common Mode Translation - System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network. computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels. | 2010-06-17 |
20100148851 | LOW VOLTAGE ANALOG CMOS SWITCH - A CMOS analog switch circuit includes an NMOS switch transistor, a PMOS switch transistor, and a bias circuit. In an embodiment, the bias circuit includes a first and a second native bias transistors having their gate terminals coupled to a first and a second terminals of the CMOS switch circuit, respectively. The source terminals of the first and the second native bias transistors are coupled together and are also coupled to the body terminal of the PMOS switch transistor. In an configuration, the first and the second native bias transistors are characterized by substantially 0V threshold voltages, and the PMOS switch transistor is configured to exhibit a lower on-resistance in response to the greater of the voltages of the first terminal and the second terminal of the CMOS analog switch circuit. | 2010-06-17 |
20100148852 | ORIENTATION DETECTION CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - An orientation detection circuit is provided. The circuit includes a processor, a first resistor, a second resistor, a third resistor, a vibration switch, a first transistor, and a second transistor. The processor includes a first input pin and a second input pin. The third resistor has a resistance value greater than that of the first resistor and the third resistor. The vibration switch includes a first terminal being grounded, a second terminal connected to the second input pin, a third terminal connected to a power source, and a fourth terminal connected via the third resistor to the second terminal and connected to the first input pin. The first transistor has a first source connected via the first resistor to the power source, a first drain connected to the first input pin, and a first gate connected to the second input pin. | 2010-06-17 |
20100148853 | SYSTEMS, DEVICES, AND METHODS FOR CONTROLLABLY COUPLING QUBITS - A system for communicably coupling between two superconducting qubits may include an rf-SQUID coupler having a loop of superconducting material interrupted by a compound Josephson junction and a first magnetic flux inductor configured to controllably couple to the compound Josephson junction. The loop of superconducting material may be positioned with respect to a first qubit and a second qubit to provide respective mutual inductance coupling therebetween. The coupling system may be configured to provide ferromagnetic coupling, anti-ferromagnetic coupling, and/or zero coupling between the first and second qubits. The rf-SQUID coupler may be configured such that there is about zero persistent current circulating in the loop of superconducting material during operation. | 2010-06-17 |
20100148854 | COMPARATOR WITH REDUCED POWER CONSUMPTION - A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected in an identical configuration, as those contained in the comparison circuit to generate a comparison result based on the bias signal generated by the bias generator circuit. A transistor of the comparison circuit receiving the bias signal is connected to a corresponding transistor in the bias generator circuit, in a current mirror configuration. The same bias circuit may be shared by many comparison circuits of corresponding comparator components. The features can be extended to provide hysteresis. | 2010-06-17 |
20100148855 | Constant Reference Cell Current Generator For Non-Volatile Memories - A reference current generation circuit generates a first branch current that varies by a first percentage in response to variations in a first supply voltage and variations in transistor threshold voltage. The first branch current is mirrored to create a corresponding second branch current. A first portion (sub-current) of the second branch current is supplied through a first transistor, which exhibits the transistor threshold voltage wherein the first sub-current varies by a second percentage in response to the variations in the first supply voltage and variations in transistor threshold voltage, wherein the second percentage is greater than the first percentage. A second portion (sub-current) of the second branch current is supplied through a second transistor. The second portion of the second branch current is mirrored to create a reference current (I | 2010-06-17 |
20100148856 | Regulation of Recovery Rates in Charge Pumps - A method is presented of setting a frequency of a clock for a charge pump system including the clock and a charge pump. This includes setting an initial value for the frequency of the clock and, while operating the charge pump system using the clock running at the initial frequency value, determining the ramp rate of an output voltage for the charge pump during a recovery phase. The frequency of the clock is then adjusted so that the ramp rate of the output voltage for the charge pump during the recovery phase falls in a range not exceeding a predetermined maximum rate. A charge pump system is also described that includes a register having a settable value, where the charge pump clock frequency is responsive to the register value, and count and comparison circuitry is connectable to receive the pump's output voltage and the clock signal and determine from them the number of clock cycles the charge pump uses to recover from a reset value to a predetermined value. | 2010-06-17 |
20100148857 | METHODS AND APPARATUS FOR LOW-VOLTAGE BIAS CURRENT AND BIAS VOLTAGE GENERATION - Methods and apparatus for low-voltage bias current and bias voltage generation are disclosed. An example bias signal generation circuit disclosed herein comprises a first amplifier stage, an output amplifier stage electrically coupled with the first amplifier stage, the first amplifier stage and the output amplifier stage configured to generate an output bias signal, the output amplifier stage configured to provide the output bias signal, a low impedance circuit electrically coupled with the output amplifier stage, the low impedance circuit configured to reduce an impedance of the output amplifier stage, and a current source electrically coupled with the low impedance circuit, the current source configured to drive the low impedance circuit to reduce loading of the output amplifier stage by the low impedance circuit. | 2010-06-17 |
20100148858 | BIAS CIRCUIT - A bias circuit is provided in a circuit including an input line and an output line, and is formed on a substrate that supplies dc power to an active component. The input line reaches an input terminal of the active component from a signal line input terminal to which a signal is inputted, and the output line reaches, from an output terminal of the active component, a signal line output terminal that outputs a signal therefrom. This bias circuit includes: a power supply line supplied with the dc power; a bridge-like metal structure subjected to a bending process, which connects the output line and the power supply line to each other; and a capacitive component provided between a ground and a node between the power supply line and the metal structure. | 2010-06-17 |
20100148859 | Methods for Manufacturing RFID Tags and Structures Formed Therefrom - Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g., improved electrical characteristics) as compared to tags containing organic electronic devices. | 2010-06-17 |
20100148860 | Multiport amplifier adjustment - The invention provides a method and apparatus for applying test signals to a multiport amplifier (MPA) and a method, apparatus and system for determining parameter adjustments for an MPA. Applying test signals to an MPA is performed so as to provide an output signal indicative of parameter adjustments for the MPA, the multiport amplifier arrangement comprising an input network, an amplifier unit and an output network, where the method includes providing a test signal directly to a point in the multiport amplifier arrangement between an output of the input network and an input of the amplifier unit. The method of determining parameter adjustments for a multiport amplifier arrangement includes receiving first and second output signals associated with an output of the multiport amplifier arrangement, the first output signal corresponding to a first signal path through the multiport amplifier arrangement and the second output signal corresponding to a second signal path through the multiport amplifier arrangement and determining parameter adjustments based on the first and second output signals. | 2010-06-17 |
20100148861 | METHOD OF FORMING A CHARGE PUMP CONTROLLER AND STRUCTURE THEREFOR - In one embodiment, an amplifier circuit is formed to minimize pop and click noise on the outputs of the amplifier circuit. The amplifier circuit is configured to place an output stage of the amplifier circuit in a high impedance state to minimize the pop and click noise. In another embodiment, the amplifier circuit is configured to couple the inputs of two amplifiers together to minimize the pop and click noise. | 2010-06-17 |
20100148862 | METHOD AND APPARATUS FOR ENHANCING PERFORMANCE OF DOHERTY POWER AMPLIFIER - An apparatus and method for enhancing performance of a Doherty power amplifier are provided. The method includes a signal separation unit for generating a first input signal serving as an input signal of a carrier power amplifier using an input signal and a second input signal serving as an input signal of a peaking power amplifier using the input signal, in which the first input signal is different from the second input signal. | 2010-06-17 |
20100148863 | Arrangement for reducing interference - An arrangement for reducing interference between circuit blocks having differences in the amount of input power and phase differences includes isolation wires located between the circuit blocks and connected to a ground. | 2010-06-17 |
20100148864 | Amplifier Control Device - A bias control signal generation unit detects ON and OFF of a transmission signal input to an amplifier and having a property of a burst according to burst information. The bias control signal generation unit controls a bias voltage to be applied to an amplifier such that an idle current flowing through the amplifier can be flowing in a larger amount in a transmission OFF period, and can return to a normal level in a transmission ON period. | 2010-06-17 |
20100148865 | METHOD AND SYSTEM FOR CALCULATING THE PRE-INVERSE OF A NONLINEAR SYSTEM - An apparatus is provided to determine pre-distortion for a nonlinear system. The apparatus comprises a datapath and a power amplifier. The datapath employs predistortion data to generally linearized the power amplifier. To generate this predistortion data, an indirect learning circuit and a direct learning circuit can be employed. The indirect learning circuit is generally coupled to the amplifier circuit so that it can iteratively adjust predistortion data during an indirect learning mode until convergence is reached. The direct learning circuit is generally coupled to the amplifier circuit and the indirect learning circuit and that receives the input signal so that the predistortion data can be copied to the direct learning circuit from the indirect learning after convergence is reached and so that the direct learning circuit can adjust the predistortion data during a direct learning mode. | 2010-06-17 |
20100148866 | Systems and Methods for Power Amplifiers with Voltage Boosting Multi-Primary Transformers - Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns. | 2010-06-17 |
20100148867 | Audio Out Unit - A DC-coupled audio out unit is provided, including at least one regulator and at least one audio amplifier. The regulator is coupled to at least one power terminal of the audio amplifier. | 2010-06-17 |
20100148868 | Differential amplifier - In a wireless communications system, it is important to realize a limiter operation by which a differential amplifier for amplifying a local signal may stably supply an output signal having a constant amplitude. However, when a signal handled by the system has a high frequency, a gain of the differential amplifier is reduced and the limiter operation may not be performed appropriately. The differential amplifier is configured employing a double cascode connection to enhance an output impedance, an upper transistor of the double cascode connection realizes enhancement in gain and frequency characteristics based on a positive feedback signal, and a lower transistor of the double cascode connection controls an operating point and suppresses an allowable output voltage range by operating in a linear region and based on a negative feedback signal to facilitate the limiter operation. | 2010-06-17 |
20100148869 | POWER AMPLIFICATION CIRCUIT HAVING TRANSFORMER - In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted. | 2010-06-17 |
20100148870 | ADAPTIVE FEEDBACK CASCODE - A current minor for generating a substantially identical current flow in two parallel current paths, each current path comprising a switching device and each switching device comprising first and second active terminals and a control terminal for controlling current flow between the first and second active terminals, the current minor comprising a first switching device arranged such that its first active terminal is arranged to receive a first voltage, its second active terminal is arranged to receive a variable voltage that varies independently of the first voltage and its control terminal is arranged to receive a control voltage, a second switching device connected such that its first active terminal is arranged to receive the first voltage and its control terminal is arranged to receive the control voltage and a voltage control device connected to the second switching device such that an input of the voltage control device is connected to the second active terminal of the second switching device, the voltage control device being arranged to receive a control signal indicative of the variable voltage and to alter the voltage at its input terminal in dependence on the control signal such that the difference between the voltage across the active terminals of the second switching device and the voltage across the active terminals of the first switching device remains substantially constant. | 2010-06-17 |
20100148871 | SYSTEMS AND METHODS FOR AN ADAPTIVE BIAS CIRCUIT FOR A DIFFERENTIAL POWER AMPLIFIER - Systems and methods for providing an adaptive bias circuit that may include a differential amplifier, low-pass filter, and common source amplifier or common emitter amplifier. The adaptive bias circuit may generate an adaptive bias output signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit may increase the bias voltage or bias current of the adaptive bias output signal. A power amplifier (e.g., a differential amplifier) may be biased according to the adaptive bias output signal in order to reduce current consumption at low power operation levels. | 2010-06-17 |
20100148872 | POWER AMPLIFIER HAVING TRANSFORMER - A power amplifier amplifying and compositing differential signals and capable of suppressing harmonics is provided. The power amplifier includes first amplifiers amplifying a first input signal and a second input signal, which are differential signals, a first coil receiving the first input signal and the second input signal amplified by the first amplifiers, a second coil magnetically coupled with the first coil and outputting a composite signal of the amplified first input signal and second input signal, a third coil magnetically coupled with the second coil, and a first capacitor coupled between both ends of the third coil, wherein one end of the first capacitor is coupled to a ground node. | 2010-06-17 |
20100148873 | TECHNIQUES FOR IMPROVING AMPLIFIER LINEARITY - Techniques for improving the linearity of a cascode amplifier. In an exemplary embodiment, an auxiliary common-gate amplifier is provided in parallel with the principal cascode branch. The auxiliary common-gate amplifier samples a cascoded node in the principal cascode branch. The auxiliary common-gate amplifier generates a current which, when combined with the current generated by the principal cascode branch, cancels a distortion component to generate an output current with improved linearity characteristics. In an exemplary embodiment, a phase shifting network couples the cascoded node to the auxiliary common-gate amplifier, and may include, e.g., a capacitor coupled to an inductor. | 2010-06-17 |
20100148874 | METHODS AND SYSTEMS FOR STABILIZING AN AMPLIFIER - The invention generally relates to stabilizing an MRI power delivery system. In one aspect, a stabilization module that is in electrical communication with the MRI power delivery system is provided. The stabilization module includes a closed loop control system. The closed loop control system is used to modify the at least one characteristic of the input signal. The modified input signal is provided to the MRI power delivery system. | 2010-06-17 |
20100148875 | CIRCUIT FOR COMPENSATION OF LEAKAGE CURRENT-INDUCED OFFSET IN A SINGLE-ENDED OP-AMP - An electronic device includes an operational amplifier, with the operational amplifier having an amplifier input stage coupled with a first output node to an amplifier output stage. A compensation capacitance is connected between an output node of the amplifier output stage and the first output node of the amplifier input stage, thereby operating as a compensator for stabilizing the operational amplifier. The compensation capacitance provides a parasitic diode drawing a first leakage current from the first output node of the amplifier input stage, a leakage current compensation circuit being coupled to the first output node of the amplifier input stage and coupled to a second output node of the amplifier input stage for drawing a first current from the first output node and a second current from the second output node. The leakage current compensation circuit is adapted such that the second current is greater than the first current by an amount corresponding to the first leakage current. | 2010-06-17 |
20100148876 | Amplifier Arrangement and Method for Amplifying a Signal - An amplifier arrangement has an amplifier ( | 2010-06-17 |
20100148877 | INTEGRATED POWER AMPLIFIERS FOR USE IN WIRELESS COMMUNICATION DEVICES - An integrated power amplifier can include a carrier amplifier, where the carrier amplifier is connected to a first quarter wave transformer at the input of the carrier amplifier. In addition, the power amplifier can further include at least one peaking amplifier connected in parallel with the carrier amplifier; a first differential combining structure, where the first combining structure includes a first plurality of quarter wave transformers that are configured to combine respective first differential outputs of the carrier amplifier in phase to generate a first single-ended output signal, and a second differential combining structure, where the second combining structures includes a second plurality of quarter wave transformers that are configured to combine respective second differential outputs of the at least one peaking amplifier in phase to generate a second single-ended output signal, where the first single-ended output signal and the second single-ended output signal are combinable in-phase to provide an overall output. | 2010-06-17 |
20100148878 | AMPLIFIER WITH DITHER - An analog amplifier includes at least one signal path. Each of the at least one signal path extends between an input and an output and includes a load device coupled to the output and a transistor coupled to the input. The analog amplifier further includes a dither current source selectively coupled to one of the at least one signal path. The dither current source is capable of supplying dither current to the load device of the selected signal path directly by bypassing the transistor of the selected signal path. | 2010-06-17 |
20100148879 | ATOMIC FREQUENCY ACQUIRING APPARATUS AND ATOMIC CLOCK - An atomic frequency acquisition apparatus includes: a cell enclosing atomic gas therein; a laser light source that oscillates a laser light that enters the cell and excites the atomic gas; and a photodetecting section that detects the laser light that has passed through the cell, wherein the cell has at least a laser light reflection section inside thereof. | 2010-06-17 |