24th week of 2010 patent applcation highlights part 16 |
Patent application number | Title | Published |
20100148180 | THIN FILM TRANSISTOR ARRAY PANEL WITH COMMON BARS OF DIFFERENT WIDTHS - A gate wire and a storage electrode wire extending in a transverse direction are provided, and a data wire extending in a longitudinal direction intersects the gate wire and the storage electrode wire. A plurality of pixel electrodes and a plurality of TFTs are provided on pixel areas defined by the intersections of the data wire and the gate wire. The storage electrode wire is interconnected by a plurality of storage electrodes connections provided on the pixel areas. In this way, a common bar disposed between gate pads and a display area is omitted or has reduced width. Therefore, the fan-out areas becomes to have sufficient size to reduce the resistance difference between the signal lines. | 2010-06-17 |
20100148181 | NANOCRYSTAL SILICON LAYER STRUCTURES FORMED USING PLASMA DEPOSITION TECHNIQUE, METHODS OF FORMING THE SAME, NONVOLATILE MEMORY DEVICES HAVING THE NANOCRYSTAL SILICON LAYER STRUCTURES, AND METHODS OF FABRICATING THE NONVOLATILE MEMORY DEVICES - Provided are nanocrystal silicon layer structures formed using a plasma deposition technique, methods of forming the same, nonvolatile memory devices including the nanocrystal silicon layer structures, and methods of fabricating the nonvolatile memory devices. A method of forming a nanocrystal silicon layer structure includes forming a buffer layer on a substrate and forming a nanocrystal silicon layer on the buffer layer by a plasma deposition technique using silicon (Si)-containing gas and hydrogen (H | 2010-06-17 |
20100148182 | THIN FLIM TRANSISTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer. | 2010-06-17 |
20100148183 | Method of Forming a Carbon Nanotube-Based Contact to Semiconductor - Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting characteristics in conjunction with the fact that a fabric of CNTs has high optical transparency. The physical structure of the contact scheme is broken down into three components, a) the GaN, b) an interface material and c) the metallic conductor. The role of the interface material is to make suitable contact to both the GaN and the metal so that the GaN, in turn, will make good electrical contact to the metallic conductor that interfaces the device to external circuitry. A method of fabricating contact to GaN using CNTs and metal while maintaining protection of the GaN surface is provided. | 2010-06-17 |
20100148184 | GAN-BASED FIELD EFFECT TRANSISTOR - A GaN-based field effect transistor (MOSFET) is comprised of a channel layer comprised of p-type GaN, an electron supply layer, a surface layer having band gap energy smaller than that of said electron supply layer, sequentially laminated on a substrate, and recess section is formed by removing a part of the drift layer, the electron supply layer, and the surface layer down to a depth that reaches to the channel layer. A source electrode and a drain electrode are formed so that the recess section positions between them, a gate insulation film is formed on the surface layer and on inner-surface of the recess section including the channel layer, and a gate electrode is formed on the gate insulating film in the recess section. | 2010-06-17 |
20100148185 | FLIP-CHIP LIGHT-EMITTING DIODE DEVICE - A flip-chip light-emitting diode (LED) device is provided. The flip-chip LED device includes a substrate, an n-GaN layer, an epitaxy layer, a p-GaN layer, a first electrode, and a second electrode. The n-GaN layer is formed on a surface of the substrate. The epitaxy layer is formed on the n-GaN layer. The p-GaN layer is formed on the epitaxy layer. The first electrode has a first polarity and is formed on the p-GaN layer. The first electrode substantially covers the p-GaN layer. The second electrode is formed on the n-GaN layer and has a second polarity opposite to the first polarity. | 2010-06-17 |
20100148186 | VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation. | 2010-06-17 |
20100148187 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a transistor including a gate electrode formed on a semiconductor substrate of a predetermined crystal via a gate insulating film and a source-drain region formed in the semiconductor substrate so as to have a convex portion in a direction of a gate width and in which an epitaxial crystal having a lattice constant different from that of the predetermined crystal is embedded, and a contact plug formed on the source-drain region other than the convex portion. | 2010-06-17 |
20100148188 | LASER-INDUCED FLAW FORMATION IN NITRIDE SEMICONDUCTORS - An embodiment is a method and apparatus to induce flaw formation in nitride semiconductors. Regions of a thin film structure are selectively decomposed within a thin film layer at an interface with a substrate to form flaws in a pre-determined pattern within the thin film structure. The flaws locally concentrate stress in the pre-determined pattern during a stress-inducing operation. The stress-inducing operation is performed. The stress-inducing operation causes the thin film layer to fracture at the pre-determined pattern. | 2010-06-17 |
20100148189 | LIGHT EMITTING DIODE - A LED chip including a substrate, a semiconductor device layer, a current blocking layer, a current spread layer, a first electrode and a second electrode is provided. The semiconductor device layer is disposed on the substrate. The current blocking layer is disposed on a part of the semiconductor device layer and includes a current blocking segment and a current distribution adjusting segment. The current spread layer is disposed on a part of the semiconductor device layer and covers the current blocking layer. The first electrode is disposed on the current spread layer, wherein a part of the current blocking segment is overlapped with the first electrode. Contours of the current blocking segment and the first electrode are similar figures. Contour of the first electrode and is within contour of the current blocking segment. The current distribution adjusting segment is not overlapped with the first electrode. | 2010-06-17 |
20100148190 | LIGHT EMITTING DIODE WITH ITO LAYER AND METHOD FOR FABRICATING THE SAME - The present invention relates to a light emitting diode with enhanced luminance and light emitting performance due to increase in efficiency of current diffusion into an ITO layer, and a method of fabricating the light emitting diode. According to the present invention, there is manufactured at least one light emitting cell including an N-type semiconductor layer, an active layer and a P-type semiconductor layer on a substrate. The method of the present invention comprises the steps of (a) forming at least one light emitting cell with an ITO layer formed on a top surface of the P-type semiconductor layer; (b) forming a contact groove for wiring connection in the ITO layer through dry etching; and (c) filling the contact groove with a contact connection portion made of a conductive material for the wiring connection. | 2010-06-17 |
20100148191 | High Luminous Flux Warm White Solid State Lighting Device - A high luminous flux warm white solid state lighting device with a high color rendering is disclosed. The device comprising two groups of semiconductor light emitting components to emit and excite four narrow-band spectrums of lights at high luminous efficacy, wherein the semiconductor light emitting components are directly mounted on a thermal effective dissipation member; a mixing cavity for blending the multi-spectrum of lights; a back-transferred light recycling member deposited on top of an LED driver and around the semiconductor light emitters; and a diffusive member to diffuse the mixture of output light from the solid state lighting device. The solid state lighting device produces a warm white light with luminous efficacy at least 80 lumens per watt and a color rendering index at least 85 for any lighting application. | 2010-06-17 |
20100148192 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes: a substrate member; a pixel electrode formed on the substrate member; a pixel defining film having an opening through which the pixel electrode is exposed, and formed on the substrate member; a light absorbing layer pattern for dividing the opening into a plurality of sub-emitting areas within the opening of the pixel defining film; an organic light emitting layer formed on the pixel electrode; and a common electrode formed on the organic light emitting layer. | 2010-06-17 |
20100148193 | SYSTEMS AND METHODS FOR PACKAGING LIGHT-EMITTING DIODE DEVICES - Embodiments disclosed herein provide packaged LED devices in which the majority of the emitted light comes out the top of each LED chip with very little side emissions. Because light only comes out from the top, phosphor deposition and color temperature control can be significantly simplified. A package LED may include a housing positioned on a supporting submount, sized and dimensioned to accommodate a single LED chip or an array of LED chips. The LED chip(s) may be attached to the submount utilizing the Gold-to-Gold Interconnect (GGI) process or solder-based approaches. In some embodiments, phosphor may be deposited on top of the LED chip(s) or sandwiched between glass plates on top of the LED chip(s). The phosphor layer may be inside or on top of the housing and be secured to the housing utilizing an adhesive. The housing may be adhered to the submount utilizing a thermal epoxy. | 2010-06-17 |
20100148194 | LIGHT-EMITTING DIODE ILLUMINATING APPARATUS - The invention provides a light-emitting diode illuminating apparatus. The light-emitting diode illuminating apparatus includes a carrier, a substrate, a light-emitting diode chip, a heat-conducting device, and a thermal phase-change material. The carrier includes a top surface and a bottom surface. A first recess is formed on the top surface of the carrier. A second recess is formed on the bottom surface of the carrier. The first recess communicates with the second recess. The substrate is embedded into the second recess. The light-emitting diode chip is disposed on the substrate. The heat-conducting device includes a flat part. And, the substrate is disposed on the flat part. | 2010-06-17 |
20100148195 | METHOD FOR IMPROVED GROWTH OF SEMIPOLAR (AL,IN,GA,B)N - A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an In | 2010-06-17 |
20100148196 | LED LIGHTING FIXTURE - A light-emitting device held on a fixture body includes an LED chip, a heat transfer plate made of a thermally conductive material on which the LED chip is mounted, a wiring board having, on one side, patterned conductors, for supplying an electric power to the LED chip and formed with an aperture (exposure part) through which a LED chip mount surface of the heat transfer plate is exposed, an encapsulation part in which the LED chip is encapsulated on the one side of the wiring board, and a dome-shaped color-changing member made of a fluorescent material and an optically transparent material and placed on the one side of the wiring board. The light-emitting device is bonded to the fixture body with an insulating layer interposed therebetween, and the insulating layer has electrical insulating properties and is interposed between the heat transfer plate and the fixture body to thermally couple the same. | 2010-06-17 |
20100148197 | SELECTIVE DECOMPOSITION OF NITRIDE SEMICONDUCTORS TO ENHANCE LED LIGHT EXTRACTION - A method of texturing a surface within or immediately adjacent to a template layer of a LED is described. The method uses a texturing laser directed through a substrate to decompose and pit a semiconductor material at the surface to be textured. By texturing the surface, light trapping within the template layer is reduced. Furthermore, by patterning the arrangement of pits, metal coating each pit can be arranged to spread current through the template layer and thus through the n-doped region of a LED. | 2010-06-17 |
20100148198 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a light emitting device includes: forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate; forming a dielectric film on a second surface side opposite to the first surface of the multilayer body, the dielectric film having a first and second openings on a p-side electrode and an n-side electrode provided on the second surface; forming a seed metal on the dielectric film and an exposed surface of the first and second openings; forming a p-side metal interconnect layer and an n-side metal interconnect layer on the seed metal; separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal, which is provided between the p-side metal interconnect layer and the n-side metal interconnect layer; and forming a resin in a space from which the seed metal is removed. | 2010-06-17 |
20100148199 | Light emitting device with fine pattern - A semiconductor light emitting device includes a semiconductor light emitting structure including first and second conductivity type semiconductor layers, and an active layer disposed therebetween, first and second electrodes connected to the first and second conductivity type semiconductor layers, respectively, and a fine pattern for light extraction, formed on a light emitting surface from which light generated from the active layer is emitted. The fine pattern for light extraction is formed as a graded refractive index layer having a refractive index which decreases with vertical distance from the light emitting surface. | 2010-06-17 |
20100148200 | LIGHT EMITTING DIODE WITH LIGHT CONVERSION - An exemplary light emitting diode includes a light emitting diode chip, two optical wavelength converting layers, and an encapsulant layer. The light emitting diode chip has an light emitting surface. The light emitting diode chip is used to emit a monochromatic light from the light emitting surface. The light emitting surface includes a first region, a second region, and a third region. The two optical wavelength converting layers covers the first and the third regions of the light emitting surface. The two optical wavelength converting layers are configured for converting the monochromatic light received from the light emitting diode chip and emitting light with a converted wavelength from the light emitting diode. The encapsulant layer covers the second region of the light emitting surface for directing light therefrom. | 2010-06-17 |
20100148201 | LED PACKAGE - There is provided an LED package including: a body unit; an LED chip mounted onto the body unit; lead frames mounted onto the body unit and electrically connected to the LED chip; and a reflection unit having a cavity to receive the LED chip therein and reflecting light emitted from the LED chip to the outside. Here, the reflection unit has a curved cross-section. | 2010-06-17 |
20100148202 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light-emitting device includes (A) a light-emitting portion obtained by laminating in sequence a first compound semiconductor layer, an active layer, and a second compound semiconductor layer; (B) a first electrode electrically connected to the first compound semiconductor layer; (C) a transparent conductive material layer formed on the second compound semiconductor layer; (D) an insulating layer composed of a transparent insulating material and having an opening, the insulating layer being formed on the transparent conductive material layer; and (E) a second electrode that reflects light from the light-emitting portion, the second electrode being formed on the transparent conductive material layer and on the insulating layer in a continuous manner, wherein, assuming that areas of the active layer, the transparent conductive material layer, the insulating layer, and the second electrode are respectively S | 2010-06-17 |
20100148203 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - There is provided a semiconductor light-emitting device including a semiconductor light-emitting element, a phosphor layer disposed in a light path of a light emitted from the semiconductor light-emitting element, containing a phosphor to be excited by the light and having a cross-section in a region of a diameter which is 1 mm larger than that of a cross-section of the light path, and a heat-releasing member disposed in contact with at least a portion of the phosphor layer and exhibiting a higher thermal conductance than that of the phosphor layer. | 2010-06-17 |
20100148204 | Light-Emitting Element and Display Device - There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer (passivation film) such as SiN provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. According to the present invention, a light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided. | 2010-06-17 |
20100148205 | LENS, MANUFACTURING METHOD THEREOF AND LIGHT EMITTING DEVICE PACKAGE USING THE SAME - A lens and a light emitting device package formed by introducing surface mount technology (SMI) are disclosed. The lens includes a refractive portion which refracts incident light, and at least one surface mount portion, wherein a portion of the surface mount portion is formed in the refractive portion. | 2010-06-17 |
20100148206 | LED package and method of assembling the same - An LED package is provided. The LED package includes a carrier, an LED chip, a conductive structure, a first encapsulant, a lens and a heat sink. The carrier is cup shaped and comprises a bottom portion and a lateral wall. The LED chip is received in the carrier and disposed on the bottom portion. The conductive structure is electrically connected to the LED chip. The first encapsulant is received in the carrier and fixing the carrier and the conductive structure. The lens is corresponding to the LED chip. The carrier is embedded in the heat sink, and heat generated by the LED chip is transmitted to the heat sink via the bottom portion and the lateral wall of the carrier. | 2010-06-17 |
20100148207 | SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device in which a semiconductor has good heat dissipation efficiency, a display employing such a semiconductor device and a method for manufacturing a semiconductor device. A conductive pattern providing a semiconductor-connecting terminal portion and further providing first and second external-connection terminal portion on the opposite sides of the semiconductor-connecting terminal portion is formed on the surface of a flexible insulating substrate to produce a flexible printed wiring board on which a semiconductor is mounted and connected with the semiconductor-connecting terminal portion in the conductive pattern. In such a semiconductor device, a slit is formed in the insulating substrate to surround the semiconductor while leaving a part around the semiconductor thus providing a semiconductor holding part. The insulating substrate is turned down such that the surface comes inside excepting the semiconductor holding part, and the slit is formed such that the mounted semiconductor projects from the backside of the insulating substrate to the outside when the first and second external-connection terminal portion are connected, respectively, with other components. | 2010-06-17 |
20100148208 | LED LIGHTING ASSEMBLY WITH IMPROVED HEAT MANAGEMENT - The present invention provides a lighting head assembly that incorporates a high intensity LED package into an integral assembly including a heat sink and circuit board for further incorporation into other useful lighting devices. The present invention primarily includes a heat sink member that also serves as a mounting die and a reflector cup into which the LED package is mounted. The circuit board is placed behind the reflector cup and includes riser members that extend through holes in the rear wall of the reflector cup to facilitate electrical connections to the leads of the LED. This particular means for assembly allows the reflector cup and circuit board to cooperate to retain the LED package, provide electrical and control connections, provide integral heat sink capacity and includes an integrated reflector cup. In this manner, high intensity LED packages can be incorporated into lighting assemblies through the use of the present invention by simply installing the present invention into a housing and providing power connections thereto. | 2010-06-17 |
20100148209 | LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE - An object is to provide a light-emitting device having a structure in which an external connection portion can easily be connected and a method for manufacturing the light-emitting device. A light-emitting device includes a lower support | 2010-06-17 |
20100148210 | PACKAGE STRUCTURE FOR CHIP AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a package structure for chip. The package structure for chip includes: a carrier substrate having an upper surface and an opposite lower surface; a chip overlying the carrier substrate and having a first surface and an opposite second surface facing the upper surface, wherein the chip includes a first electrode and a second electrode; a first conducting structure overlying the carrier substrate and electrically connecting the first electrode; a second conducting structure overlying the carrier substrate and electrically connecting the second electrode; a first through-hole penetrating the upper surface and the lower surface of the carrier substrate and disposed next to the chip without overlapping the chip; a first conducting layer overlying a sidewall of the first through-hole and electrically connecting the first conducting electrode; and a third conducting structure overlying the carrier substrate and electrically connecting the second conducting structure. | 2010-06-17 |
20100148211 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - A light emitting diode (LED) package structure including a leadframe, a housing, a LED chip and a light-transmissive encapsulant is provided. The leadframe has a first electrode and a second electrode separated from each other. The housing wraps the first electrode and the second electrode and includes a recess having a bottom and a sidewall. The bottom of the recess has a cover layer covering the leadframe and having an opening exposing an end of the first electrode, an end of the second electrode and a spacer disposed therebetween and connected thereto wherein the spacer, the end of the first electrode and the end of the second electrode are substantially coplanar. The LED chip is disposed in the recess and electrically connected to leadframe. The light-transmissive encapsulant is filled in the recess. | 2010-06-17 |
20100148212 | METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR CRYSTAL, GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR LIGHT- EMITTING DEVICE - The method for producing a group III nitride semiconductor crystal of the invention comprises a step of preparing a seed crystal having a non-polar plane followed by growing a group III nitride semiconductor from the non-polar plane in a vapor phase, wherein the growing step includes growing the group III nitride semiconductor so as to extend in the +C-axis direction of the seed crystal. A group III-V nitride semiconductor crystal having high quality and a large-area non-polar plane can be obtained by the method. | 2010-06-17 |
20100148213 | TUNNEL DEVICE - The present invention has provided a new diode and transistor by employing the characteristic of the tunnel diode. The new diode and transistor are field interacted and can be a solarcell, light sensor, thermal device, Hall device, pressure device or acoustic device which outputs self-excited multi-band waveforms with broad bandwidth. The present invention has also revealed a precisional switch which can works at high speeds and a capacitor whose capacitance can be actively controlled. | 2010-06-17 |
20100148214 | SEMICONDUCTOR DEVICE INTERNALLY HAVING INSULATED GATE BIPOLAR TRANSISTOR - The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically connected to the drain electrode. P-type impurity region is electrically connected to the collector electrode. P-type impurity region is electrically connected to the drain electrode. The semiconductor device further includes an N-type impurity region and an electrode. N-type impurity region is electrically connected to the gate electrode. The electrode is formed on the P-type semiconductor region with an insulating film therebetween, and is electrically connected to gate electrode. Thereby, an element footprint can be reduced while maintaining characteristics. | 2010-06-17 |
20100148215 | IGBT Having One or More Stacked Zones Formed within a Second Layer of the IGBT - An IGBT includes a first region, a second region located within the first region, a first contact coupled to the first region, a first layer arranged below the first region, a gate overlying at least a portion of the first region between the second region and the first layer and a second layer formed under the first layer. One or more stacked zones are formed within the second layer. Each one or more stacked zones includes a first zone and a second zone that overlies the first zone. Each first zone is inversely doped with respect to the second layer and each second zone is inversely doped with respect to the first zone. The IGBT further includes a third layer formed under the second layer and a second contact coupled to the third layer. | 2010-06-17 |
20100148216 | SEMICONDUCTOR LIGHT RECEIVING ELEMENT AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT RECEIVING ELEMENT - A semiconductor light detecting element having a mesa structure comprises: a first semiconductor layer having n-type conductivity located on a semiconductor substrate, a light absorbing layer located on the first semiconductor layer, and a second semiconductor layer located on the light absorbing layer; a burying layer burying peripheries of the light absorbing layer and the second semiconductor layer. The burying layer has a band gap larger than the band gap of the light absorbing layer. The second semiconductor layer has a first region having p-type conductivity, and a second region having i-type or n-type conductivity and located between the first region and the burying layer. | 2010-06-17 |
20100148217 | Graded high germanium compound films for strained semiconductor devices - Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed. | 2010-06-17 |
20100148218 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR DESIGNING THE SAME - The layout of an LSI is previously designed so that cells below pads which will be affected by stress are arranged so that the occurrence of a malfunction of the LSI which will be caused by the influence of stress is reduced or prevented. In addition to or instead of the cell arrangement, the arrangement of pads, bumps or the like may be adjusted. | 2010-06-17 |
20100148219 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines]. | 2010-06-17 |
20100148220 | STACK ARRAY STRUCTURE FOR A SEMICONDUCTOR MEMORY DEVICE - In a stack array structure for a semiconductor memory device, a first semiconductor layer includes a plurality of first cell strings, and a second semiconductor including a plurality of second cell strings. Bit-line contact plugs are configured to couple a bit-line to two adjacent first cell strings aligned in series in a bit-line direction, and to further couple the bit-line to two adjacent second cell strings respectively located over the two adjacent first cell strings. Common source line contact plugs are configured to couple a common source line to the two adjacent first cell strings and the two adjacent second cell strings. Pocket p-well contact plugs are located at positions corresponding to a layout of the bit-line plugs and/or common source line plugs, and are configured to couple a pocket p-well line to the first semiconductor layer and the second semiconductor layer. | 2010-06-17 |
20100148221 | VERTICAL PHOTOGATE (VPG) PIXEL STRUCTURE WITH NANOWIRES - An embodiment relates to a device comprising a nanowire photodiode comprising a nanowire and at least on vertical photogate operably coupled to the nanowire photodiode. | 2010-06-17 |
20100148222 | GAS SENSOR HAVING A FIELD-EFFECT TRANSISTOR - A gas sensor having a field-effect transistor for detecting gases or gas mixtures is provided. The gas sensor includes a substrate having a source, drain and gate region, a gas-sensitive layer being applied on the gate region. A porous adhesive agent is provided for the adhesion of the gas-sensitive layer in the gate region. | 2010-06-17 |
20100148223 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <−110> direction, and a first element isolation insulation film which is buried in a trench in an element isolation region of the semiconductor substrate and has a positive expansion coefficient, the first element isolation insulation film applying a compressive stress by operation heat to the insulated-gate field-effect transistor in the channel length direction. | 2010-06-17 |
20100148224 | POWER JUNCTION FIELD EFFECT POWER TRANSISTOR WITH HIGHLY VERTICAL CHANNEL AND UNIFORM CHANNEL OPENING - A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a top layer as source layer. A plurality of laterally spaced U-shaped trenches with highly vertical side walls defines a plurality of laterally spaced mesas. The mesas are surrounded on the four sides by U-shaped semiconductor regions having conductivity type opposite to that of the mesas forming U-shaped pn junctions and defining a plurality of laterally spaced long and vertical channels with a highly uniform channel opening dimension. A source contact is formed on the top source layer and a drain contact is formed on the bottom drain layer. A gate contact is formed on the bottom of the U-shaped trenches for the purpose of creating and interrupting the vertical channels so as to turn on and turn off the transistor. | 2010-06-17 |
20100148225 | LOW POWER MEMORY DEVICE WITH JFET DEVICE STRUCTURES - There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation. | 2010-06-17 |
20100148226 | JFET DEVICE STRUCTURES AND METHODS FOR FABRICATING THE SAME - In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source. | 2010-06-17 |
20100148227 | ELECTRONIC DEVICE INCLUDING AN INSULATING LAYER HAVING DIFFERENT THICKNESSES AND A CONDUCTIVE ELECTRODE AND A PROCESS OF FORMING THE SAME - An electronic device includes a transistor, wherein the electronic device can include a semiconductor layer having a primary surface, a channel region, a gate electrode, a source region, a conductive electrode, and an insulating layer lying between the primary surface of the semiconductor layer and the conductive electrode. The insulating layer has a first region and a second region, wherein the first region is thinner than the second region. The channel region, gate electrode, source region, or any combination thereof can lie closer to the first region than the second region. The thinner portion can allow for faster switch of the transistor, and the thicker portion can allow a relatively large voltage difference to be placed across the insulating layer. Alternative shapes for the transitions between the different regions of the insulating layer and exemplary methods to achieve such shapes are also described. | 2010-06-17 |
20100148228 | SEMICONDUCTOR AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a gate formed on a semiconductor substrate. A first junction region is formed on a first side of the gate and a second junction region formed on a second side of the gate. A bit line is formed over the gate to be electrically coupled with the first junction region. A first metal plug is formed electrically coupling the second junction region. A bit line contact plug is provided between the first junction region and the bit line, and electrically couples the first junction region and the bit line. A second metal plug is formed over the first metal plug and electrically couples the first metal plug. The junction region of a gate in a core or peripheral region is connected to the metal line using a metal plug so that bit lines formed in the core and peripheral area can have a pattern similar to that formed in a cell region. | 2010-06-17 |
20100148229 | INSULATING RESIN COMPOSITION - An insulating resin composition is provided. The insulating resin composition includes (A) a silicon-based polymer having either primary or secondary amine groups or both, (B) an organometallic compound, and (C) a solvent. The physicochemical properties of the insulating resin composition are maintained during processing steps for the fabrication of a semiconductor device. Therefore, the use of the insulating resin composition prevents deterioration of the characteristics of the semiconductor device arising from defects, spots, aggregates, and the like, in an insulating film and reduces the hysteresis of the semiconductor device to improve the characteristics of the semiconductor device. | 2010-06-17 |
20100148230 | TRENCH ISOLATION REGIONS IN IMAGE SENSORS - Trenches are formed in a substrate or layer and a solid source doped with one or more dopants is deposited over the image sensor such that the solid source fills the one or more trenches and is disposed on the surface of the substrate. The surface of the image sensor is then planarized so that the solid source remains only in the trenches. A thermal drive operation is performed to cause at least a portion of the one or more dopants in the solid source to diffuse into the portions of the substrate or layer that are immediately adjacent to and surround the sidewall and bottom surfaces of the trenches. The diffused dopant or dopants form passivation regions that passivate the interface between the substrate or layer and the sidewall and bottom surfaces of the trenches. | 2010-06-17 |
20100148231 | ELIMINATION OF GLOWING ARTIFACT IN DIGITAL IMAGES CAPTURED BY AN IMAGE SENSOR - A source/drain region of a transistor or amplifier is formed in a substrate layer and is connected to a voltage source. A glow blocking structure is formed at least partially around the source/drain region and is disposed between the source/drain region and an imaging array of an image sensor. A trench is formed in the substrate layer adjacent to and at least partially around the source/drain region. The glow blocking structure includes an opaque material formed in the trench and one or more layers of light absorbing material overlying the source/drain region and the opaque material. | 2010-06-17 |
20100148232 | SURFACE TREATMENT OF HYDROPHOBIC FERROELECTRIC POLYMERS FOR PRINTING - An embodiment is a method and apparatus to treat surface of polymer for printing. Surface of a polymer having a surface energy modified for a time period to control a feature characteristic and/or provide a hysteresis behavior. A material is printed on the surface to form a circuit pattern having at least one of the controlled feature characteristic and the hysteresis behavior. | 2010-06-17 |
20100148233 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DEVICE - A semiconductor device include a semiconductor substrate comprising a substrate body, a base over the substrate body and a pillar over a first region of the base; a buried line adjacent to a side surface of the base; a first diffusion layer over a second region of the base; a second diffusion layer over the pillar, the second diffusion layer being higher in level than the first diffusion layer; and a third diffusion layer disposed between the buried line and the semiconductor substrate. The third diffusion layer is different in level from the first diffusion layer. The top level of the third diffusion layer is lower than the top level of the first diffusion layer. | 2010-06-17 |
20100148234 | SUBRESOLUTION SILICON FEATURES AND METHODS FOR FORMING THE SAME - Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch. | 2010-06-17 |
20100148235 | SEMICONDUCTOR INTEGRATED CIRCUIT, STANDARD CELL, STANDARD CELL LIBRARY, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING EQUIPMENT - A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate. | 2010-06-17 |
20100148236 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having a 6F | 2010-06-17 |
20100148237 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers. | 2010-06-17 |
20100148238 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF - A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer. | 2010-06-17 |
20100148239 | GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHODS OF FORMING WORD LINE STRUCTURE AND MEMORY - A gate structure for a semiconductor device is provided. The gate structure includes a conductive structure. The conductive structure insulatively disposed over a substrate includes a middle portion and two spacer portions. The middle portion has a first surface and two second surfaces. The first surface is between the two second surfaces. The two spacer portions are respectively connected to the two second surfaces of the middle portion. A width of each of the two spacer portions gradually increases from top to bottom. | 2010-06-17 |
20100148240 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first insulating layer pattern on a semiconductor substrate, a second insulating layer including fluorine on the first insulating layer pattern, a third insulating layer pattern on the second insulating layer pattern, and a polysilicon pattern on the third insulating layer pattern. The fluorine is included in the second insulating layer that may be a nitride layer that stores data in a flash memory device, so that data retention and reliability are improved without exerting an influence upon capacitor characteristics. | 2010-06-17 |
20100148241 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device has a stacked structure in which a tunnel oxide layer, a charge trapping layer, a blocking oxide layer, and a gate electrode are sequentially formed on a silicon substrate, wherein the blocking oxide layer includes a crystalline layer disposed adjacent to the charge trapping layer and an amorphous layer disposed adjacent to the gate electrode. | 2010-06-17 |
20100148242 | SEMICONDUCTOR DEVICE - A semiconductor device suppresses short-circuit failure between a selection gate electrode and a control gate electrode while shortening the distance between the upper portions of the selection gate electrode and the control gate electrode. The device includes an impurity region formed on both sides of a channel region of a semiconductor substrate; a selection gate electrode on the channel region via a gate insulating film; a control gate electrode in the shape of sidewall via a gate isolation insulating film on both side surfaces of the selection gate electrode and on the surface of the channel region; a protective insulating film covering the sidewall of the control gate electrode; and a silicide layer on the selection gate electrode. The protective insulating film is a two-layer structure of a silicon nitride film covering the sidewall of the control gate electrode and a silicon oxide film covering the silicon nitride film. | 2010-06-17 |
20100148243 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substrate located between the gates as a seed layer, and formed to have a larger line-width than that of the second active area in a longitudinal direction of the gate. | 2010-06-17 |
20100148244 | SEMICONDUCTOR ELEMENT AND ELECTRICAL APPARATUS - In a semiconductor element ( | 2010-06-17 |
20100148245 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - An electronic device can include a transistor. In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure. The conductive structure can include a horizontally-oriented doped re-ion lying adjacent to the primary surface, an underlying doped region spaced apart from the primary surface and the horizontally-oriented doped region, and a vertically-oriented conductive region extending through a majority of the thickness of the semiconductor layer and electrically connecting the doped horizontal region and the underlying doped region. In another embodiment, the transistor can include a gate dielectric layer, wherein the field-effect transistor is designed to have a maximum gate voltage of approximately 20 V, a maximum drain voltage of approximately 30 V, and a figure of merit no greater than approximately 30 mΩ*nC. | 2010-06-17 |
20100148246 | Power mosfet device structure for high frequency applications - This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device. | 2010-06-17 |
20100148247 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G | 2010-06-17 |
20100148248 | SEMICONDUCTOR DEVICE HAVING GATE TRENCHES AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first gate trench, a second gate trench, and a dummy gate trench provided in an active region extending in an X direction; and a first gate electrode, a second gate electrode, and a dummy gate electrode extending in a Y direction crossing the active region, at least a part of which are buried in the first gate trench, the second gate trench, and the dummy gate trench, respectively. The dummy gate electrode arranged between second and third diffusion layers isolates and separates a transistor constituted by the first gate electrode and first and second diffusion layers provided on both sides of the first gate electrode, respectively, from a transistor constituted by the second gate electrode and third and fourth diffusion layers provided on both sides of the second gate electrode, respectively. | 2010-06-17 |
20100148249 | Method Of Manufacturing A Memory Device - A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F. | 2010-06-17 |
20100148250 | METAL OXIDE SEMICONDUCTOR DEVICE - A metal oxide semiconductor device comprising a substrate, at least an isolation structure, a deep N-type well, a P-type well, a gate, a plurality of N-type extension regions, an N-type drain region, an N-type source region and a P-type doped region is provided. The N-type extension regions are disposed in the substrate between the isolation structures and either side of the gate, while the N-type drain region and the N-type source region are respectively disposed in the N-type extension regions at both sides of the gate. The P-type well surrounds the N-type extension regions, and the P-type doped region is disposed in the P-type well of the substrate and is isolated from the N-type source region by the isolation structure. | 2010-06-17 |
20100148251 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a substrate on and/or over which a first conductive type well is formed; and an LDMOS device that includes a gate electrode and has a drain region formed in the substrate. The LDMOS device includes a trench formed on the substrate, a second conductive type body that is formed on one side of the trench and on the substrate therebeneath, and a first conductive type source region that is formed in the second conductive type body. | 2010-06-17 |
20100148252 | SEMICONDUCTOR DEVICE HAVING TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode. | 2010-06-17 |
20100148253 | HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH SCHOTTKY DIODES - High voltage semiconductor devices with Schottky diodes are presented. A high voltage semiconductor device includes an LDMOS device and a Schottky diode device. The LDMOS device includes a semiconductor substrate, a P-body region in a first region of the substrate, and an N-drift region in the second region of the substrate with a junction therebetween. A patterned isolation region defines an active region. An anode electrode is disposed on the P-body region. An N | 2010-06-17 |
20100148254 | Power semiconductor device and method of manufacturing the same - A semiconductor device and a method of manufacturing the same. The method includes preparing a semiconductor substrate having high-voltage and low-voltage device regions, forming a field insulating layer in the high-voltage device region, forming a first gate oxide layer on the semiconductor substrate, exposing the semiconductor substrate in the low-voltage device region by etching part of the first gate oxide layer and also etching part of the field insulating layer to form a stepped field insulating layer, forming a second gate oxide layer on the first gate oxide layer in the high-voltage device region and on the exposed semiconductor substrate in the low-voltage device region, and forming a gate over the stepped field insulating layer and part of the second gate oxide layer in the high-voltage device region adjoining the field insulating layer. | 2010-06-17 |
20100148255 | LATERAL HIGH-VOLTAGE MOS TRANSISTOR WITH A RESURF STRUCTURE - For achieving an enhanced combination of a low on-resistance at a high break-through voltage a lateral high-voltage MOS transistor comprises a plurality of doped RESURF regions of the first conductivity type within the drift region, wherein the doped RESURF regions are separated from each other by drift region sections in a first lateral direction (y), which is parallel to a substrate surface and is orthogonal to a connecting line from the source region to the drain region, and also in a depth direction, which is orthogonal to the substrate surface, such that in each of said two directions an alternating arrangement of regions of the first and second conductivity types is provided. | 2010-06-17 |
20100148256 | LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) DEVICES WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION CAPABILITY IN INTEGRATED CIRCUIT - Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer, thereby defining a first active region and a second active region. An N-type double diffused drain (NDDD) region is formed in the first active region and a N | 2010-06-17 |
20100148257 | MOS-FET Having a Channel Connection, and Method for the Production of a MOS-FET Having a Channel Connection - A MOSFET comprising a substrate of a semiconductor material; source/drain regions, which are arranged at a distance from each other at a surface of the substrate; a gate electrode arranged above an area of the surface of the substrate between the source/drain regions, the gate electrode being electrically insulated from the semiconductor material; at least one recess in the gate electrode, a through-contact arranged in the recess of the gate electrode, the through-contact being electrically insulated from the gate electrode; a terminal contact on the semiconductor material; and a terminal conductor arranged on the side of the gate electrode that faces away from the substrate, wherein the through-contact electrically connects the terminal contact to the terminal conductor. | 2010-06-17 |
20100148258 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate formed therein with a first conductive type well, and an LDMOS device formed on the substrate. The LDMOS device includes a gate electrode, gate oxides formed below the gate electrode, a source region formed in the substrate at one side of the gate electrode, and a drain region formed in the substrate at an opposite side of the gate electrode. The gate oxide includes first and second gate oxides disposed side-by-side and having thicknesses different from each other. | 2010-06-17 |
20100148259 | SOI SUBSTRATES AND SOI DEVICES, AND METHODS FOR FORMING THE SAME - An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate. | 2010-06-17 |
20100148260 | SEMICONDUCTOR DEVICE INCLUDING A CRYSTAL SEMICONDUCTOR LAYER, ITS FABRICATION AND ITS OPERATION - In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed. | 2010-06-17 |
20100148261 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of forming a second planarization film between the first planarization films to be coplanar with a surface of the first planarization film; a peeling layer formation step of forming a peeling layer by ion implantation of a peeling material into the base layer via the first planarization film or the second planarization film; and a separation step of separating part of the base layer along the peeling layer. | 2010-06-17 |
20100148262 | Resistors and Methods of Manufacture Thereof - Resistors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a semiconductive material over a workpiece, and patterning at least the semiconductive material, forming a gate of a transistor in a first region of the workpiece and forming a resistor in a second region of the workpiece. At least one substance is implanted into the semiconductive material of the gate of the transistor or the resistor so that the semiconductive material is different for the gate of the transistor and the resistor. | 2010-06-17 |
20100148263 | SEMICONDUCTOR DEVICE STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate. | 2010-06-17 |
20100148264 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING THE SAME - An ESD protection device including a substrate, a gate structure, a source region, a drain region and a first implanted region is provided. The gate structure includes a gate dielectric layer and a gate sequentially disposed on the substrate. The source region and the drain region are disposed in the substrate beside the gate structure. The first implanted region has the same conductivity type as the drain region. The first implanted region is disposed below the drain region, and the border thereof does not exceed the border of the drain region. | 2010-06-17 |
20100148265 | ESD PROTECTION DEVICE - An ESD protection device includes a substrate of a first conductivity type, a well region of a second conductivity type, a first doped region of the second conductivity type, a second doped region of the first conductivity type, a third doped region of the second conductivity type, a fourth doped region of the first conductivity type. The well region is configured in the substrate. The first doped region is configured in the well region. The second doped region is configured in the well region and surrounding the first doped region. The third doped region is configured in the well region and surrounding the first doped region and the second doped region. The fourth doped region is configured in the well region and under the first doped region and the second doped region. The fourth doped region is coupled with the first doped region and with the second doped region, respectively. | 2010-06-17 |
20100148266 | SYSTEM AND METHOD FOR ISOLATED NMOS-BASED ESD CLAMP CELL - The invention is directed to a protection circuit for protecting IC chips against ESD. An ESD protection circuit for an integrated circuit chip may comprise an isolated NMOS transistor, which may comprise an isolation region isolating a backgate from a substrate, and a first and second doped regions and a gate formed on the backgate. The ESD protection circuit may further comprise a first terminal to connect the isolation region to a first electrical node, and a second terminal to connect the second doped region to a second electrical node. The first electrical node may have a higher voltage level than the second electrical node, and the gate and backgate may be coupled to the second terminal. | 2010-06-17 |
20100148267 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a well | 2010-06-17 |
20100148268 | INSULATED-GATE SEMICONDUCTOR DEVICE - Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region. | 2010-06-17 |
20100148269 | TUNABLE SPACERS FOR IMPROVED GAPFILL - A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion. | 2010-06-17 |
20100148270 | Methods of channel stress engineering and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation. | 2010-06-17 |
20100148271 | Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device - The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift. | 2010-06-17 |
20100148272 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate having a first region including an n-type active element and a second region including a p-type active element, an element isolation region isolating plurality of the n-type active element and plurality of the p-type active element, a first insulating film having a tensile stress provided on the first region and on the element isolation regions of the second regions, and a second insulating film having a compression stress provided on the second region. | 2010-06-17 |
20100148273 | CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS - An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention. | 2010-06-17 |
20100148274 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer. | 2010-06-17 |
20100148275 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first MIS transistor formed on a first active region, and a second MIS transistor formed on a second active region. The first MIS transistor includes a first gate insulating film, and a first gate electrode including a first metal film and a first silicon film. The second MIS transistor includes a second gate insulating film, and a second gate electrode including the first metal film, a second metal film, and a second silicon film. | 2010-06-17 |
20100148276 | BIPOLAR INTEGRATION WITHOUT ADDITIONAL MASKING STEPS - The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the downward direction past the depletion region into the body doping region while, in a second active region, ( | 2010-06-17 |
20100148277 | ISOLATED METAL PLUG PROCESS FOR USE IN FABRICATING CARBON NANOTUBE MEMORY CELLS - The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor. | 2010-06-17 |
20100148278 | Semiconductor Device and Fabricating Method Thereof - A semiconductor device and fabricating method thereof are disclosed. The method includes forming a polysilicon layer on a semiconductor substrate including a high-voltage area and a low-voltage area, partially etching the polysilicon layer in the low-voltage area, forming an anti-reflective layer on the polysilicon layer to reduce a step difference between the high-voltage and low-voltage areas, forming a photoresist pattern in the high-voltage and low-voltage areas, and forming a high-voltage gate and a low-voltage gate by etching the polysilicon layer using the photoresist pattern as an etch mask. | 2010-06-17 |
20100148279 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions include a first lower insulation film and a first charge accumulation film. The second field effect transistor includes a second gate electrode; second impurity diffused areas; and second sidewall portions. The second sidewall portions include a second lower insulation film and a second charge accumulation film. The first lower insulation film contains one of a silicon thermal oxide film and a non-doped silicate glass, and the second lower insulation film contains a non-doped silicate glass. The second sidewall portions have a width along a gate longitudinal direction larger than that of the first sidewall portions. The second lower insulation film has a thickness larger than that of the first lower insulation film. | 2010-06-17 |