24th week of 2013 patent applcation highlights part 64 |
Patent application number | Title | Published |
20130151823 | NEXT FETCH PREDICTOR TRAINING WITH HYSTERESIS - A system and method for efficient branch prediction. A processor includes two branch predictors. A first branch predictor generates branch prediction data, such as a branch direction and a branch target address. The second branch predictor generates branch prediction data at a later time and with higher prediction accuracy. Control logic may determine whether the branch prediction data from each of the first and the second branch predictors match. If a mismatch occurs, the first predictor may be trained with the branch prediction data generated by the second branch predictor. A stored indication of hysteresis may indicate a given branch instruction exhibits a frequently alternating pattern regarding its branch direction. Such behavior may lead to consistent branch mispredictions due to the training is unable to keep up with the changing branch direction. When such a condition is determined to occur, the control logic may prevent training of the first predictor. | 2013-06-13 |
20130151824 | BINARY TRANSLATOR WITH PRECISE EXCEPTION SYNCHRONIZATION MECHANISM - A source computer system with one instruction set architecture (ISA) configured to run on a target hardware system that has its own ISA. During execution from binary translation, synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system, and asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied. The system also includes subsystems, and related methods of operation, for detecting the occurrence of all of these types of exceptions, to handle them, and to do so with precise reentry into the interrupted instruction stream. The binary translation and exception-handling subsystems are included as components of a virtual machine monitor which is installed between the target hardware system and the source system. | 2013-06-13 |
20130151825 | Multi-Mode Power Manager For Power Management Integrated Circuit - A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes tiles including an MCU/ADC tile and a power manager tile. The power manager tile includes a set of Configurable Switching Power Supply Pulse Width Modulator (CSPSPWM) components. These components, in combination with other circuitry external to the integrated circuit, are configurable to form a selected one of a number of different switching power supply circuits. Upon power up, an internal regulator supplies power to the CSPSPWM. The CSPSPWM then controls the power supply to begin switching in a low frequency start-up mode. The CSPSPWM determines during start-up the current sensing method based on circuitry external to the integrated circuit. A supply voltage generated is then supplied via a conductor of a standardized bus to a processor in the MCU/ADC tile. The processor begins executing instructions, and as a result writes across the standardized bus to configure the various tiles of the MTPMIC. | 2013-06-13 |
20130151826 | ELECTRONIC DEVICE WITH UART AND INPUT CONTROL METHOD - The present disclosure provides an electronic device. The electronic device includes a UART connected to at least one external input device. The UART includes a number of registers. The electronic device further includes a BMC and a BIOS. The BMC is connected to the UART to initialize the registers and is further connected to a south bridge for transmitting a restarting signal to the south bridge when the BMC is restarted. The BIOS is connected to the UART for storing input from the input device, and is connected to the south bridge for detecting whether the BMC generates the restarting signal, to enable or disable the registers to store or not to store the input from the external input device. | 2013-06-13 |
20130151827 | DISTINGUISHING CIRCUIT - A distinguishing circuit includes first to fifth resistors, a front panel connector, and a jumper. The front panel connector includes first to tenth pins. When the ninth pin is connected to the tenth pin through the jumper, a BIOS (Basic Input Output System) chip will determine whether a computer system is a first type. When the eighth pin is connected to the tenth pin through the jumper, the BIOS chip will determine whether the computer system is a second type. | 2013-06-13 |
20130151828 | CONSOLIDATED NOTIFICATIONS TO NFS CLIENTS - A computer implemented method, system and apparatus for rebooting a host having a plurality of network interfaces. A server reboots the host by stopping an NFS server process on the host. The server sends at least one consolidated notification to a plurality of clients identified in a consolidated notification table, wherein the consolidated notification comprises at least two addresses of network interfaces of the host. The server determines that an acknowledgement is received from each of the plurality of clients. The server halts resending of consolidated notifications, responsive to determining that an acknowledgement is received from the each of the plurality of clients. | 2013-06-13 |
20130151829 | Multi-Chip Initialization Using a Parallel Firmware Boot Process - Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip. | 2013-06-13 |
20130151830 | MOUNT-TIME RECONCILIATION OF DATA AVAILABILITY - Systems and methods are disclosed for mount-time reconciliation of data availability. During system boot-up, a non-volatile memory (“NVM”) driver can be enumerated, and an NVM driver mapping can be obtained. The NVM driver mapping can include the actual availability of LBAs in the NVM. A file system can then be mounted, and a file system allocation state can be generated. The file system allocation state can indicate the file system's view of the availability of LBAs. Subsequently, data availability reconciliation can be performed. That is, the file system allocation state and the NVM driver mapping can be overlaid and compared with one another in order to expose any discrepancies. | 2013-06-13 |
20130151831 | Virtual Machine Monitor Bridge to Bare-Metal Booting - Mechanisms for executing a bare metal boot operation for bare metal booting a control program are provided. These mechanisms boot a computing device to a hypervisor ownership phase of the bare metal boot operation. During the hypervisor ownership phase of the bare metal boot operation a hypervisor is loaded and controls and manages platform hardware of the computing device. The computing device is then booted from the hypervisor ownership phase to a transition phase in which the hypervisor releases control and management of the platform hardware of the computing device to the control program. The computing device is then booted from the transition phase to a control program ownership phase in which the control program is in full control and manages the platform hardware. The bare metal boot operation is performed without restarting the computing device and without cycling through initialization of firmware. | 2013-06-13 |
20130151832 | FLASH MEMORY STORAGE SYSTEM AND DATA PROTECTION METHOD THEREOF - A flash memory storage system includes a flash memory, a host and a controller is provided. The controller couples to the host and the flash memory, and restricts the host to access the flash memory according to a state of the host. When the host is in a booting state or in a resetting state, the controller allows the host to access the flash memory. After the host completes a booting process or a resetting process, the controller restricts the host to access the flash memory so as to protect a data stored by the flash memory. Besides, a data protection method for which applied to the above-mentioned storage system is also provided in the present invention. | 2013-06-13 |
20130151833 | BOOTING METHOD FOR LOW TEMPERATURE ENVIRONMENT AND ELECTRONIC APPARATUS THEREFOR - A booting method for low temperature environment and an electronic apparatus therefor are provided. The booting method includes the following steps: reading a booting process record from a memory unit of the electronic apparatus; executing a booting process according to the booting process record, wherein the booting process includes a plurality of booting subroutines; and when executing one of the booting subroutines, updating the booting process record stored in the memory unit of the electronic apparatus corresponding to the booting subroutine, wherein the booting subroutines include providing a power output by controlling a power supply unit of the electronic apparatus, and an output value of the power output gradually increases as executing the booting subroutines sequentially. | 2013-06-13 |
20130151834 | Deployment of a Software Image on Multiple Targets with Streaming Technique - Deploying a software image from a source data-processing system on target data-processing entities of a target data-processing system, the software image including memory blocks being individually accessible, with a predefined subset of the memory blocks defining a bootstrap module. The deploying includes downloading the bootstrap module onto a main one of the target data-processing entities from the source data-processing system, booting the main target data-processing entity from the bootstrap module thereby loading a streaming driver in the bootstrap module, and serving each request of accessing a selected memory block of the software image on the main data-processing entity by the streaming driver. | 2013-06-13 |
20130151835 | Deployment of a Software Image on Multiple Targets with Streaming Technique - Deploying a software image from a source data-processing system on target data-processing entities of a target data-processing system, the software image including memory blocks being individually accessible, with a predefined subset of the memory blocks defining a bootstrap module. The deploying includes downloading the bootstrap module onto a main one of the target data-processing entities from the source data-processing system, booting the main target data-processing entity from the bootstrap module thereby loading a streaming driver in the bootstrap module, and serving each request of accessing a selected memory block of the software image on the main data-processing entity by the streaming driver. | 2013-06-13 |
20130151836 | SEMICONDUCTOR DEVICE INCLUDING ENCRYPTION SECTION, SEMICONDUCTOR DEVICE INCLUDING EXTERNAL INTERFACE, AND CONTENT REPRODUCTION METHOD - A secure LSI device | 2013-06-13 |
20130151837 | APPLICATION MANAGEMENT OF A PROCESSOR PERFORMANCE MONITOR - A method, system or computer usable program product for an operating system (OS) enabling an application direct control of a performance monitoring unit (PMU) including enabling the PMU to notify the application when a PMU exception occurs without interrupting the OS by controllably encoding a redirect field in an OS accessible control register, and enabling the application to reinitialize the PMU after the PMU exception. | 2013-06-13 |
20130151838 | CIRCUIT FOR REMOVING PASSWORDS - A circuit for removing passwords from a computer includes a jumper and a power circuit. The jumper includes a base and a jumper block. The base includes first to fourth pins. The first pin is idle. The third pin is grounded. The second pin is coupled to a basis input output system (BIOS) chip of the computer, the fourth pin is coupled to a complementary metal-oxide-semiconductor (CMOS) chip of the computer. The power circuit is coupled to the second and the fourth pins, to supply power for the BIOS chip and the CMOS chip. The jumper block is plugged between the second and the third pins to remove the password in the BIOS chip, and plugged between the third and the fourth pins to remove the password in the CMOS chip. | 2013-06-13 |
20130151839 | IDLE DETECTION - Idle detection techniques are disclosed. A set of idle conditions that includes one or more conditions not comprising or triggered by an absence of user input is monitored. The device is determined to be idle based at least in part on results of the monitoring. The device may be determined not to be idle even in the absence of recent user input. | 2013-06-13 |
20130151840 | MULTI-PROCESSOR ELECTRONIC SYSTEMS - Disclosed herein is a system having a multi-processor configuration for electronics devices and systems, such as, computing and communication devices like laptop, notebook, tablets, smartphones, etc. In accordance with one embodiment of the subject matter the system comprises a plurality of processors and a multi protocol multi-root input output virtualization (MPMRIOV) switch communicatively coupled to at least one of the plurality of processors. The system further includes a peripheral and interface virtualization unit (PIVU) coupled to the MPMRIOV switch. In said embodiment, the PIVU is configured to communicatively couple at least one of the plurality of processors with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral, and a non PCIe compliant peripheral. | 2013-06-13 |
20130151841 | DEVICE HARDWARE AGENT - A server includes an electronic component, manager baseboard management controller (BMC), and a device hardware agent. The device hardware agent monitors operation of the electronic component and provides updates to the electronic component without utilizing a software agent. | 2013-06-13 |
20130151842 | ENCRYPTION KEY TRANSMISSION WITH POWER ANALYIS ATTACK RESISTANCE - Methods and mechanisms for transmitting secure data. An apparatus includes a storage device configured to store data intended to be kept secure. Circuitry is configured to receive bits of the secure data from the storage device and invert the bits prior to transmission. The circuitry may invert the bits prior to conveyance if more than half of the bits are a binary one, set an inversion signal to indicate whether the one or more bits are inverted, and convey both the one or more bits and inversion signal. Embodiments also include a first source configured to transmit Q bits of the secure data on an interface on each of a plurality of clock cycles. The first source is also configured to generate one or more additional bits to be conveyed concurrent with the Q bits such that a number of binary ones transmitted each clock cycle is constant. | 2013-06-13 |
20130151843 | CRYPTOGRAPHY FOR SECURE SHELL IN EMULATED ENVIRONMENTS - Calls from an application in an emulated environment to a module in the operating system hosting the emulated environment may be combined to reduce the overhead of accessing the module. An application handling secure shell (SSH) communications may execute multiple calls to a cryptographic module in the host operating system. Because many calls to the cryptographic module during SSH communications follow patterns, two or more related calls may be combined into a single combined call to the cryptographic module. For example, a call to generate a server-to-client key and a call to generate a client-to-server key may be combined into a single call. | 2013-06-13 |
20130151844 | Method and Apparatus for Secure Setup of an Encrypted Connection between Two Communication Devices - An electronic device includes a first connection interface and a second connection interface. The first connection interface is operable to exchange security information with another electronic device for use in encrypting data transmissions with the other electronic device. The first connection interface is inoperable to communicate payload data encrypted using the security information. The second connection interface is different than the first connection interface and operable to securely communicate payload data with the other electronic device over an unsecure medium in accordance with the security information exchanged via the first connection interface. | 2013-06-13 |
20130151845 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR ENCRYPTING DIAMETER IDENTIFICATION INFORMATION IN A COMMUNICATION NETWORK - The subject matter described herein includes systems, methods, and computer readable media for encrypting Diameter identification information contained in Diameter signaling messages. The system includes a Diameter agent that comprises a network interface configured to receive, from a first Diameter node, a Diameter signaling message that includes Diameter identification information associated with the first Diameter node and a Diameter encryption topology hiding module (ETHM) configured to encrypt the Diameter identification information to generate encrypted Diameter identification information and to replace the Diameter identification information in the Diameter signaling message with the encrypted Diameter identification information. The Diameter agent further includes a routing module configured to route the Diameter signaling message with the encrypted Diameter identification information to a second Diameter node. | 2013-06-13 |
20130151846 | Cryptographic Certification of Secure Hosted Execution Environments - Implementations for providing a secure execution environment with a hosted computer are described. A security-enabled processor establishes a hardware-protected memory area with an activation state that executes only software identified by a client system. The hardware-protected memory area is inaccessible by code that executes outside the hardware-protected memory area. A certification is transmitted to the client system to indicate that the secure execution environment is established, in its activation state, with only the software identified by the request. | 2013-06-13 |
20130151847 | Authentication Certificates as Source of Contextual Information in Business Intelligence Processes - A certificate of a user is presented by a client to a server. The certificate is used to authenticate communications between the client and the server. Thereafter, data from the certificate is cached at the server. The server then initiates one or more business intelligence processes of a business intelligence application at the client using the cached data to provide context to the one or more business intelligence processes. Related apparatus, systems, techniques and articles are also described. | 2013-06-13 |
20130151848 | CRYPTOGRAPHIC CERTIFICATION OF SECURE HOSTED EXECUTION ENVIRONMENTS - Implementations for providing a persistent secure execution environment with a hosted computer are described. A host operating system of a computing system provides an encrypted checkpoint to a persistence module that executes in a secure execution environment of a hardware-protected memory area initialized by a security-enabled processor. The encrypted checkpoint is derived at least partly from another secure execution environment that is cryptographically certifiable as including another hardware-protected memory area established in an activation state to refrain from executing software not trusted by the client system. | 2013-06-13 |
20130151849 | DEVICE, METHOD, AND SYSTEM FOR PROCESSING COMMUNICATIONS FOR SECURE OPERATION OF INDUSTRIAL CONTROL SYSTEM FIELD DEVICES - A device, method, and system for processing communications for secure operation of industrial control system field devices, includes: a processing device to be placed in-line between a Master Telemetry Unit (MTU) and a field device. A software verified microkernel includes instructions for the processing device to provide a secure partitioning of memory between a communication network interface address space, a security cell address space, and a field device interface address space. The security cell address space includes instructions to: receive communication messages from the MTU via the communication network interface address space; authenticate a user identification of each communication message; verify that an operation requested in each message is authorized for the user identification; and send each communication message having an authenticated user identification and a verified operation to the field network interface address space for communication with the field device. | 2013-06-13 |
20130151850 | Auto File Locker - Novel tools and techniques to provide an online file locker system. Some such tools can employ a USB memory drive, a residential gateway, and/or a data server over a network. In some cases, when the USB memory drive is inserted into a USB port of the RG, data stored on the USB memory drive is automatically uploaded to, and/or synchronized with data stored on, the data server, which is in communication with the RG over the network. In other cases, data deletion is accomplished in a similar manner, for example, upon removal of the USB drive and/or upon detection of files deleted from the USB drive. | 2013-06-13 |
20130151851 | System, Apparatus and Method for Enabling/Disabling Display Data Channel Access to Enable/Disable High-Bandwidth Digital Content Protection - A switcher device comprises a multiplexer coupled in-between at least one input and output cards. The multiplexer detects the presence of an event signal from an activated sink. In response to the detection of the event signal, the switch dynamically switches to a closed position in order to enable the at least one source to authenticate with the input card and the output card to authenticate with the at least one sink for security protocol encryption. In response to the non-detection of the event signal, the switch switches dynamically to an open position in order to disable the at least one source from authenticating with the input card, therefore the output card also does not attempt to authenticate with the at least one sink for security protocol encryption. | 2013-06-13 |
20130151852 | METHOD, DEVICE AND SYSTEM FOR AUTHENTICATING GATEWAY, NODE AND SERVER - A method, device and system for authenticating gateway, node and server are provided in this invention. The node receives a message sent by a gateway, wherein the message comprises a number T | 2013-06-13 |
20130151853 | SYSTEMS AND METHODS FOR SECURE PEER-TO-PEER COMMUNICATIONS - Systems and methods for secure peer-to-peer communication are disclosed herein. Various embodiments of the present invention advantageously enable authentication of a remote device, but without the use of a PKI certificate, and more generally, without requiring involvement from outside parties. In an exemplary embodiment, a password-protected message may be sent to a remote device, the password-protected message containing a unique identifier of a local device and a locally generated random number. Upon accessing the password-protected message, the remote device may reply to the local device including its own unique identifier and a remotely generated random number, where the reply is encrypted using the locally generated random number. An acknowledgement message may then be sent to the remote device including a mutually unique key, where the acknowledgement message is encrypted using the remotely generated random number. Subsequent communications between these devices may then be encrypted with this mutually unique key. | 2013-06-13 |
20130151854 | METHOD FOR AUTHENTICATING A PORTABLE DATA CARRIER - A method for authenticating a portable data carrier ( | 2013-06-13 |
20130151855 | WATERMARK EMBEDDING WORKFLOW IMPROVEMENTS - Methods, devices and computer program products facilitate embedding and extraction of watermarks into and from a host content. Embedded watermarks include an automatically generated portion that is associated with metadata. The metadata, which includes one or more identifiers of the host content, is stored at a database and can be accessible to both the watermark embedder and a watermark extractor. The automatically generated portion of the payload can be a serial number is changed for each watermark embedding session. | 2013-06-13 |
20130151856 | CONDITIONAL ACCESS USING EMBEDDED WATERMARKS - Methods, devices and computer program products facilitate conditional access to a content embedded with watermarks. For such a content, when copy control rules associated with an embedded watermark message prohibits unconditional access to the content, it is determined whether or not an exception to the copy control rules exists, and if an exception to the copy control rules exists, the content is conditionally accessed. Additional watermark messages can be extracted while the content is being conditionally accessed, and based on the additionally extracted watermark messages, it is verified that conditional access to the content has been fulfilled. | 2013-06-13 |
20130151857 | System and Method for a Single Request - Single Response Protocol with Mutual Replay Attack Protection - Various embodiments of a system and method for a single request-single response protocol with mutual replay attack protection are described. Embodiments include a system that receives multiple single request messages, each of which include a respective nonce, timestamp, and digital signature. The system may create a record of previously received nonces that, at any given time, may include multiple message nonces received within a valid period of time prior to that given time. To validate a given single request message, the system verifies the digital signature of the message, determines that the timestamp of the message indicates a time within the valid period of time prior to the current time, and determines that the nonce of the message is not present within the record of previously received nonces. The system sends a single response message that includes the same nonce as the validated message. | 2013-06-13 |
20130151858 | STORAGE DEVICE PROTECTION SYSTEM AND METHOD FOR LOCKING AND UNLOCKING STORAGE DEVICE - A storage device protection system including a protection control unit, a detection unit, an account/password input unit, an ID acquiring unit, and an encryption unit is provided. The detection unit determines whether a storage device and a key storage device are both coupled to a host. The account/password input unit receives an administrator ID and an administrator password. The ID acquiring unit obtains IDs of the storage device and the key storage device. The encryption unit encrypts the administrator ID, the administrator password, and the IDs of the storage device and the key storage device into encryption data. The protection control unit stores the encryption data into the key storage device and sets an access mode of the storage device as a protection status according to the administrator ID and the administrator password. Thereby, the storage device can be effectively unlocked by using the key storage device. | 2013-06-13 |
20130151859 | KEY AND METHOD FOR ENTERING COMPUTER RELATED PASSWORDS VIA A MNEMONIC COMBINATION - A key for entering computer related passwords via a mnemonic combination includes an electronic key with a communication means, a computer program, a storage unit, and a user interface. The communication means is for communicating with a computer device where the computer device recognizing the electronic key as a human input device. The computer program is for creating a password and a mnemonic combination associated with the password. The storage unit is for storing the password and the mnemonic combination association with the password. The user interface is for allowing a user to enter the mnemonic combination into the electronic key. Wherein, when the user enters the mnemonic combination into the user interface, the electronic key communicating the password associated with the mnemonic combination to the computer device as a human input device. | 2013-06-13 |
20130151860 | METHOD AND APPARATUS FOR SECURE MEASUREMENT CERTIFICATION - The invention relates to methods and apparatuses for acquiring a physical measurement, and for creating a cryptographic certification of that measurement, such that its value and time can be verified by a party that was not necessarily present at the measurement. | 2013-06-13 |
20130151861 | SYSTEM AND METHOD TO PROTECT COMPUTER SOFTWARE FROM UNAUTHORIZED USE - A system and method encrypt a license file associated with computer software using a private key. The license file includes one or more license keys, and each license key is associated with a feature of the computer software. The license file associated with the computer software is decrypted at runtime using a public key. A module determines whether a user is permitted to execute the computer software. The module is authenticated by one or more of a determination of whether a hash code included within the module matches a hash code generated by a user of the computer software at run time of the computer software, and an encryption of the module prior to run time of the computer software using the private key and a decryption of the module at run time of the computer software using the public key. | 2013-06-13 |
20130151862 | SYSTEMS AND METHODS FOR DIGITAL EVIDENCE PRESERVATION, PRIVACY, AND RECOVERY - Systems and methods for preserving digital evidence using a self-protecting storage device are provided, by copying digital evidence from a source drive to a self-protecting storage device, writing and storing metadata relating to the copying such as date, time, and those present, and engaging the self-protecting features of the storage device such that the copied digital evidence cannot be altered. | 2013-06-13 |
20130151863 | INTERFACES FOR COMBINING CALLS IN AN EMULATED ENVIRONMENT - Calls from an application in an emulated environment to a module in the operating system hosting the emulated environment may be combined to reduce the overhead of accessing the module. An application handling secure shell (SSH) communications may execute multiple calls to a cryptographic module in the host operating system. Because many calls to the cryptographic module during SSH communications follow patterns, two or more related calls may be combined into a single combined call to the cryptographic module. For example, a call to generate a server-to-client key and a call to generate a client-to-server key may be combined into a single call. | 2013-06-13 |
20130151864 | CLIPBOARD PROTECTION SYSTEM IN DRM ENVIRONMENT AND RECORDING MEDIUM IN WHICH PROGRAM FOR EXECUTING METHOD IN COMPUTER IS RECORDED - Disclosed are a clipboard protection system in a DRM environment and a recording medium in which a program for executing the method in a computer is recorded. An identification information management unit changes first identification information of data, which is to be stored in a clipboard, into second identification information when data stored in the clipboard is requested by a reliable object, and outputs the second identification information corresponding to identification information of the reading target data if the reliable object requests extraction of the data stored in the clipboard. A data protection unit encodes the data, which is to be stored in the clipboard, and decodes the encoded data which is read from the clipboard. If the extraction request for the data stored in the clipboard is inputted from the reliable object, a control unit delivers to a clipboard management system the second identification information corresponding to the identification information of the reading target data, and requests the encoded security data to be read and provided from the clipboard. According to the present invention, the access to the security data by a non-reliable object can be blocked. | 2013-06-13 |
20130151865 | Securing microprocessors against information leakage and physical tampering - A processor system comprising: performing a compilation process on a computer program; encoding an instruction with a selected encoding; encoding the security mutation information in an instruction set architecture of a processor; and executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing a mutation instruction to enable decoding another instruction. A processor system with a random instruction encoding and randomized execution, providing effective defense against offline and runtime security attacks including software and hardware reverse engineering, invasive microprobing, fault injection, and high-order differential and electromagnetic power analysis. | 2013-06-13 |
20130151866 | METHOD AND SYSTEM FOR SECURE DATA STORAGE - A method and system for secure data storage and retrieval is provided. A sequence of data units is divided into multiple subsets of data units corresponding to multiple data channels. The multiple data channels are assigned to multiple data writers based on a key code. Then, each subset of data units is transferred to a writer via an assigned channel for writing to storage media. Thereafter, to securely retrieve the stored data, each subset of data units is read from the storage media using a data reader. The original sequence of data units can only be reassembled using the key code for properly reassembling the subsets of data units into their original sequence. | 2013-06-13 |
20130151867 | SYNCHRONIZED COMMAND THROTTLING FOR MULTI-CHANNEL DUTY-CYCLE BASED MEMORY POWER MANAGEMENT - A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., a synchronization bit or bits) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted. Each of the multiple memory controllers with the asserted associated synchronization indication then transmits the forwarded synchronization command to associated power control logic. | 2013-06-13 |
20130151868 | COMPUTER POWER SUPPLY WITH LOW STANDBY POWER - An emergency communication and dispatching system has an operating console and a plurality of 2-way radios. 2-way radios are carried separately by the staff on duty and communicated with the operating console or other staff. Of which, the operating console could receive the event information and pictures from the reporting source and transmit them to the 2-way radio of any staff, while a camera could be used by the staff to take the pictures at the scenes. The 2-way radio is used to transmit the pictures and position data to the operating console or the receiver of other staff, so as to improve the communication and execution efficiency of public security or military personnel. | 2013-06-13 |
20130151869 | METHOD FOR SOC PERFORMANCE AND POWER OPTIMIZATION - A system and method for efficient management of resources within a semiconductor chip for an optimal combination of power reduction and high performance. An intergrated circuit, such as a system on a chip (SOC), includes at least two processing units. The second processing unit includes a cache. The SOC includes a power management unit (PMU) that determines whether a first activity level for the first processing unit is above a first threshold and a second activity level for the second processing unit is below a second threshold. If this condition is true, then the PMU places a limit on a highest power-performance state (P-state) used by the second processing unit. The PMU sends an indication to flush the at least one cache within the second processing unit. The PMU changes a P-state used by the first processing unit to a higher performance P-state. | 2013-06-13 |
20130151870 | ELECTRONIC DEVICE, STORAGE MEDIUM AND METHOD FOR PROTECTING THE ELECTRONIC DEVICE - In a method for protecting an electronic device, a voltage threshold value is set for indicating that water has entered the electronic device. A voltage value is detected from each water sensor included in the electronic device at a predetermined time interval. The method determines whether water has entered the electronic device according to the detected voltage value of water sensor and the voltage threshold value. When water has entered the electronic device, the method further prompts a user of the electronic device using a predetermined prompt mode, and controls the electronic device to be powered-off. | 2013-06-13 |
20130151871 | Power Management IC Having a Power Supply PWM that is Controllable Using Either an Analog or a Digital Feedback Path - A Power Management Integrated Circuit (PMIC) includes a pulse width modulator and driver circuit (PWMDC), a processor, and high-side and low-side driver circuitry. The PWMDC, along with components external to the PMIC, forms a switching power supply. A small linear regulator powers the PWMDC from power received via a terminal. The power supply supplies power to other on-chip circuitry, including the driver circuitry and processor. The PWMDC starts an on pulse (of a power supply switching cycle) in response to a clock signal. In a first mode, the PWMDC stops the on pulse based on a signal received from a terminal via an analog feedback signal path. In a second mode, the PWMDC stops the on pulse based on a signal received via a digital feedback signal path. In one example, the digital feedback signal path extends from a terminal, through an ADC, processor, and DAC, to an error node. | 2013-06-13 |
20130151872 | POWER SUPPLY DEVICE AND COMPUTER SERVER USING THE SAME - A power supply device for a server device includes a power supply circuit, a control microchip, and a compensation element. The compensation element is a resistor having a negative temperature coefficient. The control microchip controls the power supply circuit to generate an output voltage to power the server device in response to receiving a voltage of an external power supply. When the power supply device generates excessive heat in use, a resistance of the compensation element decreases to maintain a total resistance of the power supply device at substantially an original value. | 2013-06-13 |
20130151873 | IMAGE PROCESSING APPARATUS, CONTROL METHOD THEREFOR, AND COMPUTER-READABLE STORAGE MEDIUM - When an image processing apparatus according to this invention accepts a shutdown instruction, and completes execution of shutdown processing, and switches the operation state of the power source switch to an OFF state using a driving unit of the power source switch if the shutdown instruction is accepted via an external device communicably connected to the image processing apparatus. | 2013-06-13 |
20130151874 | LINKED SHELL - An apparatus and method is provided for controlling a display device for displaying a user interface associated with an application. A processor for controlling peripheral devices and/or the display may be selected based on characteristics of a requested function to be performed. For example, a processor may be selected with a power characteristic corresponding to a power level needed to perform the requested function. Also, an instantiation of a user interface may be switched based on selection of the processor for controlling peripheral devices. In another example, the transition from one instantiation of the user interface to another instantiation of the user interface may be smooth such that a user may be unaware a change has been made. | 2013-06-13 |
20130151875 | Power Manager Tile For Multi-Tile Power Management Integrated Circuit - A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes tiles including an MCU/ADC tile and a power manager tile. The power manager tile includes a set of Configurable Switching Power Supply Pulse Width Modulator (CSPSPWM) components. These components, in combination with other circuitry external to the integrated circuit, are configurable to form a selected one of a number of different switching power supply circuits. Upon power up, an internal regulator supplies power to the CSPSPWM. The CSPSPWM then controls the power supply to begin switching in a low frequency start-up mode. The CSPSPWM determines during start-up the current sensing method based on circuitry external to the integrated circuit. A supply voltage generated is then supplied via a conductor of a standardized bus to a processor in the MCU/ADC tile. The processor begins executing instructions, and as a result writes across the standardized bus to configure the various tiles of the MTPMIC. | 2013-06-13 |
20130151876 | METHOD AND APPARATUS FOR QUICK RESUMPTION - When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed. | 2013-06-13 |
20130151877 | SYSTEMS AND METHODS FOR PREDICTIVE CONTROL OF POWER EFFICIENCY - A computer power management system ( | 2013-06-13 |
20130151878 | INFORMATION PROCESSING APPARATUS WITH FUNCTION TO SOLVE FRAGMENTATION ON MEMORY, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM STORING CONTROL PROGRAM THEREFOR - An information processing apparatus that is capable of reducing fragmentation of use areas on a memory and of shortening waiting time. The information processing apparatus has a volatile first memory and a nonvolatile second memory. A first control unit starts the information processing apparatus without using a hibernation image when a hibernation image is not stored in the second memory at the time of starting the information processing apparatus, and generates a hibernation image in the second memory. A second control unit starts the information processing apparatus while using a hibernation image when the hibernation image is stored in the second memory at the time of starting the information processing apparatus. A third control unit changes a state of the information processing apparatus to a power saving state while keeping power supply to the first memory in response to completion of the starting of the information processing apparatus. | 2013-06-13 |
20130151879 | SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED TRANSIENT DEADLINES - Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors. | 2013-06-13 |
20130151880 | IMAGE PROCESSING APPARATUS, CONTROL METHOD THEREFOR AND STORAGE MEDIUM - When the first time has elapsed after the operator operates a power switch to stop power supply, an image processing apparatus forcibly stops power supply. When stopping power supply, the image processing apparatus executes hibernation processing to retract, in a secondary storage device, the stored content of a main memory used as a work area by a CPU. When the hibernation processing will be completed within a target time necessary to complete the hibernation processing and end processing of the image processing apparatus before the first time elapses, the image processing apparatus executes the end processing of the image processing apparatus and stops power supply after completing the hibernation processing; otherwise, the image processing apparatus interrupts the hibernation processing, executes the end processing of the image processing apparatus, and stops power supply. | 2013-06-13 |
20130151881 | BRIDGING DEVICE AND POWER SAVING METHOD THEREOF - A bridging device and a power saving method thereof are disclosed. When a bridging chip of the bridging device receives a power saving command transferred from a host and thereby enters a power saving state, a voltage converter of the bridging device is disabled accordingly and a selection circuit selects to couple a bus voltage to the bridging chip to power the bridging chip. The bus voltage is transferred from the host through a power pin of a connector of the bridging device. The connector is coupled to the host. | 2013-06-13 |
20130151882 | COMPUTER PRODUCT, CONTROL APPARATUS, AND CONTROL METHOD - A computer-readable recording medium stores a control program causing a processor of a first terminal to execute a process that includes detecting that a remaining battery level of the first terminal has become less than or equal to a first threshold while a task is under execution by the first terminal; suspending execution of the task upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; transmitting identification information of the task to a second terminal upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; receiving from the second terminal and after transmitting the identification information of the task, information related to a potential of executing the task; and transmitting to the second terminal, information corresponding to the information related to the potential of executing the task. | 2013-06-13 |
20130151883 | METHOD AND DEVICES FOR CONTROLLING OPERATIONS OF A CENTRAL PROCESSING UNIT - Provided is a method in a control circuitry controlling the operations of a central processing unit, CPU. The CPU is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. According to the method, the control circuitry controls ( | 2013-06-13 |
20130151884 | CLOUD DATA STORAGE SYSTEM - A cloud data storage system is provided for multiple clients to access data of files comprising at least one node connecting to a first storage means; at least one namenode module for processing file operations issued from the clients, namenode module issuing data access instructions to access and maintain the metadata on the first storage means; at least one datanode module respectively executing on at least one node, each datanode module functioning to scan and access a second storage means connected thereto; at least one data import module selectively executing on nodes in which datanode module are executing, the data import module scanning a second storage means newly connected to the cloud data storage system and obtaining a corresponding metadata, and executing data migration operation for the data in second storage means without actual physical uploading operation. | 2013-06-13 |
20130151885 | COMPUTER MANAGEMENT APPARATUS, COMPUTER MANAGEMENT SYSTEM AND COMPUTER SYSTEM - A service processor is separated into a first management unit which performs a primitive processing such as an access processing of hardware and a computer management device which performs a complex processing such as a monitoring of the hardware. And the computer management device is implemented a virtual machine which performs a hardware control of the plurality of hardware. Thereby, the plurality of service processors is realized by a small number of hardware. | 2013-06-13 |
20130151886 | COMPUTING DEVICE AND METHOD FOR SWITCHING PHYSICAL LINKS OF A SAS EXPANDER OF THE COMPUTING DEVICE - A method switches physical links of a serial attached small computer system interface (SAS) expander of a computing device. If a physical link of the SAS expander is malfunctioning, configuration parameters of the malfunctioned physical link are stored to a storage system of the computing device, and a reserved physical link corresponding to the malfunctioned physical link is selected from firmware of the SAS expander. The method further modifies configuration parameters of the malfunction physical link, produces a new firmware according to the modified configuration parameters and the selected reserved physical link, and switches the malfunctioned physical link to the reserved physical link by writing the new firmware to the SAS expander. | 2013-06-13 |
20130151887 | PERIPHERAL INTERFACE ALERT MESSAGE FOR DOWNSTREAM DEVICE - According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface. | 2013-06-13 |
20130151888 | Avoiding A Ping-Pong Effect On Active-Passive Storage - A technique for avoiding a ping-pong effect on active-passive paths in a storage system managing one or more logical storage units (LUNs) on behalf of one or more host systems. A first path to the LUNs is designated as an active path and a second path to the LUNs is designated as a passive path. The first path is also designated as a preferred path to the LUNs. In response to a path failure in which a host system cannot access the LUNs on the first path, a failover operation is implemented wherein the second path is designated as the active path and the first path is designated as the passive path. The designation of the first path as the preferred path to the LUNs is not changed. Subsequent failback operations are conditionally inhibited so that only the failover host that initiated the failover is permitted to initiate a failback. | 2013-06-13 |
20130151889 | DISK-FREE RECOVERY OF XA TRANSACTIONS FOR IN-MEMORY DATA GRIDS - A data grid node that is hosted by a computing system receives a request to prepare transaction operations for a multi-operational transaction for a commit. The transaction operations are associated with other data grid nodes in the data grid. The data grid node stores transaction state data for the multi-operational transaction in local memory associated with the data grid node and identifies other data grid nodes in the data grid that manage the data pertaining to the transaction operations for the multi-operational transaction. The data grid node sends the transaction state data to the other data grid nodes and the other data grid nodes store the transaction state data in local memory associated with the corresponding data grid node. | 2013-06-13 |
20130151890 | Methods and Systems for Repairing Memory - In accordance with embodiments of the present disclosure, a method may comprise identifying one or more portions of the memory having defects. The method may also include storing one or more addresses in the memory defect list, each of the one or more addresses associated with a portion of the one or more identified portions. The method may further include indicating to components of an information handling system that the one or more identified portions are unusable such that the other components are prevented from allocating and using the one or more identified portions. | 2013-06-13 |
20130151891 | LIMITING CERTAIN PROCESSING ACTIVITIES AS ERROR RATE PROBABILITY RISES - A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change. The data processing apparatus further comprises performance control circuitry configured to determine when the data processing apparatus is operating close to the operating region limits where an error rate is raised and in response to determining operation close to the operating region limits to modify a behaviour of the data processing apparatus by at least one of: limiting speculative processing, and selecting timing insensitive processing paths and circuitry. | 2013-06-13 |
20130151892 | DATA STORING METHOD FOR SOLID STATE DRIVE TO PRESERVE DATA INTEGRITY AFTER POWER FAILURE - A data storing method for a solid state drive is used to preserve data integrity after a power failure. The solid state drive has a flash memory with plural blocks. Each block includes plural pages. One of the plural blocks is set as an old open block. The data storing method includes the following steps. Firstly, the solid state drive is powered on again. Then, the valid data in the old open block are stored into a new open block. | 2013-06-13 |
20130151893 | CUSTOMER PREMISES EQUIPMENT DIAGNOSTIC, RECOVERY, AND REPORTING SYSTEMS AND METHODS - Exemplary customer premises equipment (“CPE”) diagnostic, recovery, and reporting systems and methods are disclosed herein. An exemplary method includes a technical support server subsystem aggregating, over time, technical support data representing technical issues of CPE devices and operations performed to resolve the technical issues, identifying a subset of the technical support data, and providing the identified subset of the technical support data to a CPE device for local storage by the CPE device, locally stored technical support data configured to be used by the CPE device to self-recover from a future technical issue associated with the CPE device. In certain embodiments, the CPE device may be configured to function as a media server device and/or as an intermediary technical support device at a customer premises. Corresponding methods and systems are also disclosed. | 2013-06-13 |
20130151894 | Fault-Tolerant Computer System - A system and method for providing a fault-tolerant basis to execute instructions is disclosed. The system comprises an error detector, a rewriting module, a recovery engine, a fault locator and a fallback programming module. The error detector detects a first error in the execution of an instruction in a faulty stage unit of a first pipeline unit. The rewriting module rewrites the instruction to form a rewritten instruction responsive to detecting the first error. The recovery engine executes the rewritten instruction in the first pipeline unit. The error detector determines if a second error occurs in the execution of the rewritten instruction. Responsive to detecting the second error, the recovery engine selects a substitute stage unit for the faulty stage unit from a second pipeline unit. The fault locator locates a faulty component for the faulty stage unit. The fallback programming module establishes a fallback unit for the faulty component. | 2013-06-13 |
20130151895 | APPARATUS AND METHOD OF MANAGING DATABASES OF ACTIVE NODE AND STANDBY NODE OF MAIN MEMORY DATABASE MANAGEMENT SYSTEM - Databases of an active node and a standby node of a main memory database management system (MMDBMS) are managed so as to prevent loss of a transaction caused by failure of any one of the active node or the standby node. The MMDBMS is configured to prevent data mismatch between the active node and the standby node when failure of any one of the active node and the standby node occurs. In case of failure of one of the nodes, log information from the other node is obtained to recover the failed node. | 2013-06-13 |
20130151896 | INFORMATION PROCESSING APPARATUS AND TEST METHOD - Based on a seed value held by a managing apparatus for a plurality of information processing apparatuses, the same number of seed values as the total number of times of tests conducted by one or more processing units included in an information processing apparatus are generated so as not to overlap with another information processing apparatus. Then, a processing unit of the one or more processing units generates the same number of test instruction sequences as the number of times of tests performed by the processing unit based on the same number of seed values as the number of times of tests performed by the processing unit among the generated seed values, and executes the generated test instruction sequences. | 2013-06-13 |
20130151897 | DIAGNOSTIC HANDLING SERVER, DIAGNOSTIC HANDLING METHOD, AND PROGRAM FOR THE SAME SERVER - A diagnostic handling server is capable of supporting users without operator support, in which the proper handling of a problem, which users know through experience, can be reflected in the support. Preliminarily, data (e.g., dissatisfying item data) on the item with which a user feels dissatisfied and diagnostic data on the diagnoses of the electric appliances are collected from the electric appliances to be supported. The feature points of the respective electric appliances with which the user feels dissatisfied are then extracted from the collected diagnostic data. When the user feels dissatisfied with a specific electric appliance, the diagnostic data of the electric appliance is transmitted together with a search request for the proper handling, the transmitted diagnostic data is compared with the preliminarily extracted feature point, and information on the cause and the proper handling is provided to the user. | 2013-06-13 |
20130151898 | ELECTRONIC CONNECTION QUALITY TEST DEVICE FOR UNIVERSAL SERIAL BUS INTERFACES - An electronic connection quality test device includes a plurality of test circuits, a hot plug circuit, and a control circuit. The test circuits are respectively electrically connected to a plurality of universal serial bus (USB) interfaces. The hot plug circuit is electrically connected to each of the test circuits and a USB device. The control circuit is electrically connected to each of the test circuits and controls the test circuits to electrically connect selected ones of the USB interfaces with the USB device via the test circuits and the hot plug circuit, thereby forming tested electronic connections between the selected ones of the USB interfaces and the USB device. | 2013-06-13 |
20130151899 | DEBUG SYSTEM AND METHOD - A debug system includes a debug device and a computer. The debug device includes a decoding module, a first storing module, a first control module; and a signal receiving and transmitting module. The computer includes a second control module, a second storing module, and a display module. The decoding module decodes data from the LPC bus. The first storing module stores decoded data. The second control module sends a set address data to the first control module via the signal receiving and transmitting module. The first control module obtains a corresponding data from the first storing module according to the set address data and send the corresponding data to the second control module via the signal receiving and transmitting module. The second control module stores the corresponding data to the second storing module and displays the corresponding data on the display module. | 2013-06-13 |
20130151900 | DEBUG SYSTEM AND METHOD - A debug system includes a debug device and a computer. The debug device includes an SPI reading and writing module, a first control module, a detecting module, and a signal receiving and transmitting module. The computer includes a second control module and a display module. The SPI reading and writing module is connected to an SPI device. The second control module sends an inputted write command to the first control module. The first control module writes data to the SPI device according to the inputted write command. The detecting module sends a fail signal to the first control module after detecting that the data is not written to the SPI device and a written times of the data is greater than a predetermined times. The first control module sends the fail signal to the second control module. The second control module displays the fail signal on the display module. | 2013-06-13 |
20130151901 | High Volume Recording of Instrumentation Data Varying Instrumentation Volumes to Prevent Data Loss - This invention is an apparatus and method for monitoring an electronic apparatus. At least one capture unit captures data to be monitored. A repeater corresponding to each capture unit repeats the captured data. A first-in-first-out buffer corresponding to each capture unit temporarily stores the captured data. The buffered data supplies a utilization unit. Captured data may be merged after repeating. The capture unit may be in a different voltage domain than the repeater, buffer and utilization unit. | 2013-06-13 |
20130151902 | DEBUG SYSTEM AND METHOD - A debug system includes a debug device and a computer. The debug device includes an IIC reading and writing module, a first control module; and a signal receiving and transmitting module. The computer includes a second control module. The IIC reading and writing module is connected to an IIC device. The second control module sends an inputted command to the first control module via the signal receiving and transmitting module. The first control module reads data from the IIC device or writes data to the IIC device via the IIC reading and writing module according to the inputted command | 2013-06-13 |
20130151903 | IMAGE FORMING APPARATUS - An image forming apparatus has a plurality of device modules for executing predetermined functions; and a control module for controlling operation of the device modules. The control module comprises an initialization section for establishing a link; a master data transfer section for transferring data to a device module; and a link checking section for checking the state of the link. When a request for data transfer to a first device module out of the plurality of device modules is made, the link checking section checks the state of the link between the control module and the first device module. When the state of the link checked is determined to be abnormal, the initialization section establishes the link between the control module and the first device module, and then the master data transfer section transfers the data requested to be transferred to the first device module. | 2013-06-13 |
20130151904 | Memory-Module Extender Card for Visually Decoding Addresses from Diagnostic Programs and Ignoring Operating System Accesses - A diagnostic extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module and an intercepting decoder chip that receives the chip-select (CS) from the motherboard that selects the memory module for access. When CS is activated, the intercepting decoder chip illuminates a visual indicator on the extender card, allowing a user to locate a memory module being accessed. The exact translation or mapping from logical addresses of test programs to physical addresses of the memory modules is not needed, since the visual indicator shows which memory module is really being accessed, regardless of proprietary address mapping by north bridge chips. Operating system memory accesses are filtered out by a counter that counts accesses during a period set by a timer. When the number of accesses exceeds a threshold, the visual indicator is lit. | 2013-06-13 |
20130151905 | Testing A Network Using Randomly Distributed Commands - Methods and test systems for testing a network. A test system may emulate a plurality of users, each emulated user executing a user activity. Each emulated user activity may include one or more commands. At least some emulated user activities may include a command randomly selected from a predefined command pool in accordance with an associated probability distribution. The test system may report a result of emulating the plurality of users. | 2013-06-13 |
20130151906 | Analysis of Tests of Software Programs Based on Classification of Failed Test Cases - A solution is proposed for analyzing a test of a software program comprising a plurality of software components, the test comprising a plurality of test cases each one for exercising a set of corresponding exercised software components. A corresponding method comprises the steps of receiving an indication of each failed test case whose current execution has failed, retrieving a suspicion attribute of each failed test case indicative of a change to the corresponding exercised software components since a previous execution of the failed test case, retrieving a change attribute of each failed test case indicative of a change to the failed test case since the previous execution thereof, retrieving a regression attribute of each failed test case indicative of a regression of the failed test case since the previous execution thereof, and classifying each failed test case into a plurality of disjoint classes according to the corresponding suspicion attribute, change attribute and regression attribute. | 2013-06-13 |
20130151907 | OPERATIONS MANAGEMENT APPARATUS, OPERATIONS MANAGEMENT METHOD AND PROGRAM - A correlation mode is updated quickly in the case that monitored metrics arc changed. | 2013-06-13 |
20130151908 | VIRTUAL COMPUTER SYSTEM HAVING SR-IOV COMPLIANT DEVICE MOUNTED THEREON AND FAILURE DETECTION METHOD - A failure detection method including: detecting, by a virtual computer, occurrence of the failure in a virtual function of an I/O device; acquiring, a virtual device name corresponding to the virtual function in which the failure has occurred; referring, to device information retaining a virtual device name of the I/O device assigned to the virtual computer and VF specific information on the I/O device, thereby acquiring the VF specific information based on the acquired virtual device name; transmitting, the acquired VF specific information to the host; referring, by the host, to I/O correspondence information retaining a slot number of a slot in which the I/O device is mounted, and VF specific information, thereby acquiring the slot number corresponding to the VF specific information received from the virtual computer; and identifying, the acquired slot number as the slot number of the I/O device on which the failure has occurred. | 2013-06-13 |
20130151909 | SYSTEM CONTROL DEVICE, LOG CONTROL METHOD, AND INFORMATION PROCESSING DEVICE - When an error has occurred in one of a plurality of partitions and when an unused area is present in a log area, an information processing device allocates the unused area to the log area of the partition in which the error has occurred and stores a log of the error that has occurred. When an error has occurred in one of the plurality of partitions, when an unused area is not present in a log area, and when a registration count registered in a log area associated with the partition in which the error has occurred exceeds an upper limit, the information processing device allocates, to the log area of the partition in which the error has occurred, the oldest entry in a log area that stores therein error logs the number of which is equal to or greater than an upper limit count that is previously set and stores the log of the error that has occurred. | 2013-06-13 |
20130151910 | SYMBOL ENCODING FOR TOLERANCE TO SINGLE BYTE ERRORS - The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol. | 2013-06-13 |
20130151911 | REDUCTION IN DECODER LOOP ITERATIONS - An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information. | 2013-06-13 |
20130151912 | ENHANCED ERROR CORRECTION IN MEMORY DEVICES - A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position. | 2013-06-13 |
20130151913 | Expedited Memory Drive Self Test - Expedited memory drive self test, including: determining, by a drive self test module, a base block size for testing a memory drive; determining, by a drive self test module, a block group size for testing a memory drive; determining, by the drive self test module, a percentage of the memory drive to test; and for each block group size of memory in the memory drive: testing for media defects, by the drive self test module, a number of blocks in a block group that corresponds to the percentage of the memory drive to test. | 2013-06-13 |
20130151914 | FLASH ARRAY BUILT IN SELF TEST ENGINE WITH TRACE ARRAY AND FLASH METRIC REPORTING - A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array. | 2013-06-13 |
20130151915 | EFFICIENCY OF COMPRESSION OF DATA PAGES - A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied. | 2013-06-13 |
20130151916 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT - An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. | 2013-06-13 |
20130151917 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 2013-06-13 |
20130151918 | IIMPLEMENTING ENHANCED APERTURE FUNCTION CALIBRATION FOR LOGIC BUILT IN SELF TEST (LBIST) - A method and circuits for implementing aperture function calibration for Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. The aperture function calibration uses aperture calibration data, and an LBIST calibration channel having a predefined number of scan inversions between the aperture calibration data and a multiple input signature register (MISR). LBIST is run selecting the LBIST calibration channel and masking other LBIST channels to the MISR. A change in the MISR value, for example, from zero to a non-zero value, is identified and an aperture adjustment is calculated and used to identify any needed adjustment of aperture edges. | 2013-06-13 |
20130151919 | Programmable Fault Protect for Processor Controlled High-Side and Low-Side Drivers - A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes a processor, a fault protect circuit, a first terminal, a driver that drives the first terminal, a second terminal, and detection circuitry that outputs a digital detection signal indicative of whether a predetermined condition is detected on the second terminal. The processor can program the fault protect circuit so that the fault protect circuit will later disable the driver as a function of multiple signals, including the digital detection signal. The function is programmable by the processor. In one example, if the detection circuitry detects the predetermined condition on the second terminal then the fault protect circuit disables all the high-side drivers and all low-side drivers of the MTPMIC independently of and without input from the processor. | 2013-06-13 |
20130151920 | METHOD AND APPARATUS FOR DECODING - Aspects of the disclosure can provide a method and an apparatus to decode a data stream based on multiple transmissions with efficient usages of storage and power resources. The method can include receiving a first plurality of encoded code blocks corresponding to a first transmission of a transport block, decoding the first plurality of encoded code blocks into decoded code blocks, error detecting the decoded code blocks, and storing a decoding history of the decoded code blocks. Further, the method can include receiving a second plurality of encoded code blocks corresponding to a retransmission of the transport block. The second plurality of encoded code blocks can map the first plurality of encoded code blocks, respectively. The method can selectively decode a subset of the second plurality of encoded code blocks based on the decoding history. In addition, the method can include storing soft bits for code blocks that failed decoding. | 2013-06-13 |
20130151921 | ENCODING APPARATUS, ENCODING METHOD AND SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, an encoding apparatus includes an input unit and a generation unit. The input unit inputs a data symbol sequence containing q(N−J) symbols (q, J, and N are integers, N>J). The generation unit generates a codeword containing qN symbols by adding a parity symbol sequence containing qJ symbols to the data symbol sequence. The codeword satisfies parity check equations of a parity check matrix of qJ rows×qN columns. A first submatrix of qJ rows×qJ columns that corresponds to the parity symbol sequence in the parity check matrix includes a second submatrix. The second submatrix includes a first identity matrix of qL rows×qL columns (L is an integer, J>L) and a first non-zero matrix of q(J−L) rows×qL columns. | 2013-06-13 |
20130151922 | LOW DENSITY PARITY CHECK DECODER FOR IRREGULAR LDPC CODES - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order. | 2013-06-13 |