24th week of 2013 patent applcation highlights part 15 |
Patent application number | Title | Published |
20130146917 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a semiconductor lamination including a first semiconductor layer of a first conductivity type, an active layer formed on the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed on the active layer; a rhodium (Rh) layer formed on one surface of the semiconductor lamination; a light reflecting layer containing Ag, formed on the Rh layer and having an area smaller than the Rh layer; and a cap layer covering the light reflecting layer. Migration of Ag is suppressed. | 2013-06-13 |
20130146918 | Yttrium aluminum garnet phosphor, method for preparing the same, and light-emitting diode containing the same - The present invention relates to yttrium aluminum garnet phosphor, a method of preparing the same and a light-emitting diode containing the same. The yttrium aluminum garnet phosphor of the present invention is represented by the following formula (I): | 2013-06-13 |
20130146919 | RADIATION-EMITTING COMPONENT - A radiation-emitting component includes a semiconductor layer stack having an active region that emits electromagnetic radiation, and at least one surface of the semiconductor layer stack or of an optical element that transmits the electromagnetic radiation wherein the surface has a normal vector, wherein on the at least one surface of the semiconductor layer stack or of the optical element through which the electromagnetic radiation passes, an antireflection layer is arranged such that, for a predetermined wavelength, it has a minimum reflection at a viewing angle relative to the normal vector of the surface at which an increase in a zonal luminous flux of the electromagnetic radiation has approximately a maximum. | 2013-06-13 |
20130146920 | ULTRAVIOLET LIGHT EMITTING DEVICE - The ultraviolet light emitting device includes a substrate; a light emitting structure on the substrate, and including a plurality of compound semiconductors, each including at least a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a first electrode layer on the first conductive semiconductor layer; and a second electrode layer on the second conductive semiconductor layer. The first electrode layer is spaced apart from a side surface of the active layer, and is provided along a peripheral portion of the active layer. At least one of the first and second electrode layers is a reflective layer. | 2013-06-13 |
20130146921 | LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF - A light emitting device and a fabricating method thereof are described. The light emitting device includes a substrate, a light emitting chip, a tubular structure, and a fluorescent conversion layer. The tubular structure is formed on a surface of the substrate. The light emitting chip is disposed on the surface of the substrate and is surrounded by the tubular structure. The fluorescent conversion layer is disposed in the tubular structure and covers the light emitting chip. A ratio of a maximal vertical thickness and a maximal horizontal thickness of the fluorescent conversion layer at the light emitting chip is between 0.1 and 10. A distance for the light ray to pass through the fluorescent conversion layer is controlled by using the tubular structure, so as to solve a problem of the conventional art that fluorescent powder coating package technique results in non-uniform color temperature of the emitted light. | 2013-06-13 |
20130146922 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The light emitting device includes a first conductive type semiconductor layer; an active layer on the first conductive type semiconductor layer; and a first electrode pad including a plurality of reflective layers on the first conductive type semiconductor layer. | 2013-06-13 |
20130146923 | LIGHT EMITTING APPARATUS - Provided is a light emitting apparatus. The light emitting apparatus includes a substrate; a light emitting device on the substrate; a fluorescent layer formed on the substrate and the light emitting device to surround the light emitting device; an encapsulant resin layer formed on the substrate and the fluorescent layer to surround the fluorescent layer; and a lens disposed on the light emitting device and supported by the substrate, wherein the lens includes a lens body having a first recess formed at a center of a top surface of the lens body and a second recess formed at a center of a bottom surface of the lens body, and a lens supporter provided at the bottom surface of the lens body to support the lens body such that the lens body is spaced apart from the substrate. | 2013-06-13 |
20130146924 | LIGHT EMITTING DEVICE - According to one embodiment, a light emitting device includes a semiconductor light emitting element, a mounting member, a first wavelength conversion layer, and a first transparent layer. The semiconductor light emitting element emits a first light. The semiconductor light emitting element is placed on the mounting member. The first wavelength conversion layer is provided between the semiconductor light emitting element and the mounting member in contact with the mounting member. The first wavelength conversion layer absorbs the first light and emits a second light having a wavelength longer than a wavelength of the first light. The first transparent layer is provided between the semiconductor light emitting element and the first wavelength conversion layer in contact with the semiconductor light emitting element and the first wavelength conversion layer. The first transparent layer is transparent to the first light and the second light. | 2013-06-13 |
20130146925 | LIGHT EMITTING DIODE HAVING DISTRIBUTED BRAGG REFLECTOR - A light-emitting diode (LED) according to an exemplary embodiment includes a light-emitting structure arranged on a first surface of a substrate, the light-emitting structure including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. A first distributed Bragg reflector is arranged on a second surface of the substrate opposite to the first surface, the first distributed Bragg reflector to reflect light emitted from the light-emitting structure. The first distributed Bragg reflector has a reflectivity of at least 90% with respect to blue, green, and red light. | 2013-06-13 |
20130146926 | ILLUMINATING APPARATUS - Provided is a lighting apparatus that is suitable as a substitute for a conventional halogen lamp when positively utilizing leaked light. The lighting apparatus comprises: a heat dissipator | 2013-06-13 |
20130146927 | METHOD FOR COATING PHOSPHOR, APPARATUS TO PERFORM THE METHOD, AND LIGHT EMITTING DIODE COMPRISING PHOSPHOR COATING LAYER - A method of forming a phosphor coating layer on a light emitting diode (LED) chip using electrophoresis includes separating phosphor particles in a suspension according to a particle size, and coating the phosphor particles on a surface of the LED chip by sequentially depositing the separated phosphor particles on the surface of the LED chip according to the particle size. An apparatus to form a phosphor coating layer on an LED chip includes an electrophoresis bath to accommodate a suspension containing phosphor particles separated into layers according to a particle size, and electrodes disposed inside the electrophoresis bath. The electrodes may include a cathode electrode on which the LED chip may be arranged, and an anode electrode. | 2013-06-13 |
20130146928 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A nitride semiconductor light-emitting element | 2013-06-13 |
20130146929 | LIGHT EMITTING DIODE - Disclosed is a light emitting diode (LED) comprising a light emitting stacked structure and an electrode structure formed to have a pattern on the light emitting stacked structure. The electrode structure of the LED includes a cluster of reflectors disposed along the pattern on the light emitting stacked structure, and a pad material layer formed to entirely cover the reflectors. | 2013-06-13 |
20130146930 | PHOSPHOR AND LIGHT EMITTING DEVICE - The present invention provides a phosphor emitting green fluorescence when being effectively excited by excitation light in a wavelength range from blue light to near-ultraviolet light, having an emission intensity that does not vary significantly with variation in the wavelength of the excitation light, and being manufactured easily. The phosphor includes a chemical structure represented by the following general formula (A): | 2013-06-13 |
20130146931 | PIXEL STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A pixel structure and manufacturing method of the same are described. The pixel structure includes a substrate, a switch transistor, a dielectric layer, a conducting connection line, a driving transistor, a capacitor and a pixel electrode. The substrate defines a transistor region and the switch transistor is disposed on the transistor region. The dielectric layer is disposed on the substrate and covers the switch transistor. The conducting connection line disposed on the dielectric layer is located over the transistor region. The driving transistor disposed on the dielectric layer is vertically stacked over the switch transistor and transistor region. The conducting connection line electrically connects the switch transistor to the driving transistor. The pixel electrode is electrically connected to the driving transistor. | 2013-06-13 |
20130146932 | LIGHT-EMITTING DIODE ARCHITECTURES FOR ENHANCED PERFORMANCE - The present invention relates to light-emitting diodes (LEDs), and related components, processes, systems, and methods. In certain embodiments, an LED that provides improved optical and thermal efficiency when used in optical systems with a non-rectangular input aperture (e.g., a circular aperture) is described. In some embodiments, the emission surface of the LED and/or an emitter output aperture can be shaped (e.g., in a non-rectangular shape) such that enhanced optical and thermal efficiencies are achieved. In addition, in some embodiments, chip designs and processes that may be employed in order to produce such devices are described. | 2013-06-13 |
20130146933 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF FORMING THE SAME - A semiconductor light-emitting device has a first principal surface, a second principal surface formed on a side opposite to the first principal surface, and a light-emitting layer. A p-electrode on the second principal surface is in the region of the light-emitting layer and surrounds an n-electrode. An insulating layer on the side of the semiconductor layer surrounds the p- and the n-electrodes. A p-metal pillar creates an electrical connection for the p-electrode, and an n-metal pillar creates an electrical connection for the n-electrode. A resin layer surrounds the end. portions of the p- and the n-metal pillars, and also covers the side surface of the semiconductor layer, the second principal surface, the p-electrode, the n-electrode, the insulating layer, the p-metal pillar and the n-metal pillar. | 2013-06-13 |
20130146934 | LIGHT-EMITTING DIODE DEVICE - A light-emitting diode device includes a substrate, an epitaxial layer and a first electrode. The epitaxial layer is disposed on the substrate. The first electrode is disposed on the epitaxial layer and includes a connecting portion and a conductive finger. The conductive finger has a first end and a second end, and the first end is connected to the connecting portion. At least one portion of the conductive finger is tapered along an extending direction of the conductive finger. | 2013-06-13 |
20130146935 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THEREOF - Provided is a semiconductor light emitting device. The semiconductor light emitting device includes a light emitting structure disposed under an insulating layer having a plurality of holes. A first electrode is disposed on the insulating layer and a second electrode disposed is disposed under the light emitting structure. A conductive supporting member is disposed under the second electrode. The plurality of contact protrusions are disposed in the holes of the insulating layer and include filler connected to the first conductive semiconductor layer and disposed in the plurality of holes. The conductive supporting member physically contacts with the second electrode and has a thickness thicker than that of the insulating layer. The first electrode is located at a higher position than an entire region of the insulating layer and the insulating layer is located at a higher position than an entire region of the light emitting structure. | 2013-06-13 |
20130146936 | LIGHT EMITTING DIODE CHIP, LIGHT EMITTING DIODE PACKAGE STRUCTURE, AND METHOD FOR FORMING THE SAME - A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than O. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency. | 2013-06-13 |
20130146937 | MOUNTING SUBSTRATE, LIGHT-EMITTING DEVICE, AND LAMP - A substrate having a mounting surface on which an LED is mounted, including: a conductive member provided on the mounting surface and including an electrode and wiring which are electrically connected to the LED; a fitting portion to which a metal body is fitted; and a discharge-reducing portion provided between the conductive member and the fitting portion and having a face tilted with respect to a surface of the mounting substrate, thereby increasing a creeping distance between the conductive member and the fitting portion compared to the case where the discharge-reducing portion is not provided. | 2013-06-13 |
20130146938 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME - An exemplary embodiment described technology relates generally to an organic light emitting diode (OLED) display and a manufacturing method thereof. The organic light emitting diode (OLED) display according to an exemplary embodiment includes: a substrate; an encapsulation member; an organic light emitting element between the substrate and the encapsulation member; a middle sealing member including one side disposed between the substrate and the encapsulation member and another side extended from the one side to be bent and enclosing an edge of the encapsulation member; a first sealant sealing and combining the one side of the middle sealing member and the substrate to each other; a second sealant sealing and combining the other side of the middle sealing member and the encapsulation member to each other; and a getter at the one side of the middle sealing member and the encapsulation member. | 2013-06-13 |
20130146939 | SILICONE ADHESIVE FOR SEMICONDUCTOR ELEMENT - A silicone adhesive for a semiconductor element that is suitable as a die bonding material for fixing a light emitting diode chip to a substrate. The adhesive includes (a) an addition reaction-curable silicone resin composition having a viscosity at 25° C. of not more than 100 Pa·s, and yielding a cured product upon heating at 150° C. for 3 hours that has a type D hardness prescribed in JIS K6253 of at least 30, (b) a white pigment powder having an average particle size of less than 1 μm, and (c) a white or colorless and transparent powder having an average particle size of at least 1 μm but less than 10 μm. The adhesive exhibits high levels of concealment, effectively reflects light emitted from the LED chip, and also exhibits favorable chip positioning properties, superior adhesive strength, and excellent durability. | 2013-06-13 |
20130146940 | DESIGN STRUCTURE INCLUDING VOLTAGE CONTROLLED NEGATIVE RESISTANCE - Aspects of the invention provide a semiconductor tunneling device including voltage controlled negative resistance. In one embodiment, the semiconductor tunneling device includes: at least one pair of spaced apart terminals; an inter-level dielectric (ILD) layer between the at least one pair of spaced apart terminals; and a dielectric capping layer extending continuously over the at least one pair of spaced apart terminals and the ILD layer. | 2013-06-13 |
20130146941 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor having a gate electrode, a first electrode, and a second electrode and first and second protection circuits each having one end commonly connected to the gate electrode and the other end connected to the first and second electrodes, respectively. The first and second protection circuits are formed in first and second polysilicon layers, respectively, formed separately on a single field insulating film. | 2013-06-13 |
20130146942 | Method for Making FinFETs and Semiconductor Structures Formed Therefrom - A method for making FinFETs and semiconductor structures formed therefrom is disclosed, comprising: providing a SiGe layer on a Si semiconductor substrate and a Si layer on the SiGe layer, wherein the lattice constant of the SiGe layer matches that of the substrate; patterning the Si layer and the SiGe layer to form a Fin structure; forming a gate stack on top and both sides of the Fin structure and a spacer surrounding the gate stack; removing a portion of the Si layer which is outside the spacer with the spacer as a mask, while keeping a portion of the Si layer which is inside the spacer; removing a portion of the SiGe layer which is kept after the patterning, to form a void; forming an insulator in the void; and epitaxially growing stressed source and drain regions on both sides of the Fin structure and the insulator. | 2013-06-13 |
20130146943 | IN SITU GROWN GATE DIELECTRIC AND FIELD PLATE DIELECTRIC - Methods and apparatuses are disclosed for providing heterostructure field effect transistors (HFETs) with high-quality gate dielectric and field plate dielectric. The gate dielectric and field plate dielectric are in situ deposited on a semiconductor surface. The location of the gate electrode may be defined by etching a first pattern in the field plate dielectric and using the gate dielectric as an etch-stop. Alternatively, an additional etch-stop layer may be in situ deposited between the gate dielectric and the field plate dielectric. After etching the first pattern, a conductive material may be deposited and patterned to define the gate electrode. Source and drain electrodes that electrically contact the semiconductor surface are formed on opposite sides of the gate electrode. | 2013-06-13 |
20130146944 | SEMICONDUCTOR DEVICE INCLUDING STEPPED GATE ELECTRODE AND FABRICATION METHOD THEREOF - Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer. | 2013-06-13 |
20130146945 | FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION - A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode. | 2013-06-13 |
20130146946 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SAME - A semiconductor device includes: a buffer layer provided on a substrate and made of a group III-V nitride semiconductor; a first semiconductor layer provided on the buffer layer and made of a group III-V nitride semiconductor; a second semiconductor layer provided on the first semiconductor layer and made of a group III-V nitride semiconductor; a back electrode provided on a back surface of the substrate and connected to a ground; a source electrode and a drain electrode provided on the second semiconductor layer so as to be apart from each other; a gate electrode provided on the second semiconductor layer; and a plug which passes through the second semiconductor layer, the first semiconductor layer, and the buffer layer, and reaches at least the substrate to electrically connect the source electrode and the back electrode. | 2013-06-13 |
20130146947 | SELF-ALIGNED EMITTER-BASE IN ADVANCED BiCMOS TECHNOLOGY - A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot. | 2013-06-13 |
20130146948 | MICROMECHANICAL DEVICE AND METHODS TO FABRICATE SAME USING HARD MASK RESISTANT TO STRUCTURE RELEASE ETCH - A structure includes a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor having metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a hard mask formed as a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer. The hard mask protects the underlying material during a MEMS/NEMS HF vapor release procedure. | 2013-06-13 |
20130146949 | MECHANISMS FOR FORMING STRESSOR REGIONS IN A SEMICONDUCTOR DEVICE - The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved. | 2013-06-13 |
20130146950 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacture method thereof include a silicide material formed on a source region and a drain region on opposite sides of a gate, wherein the gate having sidewalls on both side surfaces is formed on a substrate. The gate has a first sidewall spacer and a second sidewall spacer on each sidewall, the first spacer has a horizontal portion and a vertical portion, the horizontal portion is located between the second sidewall spacer and the substrate, the vertical portion is located between the second sidewall spacer and the sidewalls. A protecting layer is selectively deposited on the silicide material. | 2013-06-13 |
20130146951 | CROSS-HAIR CELL WORDLINE FORMATION - Methods and devices depicting fabrication of non-planar access devices having fins and narrow trenches, among which is a method that includes wet etching a conductor to form a recessed region and subsequently etching the conductor to form gates on the fins. The wet etching may include formation of recesses which are may be backfilled with a fill material to form spacers on the conductor. Portions of a plug may be removed during the wet etch to form overhanging spacers to provide further protection of the conductor during the dry etch. | 2013-06-13 |
20130146952 | ON-CHIP CAPACITORS IN COMBINATION WITH CMOS DEVICES ON EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATES - A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material. | 2013-06-13 |
20130146953 | Method and Structure For Forming ETSOI Capacitors, Diodes, Resistors and Back Gate Contacts - An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI and BOX layers in a replacement gate HK/MG flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch. | 2013-06-13 |
20130146954 | Method Of Memory Array And Structure Form - The present invention provides a memory array including a substrate, an isolation region, a plurality of active regions, a plurality of buried bit lines, a plurality of word lines, a plurality of drain regions and a plurality of capacitors. The isolation region and the active regions are disposed in the substrate and the active regions are encompassed and isolated by the isolation region. The buried bit lines are disposed in the substrate and extend in the second direction. The word lines are disposed in the substrate extend in the first direction. The drain regions are disposed in the active region not covered by the word lines. The capacitors are disposed on the substrate and electrically connected to the drain regions. | 2013-06-13 |
20130146955 | ELECTRONIC CHIP HAVING CHANNELS THROUGH WHICH A HEAT TRANSPORT COOLANT CAN FLOW, ELECTRONIC COMPONENTS AND COMMUNICATION ARM INCORPORATING SAID CHIP - The invention relates to an electronic chip, comprising: a semiconductor substrate ( | 2013-06-13 |
20130146956 | FIELD EFFECT TRANSISTORS (FETS) AND METHODS OF MANUFACTURE - An improved field effect transistors (FETs) and methods of manufacturing the field effect transistors (FETs) are provided. The method of manufacturing a zero capacitance random access memory cell (ZRAM) includes comprises forming a finFET on a substrate and enhancing a storage capacitance of the finFET. The enhancement can be by either adding a storage capacity to the finFET or altering a portion of the finFET after formation of a fin body of the finFET. | 2013-06-13 |
20130146957 | EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE FORMED IN AN EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATE - A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill. | 2013-06-13 |
20130146958 | METHOD FOR FORMING BURIED BIT LINE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND FABRICATING METHOD THEREOF - A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines. | 2013-06-13 |
20130146959 | Method and Structure For Forming On-Chip High Quality Capacitors With ETSOI Transistors - An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch. | 2013-06-13 |
20130146960 | MEMORY CELLS HAVING A PLURALITY OF CONTROL GATES AND MEMORY CELLS HAVING A CONTROL GATE AND A SHIELD - Various embodiments comprise apparatuses having a number of memory cells. In one such apparatus, each cell has a plurality of control gates. For example, each of two control gates is adjacent a respective side of a charge storage structure. In another apparatus, each cell has a control gate and a shield, such as where the control gate is adjacent one side of a charge storage structure and the shield is adjacent another side of the charge storage structure. Additional apparatuses and methods are described. | 2013-06-13 |
20130146961 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern. | 2013-06-13 |
20130146962 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a plurality of first trenches having a first depth formed in a semiconductor substrate, a plurality of second trenches having a second depth formed in the semiconductor substrate, wherein the second depth is different from the first depth and the second trenches are formed between the first trenches, a plurality of isolation layers formed at the plurality of first trenches and the plurality of second trenches, wherein the isolation layers have upper portions formed above the semiconductor substrate, and a plurality of memory cells formed over the semiconductor substrate between the isolation layers. | 2013-06-13 |
20130146963 | METHODS OF FORMING NON-VOLATILE MEMORY - Methods of forming non-volatile memory is described. The non-volatile memory includes a substrate having a source region, a drain region and a channel region. The channel region separates the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A floating gate electrode is adjacent to the electrically insulating layer. The electrically insulating layer separates the floating gate electrode from the channel region. The floating gate electrode has a floating gate major surface. A control gate electrode has a control gate major surface and the control gate major surface opposes the floating gate major surface. A vacuum layer or gas layer at least partially separates the control gate major surface from the floating gate major surface. | 2013-06-13 |
20130146964 | METHOD OF PRODUCING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes the steps of forming a planar silicon layer, first and second pillar-shaped silicon layers on a silicon substrate; forming a gate insulating film, depositing a metal film and a polysilicon around the gate insulating film, conducting planarization, conducting etching to expose upper portions of the first and second pillar-shaped silicon layers, forming first and second insulating film sidewalls, and forming first and second gate electrodes and a gate line; forming n-type diffusion layers in upper and lower portions of the first pillar-shaped silicon layer, and forming p-type diffusion layers in upper and lower portions of the second pillar-shaped silicon layer; forming a third insulating film sidewall on side walls of the first and second insulating film sidewalls, the first and second gate electrodes, and the gate line; and forming a silicide. | 2013-06-13 |
20130146965 | METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED DRAIN REGIONS OF CMOS TRANSISTORS - A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer. | 2013-06-13 |
20130146966 | SEMICONDUCTOR STRUCTURE WITH ENHANCED CAP AND FABRICATION METHOD THEREOF - A semiconductor structure includes a substrate, a feature on the substrate, a spacer on a sidewall surface of the feature, and an enhanced cap disposed on an upper surface of the spacer. The enhanced cap compensates the thinner upper portion of the spacer. | 2013-06-13 |
20130146967 | Trench-Gate Resurf Semiconductor Device and Manufacturing Method - A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device. | 2013-06-13 |
20130146968 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step. | 2013-06-13 |
20130146969 | SWITCHING ELEMENT AND MANUFACTURING METHOD THEREOF - A switching element is provided having a semiconductor substrate. A trench gate electrode is formed in the upper surface of the semiconductor substrate. An n-type first semiconductor region, a p-type second semiconductor region, and an n-type third semiconductor region are formed in a region in contact with a gate insulating film in the semiconductor substrate. At a position below the second semiconductor region, there is formed a p-type fourth semiconductor region connected to the second semiconductor region and opposing the gate insulating film via the third semiconductor region and containing boron. A high-concentration-carbon containing region having a carbon concentration higher than that of a semiconductor region exposed on the lower surface of the semiconductor substrate is formed in at least a part of the portion of the third semiconductor region, positioned between the fourth semiconductor region and the gate insulating film, that is in contact with the fourth semiconductor region. | 2013-06-13 |
20130146970 | Semiconductor Device Including First and Second Semiconductor Elements - A semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient α | 2013-06-13 |
20130146971 | Semiconductor Device Including First and Second Semiconductor Elements - A semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient α | 2013-06-13 |
20130146972 | SEMICONDUCTOR DEVICE HAVING ISOLATION TRENCHES - A semiconductor uses an isolation trench, and one or more additional trenches to those required for isolation are provided. These additional trenches can be connected between a transistor gate and the drain to provide additional gate-drain capacitance, or else they can be used to form series impedance coupled to the transistor gate. These measures can be used separately or in combination to reduce the switching speed and thereby reduce current spikes. | 2013-06-13 |
20130146973 | CUSTOMIZED SHIELD PLATE FOR A FIELD EFFECT TRANSISTOR - A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications. | 2013-06-13 |
20130146974 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A method of forming a semiconductor device is provided. The method includes preparing a substrate having a transistor region and an alignment region, forming a first trench and a second trench in the substrate of the transistor region and in the substrate of the alignment region, respectively, forming a drift region in the substrate of the transistor region, forming two third trenches respectively adjacent to two ends of the drift region, and forming an isolation pattern in the first trench, a buried dielectric pattern in the second trench, and dielectric patterns in the two third trenches, respectively. A depth of the first trench is less than a depth of the third trenches, and the depth of the first trench is equal or substantially equal to a depth of the second trench. | 2013-06-13 |
20130146975 | SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT WITH HIGH-K/METAL GATE WITHOUT HIGH-K DIRECT CONTACT WITH STI - A method, semiconductor device, and integrated circuit with a high-k/metal gate without high-k direct contact with STI. A high-k dielectric and a pad film are deposited directly onto a semiconductor substrate. Shallow trench isolation is performed, with shallow trenches etched directly into the pad film, the high-k material, and the substrate. The shallow trench is lined with an oxygen diffusion barrier and is subsequently filled with an insulating dielectric material. Thereafter the pad film and the insulating dielectric are recessed to a point where the oxygen diffusion barrier still remains between the insulating dielectric and the high-k material, preventing any contact there between. Afterwards a conductive gate is formed overlying the device. | 2013-06-13 |
20130146976 | INTEGRATED CIRCUITS FORMED ON STRAINED SUBSTRATES AND INCLUDING RELAXED BUFFER LAYERS AND METHODS FOR THE MANUFACTURE THEREOF - Embodiments of a method for producing an integrated circuit are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes providing a strained substrate having an n-active region and a p-active region, etching a cavity into one of the n-active region and the p-active region, embedding a relaxed buffer layer within the cavity, forming a body of strain material over the relaxed buffer layer having a strain orientation opposite that of the strained substrate, and fabricating n-type and t-type transistors over the n-active and p-active regions, respectively. The channel of the n-type transistor extends within one of the strained substrate and the body of strain material, while the channel of the p-type transistor extends within the other of the strained substrate and the body of strain material. | 2013-06-13 |
20130146977 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention discloses a semiconductor structure comprising: a semiconductor base located on an insulating layer, which is located on a semiconductor substrate; source/drain regions adjacent to opposite first sides of the semiconductor base; gates, positioned on a second set of two sides of the semiconductor base and said second set of two sides are opposite to each other; an insulating plug located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer located between the insulating plug and the semiconductor base wherein the epitaxial layer is SiC for an NMOS device and the epitaxial layer is SiGe for a PMOS device. The present invention further discloses a method for manufacturing a semiconductor structure. The stress at the channel region is adjusted by forming a strained epitaxial layer, thus carrier mobility is improved and the performance of the semiconductor device is improved. | 2013-06-13 |
20130146978 | TRANSISTOR ASSISTED ESD DIODE - An integrated circuit includes a diode/bipolar ESD protection device. The diode/bipolar ESD device includes at least one gate separated ESD diode and at least one gate spaced ESD bipolar transistor coupled in parallel between a fixed voltage and an input/output pin. | 2013-06-13 |
20130146979 | Compensated Well ESD Diodes With Reduced Capacitance - An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode. | 2013-06-13 |
20130146980 | APPARATUSES AND METHODS FOR TRANSPOSING SELECT GATES - Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a group of memory cells and select gates electrically coupled to the group of memory cells. The select gates are arranged such that a pair of select gates are adjacent to each other along a first portion of each of the pair of select gates and are non-adjacent along a second portion of each of the pair of select gates. | 2013-06-13 |
20130146981 | ANTENNA CELL DESIGN TO PREVENT PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS - An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at V | 2013-06-13 |
20130146982 | SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS - A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer. | 2013-06-13 |
20130146983 | NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed herein is a nitride based semiconductor device, including: a substrate; a nitride based semiconductor layer having a lower nitride based semiconductor layer and an upper nitride based semiconductor layer on the substrate; an isolation area including an interface between the lower nitride based semiconductor layer and the upper nitride based semiconductor layer; and drain electrodes, source electrode, and gate electrodes formed on the upper nitride based semiconductor layer. | 2013-06-13 |
20130146984 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes isolation layers formed at isolation regions of a semiconductor substrate, silicon patterns formed over the semiconductor substrate between the isolation layers, insulating layers formed between the silicon patterns and the semiconductor substrate, and junctions formed in the semiconductor substrate between the silicon patterns, wherein each of the silicon patterns has a sloped top surface. | 2013-06-13 |
20130146985 | TRENCH ISOLATION STRUCTURE - A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material. | 2013-06-13 |
20130146986 | SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS - A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor. | 2013-06-13 |
20130146987 | Integrated Semiconductor Structure for SRAM and Fabrication Methods Thereof - A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures. | 2013-06-13 |
20130146988 | Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature - A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. | 2013-06-13 |
20130146989 | INTEGRATED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - An integrated device includes a field effect transistor formed within and upon an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. The resistor includes a resistor body being an enclosure portion of the first conductive layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body. A method for manufacturing a semiconductor device includes forming a gate stacked structure and a resistor stacked structure at the same time by patterning a dielectric layer, a first conductive layer and a second conductive layer. The method also includes forming a resistor having a resistor body by patterning the resistor stacked structure. | 2013-06-13 |
20130146990 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RELATED METHOD - Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film. | 2013-06-13 |
20130146991 | Device Including Two Power Semiconductor Chips and Manufacturing Thereof - A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip. | 2013-06-13 |
20130146992 | DEEP TRENCH EMBEDDED GATE TRANSISTOR - A semiconductor device includes a source extending into a surface of a substrate, a drain extending into the surface of the substrate, and an embedded gate in the substrate extending from the source to the drain. | 2013-06-13 |
20130146993 | SEMICONDUCTOR STRUCTURE HAVING A POLYSILICON STRUCTURE AND METHOD OF FORMING SAME - The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure. | 2013-06-13 |
20130146994 | METHOD FOR MANUFACTURING A HERMETICALLY SEALED STRUCTURE - A method for providing hermetic sealing within a silicon-insulator composite wafer for manufacturing a hermetically sealed structure, comprising the steps of: patterning a first silicon wafer to have one or more recesses that extend at least partially through the first silicon wafer; filling said recesses with an insulator material able to be anodically bonded to silicon to form a first composite wafer having a plurality of silicon-insulator interfaces and a first contacting surface consisting of insulator material; and using an anodic bonding technique on the first contacting surface and an opposing second contacting surface to create hermetic sealing between the silicon-insulator interfaces, wherein the second contacting surface consists of silicon. | 2013-06-13 |
20130146995 | THREE-DIMENSIONAL, ULTRASONIC TRANSDUCER ARRAYS, METHODS OF MAKING ULTRASONIC TRANSDUCER ARRAYS, AND DEVICES INCLUDING ULTRASONIC TRANSDUCER ARRAYS - Systems, apparatus, and associated methods of forming the systems and/or apparatus may include imaging devices that may comprise multiple arrays of ultrasonic transducer elements for use in a variety of applications. These multiple arrays of ultrasonic transducer elements can be arranged to form a three-dimensional imaging device. Non-coplanar arrays of ultrasonic transducer elements can be coupled together. These imaging devices may be used as medical imaging devices. Additional apparatus, systems, and methods are disclosed. | 2013-06-13 |
20130146996 | MAGNETIC DEVICE FABRICATION - The present disclosure provides for magnetic devices and methods of fabricating such a device. In one embodiment, a magnetic device includes a first elliptical pillar of first material layers; a second elliptical pillar concentrically disposed over the first elliptical pillar, the second elliptical pillar includes second material layers. The second elliptical pillar is smaller than the first elliptical pillar in size. | 2013-06-13 |
20130146997 | MAGNETIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a magnetic device includes forming a stack structure, the stack structure including a magnetic layer, and etching the stack structure by using an etching gas, the etching gas including at least 80% by volume of H | 2013-06-13 |
20130146998 | SINGLE-BAND AND DUAL-BAND INFRARED DETECTORS - Bias-switchable dual-band infrared detectors and methods of manufacturing such detectors are provided. The infrared detectors are based on a back-to-back heterojunction diode design, where the detector structure consists of, sequentially, a top contact layer, a unipolar hole barrier layer, an absorber layer, a unipolar electron barrier, a second absorber, a second unipolar hole barrier, and a bottom contact layer. In addition, by substantially reducing the width of one of the absorber layers, a single-band infrared detector can also be formed. | 2013-06-13 |
20130146999 | METHOD FOR FORMING A SELECTIVE CONTACT - A method for forming a selective contact for a photovoltaic cell is disclosed. The method includes forming a doped contact layer at the surface of a semiconductor substrate and annealing a portion of the doped contact layer with a laser beam, the portion having a 2D-pattern corresponding to at least a portion of a respective selective contact grid. Wherein the laser beam is pulsed and shaped to the 2D-pattern. A photovoltaic cell having a selective contact formed by the method is also provided. | 2013-06-13 |
20130147000 | WAFER SCALE IMAGE SENSOR PACKAGE AND OPTICAL MECHANISM INCLUDING THE SAME - There is provided an optical mechanism including a substrate, an image sensor chip, a light source, a blocking member and a securing member. The image sensor chip is attached to the substrate and has an active area. The light source is attached to the substrate. The blocking member covers the image sensor chip and has an opening to expose at least the active area of the image sensor chip. The securing member fits on the blocking member to secure the blocking member to the substrate. | 2013-06-13 |
20130147001 | WAFER SCALE IMAGE SENSOR PACKAGE AND OPTICAL MECHANISM - There is provided an optical mechanism including a substrate, an image chip, a light source and a securing member. The image chip and the light source are attached to the substrate. The securing member is secured to the substrate and includes a first containing space for accommodating the light source, a second containing space for accommodating the image chip and a blocking region between the first containing space and the second containing space. | 2013-06-13 |
20130147002 | RECEIVER MODULE AND DEVICE - Provided is a receiver module, including: a semiconductor light receiving element including an electrode; and a sub-mount including: an electrical wiring joined to the electrode with solder; and a trap region arranged around a joining surface of the electrical wiring, the trap region retaining solder by solder wetting. | 2013-06-13 |
20130147003 | PHOTOVOLTAIC DEVICE - A photovoltaic device includes a substrate, the substrate having a base region and an emitter region, the base region having a first width and the emitter region having a second width, a first electrode in contact with and electrically connected to the base region, the first electrode having a third width where it overlies the base region, the third width being greater than the first width such that the first electrode overhangs the base region at at least one side thereof, and a second electrode in contact with and electrically connected to the emitter region, the second electrode having a fourth width where it overlies the emitter region, a ratio of the third width to the fourth width being about 0.3 to about 3.4. | 2013-06-13 |
20130147004 | Integrated Capacitive Device Having a Thermally Variable Capacitive Value - An integrated circuit, comprising a capacitive device having a thermally variable capacitive value and comprising a thermally deformable assembly disposed within an enclosure, and comprising an electrically-conducting fixed body and a beam held at at least two different locations by at least two arms rigidly attached to edges of the enclosure, the beam and the arms being metal and disposed within the first metallization level. A part of the said thermally deformable assembly may form a first electrode of the capacitive device and a part of the said fixed body may form a second electrode of the capacitive device. The thermally deformable assembly has a plurality of configurations corresponding respectively to various temperatures of the said assembly and resulting in a plurality of distances separating the two electrodes and various capacitive values in the capacitive device corresponding to the plurality of distances. | 2013-06-13 |
20130147005 | ELECTROPLATING METHODS FOR FABRICATING INTEGRATED CIRCUIT DEVICES AND DEVICES FABRICATED THEREBY - Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein. | 2013-06-13 |
20130147006 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area. | 2013-06-13 |
20130147007 | DEEP ISOLATION TRENCH STRUCTURE AND DEEP TRENCH CAPACITOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions. | 2013-06-13 |
20130147008 | Metal E-Fuse With Intermetallic Compound Programming Mechanism and Methods of Making Same - Disclosed herein is a metal e-fuse device that employs an intermetallic compound programing mechanism and various methods of making such an e-fuse device. In one example, a device disclosed herein includes a first metal line, a second metal line and a fuse element that is positioned between and conductively coupled to each of the first and second metal lines, wherein the fuse element is adapted to be blown by passing a programming current therethrough, and wherein the fuse element is comprised of a material that is different from a material of construction of at least one of the first and second metal lines. | 2013-06-13 |
20130147009 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a fuse pattern formed at a first level, a first line pattern formed at a second level lower than the first level, a second line pattern formed at a third level higher than the first level, a first contact plug coupling the fuse pattern to the first line pattern | 2013-06-13 |
20130147010 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 2013-06-13 |
20130147011 | SEMICONDUCTOR DEVICE - A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section. | 2013-06-13 |
20130147012 | CIRCUIT BOARD COMPONENT SHIM STRUCTURE - Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation. | 2013-06-13 |
20130147013 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal. | 2013-06-13 |
20130147014 | Wafer Level Package Having Cylindrical Capacitor and Method Of Fabrication The Same - Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided. | 2013-06-13 |
20130147015 | DEEP TRENCH DECOUPLING CAPACITOR AND METHODS OF FORMING - Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a method of forming a semiconductor device includes: forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate; depositing a dielectric liner layer inside the trench; depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate; forming a silicide layer over a portion of the doped polysilicon layer; forming an intermediate contact layer within the inner trench; and forming a contact over a portion of the intermediate contact layer and a portion of the silicide layer. | 2013-06-13 |
20130147016 | Semiconductor Package Having Internal Shunt and Solder Stop Dimples - A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction. | 2013-06-13 |