23rd week of 2009 patent applcation highlights part 14 |
Patent application number | Title | Published |
20090140305 | IMAGING DEVICE - A solid-state imaging device, a line sensor and an optical sensor for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio are provided. The solid-state imaging device comprises an integrated array of a plurality of pixels, each of which comprises a photodiode PD for receiving light and generating photoelectric charges, a transfer transistor Tr | 2009-06-04 |
20090140306 | Semiconductor device and manufacturing method thereof - There is formed a gate electrode (word line) via a gate insulating film on a semiconductor substrate, the gate electrode extending in the direction inclining at an angle of approximately 45 degrees to the extending direction of an element region. The element region is divided into three portions by the two gate electrodes. In each element region portion, two MOS transistors are provided. A bit line is connected to a W plug provided in the central region portion and lower electrodes of two ferroelectric capacitors are connected to other W plugs provided in both end region portions. The extending direction of the bit line inclines approximately 45 degrees to the extending direction of the element region. | 2009-06-04 |
20090140307 | CONDUCTIVE LINE COMPRISING A CAPPING LAYER - An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound being different from the second compound. | 2009-06-04 |
20090140308 | Semiconductor device having capacitor formed on plug, and method of forming the same - A semiconductor device includes a silicon substrate, a capacitor element having a lower electrode, a capacitor dielectric film, a TiN film, and a W film, and an interlayer insulation film covering the end and a portion of the upper surface of the lower electrode and disposed with a concave portion at a position corresponding to the lower electrode. The lower electrode is disposed selectively at the bottom of the concave portion, the upper surface of the lower electrode is exposed from the interlayer insulation film in the region for forming the concave portion, the side wall for the concave portion of the interlayer insulation film situates to the inner side of the lower electrode from the end of the lower electrode, and the capacitor dielectric film is disposed so as to cover the upper surface of the lower electrode and cover the interlayer insulation from the side wall for the concave portion to the upper surface of the interlayer insulation film. | 2009-06-04 |
20090140309 | SEMICONDUCTOR DEVICE WITH LESS POWER SUPPLY NOISE - A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line. | 2009-06-04 |
20090140310 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the semiconductor device in which a micro controller unit (MCU) and a flash memory having the same structure as that of a logic circuit of the MCU are formed in the same chip. | 2009-06-04 |
20090140311 | Method of fabricating semiconductor device having storage capacitor and higher voltage resistance capacitor and semiconductor device fabricated using the same - Provided are a method of fabricating a semiconductor device having different kinds of capacitors, and a semiconductor device formed using the same. In a fabrication process, after preparing a substrate including a storage capacitor region and a higher voltage resistance capacitor region, a lower electrode layer may be formed on the storage capacitor region and the higher voltage resistance capacitor region. A first dielectric film may be formed on the lower electrode layer, and the first dielectric film of the storage capacitor region may be selectively removed to expose the lower electrode layer of the storage capacitor region. After forming a second dielectric film on the first dielectric film and the exposed lower electrode layer of the storage capacitor region, an upper electrode layer may be formed on the second dielectric film. | 2009-06-04 |
20090140312 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device include a semiconductor substrate, an insulating layer provided on the semiconductor substrate and having an opening, a semiconductor layer provided on the insulating layer, the semiconductor layer having a recess at a center of a surface thereof above the opening, a memory cell unit provided on the semiconductor layer and including a plurality of memory cells, current paths of the memory cells being connected in series, a selecting transistor adjacent to the memory cell unit and arranged on a region of the semiconductor layer including the recess, the selecting transistor including a gate insulating film provided on the region of the semiconductor layer including the recess and a gate electrode provided on the gate insulating film. | 2009-06-04 |
20090140313 | Nonvolatile memory devices and methods of forming the same - A method of forming nonvolatile memory devices according to example embodiments of the present invention includes forming a device isolation layer defining active regions in a semiconductor substrate; forming a plurality of transistors on the active regions, the plurality of transistors comprising a pair of adjacent string selection transistors, a pair of adjacent ground selection transistors, and a plurality of memory cell transistors connected in series between the string selection transistors and ground selection transistors; forming a common source line using SEG between a pair of adjacent ground selection transistors so that the common source line has a top surface lower than a top surface of the pair of adjacent ground selection transistors. | 2009-06-04 |
20090140314 | FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Embodiments relate to a flash memory device and a method of manufacturing the same that may include a tunnel oxide layer on and/or over a semiconductor substrate having source and drain regions. The tunnel oxide layer may have a first width The flash memory device may include a first polysilicon pattern and a second polysilicon pattern on and/or over the tunnel oxide layer and a dielectric pattern on and/or over the tunnel oxide layer, where the first and second polysilicon patterns may be provided. It may also include a third polysilicon pattern on and/or over the dielectric pattern, the third polysilicon pattern having a second width, and a spacer formed on and/or over sidewalls of the first, second and third polysilicon patterns, the dielectric pattern and the tunnel oxide pattern. According to embodiments, the second width may be greater than the first width. | 2009-06-04 |
20090140315 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprises: a plurality of transistors having a stacked-gate structure, each transistor including a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a silicide suppression region between the aperture and the gate insulator to suppress diffusion of metal atoms from the silicided upper gate. | 2009-06-04 |
20090140316 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes an insulating film formed on a semiconductor substrate, a plurality of active areas formed on the insulating film from a semiconductor layer which is formed integrally with the substrate through openings of the insulating film, the active areas being formed by being divided into a striped shape by a plurality of trenches reaching an upper surface of the insulating film, the active areas having upper surfaces and sides respectively, a first gate insulating film formed so as to cover the upper surfaces and sides of the active areas, a charge trap layer having a face located on the first gate insulating film and confronting the upper surfaces and the sides of the active areas with the first gate insulating film being interposed therebetween, a second gate insulating film formed on the charge trap layer, and a gate electrode formed on the second gate insulating film. | 2009-06-04 |
20090140317 | Multiple Layer floating gate non-volatile memory device - The disclosed systems and methods relate to floating gate non-volatile memory cells, with a floating gate comprising at least two layers constructed in different conductive or semiconductive materials. At least two of the layers of the floating gate are separated by an intermediate dielectric layer having a predetermined thickness enabling direct tunneling current between the layers | 2009-06-04 |
20090140318 | NONVOLATILE MEMORIES WITH HIGHER CONDUCTION-BAND EDGE ADJACENT TO CHARGE-TRAPPING DIELECTRIC - In a nonvolatile memory, the tunnel dielectric ( | 2009-06-04 |
20090140319 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory devices and a method of fabricating the same includes sequentially stacking a tunnel insulating layer, a first nano-grain film, a conductive layer for a floating gate, and a second nano-grain film over a semiconductor substrate, forming a trench by etching the second nano-grain film, the conductive layer for the floating gate, the first nano-grain film, the tunnel insulating layer, and the semiconductor substrate, gap-filling the trench with an insulating layer, thus forming an isolation layer, and forming a third nano-grain film on sidewalls of the conductive layer for the floating gate. | 2009-06-04 |
20090140320 | NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE NONVOLATILE MEMORY DEVICE INCLUDING GIVING AN UPPER PORTION OF AN INSULATING LAYER AN ETCHING SELECTIVITY WITH RESPECT TO A LOWER PORTION - A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure. | 2009-06-04 |
20090140321 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. First, a first oxide layer and a nitride layer are formed on a base having a first region and a second region. Next, the nitride layer is oxidized. A part of nitride in the nitride layer moves to the first oxide layer and the base. An upper portion of the nitride layer is converted to an upper oxide layer. Then, the upper oxide layer, the nitride layer and the first oxide layer in the second region are removed. Thereon, a second oxide layer is grown on the base in the second region. Nitride in the second region moves to the second oxide layer. | 2009-06-04 |
20090140322 | Semiconductor Memory Device and Method of Manufacturing the Same - A first insulation film (silicon dioxide film) and a second insulation film (aluminum oxide film) are laminated on a surface of a silicon substrate in this order to form a gate insulation film. At least one element (aluminum) of elements, which constitutes the second insulation film but is different from elements commonly contained in the whole area of the first insulation film, is caused to be contained in a part of the first insulation film, whereby a charge trapping site region is formed in the first insulation film. | 2009-06-04 |
20090140323 | Integrated Circuit having Memory Cell Array including Barriers, and Method of Manufacturing Same - An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells include a layout that provides a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions. A plurality of electrical contacts, wherein an electrical contact is disposed on a (i) common first region and/or second region and (ii) barrier(s) associated therewith which is disposed therein and/or therebetween. Also disclosed are inventive methods of manufacturing such integrated circuit devices. | 2009-06-04 |
20090140324 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device and a flash memory device in which a tunnel oxide layer and a first polysilicon pattern are formed on and/or over a semiconductor substrate. A second polysilicon pattern and a third polysilicon pattern are formed on and/or over a sidewall of the first polysilicon pattern and a dielectric layer and a polysilicon layer formed on and/or over the first, second and third polysilicon patterns. An etching process is performed to form a tunnel oxide layer pattern, a dielectric pattern, and a fourth polysilicon pattern. | 2009-06-04 |
20090140325 | FORMING METAL-SEMICONDUCTOR FILMS HAVING DIFFERENT THICKNESSES WITHIN DIFFERENT REGIONS OF AN ELECTRONIC DEVICE - A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and then reacting the metal-containing film with the semiconductor material to form a first metal-semiconductor film within the first region and a second metal-semiconductor film within the second region. The first metal-semiconductor film has a first thickness and the second metal-semiconductor film has a second thickness that is different from the first thickness. | 2009-06-04 |
20090140326 | SHORT GATE HIGH POWER MOSFET AND METHOD OF MANUFACTURE - A short gate high power metal oxide semiconductor field effect transistor formed in a trench includes a short gate having gate length defined by spacers within the trench. The transistor further includes a buried region that extends beneath the trench and beyond a corner of the trench, that effectively shields the gate from high drain voltage, to prevent short channel effects and resultantly improve device performance and reliability. | 2009-06-04 |
20090140327 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The vertical trench MOSFET comprises: an N type epitaxial region formed on an upper surface of an N | 2009-06-04 |
20090140328 | Bridged Gate FinFet - In a fin-type field effect transistor (FinFET) structure, a gate strap is positioned on the top of a gate conductor and runs along the gate conductor. The top of the gate strap is positioned a greater height above the top surface of the substrate than the top of the fin cap. The gate strap is conformal and, therefore, the top of the portion of the gate strap that crosses the fin cap has a greater height above the top surface of the substrate than top portions of other regions of the gate strap. Further, the material of the gate strap can have a different work function than a material of the gate conductor. | 2009-06-04 |
20090140329 | Semiconductor Device - A semiconductor device (such as a MOSFET) can prevent a lowering in the reliability of a gate insulating film and can cope with a finer trench pattern. The MOSFET has a plurality of trenches penetrating a p | 2009-06-04 |
20090140330 | Semiconductor device and method of manufacturing semiconductor device - The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity. | 2009-06-04 |
20090140331 | METHOD OF FABRICATING HIGH VOLTAGE DEVICE - A method of fabricating a high voltage device by which an area due to isolation between a source and a drain can be reduced by planarizing a gate in forming a symmetric high voltage device having vertical-type drift regions. Accordingly, the gate is formed in a trench at a height lower than an oxide spacer to reduce an area for isolation between source and drain. | 2009-06-04 |
20090140332 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same includes a groove formed in a semiconductor substrate, a gate electrode formed in the groove, source/drain regions disposed adjacent sidewalls of the gate electrode, and spacers interposed between the gate electrode and the source/drain regions such that the uppermost surface of the source/drain regions, the uppermost surface of the gate electrode and the uppermost surface of the spacers are formed on the same plane. | 2009-06-04 |
20090140333 | Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop - A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: | 2009-06-04 |
20090140334 | Transistor, display driver integrated circuit including a transistor, and a method of fabricating a transistor - A transistor, a display driver integrated circuit having the transistor, and a method for fabricating a transistor are provided. A transistor, according to example embodiments, may include a substrate with a device active region defined by an isolation layer, wherein the device active region may include a source active region, a channel active region, and a drain active region and the channel active region may include a pair of edges contacting the isolation layer. The transistor, according to example embodiments, may also include a gate electrode overlapping the channel active region, wherein the edges are exposed beyond a periphery of the gate electrode, a gate dielectric between the gate electrode and the channel active region, and source and drain impurity regions within the source and drain active regions. | 2009-06-04 |
20090140335 | Drain-Extended Field Effect Transistor - A drain-extended field effect transistor includes a drain contact region and a drain extension region. The drain-extended field effect transistor further includes an electrostatic discharge protection region that is electrically connected between the drain contact region and the drain extension region to protect the drain-extended field effect transistor against electrostatic discharge. The electrostatic discharge protection region has a dopant concentration level such that in case of an electrostatic discharge event, a base push-out is prevented from reaching the drain contact region. | 2009-06-04 |
20090140336 | SILVER NANOPARTICLE COMPOSITIONS - A silver nanoparticle composition is formed by the process comprising:
| 2009-06-04 |
20090140337 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device with increased freedom of wirings and a manufacturing method thereof are provided by enabling favorable connection between an upper wiring layer and a lower wiring layer through a semiconductor element. The semiconductor device includes: a first insulating layer over an insulating substrate; a first wiring layer and a second insulating layer on the first insulating layer; a single crystal semiconductor layer including a channel region and an impurity region, on the first wiring layer and the second insulating layer; a gate electrode over the channel region with a gate insulating layer interposed therebetween; a third insulating layer covering the first wiring layer, the single crystal semiconductor layer, and the gate electrode; and a second wiring layer over the third insulating layer. The first wiring layer is in contact with the impurity region, and the first and wiring layers are electrically connected to each other. | 2009-06-04 |
20090140338 | METHOD OF FABRICATING PATTERNED SOI DEVICES AND THE RESULTING DEVICE STRUCTURES - A method and resulting structure for fabricating a FET transistor for an integrated circuit on a silicon oxide (SOI) substrate comprising the steps of forming recesses in a substrate on both sides of a gate on the substrate, implanting oxygen ions into the recesses, and annealing the substrate to convert the oxygen ions into a SOI layer below each recess. | 2009-06-04 |
20090140339 | ESD Protection Device and Method for Manufacturing the Same - Disclosed is an electro-static discharge protection device. The electro-static discharge protection device can include a second conductive type epitaxial layer on a substrate; a second conductive type well on a first region above the second conductive type epitaxial layer; a first conductive type deep well in the second conductive type epitaxial layer between the second conductive type epitaxial layer and the second conductive type well; a plurality of active regions defined by a plurality of isolation layers above the second conductive type epitaxial layer; and a transistor and an ion implantation region in the active regions. | 2009-06-04 |
20090140340 | ESD protection device structure - An electrostatic discharge (ESD) protective device structure is disclosed. The ESD protection device includes: at least a first conductive type metal-oxide semiconductor (MOS), in which the drain and source of the first conductive type MOS are electrically connected to a first power terminal and a second power terminal separately; at least a second conductive type diffusion region; and at least a dummy gate disposed between the first conductive type MOS and the second conductive type diffusion region, wherein the gate length of the dummy gate is less than the gate length of the first conductive type MOS gate, such that the junction between the second conductive type diffusion region and the drain of the first conductive type MOS have a low breakdown voltage. | 2009-06-04 |
20090140341 | INDEPENDENT N-TIPS FOR MULTI-GATE TRANSISTORS - Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device. | 2009-06-04 |
20090140342 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME, A METHOD OF MANUFACTURING A VERTICAL MISFET AND A VERTICAL MISFET, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film. | 2009-06-04 |
20090140343 | LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH A TRENCH FIELD PLATE - A dielectric material layer is formed on a bottom surface and sidewalls of a trench in a semiconductor substrate. The silicon oxide layer forms a drift region dielectric on which a field plate is formed. Shallow trench isolation may be formed prior to formation of the drift region dielectric, or may be formed utilizing the same processing steps as the formation of the drift region dielectric. A gate dielectric layer is formed on exposed semiconductor surfaces and a gate conductor layer is formed on the gate dielectric layer and the drift region dielectric. The field plate may be electrically tied to the gate electrode, may be an independent electrode having an external bias, or may be a floating electrode. The field plate biases the drift region to enhance performance and extend allowable operating voltage of a lateral diffusion field effect transistor during operation. | 2009-06-04 |
20090140344 | SEMICONDUCTOR DEVICE - A semiconductor device including a SRAM cell may include a data holding unit including a driver transistor and a load transistor, and receiving and holding data; and a data transferring unit including a transfer gate transistor whose source and drain are connected between the data holding unit and one of a pair of bit lines, and whose gate is connected to a word line, the data transferring unit either transferring the data transferred from the one of the pair of bit lines to the data holding unit or receiving the data held in the data holding unit and transferring the data to the one of the pair of bit lines, wherein at least one of the driver transistor and the load transistor has higher capacitance between the gate and the source and between the gate and the drain than the transfer gate transistor. | 2009-06-04 |
20090140345 | SEMICONDUCTOR STRUCTURE INCLUDING SELF-ALIGNED DEPOSITED GATE DIELECTRIC - A semiconductor structure, such as a field effect device structure, and more particularly a CMOS structure, includes a gate dielectric that is at least in-part aligned to an active region of a semiconductor substrate over which is located the gate dielectric. The gate dielectric comprises other than a thermal processing product of the semiconductor substrate. In particular, the gate dielectric may be formed using an area selective deposition method such as but not limited to an area selective atomic layer deposition method. Within the context of a CMOS structure, the invention provides particular advantage insofar as the use of a self-aligned method for forming a gate dielectric aligned upon an active region of a semiconductor substrate may avoid a masking process that may otherwise be needed to strip portions of an area non-selective blanket gate dielectric. | 2009-06-04 |
20090140346 | MATCHED ANALOG CMOS TRANSISTORS WITH EXTENSION WELLS - One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed. | 2009-06-04 |
20090140347 | METHOD AND STRUCTURE FOR FORMING MULTIPLE SELF-ALIGNED GATE STACKS FOR LOGIC DEVICES - A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material. | 2009-06-04 |
20090140348 | METHOD AND A SEMICONDUCTOR DEVICE COMPRISING A PROTECTION LAYER FOR REDUCING STRESS RELAXATION IN A DUAL STRESS LINER APPROACH - By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches. | 2009-06-04 |
20090140349 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines. | 2009-06-04 |
20090140350 | LITHOGRAPHY FOR PRINTING CONSTANT LINE WIDTH FEATURES - An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width. | 2009-06-04 |
20090140351 | MOS Devices Having Elevated Source/Drain Regions - A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 Å. | 2009-06-04 |
20090140352 | METHOD OF FORMING INTERLAYER DIELECTRIC FOR SEMICONDUCTOR DEVICE - A method of forming an interlayer dielectric for a semiconductor device minimizing voids. During a process for forming a PMD oxide film being used as an interlayer dielectric, since TEOS impurities are added under a low-pressure controlled atmosphere, and gap filling characteristics are improved. Therefore, voids are minimized in the PMD oxide film. As a result, contact holes are prevented from shorting with each other through a void, and thus current leakage is suppressed. Further, it is not necessary to perform a rapid thermal anneal to improve the density of the PMD oxide film, nor to deposit a second PMD oxide film after planarization. As a result, the manufacturing process can be simplified. | 2009-06-04 |
20090140353 | Method of Film Deposition and Film Deposition System - The present invention is a method of film deposition that comprises a film-depositing step of supplying a high-melting-point organometallic material gas and a nitrogen-containing gas to a processing vessel that can be evacuated, so as to deposit a thin film of a metallic compound of a high-melting-point metal on a surface of an object to be processed placed in the processing vessel. A partial pressure of the nitrogen-containing gas during the film-depositing step is 17% or lower, in order to increase carbon density contained in the thin film. | 2009-06-04 |
20090140354 | Semiconductor Device and Method for Manufacturing the Same - Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a gate structure which includes a silicon oxynitride (SiON) layer formed on a semiconductor substrate, a hafnium silicon oxynitride (HfSiON) layer formed on the silicon oxynitride (SiON) layer, a polysilicon layer formed on the hafnium silicon oxynitride (HfSiON) layer, and a silicide layer formed on the polysilicon layer, spacers at sidewalls of the gate structure, and source and drain regions at opposite sides of the gate structure. | 2009-06-04 |
20090140355 | SEMICONDUCTOR PRESSURE SENSOR AND ITS FABRICATION METHOD - A semiconductor pressure sensor comprises a silicon support substrate ( | 2009-06-04 |
20090140356 | INTEGRATED SENSOR AND CIRCUITRY AND PROCESS THEREFOR - A micromachined sensor having a capacitive sensing structure. The sensor includes a first substrate with first and second conductive layers separated by a buried insulator layer, and a member defined by the first and second conductive layers and the buried insulator layer. A first set of elements defined with the first conductive layer is connected to the member and includes first and second elements that are electrically isolated from each other by the buried insulator layer. A second set of elements is defined with the first conductive layer and capacitively coupled with the first set of elements. A second substrate is bonded to the first substrate so that the member and the first set of elements are movably supported above the second substrate. The second set of elements is anchored to the second substrate, and the first and second sets of elements are physically interconnected through the second substrate. | 2009-06-04 |
20090140357 | High-temperature electrostatic transducers and fabrication method - A high temperature micromachined ultrasonic transducer (HTCMUT) is provided. The HTCMUT includes a silicon on insulator (SOI) substrate having a doped first silicon layer, a doped second silicon layer, and a first insulating layer disposed between the first and second silicon layers. A cavity is disposed in the first silicon layer, where a cross section of the cavity includes a horizontal cavity portion on top of vertical cavity portions disposed at each end of the horizontal cavity portion, and the vertical cavity portion spans from the first insulating layer through the first silicon layer, such that a portion of the first silicon layer is isolated by the first insulating layer and the cavity. A membrane layer is disposed on the first silicon layer top surface, and spans across the cavity. A bottom electrode is disposed on the bottom of the second silicon layer. | 2009-06-04 |
20090140358 | MAGNETORESISTIVE ELEMENT - A magnetoresistive element includes a first ferromagnetic layer having a first magnetization, the first magnetization having a first pattern when the magnetoresistive element is half-selected during a first data write, a second pattern when the magnetoresistive element is selected during a second data write, and a third pattern of residual magnetization, the first pattern being different from the second and third pattern, a second ferromagnetic layer having a second magnetization, and a nonmagnetic layer arranged between the first ferromagnetic layer and the second ferromagnetic layer and having a tunnel conductance changing dependent on a relative angle between the first magnetization and the second magnetization. | 2009-06-04 |
20090140359 | Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device - A semiconductor device ( | 2009-06-04 |
20090140360 | IMAGE SENSOR AND FABRICATING METHOD THEREOF - An image sensor and fabricating method thereof may include a semiconductor substrate, a plurality of photodiodes formed on and/or over the semiconductor substrate, a first insulating layer formed on and/or over the semiconductor substrate including the plurality of photodiodes, at least one metal line formed on and/or over the first insulating layer, a second insulating layer having a plurality of wells formed on and/or over the plurality of photodiodes, a plurality of color filters formed by embedding color filter layers in a plurality of the wells, and a plurality of microlenses formed on and/or over the color filters. | 2009-06-04 |
20090140361 | Image Sensor and Method of Manufacturing the Same - An image sensor and manufacturing method thereof are provided. The image sensor can includes a semiconductor substrate including a light receiving element, a metal interconnection layer having a trench, a guide pattern on a sidewall of the trench, and a color filter in the trench. Since the color filter can be formed in the trench, a length of a light path can be reduced, thereby improving the performance of the image sensor. | 2009-06-04 |
20090140362 | PHOTO DETECTOR - A photo detector comprising a grating (PC). The grating (PC) is arranged on top of a surface of an active semiconductor layer. The grating (PC) is patterned in uninterrupted first strips (ST | 2009-06-04 |
20090140363 | Optical semiconductor device having photosensitive diodes and process for fabricating such a device - An optical semiconductor device includes, in a zone ( | 2009-06-04 |
20090140364 | PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention connects a first wiring portion located at one side of a substrate and a second wiring portion located at the other side. A side electrode connected to the first wiring portion is formed, and the second wiring portion is formed on an insulating layer formed on the substrate. An exposed end of the second wiring portion formed when singulated into individual semiconductor package and the side electrode are wired by ink jet system using nano metal particles. Particularly, when copper is used, the wiring by the ink jet system is performed by the reduction of a metal surface oxidation film and/or removal of organic matters by atomic hydrogen. | 2009-06-04 |
20090140365 | Image sensor with back-side illuminated photoelectric converters - An image sensor includes a circuit substrate, a plurality of isolation regions, a plurality of photoelectric converters, and an insulation layer. The isolation regions are formed in a pixel region having the photoelectric converters formed therein with each photoelectric converter being electrically isolated by the isolation regions. The insulation layer is formed in a pad region with a substantially same depth as the isolation regions. The isolation region and the insulation layer are simultaneously formed for efficient fabrication of the image sensor. | 2009-06-04 |
20090140366 | Photodiode with Controlled Current Leakage - The present invention is directed towards radiation detectors and methods of detecting incident radiation. In particular the present invention is directed towards photodiodes with controlled current leakage detector structures and a method of manufacturing photodiodes with controlled current leakage detector structures. The photodiodes of the present invention are advantageous in that they have special structures to substantially reduce detection of stray light. Additionally, the present invention gives special emphasis to the design, fabrication, and use of photodiodes with controlled leakage current. | 2009-06-04 |
20090140367 | OPTICAL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optical semiconductor device is provided with a low concentration p-type silicon substrate ( | 2009-06-04 |
20090140368 | Method of producing photodiode and the photodiode - A photodiode includes a photosensitive element formed in a silicon semiconductor layer on an insulation layer. The photosensitive element includes a low concentration diffusion layer, a P-type high concentration diffusion layer, and an N-type high concentration diffusion layer. A method of producing the photodiode includes the steps of: forming an insulation material layer on the silicon semiconductor layer after the P-type impurity and the N-type impurity are implanted into the low concentration diffusion layer, the P-type high concentration diffusion layer, and the N-type high concentration diffusion layer; forming an opening portion in the insulation material layer in an area for forming the low concentration diffusion layer; and etching the silicon semiconductor layer in the area for forming the low concentration diffusion layer so that a thickness of the silicon semiconductor layer is reduced to a specific level. | 2009-06-04 |
20090140369 | SEMICONDUCTOR POWER MODULE PACKAGE WITHOUT TEMPERATURE SENSOR MOUNTED THEREON AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor power module package and a method of fabricating the same. The semiconductor power module package includes a substrate, semiconductor chips arranged on a top surface of the substrate, and a temperature sensor mounted on a top surface of at least one of the semiconductor chips. The semiconductor chips and the temperature sensor are electrically connected to each other through leads. A sealing material covers the top surface of the substrate, the semiconductor chips, and the temperature sensor except for portions of the leads and a bottom surface of the substrate. The temperature sensor may include a thermistor, and the thermistor may include first and second electrode terminals connected to corresponding leads of the leads. A first wiring pattern may be in contact with the first electrode terminal, and a second wiring pattern may be in contact with the second electrode terminal. | 2009-06-04 |
20090140370 | SEMICONDUCTOR DEVICE - A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device. | 2009-06-04 |
20090140371 | Semiconductor integrated device and manufacturing method for the same - A first exemplary aspect of an exemplary embodiment of the present invention is a semiconductor integrated device comprising a semiconductor substrate, a first impurity layer of a first conductivity type formed in the semiconductor substrate, a second impurity layer of a second conductivity type formed on the first impurity layer, a first well of the first conductivity type formed on the second impurity layer and supplied with potential from the first impurity layer via an impurity region of the first conductivity type selectively formed in a part of the second impurity layer, and a second well of the second conductivity type formed on the second impurity layer and supplied with potential from the second impurity layer, wherein the impurity concentrations of the first impurity layer and the impurity region are higher than that of the first well, and the impurity concentration of the second impurity layer is higher than that of the second well. | 2009-06-04 |
20090140372 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The at least one first region includes at least one first device oriented in a first direction. The at least one second region includes at least one second device oriented in a second direction. The second direction is different than the first direction. | 2009-06-04 |
20090140373 | Method of Manufacturing LCD Driver IC - Disclosed is a method of manufacturing an LCD driver IC. The method includes forming a plurality of gate patterns on a semiconductor substrate by sequentially forming a plurality of gate insulating films and gate electrodes; sequentially depositing a plurality of spacer material layers covering the gate electrodes; forming spacers on the side walls of the gate electrodes by performing an etchback process on the plurality of spacer material layers such that the lowermost spacer material layer remains on the semiconductor substrate; and controlling the thickness of the lowermost spacer material layer (or removing the lowermost spacer material layer) by etching the lowermost spacer material layer. | 2009-06-04 |
20090140374 | SEMICONDUCTOR DEVICE WITH IMPROVED CONTROL ABILITY OF A GATE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a semiconductor device capable of improving a control ability of a gate and enhancing operation characteristics of the gate. The semiconductor device comprises a semiconductor substrate having a recessed active region. An isolation structure is formed to define the recessed active region in the semiconductor substrate and the isolation structure includes a trench, a side wall insulation layer formed over the surface of the trench, and an insulation layer formed over the side wall insulation layer to fill the trench. A portion of the side wall insulation layer adjoining a gate forming area of the recessed active region is removed to form a moat, and a gate is formed over the semiconductor substrate including the moat. | 2009-06-04 |
20090140375 | METHOD OF FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE - A semiconductor device can include a semiconductor substrate, a first trench formed in the semiconductor substrate, a second trench formed in the semiconductor substrate, a first device isolation layer formed in the first trench, a second device isolation layer formed in the second trench having a different structure than the first device isolation layer. | 2009-06-04 |
20090140376 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - A method for forming a device isolation layer in a semiconductor substrate by destroying a lattice structure of the semiconductor substrate through a high-energy ion implantation process. | 2009-06-04 |
20090140377 | DIELECTRIC ISOLATION TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over another. The semiconductor substrate includes a first semiconductor region of a first conductive type having a high impurity concentration, a second semiconductor region of a second conductive type having a high impurity concentration arranged so as to surround the first semiconductor region, a first main electrode joined to a surface of the first semiconductor region, and a second main electrode joined to a surface of the second semiconductor region. A first dielectric portion is arranged adjacent the embedded dielectric layer so as to surround a region of the support substrate superposed on the first semiconductor region in a direction of lamination thereof, and a wire connected with the first main electrode. | 2009-06-04 |
20090140378 | FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a flash memory device, trenches are formed in an isolation area of a semiconductor substrate. A first insulating layer is formed on sidewalls and bottoms of the trenches. Conductive layer patterns are formed on the first insulating layers at the bottoms of the trenches. A second insulating layer is formed on the conductive layer patterns. Gate lines are formed over a semiconductor substrate including the second insulating layer. The gate lines intersect the conductive layer patterns. Junctions are formed on the semiconductor substrate between the gate lines. An interlayer insulating layer is formed over the semiconductor substrate including the gate lines. Contact holes are formed through which the conductive layer patterns and the junctions located on one side of the conductive layer patterns are exposed. The contact holes are gap-filled with a conductive material, thereby forming contact plugs. | 2009-06-04 |
20090140379 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a device isolation region formed on a part of shallow trench isolation (STI) sidewalls to relieve stress applied to an active region, thereby improving current flowing toward a channel region. | 2009-06-04 |
20090140380 | DEVICE WITH GAPS FOR CAPACITANCE REDUCTION - A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps. | 2009-06-04 |
20090140381 | Semiconductor Device and Method for Forming Passive Circuit Elements with Through Silicon Vias to Backside Interconnect Structures - A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate. | 2009-06-04 |
20090140382 | ELECTRIC FUSE DEVICE MADE OF POLYSILICON SILICIDE - A polysilicon silicide electric fuse device, comprising: a substrate; a semiconductor material layer disposed on said substrate, said semiconductor material layer includes lead-out areas of the same doping type at both ends, and an intermediate area of non-doping or having dopant concentration lower than those of said lead-out areas at both ends; and one or more burn-out areas is/are provided in said intermediate area; and a metal silicide layer is provided on said semiconductor material layer. Through the application of said polysilicon silicide electric fuse device, the burning out of said fuse device is thus controlled to within said intermediate area of no doping or light doping, hereby increasing the mean value and reducing distribution area of electrical resistance after burning out of a fuse, and alleviating the overheating of surrounding areas as caused by a current during the burning out of a fuse. | 2009-06-04 |
20090140383 | METHOD OF CREATING SPIRAL INDUCTOR HAVING HIGH Q VALUE - A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided over which a spirally patterned conductor layer is formed to produce a planar spiral inductor. A via hole is formed in the substrate within the spirally patterned conductor layer, the via hole being formed by through silicon via (TSV). Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface thereof. | 2009-06-04 |
20090140384 | PROCESS FOR OBTAINING A THIN, INSULATING, SOFT MAGNETIC FILM OF HIGH MAGNETIZATION, CORRESPONDING FILM AND CORRESPONDING INTEGRATED CIRCUIT - A thin soft magnetic film combines a high magnetization with an insulating character. The film is formed by nitriding Fe-rich ferromagnetic nanograins immersed in an amorphous substrate. A selective oxidation of the amorphous substrate is then performed. The result is a thin, insulating, soft magnetic film of high magnetization. Many types of integrated circuits can be made which include a component using a membrane incorporating the above-mentioned thin film. | 2009-06-04 |
20090140385 | Capacitor with nanotubes and method for fabricating the same - A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer. | 2009-06-04 |
20090140386 | SEMICONDUCTOR DEVICE HAVING CAPACITOR ELEMENT - Provided is a semiconductor device which includes a capacitor element having a flat-plate-type lower electrode provided over a semiconductor substrate, a flat-plate-type TiN film provided over the lower electrode in parallel therewith, and a capacitor film provided between the lower electrode and the TiN film; and a first Cu plug brought into contact with the bottom surface of the lower electrode, and is composed of a metal material, wherein the capacitor film has a film which contains an organic molecule as a constituent. | 2009-06-04 |
20090140387 | HIGH-DENSITY 3-DIMENSIONAL RESISTORS - Interconnect, i.e., BEOL structures comprising at least one thin film resistor that is located at the same level as that of a neighboring conductive interconnect are provided. The present invention also provides a method of fabricating such interconnect structures utilizing processing steps that are compatible with current interconnect processing. Moreover, the inventive method of the present invention provides better technology extendibility in terms of higher density than prior art schemes. | 2009-06-04 |
20090140388 | INTEGRATED CIRCUIT INCLUDING AN EMITTER STRUCTURE AND METHOD FOR PRODUCING THE SAME - A semiconductor emitter structure for emitting charge carriers of a first conductivity type in a base volume of a second conductivity type material neighbored to the emitter structure in a vertical direction, includes multiple emitter volumes of first conductivity tape material having a predetermined lateral dimension in a lateral direction perpendicular to the vertical direction. The emitter volumes are, in the lateral direction, neighbored by semiconductor volumes of second conductivity type material, wherein the predetermined lateral dimension is such that space charges created by second conductivity type carriers laterally diffusing into the emitter volumes from the semiconductor volumes limit a maximum density of first conductivity type carriers within the emitter volumes by more than 20% as compared to emitter volumes of the same lateral dimension not neighbored by semiconductor volumes of the second conductivity type material. | 2009-06-04 |
20090140389 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing oxidation of the Ta film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film as an antioxidant film is formed on the entire upper surface of the Ta film which forms the p electrode, to prevent oxidation of the Ta film. This inhibits the resistance between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the low-resistance p electrode. | 2009-06-04 |
20090140390 | GaAs SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND GROUP III-V COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A GaAs semiconductor substrate includes a main surface ( | 2009-06-04 |
20090140391 | Seal Ring in Semiconductor Device - A semiconductor device includes a first circuit, a first seal ring and at least one first notch. The first seal ring surrounds the first circuit. The first notch cuts the first seal ring. Specifically, the first notch includes an inner opening, an outer opening and a connecting groove. The inner opening is located on the inner side of the first seal ring. The outer opening is located on the outer side of the first seal ring. The outer opening and the inner opening are not aligned. The connecting groove connects the inner opening and the outer opening. | 2009-06-04 |
20090140392 | WARPAGE RESISTANT SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during gringing. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface. The substrate has a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes. | 2009-06-04 |
20090140393 | WAFER SCRIBE LINE STRUCTURE FOR IMPROVING IC RELIABILITY - A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation. | 2009-06-04 |
20090140394 | Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die - A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die. | 2009-06-04 |
20090140395 | EDGE SEAL FOR THRU-SILICON-VIA TECHNOLOGY - One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel. | 2009-06-04 |
20090140396 | STRESSED INTERLAYER DIELECTRIC WITH REDUCED PROBABILITY FOR VOID GENERATION IN A SEMICONDUCTOR DEVICE BY USING AN INTERMEDIATE ETCH CONTROL LAYER OF INCREASED THICKNESS - By forming an etch control material with increased thickness on a first stressed dielectric layer in a dual stress liner approach, the surface topography may be smoothed prior to the deposition of the second stressed dielectric material, thereby allowing the deposition of an increased amount of stressed material while not contributing to yield loss caused by deposition-related defects. | 2009-06-04 |
20090140397 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes capacitors formed on the surface of an interlayer insulating film in connection with capacitive contact plug, wherein capacitors are constituted of base-side lower electrode films having hollow-pillar shapes, metal plugs embedded in hollows of base-side lower electrode films, and top-side lower electrode films having hollow-pillar shapes engaged with the upper portions of the hollows as well as dielectric films and upper electrode films which are sequentially laminated so as to cover the peripheral surfaces of the base-side and top-side lower electrode films and the interior surfaces of the top-side lower electrode films. Side walls are further formed to connect together the adjacent base-side lower electrode films. Thus, it is possible to control the aspect ratio of a capacitor hole for embedding the metal plug from being excessively increased, and it is possible to increase the capacitive electrode area of each capacitor. | 2009-06-04 |
20090140398 | HARD MASK PATTERNS OF A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING THE SAME - In a method for forming hard mask patterns of a semiconductor device first hard mask patterns are formed on a semiconductor substrate. Second hard mask patterns are formed and include first patterns which are substantially perpendicular to the first hard mask patterns and second patterns which are positioned between the first hard mask patterns. Third hard mask patterns are formed between the first patterns. | 2009-06-04 |
20090140399 | Semiconductor Module with Switching Components and Driver Electronics - A semiconductor module comprises at least one semiconductor chip having at least one semiconductor switch. The at least one semiconductor chip is arranged on a carrier substrate. At least one driver component drives the at least one semiconductor switch. The at least one driver component is arranged on a circuit board. The at least one driver component has at least one input for receiving a control signal. The circuit board has a galvanic isolation in a signal path between the at least one driver component and the at least one semiconductor chip. | 2009-06-04 |
20090140400 | Method of Mid-Frequency Decoupling - A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance. | 2009-06-04 |
20090140401 | System and Method for Improving Reliability of Integrated Circuit Packages - An integrated circuit package includes a die, a bump, an underbump metallization layer formed between the bump and the die, a portion of the underbump metallization layer under the bump having a first radius, and a redistribution layer formed between the underbump metallization layer and the die. The redistribution layer has a pad positioned under the underbump metallization layer. The pad has a second radius, and makes contact with the underbump metallization layer. The second radius is less than or equal to the first radius. The integrated circuit package also includes a first dielectric layer disposed between the die and the redistributing layer. | 2009-06-04 |
20090140402 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method includes: mounting a plurality of semiconductor elements on a substrate having wirings; connecting electrically electrodes of the semiconductor elements and the wirings; sealing the semiconductor elements with a resin, which is carried out by bringing a thermal conductor having a concavity and the substrate to be in contact with each other so that the semiconductor elements are positioned within the concavity and by filling the concavity with the resin; and separating respective semiconductor elements | 2009-06-04 |
20090140403 | ELECTRONIC DEVICE - Embodiments provide an electronic device including a leadframe, a chip attached to the leadframe, and encapsulation material disposed over a portion of the leadframe. The leadframe includes a first main face opposite a second main face and a plurality of edges extending between the first and second main faces. At least one of the plurality of edges includes a first profiled element and a second profiled element different than the first profiled element. The encapsulation material is disposed over the chip and the plurality of edges of the leadframe. | 2009-06-04 |
20090140404 | HERMETIC SEAL AND RELIABLE BONDING STRUCTURES FOR 3D APPLICATIONS - A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure. | 2009-06-04 |