22nd week of 2012 patent applcation highlights part 39 |
Patent application number | Title | Published |
20120135520 | UNSHRUNKEN TISSUE EQUIVALENT, SKIN EQUIVALENT COMPRISING SUCH AN UNSHRUNKEN TISSUE EQUIVALENT, AND METHODS FOR PRODUCING SUCH AN UNSHRUNKEN TISSUE EQUIVALENT AND SUCH A SKIN EQUIVALENT - The invention relates to a method for producing an unshrunken tissue equivalent. Said method is comprising in that: a mixture is produced that contains at least one element of an extracellular matrix; at least one pluridimensional medium is soaked with said mixture; from the components of the mixture, a lattice comprising at least one element of an extracellular matrix is produced, at least at the medium; at least part of the components of said mixture is attached to the structure of the medium; the shrinking of at least the lattice is prevented and at least said lattice is tensioned on said medium; fibroblasts are integrated into the lattice and at least one cell culture of said fibroblasts is carried out, at least in the lattice. The invention also relates to a method for producing a skin equivalent that comprises at least one dermal equivalent formed by an unshrunken tissue equivalent and at least one epidermal equivalent. | 2012-05-31 |
20120135521 | ANTIGENE LOCKS AND THERAPEUTIC USES THEREOF - An oligonucleotide based therapeutic strategy, called anti-gene locks, is described which specifically kills cells based on their genotype. The strategy employs oligonucleotides with arms and a backbone that are complementary to both strands of the gene target. Anti-gene locks bind in vitro in a sequence dependent fashion and inhibit DNA synthesis. In bacterial cells containing an episome target, they cause elimination of the extra-chromosomal DNA structure. When the target is present in the bacterial or human genome, they selectively kill the majority of these cells. | 2012-05-31 |
20120135522 | METHODS OF MODULATING CELL REGULATION BY INHIBITING P53 - Disclosed herein are methods of inhibiting the function of p53 in a cell by contacting the cell with an effective amount of a PP2A inhibitor. Also disclosed herein are processes for producing an induced pluripotent stem (iPS) cell by contacting a somatic cell expressing at least one gene that encodes a reprogramming factor with an amount of a PP2A inhibitor effective to produce the iPS cell; reversibly inhibiting p53 function during production of an iPS cell by contacting a somatic cell with an amount of a PP2A inhibitor effective to reversibly inhibit p53 function; increasing the likelihood of producing an (iPS) cell. | 2012-05-31 |
20120135523 | PREPARATION AND USES OF POLYARYLATES - The present invention is directed to polyarylates comprising repeating units having the structure: | 2012-05-31 |
20120135524 | Novel Nucleic Acid Constructs Containing Orthogonal Site Selective Recombinases (OSSRs) - The present invention provides for a recombinant nucleic acid comprising a nucleotide sequence comprising a plurality of constructs, wherein each construct independently comprises a nucleotide sequence of interest flanked by a pair of recombinase recognition sequences. Each pair of recombinase recognition sequences is recognized by a distinct recombinase. Optionally, each construct can, independently, further comprise one or more genes encoding a recombinase capable of recognizing the pair of recombinase recognition sequences of the construct. The recombinase can be an orthogonal (non-cross reacting), site-selective recombinase (OSSR). | 2012-05-31 |
20120135525 | REPROGRAMMING T CELLS AND HEMATOPOIETIC CELLS - Methods and compositions relating to the production of induced pluripotent stem cells (iPS cells) are disclosed. For example, induced pluripotent stem cells may be generated from CD34 | 2012-05-31 |
20120135526 | LOW-PRESSURE BIOLISTIC BARRELS - Low pressure biolistic barrels and biolistic devices including the same are provided. Aspects of the biolistic barrels include the presence of one or more pressure-reducing elements. Also provided are kits which include the biolistic barrels, as well as methods of delivering a molecule to a target site with the biolistic barrels and devices that include the same. The devices and methods described herein find use in a variety of applications, including in vivo and in vitro high-precision delivery applications. | 2012-05-31 |
20120135527 | Material, system, and method that provide indication of a breach - A multilayer material is described herein that includes a flexible inner layer and a flexible outer layer configured to enclose at least one signaling layer, the at least one signaling layer including at least one chemical compound. The multilayer material including the chemical compound within the at least one signaling layer is configured to release a gas-phase chemical compound to signal to a detector indicating a breach of the multilayer material. A multilayer material, a system, an article of clothing, or a method is described herein. | 2012-05-31 |
20120135528 | PAINT FOR DETECTION OF RADIOLOGICAL OR CHEMICAL AGENTS - A paint that warns of radiological or chemical substances comprising a paint operatively connected to the surface, an indicator material carried by the paint that provides an indication of the radiological or chemical substances, and a thermo-activation material carried by the paint. In one embodiment, a method of warning of radiological or chemical substances comprising the steps of painting a surface with an indicator material, and monitoring the surface for indications of the radiological or chemical substances. In another embodiment, a paint is operatively connected to a vehicle and an indicator material is carried by the paint that provides an indication of the radiological or chemical substances. | 2012-05-31 |
20120135529 | Detection of Occult Blood in Feces or Urine - The present invention relates to an improved method, reagents and kit for the detection of fecal or urine occult blood. The reagents are either supplied as solutions in small vials or incorporated into a matrix that is treated, impregnated, or imprinted with the test reagents that are capable of undergoing a chromagenic reaction. The method elucidates false positives from dietary sources, oxidants in the toilet water supply and is specific for blood. A stabilized chromogenic solution is disclosed which contains phemolphthalin in a deoxygenated, basic solution. The chromagenic solution either in a liquid or matrix form is placed into the toilet water following urination or defecation. A few moments are allowed to occur for observation of the matrix turning from colorless to a hot-pink. A hot pink color is indicative of a false positive. If no color change occurs, an oxidizing solution is added to the toilet water. If a change from colorless to a hot-pink occurs in less than thirty seconds then this test is positive and specific for occult blood in this fecal and/or urine specimen. Typically, the oxidizing solution is hydrogen peroxide. Hemoglobin or a porphyrin solution can be added to a separate matrix or | 2012-05-31 |
20120135530 | Detection of target analytes using particles and electrodes - The invention relates to the use of particles comprising binding ligands and electron transfer moieties (ETMs). Upon binding of a target analyte, a particle and a reporter composition are associated and transported to an electrode surface. The ETMs are then detected, allowing the presence or absence of the target analyte to be determined. | 2012-05-31 |
20120135531 | SENSORS FOR DETECTING SUBSTANCES INDICATIVE OF STROKE, ISCHEMIA, INFECTION OR INFLAMMATION - A system is disclosed that extracts bodily fluid to a reaction chamber for monitoring a substance or property of the patient fluid. In one embodiment, a pump is used to advance the sample of bodily fluid through a filter to produce a filtrate. Another pump advances filtrate into the reaction chamber, while another pump advances reactant into the reaction chamber. A sensor in communication with the reaction chamber determines a concentration of nitric oxide or one of its metabolic products. Methods are also disclosed. | 2012-05-31 |
20120135532 | Sensor Comprising Resrufin Levulinate Having Sulfite Ion Selectivity and Method for Monitoring Sulfite Ion Using the Same - The present invention relates to a sensor comprising a resorufin compound having sulfite ion selectivity and a method for detecting sulfite ions using the same. More specifically, the resorufin compound may have outstandingly increased fluorescence intensity by a deprotection reaction that a levulinyl group is cleaved with a sulfite ion to be used as a selective fluorescence sensor of turn-on type, and also represent a chromogenic change to detect sulfite ions by naked eye. | 2012-05-31 |
20120135533 | Chemical Analytic Apparatus and Chemical Analytic Method - A chemical analytic apparatus of the present invention is the one which proposes that a miniaturization, a making low-cost and portability are possible and also the operation of each process of separation, concentration and dilution of specimen is possible, and, which includes: an introduction means (S | 2012-05-31 |
20120135534 | ADSORPTION TEST METHOD OF SPHERICAL CARBON ADSORBENT - The present invention relates to an adsorption test method of a spherical carbon adsorbent, particularly Kremezin, which includes evaluating a test solution containing one or more kinds of particular uremic toxins or related compounds for the adsorbability, namely, adsorption titer, adsorption speed and/or adsorption selectivity, of the spherical carbon adsorbent. | 2012-05-31 |
20120135535 | AUTOMATED REAL-TIME PARTICLE CHARACTERIZATION AND THREE-DIMENSIONAL VELOCIMETRY WITH HOLOGRAPHIC VIDEO MICROSCOPY - An in-line holographic microscope can be used to analyze on a frame-by-frame basis a video stream to track individual colloidal particles' three-dimensional motions. The system and method can provide real time nanometer resolution, and simultaneously measure particle sizes and refractive indexes. Through a combination of applying a combination of Lorenz-Mie analysis with selected hardware and software methods, this analysis can be carried out in near real time. An efficient particle identification methodology automates initial position estimation with sufficient accuracy to enable unattended holographic tracking and characterization. | 2012-05-31 |
20120135536 | Method and Apparatus for Detecting and Quantifying a Chemical Substance Employing an Optical Transmission Property of Metallic Islands on a Transparent Substrate - A sensor for use in detecting and analyzing predetermined chemical substances is presented. The sensor comprises: a first structure configured for binding to a certain substance and comprising a substantially transparent substrate with respect to electromagnetic radiation of a predetermined wavelength range and a plurality of metallic islands deposited onto the transparent substrate and having a first spectral transmission profile with respect to the electromagnetic radiation of the predetermined wavelength range; the metallic islands comprising metallic films having a thickness selected such that binding of said certain substance to the first structure provides a change in a localized surface plasmon extinction in the metallic films being in a predetermined correlation with a change in a spectral transmission profile of the electromagnetic radiation of the predetermined wavelength range transmitted through the first structure and the substance as compared to said first spectral transmission profile, thereby enabling detection of said substance. | 2012-05-31 |
20120135537 | DETECTION OF A COMPONENT OF INTEREST WITH AN ULTRAVIOLET LASER AND METHOD OF USING THE SAME - Means and method for analysis of a component of interest in a sample is provided. A small sample cell is provided which decreased dispersion of the sample. Also provided is a device for detection of a component of interest in a sample in which the small sample cell is used with an ultra violet laser in which the energy of the laser is spread over an area such that energy density is above desorption threshold, but the sample not ablated. Rapid and reliable detection of a component of interest is provided with the invention. | 2012-05-31 |
20120135538 | AGENT AND METHOD FOR IDENTIFYING LYSINE CROTONYLATION IN PROTEINS - A method and related agent for detecting novel post-translational modification. This novel post-translational modification is in the form of crotonylation of lysine residues in proteins. The method includes the steps of (a) preparing a mixture of polypeptides from a protein sample; (b) separating the polypeptides by molecular weight; (c) contacting the separated polypeptides with a binding affinity reagent which binds specifically to a polypeptide containing a crotonyllysine residue; and (d) detecting presence of a binding complex between the affinity reagent and one or more of the polypeptides. An example of the binding agent is an antibody, which may be prepared from animal serums, or is a monoclonal antibody or single-chain variable fragment. | 2012-05-31 |
20120135539 | Split DNA Enzyme for Visual Single Nucleotide Polymorphism Typing - A probe that changes solution color in the presence of only one of the two DNA sequences, which differ by a single nucleotide, is reported. The probe consists of two oligodeoxyribonucleotides, which form a hydrogen peroxidase-like DNA enzyme when hybridized to the abutting fragments of the complementary analyte. The active peroxidase catalyses oxidation of colorless substrates to the colored products. The probe allows visual detection of a mutation in Alzheimer's disease-related DNA. | 2012-05-31 |
20120135540 | Methods and compositions of nucleic acid ligands for detection of clinical analytes related to human health - Specific DNA sequences for binding various clinically relevant analytes from the human body are described. Each of these sequences or their linear, two- and three-dimensional linked sequences can function in varying assay and sensor formats with varying degrees of success. Linkage of the whole or partial DNA sequences (putative binding sites) can be used to enhance specificity and affinity towards complex targets, thereby improving assay selectivity and sensitivity in many instances. In addition, a FRET-based quantitative method is described for normalizing analyte data by assessing urine creatinine and urea levels. Finally, a method is described for removing creatinine or urea by size-exclusion chromatography prior to a FRET-based aptamer assay to avoid the denaturing effects of these compounds. | 2012-05-31 |
20120135541 | MULTI-DIRECTIONAL MICROFLUIDIC DEVICES COMPRISING A PAN-CAPTURE BINDING REGION AND METHODS OF USING THE SAME - Microfluidic devices and methods for using the same are provided. Aspects of the invention include microfluidic devices that include a separation medium and a pan-capture binding medium. The microfluidic devices are configured to subject a sample to two or more directionally distinct electric fields. Also provided are methods of using the devices as well as systems and kits that include the devices. The devices, systems and methods find use in a variety of different applications, including diagnostic and validation assays. | 2012-05-31 |
20120135542 | METHODS AND MATERIALS FOR DIAGNOSING LIGHT CHAIN AMYLOIDOSIS - This document relates to methods and materials involved in diagnosing light chain amyloidosis. For example, methods and materials for using exosomes to diagnose a mammal (e.g., a human) as having immunoglobulin light chain amyloidosis are provided. | 2012-05-31 |
20120135543 | Method For Forming Magnetic Tunnel Junction Structure And Method For Forming Magnetic Random Access Memory Using The Same - A method of fabricating a magnetic tunnel junction structure includes forming a magnetic tunnel junction layer on a substrate. A mask pattern is formed on a region of the second magnetic layer. A magnetic tunnel junction layer pattern and a sidewall dielectric layer pattern on at least one sidewall of the magnetic tunnel junction layer pattern are formed by performing at least one etch process and at least one oxidation process multiple times. The at least one etch process may include a first etch process to etch a portion of the magnetic tunnel junction layer using an inert gas and the mask pattern to form a first etch product. The at least one oxidation process may include a first oxidation process to oxidize the first etch product attached on an etched side of the magnetic tunnel junction layer. | 2012-05-31 |
20120135544 | Method of Fabricating Semiconductor Device and Apparatus for Fabricating the Same - Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes forming a plurality of magnetic memory patterns spaced apart from each other on a substrate, with each of the magnetic memory patterns including a free pattern, a tunnel barrier pattern, and a reference pattern which are stacked on the substrate, performing a magnetic thermal treatment process on the magnetic memory patterns, and forming a passivation layer on the magnetic memory patterns. The magnetic thermal treatment process and the forming of the passivation layer are simultaneously performed in one reactor. | 2012-05-31 |
20120135545 | LASER APPARATUS AND METHOD FOR MANUFACTURING A SOLAR CELL MODULE USING THE SAME - A method for manufacturing a solar cell module includes forming a first electrode on a first surface of a substrate; forming a semiconductor layer on the first electrode; forming a second electrode on the semiconductor layer; inverting the substrate with the first electrode, semiconductor layer and second electrode formed thereon, and then, positioning the inverted substrate on a plurality of supports; patterning the second electrode and the semiconductor layer while the inverted substrate is on the supports by irradiating a laser on a second surface of the substrate to form a plurality of solar cells, wherein the second surface of the substrate is opposite the first surface of the substrate; identifying defective solar cells by using the supports; and repairing the defective solar cells by using the supports. | 2012-05-31 |
20120135546 | ALIGNMENT INSPECTION - The present disclosure relates to the field of microelectronic substrate fabrication and, more particularly, to alignment inspection for vias formed in the microelectronic substrates. The alignment inspection may be achieved by determining the relative positions of fluorescing and non-fluorescing elements in a microelectronic substrate. | 2012-05-31 |
20120135547 | FABRICATING METHOD AND TESTING METHOD OF SEMICONDUCTOR DEVICE AND MECHANICAL INTEGRITY TESTING APPARATUS - A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test. | 2012-05-31 |
20120135548 | SEMICONDUCTOR DEVICE - A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit. | 2012-05-31 |
20120135549 | Method of Processing Gallium-Nitride Semiconductor Substrates - Polishing a nitride semiconductor monocrystalline wafer leaves it with a process-transformed layer. The process-transformed layer has to be etched to be removed. The chemical inertness of nitride semiconductor materials has, however, precluded suitable etching. Although potassium hydroxide, for example, or sulfuric acid have been proposed as GaN etchants, their ability to corrosively remove material from the Ga face is weak. Dry etching utilizing a halogen plasma is carried out in order to remove the process-transformed layer. The Ga face can be etched off with the halogen plasma. Nevertheless, owing to the dry etching, a problem arises again—surface contamination due to metal particles. To address the problem, wet etching with, as the etchant, solutions such as HF+H | 2012-05-31 |
20120135550 | REFRACTION ASSISTED ILLUMINATION FOR IMAGING - Various embodiments are directed to systems and methods of imaging subsurface features of objects. An illumination source may be directed towards a surface of an object comprising subsurface features at a first angle relative to the normal of the surface. The object may have a portion between the subsurface features and the surface that has an index of refraction that is greater than the index of refraction of a surrounding medium. An imaging device may be placed with an objective lens oriented substantially normal to the surface. The first angle may be larger than an acceptance angle of the objective lens. | 2012-05-31 |
20120135551 | LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - Disclosed herein is a light emitting diode. The light emitting diode includes a support substrate, semiconductor layers formed on the support substrate, and a metal pattern located between the support substrate and the lower semiconductor layer. The semiconductor layers include an upper semiconductor layer of a first conductive type, an active layer, and a lower semiconductor layer of a second conductive type. The semiconductor layers are grown on a sacrificial substrate and the support substrate is homogeneous with the sacrificial substrate. | 2012-05-31 |
20120135552 | ARRAY SUBSTRATE FOR IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE INCLUDING PIXEL AND COMMON ELECTRODES ON THE SAME LAYER AND METHOD OF MANUFACTURING THE SAME - An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line along a first direction on the substrate, a data line along a second direction and crossing the gate line to define a pixel region, a common line on the substrate, a thin film transistor connected to the gate and data lines, a pixel electrode in the pixel region and connected to the thin film transistor, the pixel electrode including horizontal parts along the first direction, and a common electrode in the pixel region and connected to the common line, the common electrode including horizontal portions along the first direction, wherein the pixel electrode and the common electrode are formed on a same layer. | 2012-05-31 |
20120135553 | Method for Manufacture of Bright GaN LEDs Using a Selective Removal Process - A method of fabricating LED devices includes using a laser to form trenches between the LEDs and then using a chemical solution to remove slag creating by the laser. | 2012-05-31 |
20120135554 | GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE, AND METHOD OF FABRICATING GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE - A method of fabricating a group-III nitride semiconductor laser device includes: preparing a substrate of a hexagonal group-III nitride semiconductor, where the substrate has a semipolar primary surface; forming a substrate product having a laser structure, an anode electrode and a cathode electrode, where the laser structure includes the substrate and a semiconductor region, and where the semiconductor region is formed on the semipolar primary surface; scribing a first surface of the substrate product in part in a direction of the a-axis of the hexagonal group-III nitride semiconductor; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar. | 2012-05-31 |
20120135555 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL - A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant. | 2012-05-31 |
20120135556 | METHODS FOR MANUFACTURING ORGANIC EL DISPLAY PANEL AND ORGANIC EL DISPLAY DEVICE - Provided is an organic EL display panel offering improved luminance without increasing the current density of current flowing through organic light-emitting layers, comprising: substrate; TFT layer formed on substrate; planarizing film formed above TFT layer and having contact holes; lower electrodes arranged above planarizing film in a matrix in one-to-one correspondence with pixel units, and brought into conduction with TFT layer via contact holes; grid-shaped bank formed above planarizing film and defining openings corresponding one-to-one to lower electrodes; organic light-emitting layers formed in openings; and upper electrode formed above light-emitting layers. Each contact hole is positioned between a pair of openings adjacent in the column direction. At least one of opposing sides of any pair of openings adjacent in the column direction is reduced in width in the row direction and extends in the column direction so as to be adjacent in the row direction to the corresponding contact hole. | 2012-05-31 |
20120135557 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A method for producing a Group III nitride semiconductor light-emitting device includes forming a first stripe-pattern embossment on the top surface of a sapphire substrate, so that first grooves parallel to the x-axis direction (the c-axis direction of the sapphire substrate) are periodically arranged at specific intervals. Subsequently, an insulating film is formed over the entire surface of the first stripe-pattern embossment. Next, a second stripe-pattern embossment is formed so that second grooves, each having a flat bottom surface, are periodically arranged at specific intervals and parallel to the y-axis direction, which is orthogonal to the x-axis direction. A GaN crystal is grown through MOCVD on side surfaces of each second groove of the sapphire substrate, to thereby form, on the sapphire substrate, an m-plane GaN base layer. An LED device structure is formed on the base layer, to thereby produce a light-emitting device. | 2012-05-31 |
20120135558 | METHOD OF ETCHING ASYMMETRIC WAFER, SOLAR CELL INCLUDING THE ASYMMETRICALLY ETCHED WAFER, AND METHOD OF MANUFACTURING THE SAME - With the present invention, two wafers for a solar cell only whose light receiving surfaces are selectively etched can be simultaneously obtained by overlapping the two wafers and performing a single-sided etching or an asymmetric etching thereon. The present invention provides a method of etching a wafer comprising: performing a single-sided etching or an asymmetric etching on the wafer, wherein the performing the single-sided etching or the asymmetric etching comprises: overlapping two wafers whose one sides face each other; and etching the overlapped two wafers, and a solar cell including the etched wafers. | 2012-05-31 |
20120135559 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a solid-state imaging device including: forming photo sensor portions in a silicon substrate; forming a wiring portion above said silicon substrate; bonding another substrate onto said wiring portion; removing said substrate in response to performing the bonding of the another substrate onto the wiring portion; and sequentially forming an anti-reflective coating on the silicon substrate, a color filter on the anti-reflective coating, and an on-chip lens. | 2012-05-31 |
20120135560 | METHODS OF PACKAGING IMAGER DEVICES AND OPTICS MODULES, AND RESULTING ASSEMBLIES - A method of packaging imager devices and optics modules is disclosed which includes positioning an imager device and an optics module in each of a plurality of openings in a carrier body, introducing an encapsulant material into each of the openings in the carrier body and cutting the carrier body to singulate the plurality of imager devices and optics modules into individual units, each of which comprise an imager device and an optics module. A device is also disclosed which includes an imager device comprising a plurality of photosensitive elements and an optics module coupled to the imager device, the optics module comprising at least one lens that, when the optics module is coupled to the imager device, is positioned a fixed, non-adjustable distance from the plurality of photosensitive elements. | 2012-05-31 |
20120135561 | PHOTOELECTRIC-CONVERSION-DEVICE FABRICATION METHOD - An object is to obtain a high-efficiency photoelectric conversion device having a crystalline silicon i-layer in a photoelectric conversion layer. Disclosed is a fabrication method for a photoelectric conversion device that includes a step of forming, on a substrate, a photoelectric conversion layer having an i-layer formed mainly of crystalline silicon. The method includes the steps of determining an upper limit of an impurity concentration in the i-layer according to the Raman ratio of the i-layer; and forming the i-layer so as to have a value equal to or less than the determined upper limit of the impurity concentration. Alternatively, an upper limit of impurity-gas concentration in a film-formation atmosphere is determined according to the Raman ratio of the i-layer, and the i-layer is formed while controlling the impurity-gas concentration so as to have a value equal to or less than the determined upper limit. | 2012-05-31 |
20120135562 | METHODS OF FORMING HYDROPHOBIC SILICON DIOXIDE LAYER AND FORMING ORGANIC THIN FILM TRANSISTOR - A method of forming a hydrophobic silicon dioxide layer is provided. A substrate is provided. Thereafter, a hydrophobic silicon dioxide layer is formed on the substrate by using a plasma chemical vapour deposition (CVD) system, in which tetraethyl orthosilicate (TEOS) and an oxygen-containing gas are introduced at a reactive temperature between 25° C. and 150° C. A method of forming an organic thin film transistor (OTFT) including the hydrophobic silicon dioxide layer as a gate insulating layer is also provided. In the present invention, the hydrophobic silicon dioxide layer can be directly formed at low temperature without using the conventional surface modification treatment. Accordingly, the process is simplified and the cost is reduced. | 2012-05-31 |
20120135563 | PROCESS FOR PRODUCING MULTILAYER CHIP ZINC OXIDE VARISTOR CONTAINING PURE SILVER INTERNAL ELECTRODES AND FIRING AT ULTRALOW TEMPERATURE - A low-temperature firing process is available for cost saving to produce a multilayer chip ZnO varistor containing pure silver (Ag) formed as internal electrodes and calcined at ultralow firing temperature of 850-900° C., which process comprises:
| 2012-05-31 |
20120135564 | SOFT ERROR RATE MITIGATION BY INTERCONNECT STRUCTURE - A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier. | 2012-05-31 |
20120135565 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING FILLING GAP BETWEEN SUBSTRATES WITH MOLD RESIN - A method of manufacturing a semiconductor device in one exemplary embodiment includes preparing a first substrate and a second substrate, the first substrate including a bump electrode group formed of bump electrodes arrayed with a certain pitch, the number of bump electrodes along a first direction being larger than the number of bump electrodes along a second direction perpendicular to the first direction; joining the first substrate and the second substrate to each other through the bump electrodes so that a gap is formed between the first substrate and the second substrate; and filling the gap with a mold resin by causing the mold resin to flow in the gap from an edge of the first substrate along the second direction of the bump electrode group. | 2012-05-31 |
20120135566 | Monolithic Integration Of Photonics And Electronics In CMOS Processes - Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. | 2012-05-31 |
20120135567 | METHODS AND APPARATUSES FOR TRANSFERRING HEAT FROM STACKED MICROFEATURE DEVICES - Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The first external contacts are operatively coupled to the terminals on the support member. The assembly also includes a second microelectronic die having integrated circuitry and second external contacts electrically coupled to the first external contacts. The first die is between the support member and the second die. The assembly can further include a heat transfer unit between the first die and the second die. The heat transfer unit includes a first heat transfer portion, a second heat transfer portion, and a gap between the first and second heat transfer portions such that the first external contacts and the second external contacts are aligned with the gap. | 2012-05-31 |
20120135568 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - A semiconductor device of the present invention comprises a substrate and a first semiconductor element. The substrate comprises an inner layer conductor and a cavity comprising the bottom surface on which a part of the inner layer conductor is exposed. The first semiconductor element contacts, in the cavity, the inner layer conductor directly or via a good heat conductor material. | 2012-05-31 |
20120135569 | STACKED MICROELECTRONIC DIES AND METHODS FOR STACKING MICROELECTRONIC DIES - An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic device having a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The method can further include electrically connecting the first packaged microelectronic device to a first portion of the support member circuitry and positioning at least proximate to the first packaged microelectronic device a second packaged microelectronic device having a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configuration. The first packaged microelectronic device can be positioned between the support member and the second packaged microelectronic device. The second packaged device can be coupled directly to a second portion of the support member circuitry. Accordingly, the second packaged microelectronic device can be connected directly to the support member without connecting the second packaged device to the first packaged device. | 2012-05-31 |
20120135570 | LIFTING-OFF METHOD AND METHOD FOR MANUFACTURING TFT ARRAY SUBSTRATE - A lifting-off method and a manufacturing method for a thin film transistor (TFT) array substrate using the same are provided. A lifting-off method comprises forming a cavitation jet flow by using a lifting-off solution, and impacting a to-be-lifted-off surface of a substrate by means of the cavitation jet flow to remove a photoresist and a film deposited on the photoresist over the to-be-lifted-off surface. The disclosure may be applied to manufacturing processes for semiconductor devices or TFT array substrate. | 2012-05-31 |
20120135571 | MANUFACTURING METHOD OF A THIN FILM TRANSISTOR - A manufacturing method of a thin film transistor is provided. An insulating pattern layer having at least one protrusion is formed on a substrate. At least one spacer and a plurality of amorphous semiconductor patterns separated from each other are formed on the insulating pattern layer. The spacer is formed at one side of the protrusion and connected between the amorphous semiconductor patterns. The spacer and the amorphous semiconductor patterns are crystallized. The protrusion and the insulating pattern layer below the spacer are removed so that a beam structure having a plurality of corners is formed and suspended over the substrate. A carrier tunneling layer, a carrier trapping layer and a carrier blocking layer are sequentially formed to compliantly wrap the corners of the beam structure. Hereafter, a gate is formed on the substrate to cover the beam structure and wrap the carrier blocking layer. | 2012-05-31 |
20120135572 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A gate electrode is formed on a surface of a semiconductor substrate. A resist mask is formed that covers both end faces of the gate electrode in a gate width direction intersecting a gate length direction. Impurity ions are implanted into the semiconductor substrate in an implantation direction having a gate length direction component and a gate width direction component, to form a low-concentration impurity layer overlapping with the gate electrode at both sides of the gate electrode in the surface of the semiconductor substrate. A sidewall is formed that covers a side surface of the gate electrode. Impurity ions are implanted using the gate electrode and the sidewall as a mask, to form a high-concentration impurity layer apart from the gate electrode at both sides of the gate electrode on the surface of the semiconductor substrate. | 2012-05-31 |
20120135573 | METHOD FOR MANUFACTURING VERTICAL TRANSISTOR HAVING ONE SIDE CONTACT - A method for manufacturing a vertical transistor having a one side contact includes: forming separate active regions using trenches, on a semiconductor substrate, the active regions having first and second side surfaces facing the trenches; forming a first liner on the first and second side surfaces; forming a second liner which exposes a lower portion of the first liner on the first side surface; forming a third liner covering the portion of the first layer exposed by the second liner; forming a sacrifice layer on the third liner to fill the trench; forming an etch barrier to selectively expose upper end portions of the first to third liners positioned adjacent to the first side surface; selectively removing the third liner not covered by the etch barrier to expose a portion of the first liner not covered by the second liner; selectively removing the exposed portion of the first liner to expose a lower portion of the first side surface; and forming a buried bit line contacted with the exposed portion of the first side surface. | 2012-05-31 |
20120135574 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between. | 2012-05-31 |
20120135575 | METHODS OF FORMING INTEGRATED CIRCUITS - A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants. | 2012-05-31 |
20120135576 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method of fabricating a semiconductor device. The method includes providing a substrate having a channel region; forming a gate structure, which comprises a dummy gate pattern, on the substrate; forming first and second trenches by recessing the substrate on both sides of the gate structure, respectively; forming a first semiconductor pattern in the first and second trenches; removing the dummy gate pattern to expose a portion of the channel region; forming a recessed channel region by recessing the portion of the channel region; and forming a second semiconductor pattern in the recessed region. | 2012-05-31 |
20120135577 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics. | 2012-05-31 |
20120135578 | DOPING OF PLANAR OR THREE-DIMENSIONAL STRUCTURES AT ELEVATED TEMPERATURES - An improved method of doping a workpiece is disclosed. In this method, a film comprising the species to be implanted is introduced to the surface of a planar or three-dimensional workpiece. This film can be grown using CVD, a bath or other means. The workpiece with the film is then subjected to ion bombardment to help drive the dopant into the workpiece. This ion bombardment is performed at elevated temperatures to reduce crystal damage and create a more abrupt doped region. | 2012-05-31 |
20120135579 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method uses a line pattern to form a semiconductor device including asymmetrical contact arrays. The method includes forming a plurality of parallel first conductive line layers extending in a first direction on a semiconductor substrate. In this method, the semiconductor substrate may have active regions forming an oblique angle with the first direction. The method may further include forming a first mask layer and a second mask layer and using the first mask layer and the second mask layer to form a trench comprising a line area and a contact area by etching the first conductive line layers using the first mask layer and the second mask layer. The method further includes forming a gap filling layer filling the line area of the trench and forming a spacer of sidewalls of the contact area and forming a second conductive line layer electrically connected to the active region. | 2012-05-31 |
20120135580 | Three-Dimensional Memory Structures Having Shared Pillar Memory Cells - A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element. | 2012-05-31 |
20120135581 | MEMORY DEVICES AND METHODS OF FORMING THE SAME - Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed. | 2012-05-31 |
20120135582 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Semiconductor device manufacturing method includes forming a first mask, having a first opening to implant ion into semiconductor substrate and being used to form first layer well, on semiconductor substrate; forming first-layer well having first and second regions by implanting first ion into semiconductor substrate using first mask; forming second mask, having second opening to implant ion into semiconductor substrate and being used to form second layer well, on semiconductor substrate; and forming second-layer well below first layer well by implanting second ion into semiconductor substrate using second mask. First region is formed closer to an edge of first-layer well than second region. Upon implanting first ion, first ion deflected by first inner wall of first mask is supplied to first region. Upon implanting second ion, second ion deflected by second inner wall of second mask is supplied to second region. | 2012-05-31 |
20120135583 | METHODS OF MANUFACTURING THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES USING SUB-PLATES - A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a plurality of sub-plate stack structures between forming a plurality of vertical active patterns in the plate stack structure and forming pads of a stepped structure from the plate stack structure. | 2012-05-31 |
20120135584 | METHOD FOR MANUFACTURING SOI WAFER - A method for manufacturing an SOI wafer includes performing a flattening heat treatment on an SOI wafer under an atmosphere containing an argon gas, in which conditions of SOI wafer preparation are set so that a thickness of an SOI layer of the SOI wafer to be subjected to the flattening heat treatment is 1.4 or more times thicker than that of a BOX layer, and the thickness of the SOI layer is reduced to less than a thickness 1.4 times the thickness of the BOX layer by performing a sacrificial oxidation treatment on the SOI layer of the SOI wafer after the flattening heat treatment. | 2012-05-31 |
20120135585 | METHOD FOR MANUFACTURING CHIP - A method for manufacturing a chip constituted by a functional device formed on a substrate comprises a functional device forming step of forming the functional device on one main face of a sheet-like object to be processed made of silicon; a first modified region forming step of converging a laser light at the object so as to form a first modified region along the one main face of the object at a predetermined depth corresponding to the thickness of the substrate from the one main face; a second modified region forming step of converging the laser light at the object so as to form a second modified region extending such as to correspond to a side edge of the substrate as seen from the one main face on the one main face side in the object such that the second modified region joins with the first modified region along the thickness direction of the object; and an etching step of selectively advancing etching along the first and second modified regions after the first and second modified region forming steps so as to cut out a part of the object and form the substrate. | 2012-05-31 |
20120135586 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming silicon line patterns in a semiconductor substrate, forming an insulating layer over the silicon line patterns, forming a conductive pattern between the silicon line patterns, forming a spacer over the substrate, forming an interlayer insulating layer between the silicon line patterns, removing the spacer on one side of the silicon line patterns to expose the conductive pattern, forming a bit line contact open region by removing the interlayer insulating layer, forming a polysilicon pattern to cover the bit line contact open region, and forming a junction region diffused to the silicon line pattern through the bit line contact open region. Thereby, a stacked structure of a titanium layer and a polysilicon layer are stably formed when forming a buried bit line and a bit line contact is formed using diffusion of the polysilicon layer to prevent leakage current. | 2012-05-31 |
20120135587 | N-type carrier enhancement in semiconductors - A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage. Repeating the implantation and the thermal annealing until the target n-type carrier concentration has been reached. | 2012-05-31 |
20120135588 | METHOD FOR PATTERNING A METAL LAYER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES BY USING THE SAME - Disclosed herein is a method for patterning a metal layer, which includes the following steps. A substrate having a metal layer thereon is provided. A patterned conductive polymeric layer is formed on the metal layer, wherein a portion of the metal layer is exposed by the patterned conductive polymeric layer. The substrate having the patterned conductive polymer layer is disposed in an electrolytic cell, so that the exposed portion of the metal layer is immersed in the electrolytic solution of the electrolytic cell. The anode of the electrolytic cell is electrically coupled to the patterned conductive polymeric layer, while the cathode of the electrolytic cell is immersed in the electrolytic solution. Sequentially, an electrical potential is applied across the anode and the cathode to perform an electrolysis reaction so that the exposed portion of the metal layer is dissolved in the electrolytic solution. | 2012-05-31 |
20120135589 | CHEMICAL-MECHANICAL PLANARIZATION METHOD AND METHOD FOR FABRICATING METAL GATE IN GATE-LAST PROCESS - The present invention provides a chemical-mechanical planarization method and a method for fabricating a metal gate in gate last process. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP, thereby improving the within-die uniformity of the process, consequently, there will not be excess metal in the insulating layer between gates, thereby preventing device short circuit risk induced by POP CMP process. | 2012-05-31 |
20120135590 | SILICON REMOVAL FROM SURFACES AND METHOD OF FORMING HIGH K METAL GATE STRUCTURES USING SAME - A method of fabricating a semiconductor device, comprising carrying out a gate last process including forming a dummy gate of polysilicon, and thereafter removing the dummy gate for replacement by a metal gate, wherein the dummy gate is removed by XeF | 2012-05-31 |
20120135591 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING - Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers. | 2012-05-31 |
20120135592 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed, which reduces a step difference between a peripheral region and a cell region. In the semiconductor device, a metal contact of the peripheral region is configured in a multi-layered structure. Prior to forming a bit line and a storage node contact in the cell region, a contact and a line are formed in the peripheral region, such that a step difference between the cell region and the peripheral region is reduced, resulting in a reduction in parasitic capacitance between lines. | 2012-05-31 |
20120135593 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors. | 2012-05-31 |
20120135594 | METHOD FOR FORMING A GATE ELECTRODE - A method for forming a gate electrode includes: providing a substrate; forming a gate dielectric layer and forming a sacrificial layer, the sacrificial layer including doping ions, a density of the doping ions in the sacrificial layer decreasing with increasing distance from the substrate; forming a hard mask layer; patterning the sacrificial layer and the hard mask layer; removing part of the patterned sacrificial layer by wet etching with the patterned hard mask layer as a mask, to form a dummy gate electrode which has a top width bigger than a bottom width, and removing the patterned hard mask layer; removing the dummy gate electrode and filling a gate trench with gate material to form a gate electrode which has a top width bigger than a bottom width, which facilitates the filling of the gate material and can avoid or reduce cavity forming in the gate material. | 2012-05-31 |
20120135595 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer. | 2012-05-31 |
20120135596 | METHOD OF REMOVING NANOCRYSTALS - A method for forming a semiconductor structure includes providing a semiconductor layer, forming nanocrystals over the semiconductor layer, and using a solution comprising pure water, hydrogen peroxide, and ammonium hydroxide to remove at least a portion of the nanocrystals. A ratio by volume of pure water to ammonium hydroxide of the solution may be equivalent to or less than a ratio by volume of 10:1 of pure water to ammonium hydroxide when ammonium hydroxide has a concentration of 29% ammonia by weight. The step of using the solution to remove the at least a portion of the nanocrystals may be performed at a temperature of 50 degrees Celsius or more. | 2012-05-31 |
20120135597 | METHOD OF FORMING TiO2 ARRAY USING ZnO TEMPLATE - Provided is a method of forming a method of forming a titanium dioxide (TiO | 2012-05-31 |
20120135598 | METHOD FOR FABRICATING INTERCONNECTIONS WITH CARBON NANOTUBES - A method for fabricating interconnections with carbon nanotubes of the present invention comprises the following steps: forming a dual-layer that contains a catalytic layer and an upper covering layer on the periphery of a hole connecting with a substrate; and growing carbon nanotubes on the catalytic layer with the upper covering layer covering the carbon nanotubes. The present invention grows the carbon nanotubes between the catalytic layer and the upper covering layer. The upper covering layer protects the catalytic layer from being oxidized and thus enhances the growth of the carbon nanotubes. The carbon nanotubes are respectively connected with the lower substrate and an upper conductive wire via the catalytic layer and the upper covering layer, which results in a lower contact resistance. Moreover, the upper covering layer also functions as a metal-diffusion barrier layer to prevent metal from spreading to other materials via diffusion or other approaches. | 2012-05-31 |
20120135599 | CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYERS CONFIGURED TO BLOCK ELECTROMAGNETIC EDGE INTERFERENCE - Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough. | 2012-05-31 |
20120135600 | METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING - The embodiments of via mask splitting methods for double patterning technology described enable via patterning to align to a metal layer underneath or overlying to reduce overlay error and to increase via landing. If adjacent vias violate the G | 2012-05-31 |
20120135601 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a plurality of hole patterns is disclosed. The method includes: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns where the plurality of first line patterns and the plurality of second line patterns cross each other. | 2012-05-31 |
20120135602 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having a cooling mechanism comprises a modified region forming step of converging a laser light at a sheet-like object to be processed made of silicon so as to form a modified region within the object along a line to form a modified region, an etching step of anisotropically etching the object after the modified region forming step so as to advance the etching selectively along the first modified region and form a flow path for circulating a coolant as a cooling mechanism within the object, and a functional device forming step of forming a functional device on one main face side of the object. | 2012-05-31 |
20120135603 | METHODS FOR INCREASED ARRAY FEATURE DENSITY - The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays. | 2012-05-31 |
20120135604 | PROCESSING LIQUID FOR SUPPRESSING PATTERN COLLAPSE OF FINE METAL STRUCTURE, AND METHOD FOR PRODUCING FINE METAL STRUCTURE USING SAME - There are provided a processing liquid that is capable of suppressing pattern collapse of a fine metal structure, such as a semiconductor device and a micromachine, and a method for producing a fine metal structure using the same. The processing liquid for suppressing pattern collapse of a fine metal structure, contains a phosphate ester and/or a polyoxyalkylene ether phosphate ester, and the method for producing a fine metal structure, uses the same. | 2012-05-31 |
20120135605 | METHOD FOR FORMING SIDE-CONTACT REGION IN SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a first trench by etching a substrate, forming a liner layer on a surface of the first trench, forming a sacrificial spacer pattern covering one sidewall of the first trench over the liner layer, forming a second trench by etching the substrate under the first trench using the sacrificial spacer pattern and the liner layer as etch barriers, forming a protection layer on a surface of the second trench, and forming a side contact region by selectively removing the protection layer formed on an upper portion of one sidewall of the second trench. | 2012-05-31 |
20120135606 | LASER PROCESSING METHOD - A laser processing method of converging laser light into an object to be processed made of silicon so as to form a modified region and etching the object along the modified region so as to form the object with a through hole comprises an etch resist film producing step of producing an etch resist film resistant to etching on an outer surface of the object; a laser light converging step of converging the laser light at the object after the etch resist film producing step so as to form the modified region along a part corresponding to the through hole in the object and converging the laser light at the etch resist film so as to form a defect region along a part corresponding to the through hole in the etch resist film; and an etching step of etching the object after the laser light converging step so as to advance the etching selectively along the modified region and form the through hole. | 2012-05-31 |
20120135607 | SUBSTRATE PROCESSING METHOD - A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and produce a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of 45° or greater therebetween, and the modified spots are made align in one row along the line. | 2012-05-31 |
20120135608 | SUBSTRATE PROCESSING METHOD - A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and construct a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of less than 45° therebetween, and the modified spots are made align in a plurality of rows along the line. | 2012-05-31 |
20120135609 | Apparatus and Process for Atomic Layer Deposition - Provided are gas distribution plates (showerheads) for use in an apparatus configured to form a film during, for example, an atomic layer deposition (ALD) process. The gas distribution plate comprises a body defining a thickness and a peripheral edge and has a front surface for facing the substrate. The front surface has a central region with a plurality of openings configured to distribute process gases over the substrate and a focus ring with a sloped region. The focus ring is concentric to the central region such that the thickness at the focus ring is greater than the thickness at the central region. | 2012-05-31 |
20120135610 | SYSTEM AND METHOD FOR PROCESSING SUBSTRATE - A substrate processing system including a cleaning equipment; a resist coating equipment forming a resist layer on a surface of a substrate; an edge exposure equipment that exposes to light an edge portion of the resist layer formed on a peripheral edge of the substrate; a substrate transport mechanism; and a system controller. The system controller includes a waiting time monitor and a process controller. The waiting time monitor monitors a waiting time that is a time interval between the formation of the resist layer and start of the exposure of the edge portion of the resist layer. The process controller causes the substrate transport mechanism to transport the substrate into the cleaning equipment when the monitored waiting time exceeds a prescribed limit, removing the resist layer from the substrate. The process controller then causes the substrate transport mechanism to transport the substrate into the resist coating equipment. | 2012-05-31 |
20120135611 | METHOD OF MANUFACTURING POROUS INSULATING FILM - A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group. | 2012-05-31 |
20120135612 | FILM FORMING METHOD, PRETREATMENT DEVICE, AND PROCESSING SYSTEM - A film forming method is disclosed in which a thin film comprising manganese is formed on an object to be processed which has, on a surface thereof, an insulating layer constituted of a low-k film and having a recess. The method comprises a hydrophilization step in which the surface of the insulating layer is hydrophilized to make the surface hydrophilic and a thin-film formation step in which a thin film containing manganese is formed on the surface of the hydrophilized insulating layer by performing a film forming process using a manganese-containing material gas on the surface of the hydrophilized insulating layer. Thus, a thin film comprising manganese, e.g., an MnOx film, is effectively formed on the surface of the insulating layer constituted of a low-k film, which has a low dielectric constant. | 2012-05-31 |
20120135613 | ELECTRICAL CONNECTION BETWEEN DEVICES - Concepts for forming an electrical connection between devices are disclosed. A cord for transferring electrical power and signals can be provided to connect a first device to a second device. One or more magnetic couplings can be provided to exert magnetic forces between the cord and the first device and/or between the cord and the second device. The one or more magnetic couplings can allow transfer of electrical power and signals therethrough. | 2012-05-31 |
20120135614 | ELECTRICAL JUNCTION BOX - An object of the present invention is to provide an electrical junction box having a new structure that can simplify a parts control and can lower a cost in production by enabling already available connecting terminals to be converted. Support projections are provided on an insulation plate. The support projections receive and support connecting terminals and have projecting dimensions corresponding to the connecting terminals. A casing contains the insulation plate. The casing is provided on a surface opposed to the support projections with recess-like or bump-like matching portions that contact with projection end surfaces of the support projections to position the support projections. | 2012-05-31 |
20120135615 | ELECTRONIC CONNECTOR - An electronic connector includes a plurality of pairs of terminal parts for transmitting an electric signal; and grounding parts shaped like plates and connected to have a ground potential, wherein the grounding parts have protrusions protruding on a side of the pairs of terminal parts, and the protrusions are respectively interposed between the pairs of terminal parts which are adjacent to each other. | 2012-05-31 |
20120135616 | ADAPTER APPARATUS - An adapter apparatus includes a main body, two conductive head portions, and two covers. The main body includes a first end and a second end opposite to the first end. The conductive head portions are electrically connected to each other, and pivotably mounted to the first and second ends, respectively, to pivot between first positions where the covers cover the corresponding head portions, and second positions where the covers are latched to the main body to expose the corresponding head portions. | 2012-05-31 |
20120135617 | COMMUNICATION DEVICE - A communication device is configured to perform data communications with a communication target while being connected to an information processing apparatus, and includes a communication unit and a holding unit. The communication unit is provided with a connector connectable to a connection port of the information processing apparatus and performs data communications with the communication target under control of the information processing apparatus. The holding unit holds the communication target. The holding unit is attached to the communication unit so as to be movable to a position where the holding unit covers the connector in a stored state, and movable to a position where the holding unit exposes the connector in a used state. | 2012-05-31 |
20120135618 | CARD EDGE CONNECTOR HAVING IMPROVED EJECTOR - A card edge connector ( | 2012-05-31 |
20120135619 | ELECTRICAL JUNCTION BOX - An object of the present invention is to provide an electrical junction box having a new structure in which a lever of a lever type connector engages a connector hood and a deflection of a wall portion can be prevented without increasing an amount of a resin. Latch projections protrude from a wall portion of a connector hood toward the inside of the connector hood. The latch projections engage guide grooves in a lever of a connector. A plurality of lightening holes are formed in the wall portion. The latch projections are supported on a solid part of the wall portion that is not provided with the lightening holes. | 2012-05-31 |