22nd week of 2015 patent applcation highlights part 15 |
Patent application number | Title | Published |
20150145002 | CMOS Devices with Reduced Leakage and Methods of Forming the Same - A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer. The semiconductor region and the second semiconductor layer comprise different material. The bottom surface of the semiconductor region has a slanted portion contacting a ( | 2015-05-28 |
20150145003 | FINFET SEMICONDUCTOR DEVICES INCLUDING RECESSED SOURCE-DRAIN REGIONS ON A BOTTOM SEMICONDUCTOR LAYER AND METHODS OF FABRICATING THE SAME - FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, and a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin opposite the first side. | 2015-05-28 |
20150145004 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse. | 2015-05-28 |
20150145005 | TRANSISTOR AMPLIFIER CIRCUIT AND INTEGRATED CIRCUIT - Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region) of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed. | 2015-05-28 |
20150145006 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - The semiconductor device includes a plurality of pixels arranged in rows and columns, and first transistors fewer than the number of the plurality of pixels. The plurality of pixels each includes a photodiode and an amplifier circuit. The amplifier circuit holds the accumulated charge and includes at least a second transistor electrically connected to a cathode of the photodiode. The cathode of the photodiode in the pixel in an n-th row and the cathode of the photodiode in the pixel in an (n+1)-th row are electrically connected to the first transistor. The number n is a natural number. The pixel in the n-th row and the pixel in the (n+1)-th row are in an identical column. | 2015-05-28 |
20150145007 | IMAGING SYSTEMS WITH IMAGE PIXELS HAVING ADJUSTABLE RESPONSIVITY - An imaging system may include an image sensor having an array of image pixels. Some image pixels in the array may be provided with responsivity adjustment structures. For example, broadband pixels in a pixel array may include responsivity adjustment circuitry. The responsivity adjustment circuitry may be configured to narrow the spectral response or to reduce the conversion gain of the broadband pixels in high light conditions. For example, a deep photodiode may divert charge away from a signal photodiode during an integration period. The deep photodiode may divert charge to a power supply or the charge may be transferred to a storage node and used in image processing, if desired. The responsivity adjustment circuitry may include channel-dependent conversion circuitry that is formed in pixels corresponding to a first color channel, while the conversion gains of pixels corresponding to a second color channel may remain fixed. | 2015-05-28 |
20150145008 | FIN CAPACITOR EMPLOYING SIDEWALL IMAGE TRANSFER - Spacer structures are formed around an array of disposable mandrel structures and above a doped semiconductor material portion. A sidewall image transfer process is employed to pattern an upper portion of the doped semiconductor material portion into an array of doped semiconductor fins. After formation of a dielectric material layer on the top surfaces and sidewall surfaces of the doped semiconductor fins, gate-level mandrel structures are formed to straddle multiple semiconductor fins. A conductive hole-containing structure is formed to laterally surround a plurality of gate-level mandrel structures, which is subsequently removed. A contact-level dielectric layer is formed over the conductive hole-containing structure and the plurality of doped semiconductor fins. The semiconductor fins function as a lower electrode of a fin capacitor, and the conductive hole-containing structure functions as an upper electrode of the fin capacitor. | 2015-05-28 |
20150145009 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - In order to achieve high-speed operation of an eDRAM, the eDRAM includes: a selection MISFET having a gate electrode that serves as a word line, a source region, and a drain region; a source plug electrode coupled to the source region; and a drain plug electrode coupled to the drain region DR | 2015-05-28 |
20150145010 | DYNAMIC RANDOM ACCESS MEMORY CELL EMPLOYING TRENCHES LOCATED BETWEEN LENGTHWISE EDGES OF SEMICONDUCTOR FINS - After formation of semiconductor fins in an upper portion of a bulk semiconductor substrate, a shallow trench isolation layer is formed, which includes a dielectric material and laterally surround lower portions of each semiconductor fin. Trenches are formed between lengthwise sidewalls of neighboring pairs of semiconductor fins. Portions of the shallow trench isolation layer laterally surrounding each trench provide electrical isolation between the buried plate and access transistors. A strap structure can be formed by etching a via cavity overlying a portion of each trench and a source region of the corresponding access transistor, and filling the via cavity with a conductive material. A trench top oxide structure electrically isolates an inner electrode of each trench capacitor from an overlying gate line for the access fin field effect transistor. | 2015-05-28 |
20150145011 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor substrate; a memory capacitor; and a first compensation capacitor. The semiconductor substrate has at least first and second regions. The memory capacitor is positioned over the first region. The memory capacitor may include, but is not limited to: a first lower electrode; and a first dielectric film covering inner and outer surfaces of the first lower electrode. The first compensation capacitor is positioned over the second region. The first compensation capacitor includes, but is not limited to: a second lower electrode; a second dielectric film covering an inner surface of the second lower electrode; and a first insulating film covering an outer surface of the second lower electrode. | 2015-05-28 |
20150145012 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A semiconductor structure is provided. The semiconductor structure includes a first stacked structure. The first stacked structure includes a first stacked portion disposed along a first direction, at least one second stacked portion connected with the first stacked portion and disposed along a second direction perpendicular to the first direction, and at least one third stacked portion connected with the first direction and arranged alternately with the second stacked portion along the first direction. The width of the third stacked portion is smaller than the width of the second stacked portion along the second direction. | 2015-05-28 |
20150145013 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes an active region tilted at an angle with respect to a buried bit line. The buried bit line includes a metal silicide pattern and a metal pattern. The metal silicide pattern has a plurality of metal silicide films each disposed at a lower portion of the active region and corresponding to a bit line contact region. The metal pattern has a plurality of metal films. The metal silicide films and the metal films are alternately arranged and electrically coupled to each other. | 2015-05-28 |
20150145014 | VERTICAL MEMORY DEVICES - A vertical memory device includes a substrate, a first cell block and a second cell block. The substrate includes a central region and a peripheral region. At least one first cell block is on the central region. The first cell block includes a first channel and first gate lines. At least one second cell block is on the peripheral region. The second cell block includes a second channel and second gate lines. The second cell block has a width greater than a width of the first cell block. The first and second channel extend in a first direction vertical to a top surface of the substrate. The first gate lines surround the first channel and the first gate lines are spaced apart from each other in the first direction. The second gate lines surround the second channel and are spaced apart from each other in the first direction. | 2015-05-28 |
20150145015 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure. | 2015-05-28 |
20150145016 | THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES INCLUDING INTERPOSED FLOATING GATES - Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers. | 2015-05-28 |
20150145017 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary method, a substrate can be provided. The substrate can have a plurality of isolation structures. A top surface of the plurality of isolation structures can be higher than a surface of the substrate. A device layer can be formed on the substrate and on the plurality of isolation structures. The device layer can be polished using a polishing process, such that the top surface of the plurality of isolation structures are exposed, with residue remaining on the device layer and on the plurality of isolation structures. The residue can be removed from the device layer and from the plurality of isolation structures using a non-polishing-removal process, such that the top surface of the plurality of isolation structures and a top surface of the device layer are substantially leveled and smooth. | 2015-05-28 |
20150145018 | Semiconductor Devices - Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration. | 2015-05-28 |
20150145019 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device may include: an isolation layer formed in a substrate and defining an active region; a control plug formed over the isolation layer; a floating gate formed over the substrate and including a plurality of fingers adjacent to the control plug with a gap provided therebetween; and a charge blocking layer formed on sidewalls of the floating gate so as to fill the gap. The control plug may include: a first control plug formed between the plurality of fingers and having sidewalls facing inner walls of the fingers; and a second control plug formed outside the floating gate and having sidewalls facing outer walls of the fingers. | 2015-05-28 |
20150145020 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a three-dimensional ( | 2015-05-28 |
20150145021 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions. | 2015-05-28 |
20150145022 | CMP FABRICATION SOLUTION FOR SPLIT GATE MEMORY EMBEDDED IN HK-MG PROCESS - A semiconductor device includes a substrate, at least one logic device and a split gate memory device. The at least one logic device is located on the substrate. The split gate memory device is located on the substrate and comprises a memory gate and a select gate. The memory gate and the select gate are adjacent to and electrically isolated with each other. A top of the select gate is higher than a top of the memory gate. | 2015-05-28 |
20150145023 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy. | 2015-05-28 |
20150145024 | INTEGRATED CIRCUITS HAVING IMPROVED SPLIT-GATE NONVOLATILE MEMORY DEVICES AND METHODS FOR FABRICATION OF SAME - Integrated circuits are provided. An exemplary integrated circuit includes a source/drain region in a semiconductor substrate. The integrated circuit includes a charge storage structure overlying the semiconductor substrate and having a first sidewall overlying the source/drain region. The integrated circuit also includes a control gate overlying the source/drain region. Further, the integrated circuit includes a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. | 2015-05-28 |
20150145025 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends. | 2015-05-28 |
20150145026 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device including a substrate having an active region and a field-plate region therein is disclosed. At least one trench-gate structure is in the substrate. The field-plate region is at a first side of the trench-gate structure. At least one source doped region is in the substrate at a second side opposite to the first side of the trench-gate structure. The source doped region adjoins the sidewall of the trench-gate structure. A drain doped region is in the substrate corresponding to the active region. The field-plate region is between the drain doped region and the trench-gate structure. An extending direction of length of the trench-gate structure is perpendicular to that of the drain doped region as viewed from a top-view perspective. | 2015-05-28 |
20150145027 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film. | 2015-05-28 |
20150145028 | Semiconductor Device with Cell Trench Structures and Contacts and Method of Manufacturing a Semiconductor Device - A semiconductor mesa is formed in a semiconductor layer between a first cell trench structure and a second cell trench structure extending from a first surface into the semiconductor layer. An opening is formed in a capping layer formed on the first surface, wherein the opening exposes at least a portion of the semiconductor mesa. Through the opening impurities of a first conductivity type are introduced into the exposed portion of the semiconductor mesa. A recess defined by the opening is formed. | 2015-05-28 |
20150145029 | SEMICONDUCTOR DEVICE HAVING BURIED GATE ELECTRODE STRUCTURES - A semiconductor device includes first and second gate electrode structures and a connection plug. The first gate electrode structure is buried in a semiconductor portion and has array stripes inside a first cell array of transistor cells and a contact stripe outside the first cell array, the contact stripe structurally connected with the array stripes. The second gate electrode structure is buried in the semiconductor portion and has array stripes inside a second cell array of transistor cells. An array isolation region of the semiconductor portion separates the first and second gate electrode structures. The connection plug extends between a first surface of the semiconductor portion and the contact stripe of the first gate electrode structure. | 2015-05-28 |
20150145030 | Semiconductor Device and Integrated Circuit - A semiconductor device in a semiconductor substrate includes a first drain region and a second drain region, a first drift zone and a second drift zone, at least two gate electrodes in the semiconductor substrate, and a channel region between the gate electrodes. The first drift zone is arranged between the channel region and the first drain region, and the second drift zone is arranged between the channel region and the second drain region. The second drain region is disposed on a side of the gate electrode, the side of the gate electrode being remote from the side of the first drain region. | 2015-05-28 |
20150145031 | VERTICAL-TYPE SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF - A semiconductor apparatus includes a semiconductor substrate including first and second regions, an inactive region formed in the semiconductor substrate of the second region and from a surface thereof, one or more first pillars vertically extending from the semiconductor substrate of the first region, one or more second pillars vertically extending from the inactive region, a gate conductive layer formed on the semiconductor substrate and surrounding the first and second pillars, and a gate contact formed on at least one of the second pillars to be coupled to the gate conductive layer, wherein the at least one of the second pillars has a height lower than the gate conductive layer. | 2015-05-28 |
20150145032 | Field-effect transistor and method for the fabrication thereof - The invention relates to a field-effect transistor and a method for its manufacturing having at least one layer, said layer comprising a III-V compound semiconductor, wherein the compound semiconductor comprises at least one element from the chemical group III being selected from any of gallium, aluminium, indium and/or boron and wherein the compound semiconductor comprises at least one element from the chemical group V being selected from nitrogen, phosphorous and/or arsenic, wherein the compound semiconductor comprises at least nitrogen, wherein the field-effect transistor comprises at least any of a source electrode and/or a drain electrode, said source electrode and/or drain electrode comprising at least one doped region extending from the surface into the at least one layer, wherein the depth of penetration of said doped region is selected from approximately 10 nm to approximately 200 nm. | 2015-05-28 |
20150145033 | HALO REGION FORMATION BY EPITAXIAL GROWTH - A structure including a semiconductor substrate including a source region and a drain region, a gate located above the semiconductor substrate and between the source region and the drain region, and two opposing halo regions being part of the source and drain regions, respectively, the halo regions being grown epitaxially, wherein the source region and the drain region include a stressor material. | 2015-05-28 |
20150145034 | LDMOS STRUCTURE AND MANUFACTURING METHOD THEREOF - A LDMOS structure including a semiconductor substrate, a drain region, a lightly doped drain (LDD) region, a source region and a gate structure is provided. The substrate has a trench. The drain region is formed in the semiconductor substrate under the trench. A LDD region is formed in the semiconductor substrate at a sidewall of the trench. The source region is formed in the semiconductor substrate. The gate structure is formed on a surface of the semiconductor substrate above the LDD region between the drain region and the source region. A method for manufacturing the LDMOS structure is also provided. | 2015-05-28 |
20150145035 | SEMICONDUCTOR DEVICE - In the interior of a semiconductor substrate having a main surface, a first p | 2015-05-28 |
20150145036 | POWER INTEGRATED CIRCUIT INCLUDING SERIES-CONNECTED SOURCE SUBSTRATE AND DRAIN SUBSTRATE POWER MOSFETS - A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate. | 2015-05-28 |
20150145037 | HIGH DENSITY TRENCH-BASED POWER MOSFETS WITH SELF-ALIGNED ACTIVE CONTACTS AND METHOD FOR MAKING SUCH DEVICES - Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T | 2015-05-28 |
20150145038 | SUPER JUNCTION SEMICONDUCTOR DEVICE HAVING COLUMNAR SUPER JUNCTION REGIONS - A super junction semiconductor device includes a semiconductor portion with a first surface and a second surface parallel to the first surface. The semiconductor portion includes a doped layer of a first conductivity type formed at least in a cell area. The super junction semiconductor device further includes columnar first super junction regions of a second, opposite conductivity type extending in a direction perpendicular to the first surface and separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A distance between the first super junction regions and the second surface does not exceed 30 μm. | 2015-05-28 |
20150145039 | SEMICONDUCTOR DEVICE HAVING DRAIN SIDE CONTACT THROUGH BURIED OXIDE - A semiconductor device configured to provide high heat dissipation and improve breakdown voltage comprises a substrate, a buried oxide layer over the substrate, a buried n+ region in the substrate below the buried oxide layer, and an epitaxial layer over the buried oxide layer. The epitaxial layer comprises a p-well, an n-well, and a drift region between the p-well and the n-well. The semiconductor device also comprises a source contact, a first electrode electrically connecting the source contact to the p-well, and a gate over a portion of the p-well and a portion of the drift region. The semiconductor device further comprises a drain contact, and a second electrode extending from the drain contact through the n-well and through the buried oxide layer to the buried n+ region. The second electrode electrically connects the drain contact to the n-well and to the buried n+ region. | 2015-05-28 |
20150145040 | METAL OXIDE SEMICONDUCTOR AND METHOD OF MAKING - A drain extended metal oxide semiconductor (MOS) includes a substrate having a semiconductor. A gate is located on the semiconductor, a source is located on the semiconductor and on one side of the gate, and a drain is located on the semiconductor and on another side of said gate. The MOS includes least one first finger having a first finger drain component located adjacent the drain, the first finger drain component has a silicide layer. At least one second finger has a second finger drain component located adjacent the drain, the second finger drain component has less silicide than the first finger drain component. | 2015-05-28 |
20150145041 | SUBSTRATE LOCAL INTERCONNECT INTEGRATION WITH FINFETS - A substrate local interconnect structure and method is disclosed. A buried conductor is formed in the insulator region or on the semiconductor substrate. The buried conductor may be formed by metal deposition, doped silicon regions, or silciding a region of the substrate. Metal sidewall portions connect transistor contacts to the buried conductor to form interconnections without the use of middle-of-line (MOL) metallization and via layers. | 2015-05-28 |
20150145042 | TRANSISTORS HAVING MULTIPLE LATERAL CHANNEL DIMENSIONS - Fin field effect transistors or semiconductor nanowire field effect transistors having different lateral channel dimensions can be formed by providing multiple disposable gate structures, removing one type of disposable gate structures while masking at least another type of disposable gate structures, thinning physically exposed semiconductor material portions by oxidation and an oxide etch, repeatedly performing the thinning process for any additional type of disposable gate structures, and filling gate cavities with replacement gate structures. Field effect transistors having different lateral channel dimensions can provide different threshold voltages and other device characteristics to provide a variety of field effect transistors on a same semiconductor substrate. | 2015-05-28 |
20150145043 | RF SOI SWITCH WITH BACKSIDE CAVITY AND THE METHOD TO FORM IT - An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved. | 2015-05-28 |
20150145044 | Floating Body Transistor Constructions, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays. | 2015-05-28 |
20150145045 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer. | 2015-05-28 |
20150145046 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes formation of a buried ground layer contact plug, which thence connects buried ground layer electrically to source region, thereby enhancing control capabilities of a semiconductor device over threshold voltages, suppressing short-channel effects and improving device performance; whereas no independent contact is required to build for the buried ground layer, which thence saves device area and simplifies manufacturing process accordingly. | 2015-05-28 |
20150145047 | IMPLEMENTING BURIED FET UTILIZING DRAIN OF FINFET AS GATE OF BURIED FET - A method and circuit for implementing an enhanced transistor topology with a buried field effect transistor (FET) utilizing the drain of a FinFET as the gate of the new buried FET and a design structure on which the subject circuit resides are provided. A drain area of the fin area of a FinFET over a buried dielectric layer provides both the drain of the FinFET as well as the gate node of a second field effect transistor. This second field effect transistor is buried in the carrier semiconductor substrate under the buried dielectric layer. | 2015-05-28 |
20150145048 | STRUCTURE AND METHOD FOR FORMING CMOS WITH NFET AND PFET HAVING DIFFERENT CHANNEL MATERIALS - Embodiments of the present invention provide an improved structure and method for forming CMOS field effect transistors. In embodiments, silicon germanium (SiGe) is formed on a PFET side of a semiconductor structure, while silicon is disposed on an NFET side of a semiconductor structure. A narrow isolation region is formed between the PFET and NFET. The NFET fins are comprised of silicon and the PFET fins are comprised of silicon germanium. | 2015-05-28 |
20150145049 | COMPLEMENTARY FET INJECTION FOR A FLOATING BODY CELL - The present invention relates to a floating body memory cell comprising: a first MOS transistor and a second MOS transistor, wherein at least the second MOS transistor has a floating body; and wherein the first and second MOS transistors are configured such that charges can be moved to/from the floating body of the second MOS transistor via the first MOS transistor. | 2015-05-28 |
20150145050 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer. | 2015-05-28 |
20150145051 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer. | 2015-05-28 |
20150145052 | Circuit and Method for Improving ESD Tolerance and Switching Speed - Embodiments of systems, methods, and apparatus for improving ESD tolerance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on semiconductor-on-insulator and silicon-on-sapphire substrates. Embodiments provide an improved FET structure having an accumulated charge sink (ACS) circuit, fast switching times, and improved ESD tolerance. | 2015-05-28 |
20150145053 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH TSV BUMPS - A semiconductor integrated circuit is provided. In the semiconductor integrated circuit, each of ESD protection circuitries is disposed between two of TSV bumps arrayed in a matrix, the two being arranged adjacent to each other. First main power lines are disposed to overlap P-channel ESD protection elements. Second main power lines are disposed to overlap N-channel ESD protection elements. The first and second main power lines are arranged orthogonally to each other. | 2015-05-28 |
20150145054 | TRANSISTOR AND METHOD FOR FORMING THE SAME - Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate is provided, having a dummy gate structure including a dummy gate dielectric layer on the substrate and a dummy gate layer on the dummy gate dielectric layer. A dielectric layer is formed on the substrate and on sidewall surfaces of the dummy gate structure. A top surface of the dielectric layer is leveled with a top surface of the dummy gate structure. A barrier layer is formed on the dielectric layer for protecting the dielectric layer. The dummy gate layer and the dummy gate dielectric layer are removed, to form an opening in the dielectric layer without reducing a thickness of the dielectric layer. A gate dielectric layer is formed on sidewall surfaces and a bottom surface of the opening. A gate layer is formed on the gate dielectric layer to fill the opening. | 2015-05-28 |
20150145055 | HIGH VOLTAGE DEVICES AND METHOD OF MANUFACTURING THE SAME - Disclosed is a high voltage device including a substrate structure having a high voltage transistor and a lower wiring connected to the high voltage transistor, a linker structure having a supplemental insulation pattern on the substrate structure and an interconnecting linker penetrating through the supplemental insulation pattern and connected to the lower wiring, an insulation interlayer pattern on the supplemental insulation pattern, and an upper wiring structure penetrating through insulation interlayer pattern and connected to the interconnecting linker. The thickness of the inter-metal dielectric layer between the upper and the lower wirings is increased to thereby improve the insulation characteristics of the inter-metal dielectric layer. As a result, the breakdown voltage and the current leakage characteristics of the high voltage device are improved. | 2015-05-28 |
20150145056 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern. | 2015-05-28 |
20150145057 | INTEGRATED MULTIPLE GATE LENGTH SEMICONDUCTOR DEVICE INCLUDING SELF-ALIGNED CONTACTS - A multi-channel semiconductor device includes a first and second gate channels formed in a semiconductor substrate. The first gate channel has a first length and the second gate channel has a second length greater than the first length. A gate dielectric layer is formed in the first and second gate channels. A first plurality of work function metal layers is formed on the gate dielectric layer of the first gate channel. A second plurality of work function metal layers is formed on the gate dielectric layer of the second gate channel. A barrier layer is formed on each of the first and second plurality of work function metal layers, and the gate dielectric layer. The multi-channel semiconductor device further includes metal gate stacks formed on of the barrier layer such that the barrier layer is interposed between the metal gate stacks and the gate dielectric layer. | 2015-05-28 |
20150145058 | TRANSISTOR WITH DEEP NWELL IMPLANTED THROUGH THE GATE - A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions. | 2015-05-28 |
20150145059 | METHODS OF FORMING AN E-FUSE FOR AN INTEGRATED CIRCUIT PRODUCT AND THE RESULTING INTEGRATED CIRCUIT PRODUCT - An integrated circuit product is disclosed that includes a resistor body and an e-fuse body positioned on a contact level dielectric material, wherein the resistor body and the e-fuse body are made of the same conductive material, a first plurality of conductive contact structures are coupled to the resistor body, conductive anode and cathode structures are conductively coupled to the e-fuse body, wherein the first plurality of conductive contact structures and the conductive anode and cathode structures are made of the same materials. | 2015-05-28 |
20150145060 | LOW RESISTANCE CONTACTS WITHOUT SHORTING - Devices and methods of forming a device are disclosed. A substrate prepared with at least a first transistor and a second transistor is provided. Each of the first and second transistors includes a gate disposed on the substrate between first and second contact regions in the substrate. A silicide block layer is formed on the substrate and is patterned to expose portions of the first and second contact regions. Silicide contacts are formed in the exposed first and second contact regions. The silicide contacts are displaced from sides of the gates of the first and second transistors. A contact dielectric layer is formed and contacts are formed in the contact dielectric layer. The contacts are in communication with the silicide contacts in the contact regions. | 2015-05-28 |
20150145061 | NOVEL CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME - A device includes first and second spaced-apart active regions positioned in a semiconducting substrate, an isolation region positioned between and separating the first and second spaced-apart active regions, and a layer of gate insulation material positioned on the first active region. A first conductive line feature extends continuously from the first active region and across the isolation region to the second active region, wherein the first conductive line feature includes a first portion that is positioned directly above the layer of gate insulation material positioned on the first active region and a second portion that conductively contacts the second active region. | 2015-05-28 |
20150145062 | VARIABLE LENGTH MULTI-CHANNEL REPLACEMENT METAL GATE INCLUDING SILICON HARD MASK - A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks. | 2015-05-28 |
20150145063 | FIELD EFFECT TRANSISTORS WITH VARYING THRESHOLD VOLTAGES - A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device. | 2015-05-28 |
20150145064 | FinFET HAVING SUPPRESSED LEAKAGE CURRENT - A FinFET device which includes: a semiconductor substrate; a three dimensional fin oriented perpendicularly to the semiconductor substrate; a local trench isolation between the three dimensional fin and an adjacent three dimensional fin; a nitride layer on the local trench isolation; a gate stack wrapped around a central portion of the three dimensional fin and extending through the nitride layer; sidewall spacers adjacent to the gate stack and indirectly in contact with the nitride layer, two ends of the three dimensional fin extending from the sidewall spacers, a first end being for the source of the FET device and a second end being for a drain of the FET device; and an epitaxial layer covering each end of the three dimensional fin and being on the nitride layer. Also disclosed is a method of fabricating a FinFET device. | 2015-05-28 |
20150145065 | finFET Isolation by Selective Cyclic Etch - Etching interleaved structures of semiconductor material forming fins of finFETs and local isolation material interposed between the fins is performed alternately and cyclically by alternating etchants cyclically such as by alternating gases during reactive ion etching. Etchants are preferably alternated when one of the semiconductor material and the local isolation material protrudes above the other by a predetermined distance. Since protruding surfaces are etched more rapidly than recessed surfaces, the overall etching process is accelerated and completed in less time such that erosion of other materials to which the etchants are less than optimally selective is reduced and allow improved etching of trenches for improved isolation structures to be formed. | 2015-05-28 |
20150145066 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING - A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided. | 2015-05-28 |
20150145067 | FIN STRUCTURE - A fin structure includes a substrate and a fin disposed on a top surface of the substrate. The fin has a height. An epitaxial structure surrounds the fin and the epitaxial structure has a top point which is the farthest point on the epitaxial structure away from the top surface of the substrate. There is a distance between the top point and the top surface of the substrate. A rational number of the distance to the height is not less than 7. | 2015-05-28 |
20150145068 | STRUCTURE OF FinFETs - The present invention relates to a method for fabricating FinFETs and the structure thereof. The present invention uses an additional mask to define regions forming semiconductor fins having high semiconductor-fin height. By making use of multiple etching processes of the insulating layer, structures with differences in the height of semiconductor fins are achieved. The method can be combined with current process for semiconductor-based FinFETs for overcoming effectively the problem of electron-channel-width quantization effect as well as improving the performance of FinFETs. | 2015-05-28 |
20150145069 | SILICON GERMANIUM FINFET FORMATION - Methods for fabricating a fin in a fin field effect transistor (FinFET), include exposing a single crystal fin structure coupled to a substrate of the FinFET. The single crystal fin structure is of a first material. The method further includes implanting a second material into the exposed single crystal fin structure at a first temperature. The first temperature reduces amorphization of the single crystal fin structure. The implanted single crystal fin structure comprises at least 20% of the first material. The method also includes annealing the implanted fin structure at a second temperature. The second temperature reduces crystal defects in the implanted fin structure to form the fin. | 2015-05-28 |
20150145070 | MERGING LITHOGRAPHY PROCESSES FOR GATE PATTERNING - Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate length or a second CPP with a second process. The second CPP is smaller than the single pattern lithographic limit. The second gate length is different than the first gate length. | 2015-05-28 |
20150145071 | METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure. | 2015-05-28 |
20150145072 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A MOS transistor includes a pair of impurity regions formed in a substrate as spaced apart from each other, and a gate electrode formed on a region of the substrate located between the pair of impurity regions. Each of the impurity regions is formed of a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is formed of at least one first sub-epitaxial layer and a respective second sub-epitaxial layer stacked on each first sub-epitaxial layer. An impurity concentration of the first sub-epitaxial layer is less than that of the second sub-epitaxial layer. | 2015-05-28 |
20150145073 | LOW-K DIELECTRIC SIDEWALL SPACER TREATMENT - Systems and methods are provided for fabricating a semiconductor structure including sidewall spacers. An example semiconductor structure includes: a gate structure, a first sidewall spacer, and a second sidewall spacer. The gate structure is formed over a substrate. The first sidewall spacer is adjacent to the gate structure, a top part of the first sidewall spacer including a first dielectric material, a bottom part of the first sidewall spacer including a second dielectric material. The second sidewall spacer is adjacent to the first sidewall spacer, the second sidewall spacer including a third dielectric material. | 2015-05-28 |
20150145074 | MEMS Device - A MEMS device includes a fixed electrode and a movable electrode arranged isolated and spaced from the fixed electrode by a distance. The movable electrode is suspended against the fixed electrode by one or more spacers including an insulating material, wherein the movable electrode is laterally affixed to the one or more spacers. | 2015-05-28 |
20150145075 | MEMS DEVICES UTILIZING A THICK METAL LAYER OF AN INTERCONNECT METAL FILM STACK - A MEMS device, such as an accelerometer or gyroscope, fabricated in interconnect metallization compatible with a CMOS microelectronic device. In embodiments, a proof mass has a first body region utilizing a thick metal layer that is separated from a thin metal layer. The thick metal layer has a film thickness that is significantly greater than that of the thin metal layer for increased mass. The proof mass further includes a first sensing structure comprising the thin metal layer, but lacking the thick metal layer for small feature sizes and increased capacitive coupling to a surrounding fame that includes a second sensing structure comprising the thin metal layer, but also lacking the thick metal layer. In further embodiments, the frame is released and includes regions with the thick metal layer to better match film stress-induced static deflection of the proof mass. | 2015-05-28 |
20150145076 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - There is provided a semiconductor package including: an application specific integrated circuit (ASIC) chip including a first bump ball and a second bump ball formed inwardly of the first bump ball; a micro electro mechanical system (MEMS) sensor electrically connected to the second bump ball; a lead frame electrically connected to the first bump ball and including a through hole formed therein; and a molded part covering the ASIC chip, the MEMS sensor, and the lead frame, wherein the ASIC chip is disposed above the lead frame. | 2015-05-28 |
20150145077 | METHOD OF STACKING A PLURALITY OF DIES TO FORM A STACKED SEMICONDUCTOR DEVICE, AND STACKED SEMICONDUCTOR DEVICE - A method of stacking a plurality of first dies to a respective plurality of second dies, each one of the first dies having a surface including a surface coupling region which is substantially flat, each one of the second dies having a respective surface including a respective surface coupling region which is substantially flat, the method comprising the steps of: forming, by means of a screen printing technique, an adhesive layer on the first dies at the respective surface coupling regions; and arranging the surface coupling region of each second die in direct physical contact with a respective adhesive layer of a respective first die among said plurality of first dies. | 2015-05-28 |
20150145078 | Semiconductor Package with Air Gap - A semiconductor package includes a semiconductor die having a first main side and a second main side opposite the first main side, the first main side having an inner region surrounded by a periphery region. The semiconductor package further includes a film covering the semiconductor die and adhered to the periphery region of the first main side of the semiconductor die. The film has a curved surface so that the inner region of the first main side of the semiconductor die is spaced apart from the film by an air gap. Electrical conductors are attached at a first end to pads at the periphery region of the first main side of the semiconductor die. A corresponding method of manufacture is also provided. | 2015-05-28 |
20150145079 | Semiconductor Devices and Methods of Fabrication Thereof - In one embodiment, a method of manufacturing a semiconductor device includes oxidizing a substrate to form local oxide regions that extend above a top surface of the substrate. A membrane layer is formed over the local oxide regions and the top surface of the substrate. A portion of the substrate under the membrane layer is removed. The local oxide regions under the membrane layer is removed. | 2015-05-28 |
20150145080 | MEMORY ELEMENT AND MEMORY DEVICE - There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, and in regard to the insulating layer and the other side layer with which the memory layer comes into contact at a side opposite to the insulating layer, at least an interface that comes into contact with the memory layer is formed of an oxide film. | 2015-05-28 |
20150145081 | MAGNETIC MEMORY DEVICES HAVING A UNIFORM PERPENDICULAR NONMAGNETIC RICH ANTISOTROPY ENHANCED PATTERN - Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration. | 2015-05-28 |
20150145082 | BACKSIDE-ILLUMINATED PHOTODETECTOR STRUCTURE AND METHOD OF MAKING THE SAME - A backside-illuminated photodetector structure comprising a first reflecting region, a second reflecting region and a semiconductor region. The semiconductor region is between the first reflecting region and the second reflecting region. The semiconductor region comprises a first doped region and a second doped region. | 2015-05-28 |
20150145083 | Structure Of Dielectric Grid For A Semiconductor Device - An image sensor device and a method for manufacturing the image sensor device are provided. An image sensor device includes a pixel region and a non-pixel region in a substrate. In the pixel region there is a plurality of sensor elements. The non-pixel region is adjacent to the pixel region and has no sensor element. Dielectric grids are disposed in the pixel region with a first dielectric trench between two adjacent dielectric grids. The first dielectric trench aligns to a respective sensor element. Second dielectric trenches are disposed in the non-pixel region. | 2015-05-28 |
20150145084 | Diffraction Grating with Multiple Periodic Widths - An integrated circuit includes a substrate, a plurality of photo detectors formed in the substrate, and a diffraction grating having multiple sections disposed over the plurality of photo detectors. Each section of the diffraction grating has a respective periodic width for a respective target wavelength. The diffraction grating has at least two different target wavelengths. The diffraction grating is interlaced with filters. The filters in each section of the diffraction grating are configured to pass a respective electromagnetic wave with the respective target wavelength. | 2015-05-28 |
20150145085 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor includes a substrate including a pixel array region and a logic region where a surface of the pixel array region is higher than a surface of the logic region, and a light shielding pattern formed over the substrate of the logic region and having a surface on substantially the same plane as a surface of the substrate. | 2015-05-28 |
20150145086 | OPTICAL COMMUNICATION DEVICE, RECEPTION APPARATUS, TRANSMISSION APPARATUS, AND TRANSMISSION AND RECEPTION SYSTEM - An optical communication device, reception apparatus, transmission apparatus and transmission and reception system are disclosed. The optical communication device includes a drive circuit substrate. A first through via extends through the drive circuit substrate and is configured to electrically connect an optical element disposed on a first surface side of the drive circuit substrate to a drive circuit disposed on a second surface side of the drive circuit substrate. A positioning element is attached to an interposer substrate and is configured to align optical axes of a first lens that is attached to a lens substrate and that faces a second lens that is disposed on the first surface side of the drive circuit substrate. A second through via extends through the interposer substrate and electrically connects the drive circuit to a signal processing circuit disposed on a signal processing substrate positioned above the interposer substrate. | 2015-05-28 |
20150145087 | MANUFACTURING METHOD FOR PHOTOELECTRIC CONVERSION APPARATUS AND PHOTOELECTRIC CONVERSION APPARATUS - A manufacturing method for a photoelectric conversion apparatus in which a microlens is arranged for multiple electric charge accumulation regions formed on a semiconductor substrate, includes forming a first impurity region of a first conductive type on the semiconductor substrate; and forming a second impurity region of a second conductive type that is opposite the first conductive type in a part of the first impurity region to isolate the first impurity region into multiple regions such that each of the multiple electric charge accumulation regions includes isolated first impurity regions. | 2015-05-28 |
20150145088 | IMAGE SENSOR AND FABRICATING METHOD THEREOF - A method of fabricating an image sensor is provided. The method may include preparing a substrate with first to third pixel regions, coating a first color filter layer on the substrate, sequentially forming a first sacrificial layer and a first protection layer to cover the first color filter layer, forming a first photoresist pattern on the first protection layer to be overlapped with the first pixel region, performing a first dry etching process using the first photoresist pattern as an etch mask to the first sacrificial layer and the first protection layer to form a first color filter, a first sacrificial pattern, and a first protection pattern sequentially stacked on the first pixel region, and selectively removing the first sacrificial pattern to separate the first protection pattern from the first color filter. | 2015-05-28 |
20150145089 | SOLID-STATE IMAGE SENSOR, METHOD OF MANUFACTURING THE SAME AND CAMERA - An image sensor includes a semiconductor layer having first and second faces, and a wiring structure arranged on a side of the first face, wherein photoelectric converters are arranged in the semiconductor layer and light is incident on the second face. The wiring structure includes reflection portions having reflection regions and arranged for at least some of the photoelectric converters, absorbing portions arranged around the reflection regions, an insulator portion arranged to surround the absorbing portions, and an interlayer insulating film arranged between the first face and a group of the reflection portions, the light absorbing portions, and the insulator portion, and a reflectance of the light absorbing portions is smaller than a reflectance of the reflection regions, and a light transmittance of the light absorbing portions is smaller than a light transmittance of the insulator portion. | 2015-05-28 |
20150145090 | SYSTEM AND METHOD FOR REDUCING DARK CURRENT DRIFT IN A PHOTODIODE BASED ELECTRON DETECTOR - A sensing element that may include (a) a PIN diode that may include an anode that is coupled to an anode contact; a cathode that is coupled to a cathode contact; a semiconductor portion that has a sensing region; and an insulator that is positioned between the cathode contact and the anode contact; and (b) a shielding element. The insulator, the cathode contact and the anode contact are positioned between the shielding element and the semiconductor portion. The shielding element is shaped and positioned to facilitate radiation to impinge onto the sensing region of the semiconductor portion while at least partially shielding the insulator from electrons that are emitted from the sensing region. | 2015-05-28 |
20150145091 | Single-Band and Dual-Band Infrared Detectors - Bias-switchable dual-band infrared detectors and methods of manufacturing such detectors are provided. The infrared detectors are based on a back-to-back heterojunction diode design, where the detector structure consists of, sequentially, a top contact layer, a unipolar hole barrier layer, an absorber layer, a unipolar electron barrier, a second absorber, a second unipolar hole barrier, and a bottom contact layer. In addition, by substantially reducing the width of one of the absorber layers, a single-band infrared detector can also be formed. | 2015-05-28 |
20150145092 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a photoelectric conversion element, a first isolation insulating film, and a current blocking region. The first isolation insulating film is formed around the photoelectric conversion element. The current blocking region is formed in a region between the photoelectric conversion element and the first isolation insulating film. The current blocking region includes an impurity diffusion layer, and a defect extension preventing layer disposed in contact with the impurity diffusion layer to form a twin with the impurity diffusion layer. The defect extension preventing layer has a different crystal structure from that of the impurity diffusion layer. At least a part of the current blocking region is disposed in contact with the first isolation insulating film. | 2015-05-28 |
20150145093 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - An image sensor includes a substrate having a front side and a back side, an insulating structure containing circuits on the front side of the substrate, contact holes extending through the substrate to the circuits, respectively, and a plurality of pads disposed on the backside of the substrate, electrically connected to the circuits along conductive paths extending through the contact holes, and located directly over the circuits, respectively. The image sensor is fabricated by a process in which a conductive layer is formed on the back side of the substrate and patterned to form the pads directly over the circuits. | 2015-05-28 |
20150145094 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads. | 2015-05-28 |
20150145095 | FREE-STANDING TWO-SIDED DEVICES - Devices having features deposited on two sides of a device substrate and methods for making the same. The devices are useful, for example, as the components in a macroelectronic system. In a preferred embodiment, the devices are photosensors having a plurality of electrodes patterned on a first side of the device and an electromagnetic interference filter patterned on a second side of the device. The method facilitates the fabrication of two-sided devices through the use of an immobilizing layer deposited on top of devices patterned on a first side of a device substrate; flipping the device substrate; processing the second side of the device substrate to produce patterned features on the second side of the device substrate; and releasing the devices having patterned elements on two sides of each device. | 2015-05-28 |
20150145096 | MECHANISMS FOR FORMING IMAGE-SENSOR DEVICE WITH EPITAXIAL ISOLATION FEATURE - Embodiments of mechanisms for forming an image-sensor device are provided. The image-sensor device includes a substrate having a front surface and a back surface. The image-sensor device also includes a radiation-sensing region formed in the substrate. The radiation-sensing region is operable to detect incident radiation that enters the substrate through the back surface. The radiation-sensing region further includes an epitaxial isolation feature formed in the substrate and adjacent to the radiation-sensing region. The radiation-sensing region and the epitaxial isolation feature have different doping polarities. | 2015-05-28 |
20150145097 | PHOTODIODE WITH A DARK CURRENT SUPPRESSION JUNCTION - This invention relates to field photodiodes based on PN junctions that suffer from dark current leakage. An NBL is added to prove a second PN junction with the anode. The second PN junction is reversed biased in order to remove dark current leakage. The present solution requires no additional masks or thin films steps relative to a conventional CMOS process flow. | 2015-05-28 |
20150145098 | MINIATURE PASSIVE STRUCTURES, HIGH FREQUENCY ELECTROSTATIC DISCHARGE PROTECTION NETWORKS, AND HIGH FREQUENCY ELECTROSTATIC DISCHARGE PROTECTION SCHEMES - According to various embodiments, a miniature passive structure for electrostatic discharge protection and input/output matching for a high frequency integrated circuit may be provided. The structure may include: either a transmission line or an inductor for providing at least one electrostatic discharge path; and a capacitor with a first end connected to the transmission line or inductor and a second end connected to ground. | 2015-05-28 |
20150145099 | Formation Of Semiconductor Device With Resistors - A semiconductor device includes a semiconductor substrate, trench isolations, a sacrificial layer, a first resist protect oxide (RPO) layer, a second RPO layer and a silicide layer. The semiconductor substrate has first portions and second portions which are alternately disposed, and each of the second portions includes a first resist region with a first resistance, a second resist region with a second resistance and a silicide region. The second resistance is greater than the first resistance. The trench isolations are in the first portions. The sacrificial layer is on the first resist region. The first RPO layer is on the sacrificial layer. The first RPO layer together with the sacrificial layer have a first thickness. The second RPO layer is on the second resist region, in which the second RPO layer has a second thickness smaller than the first thickness. The silicide layer is on the silicide region. | 2015-05-28 |
20150145100 | SEMICONDUCTOR ARRANGMENT WITH CAPACITOR - A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor. | 2015-05-28 |
20150145101 | SEMICONDUCTOR ARRANGEMENT WITH CAPACITOR - A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion. | 2015-05-28 |