21st week of 2011 patent applcation highlights part 16 |
Patent application number | Title | Published |
20110121302 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device with a simplified manufacturing process and improved electrical characteristics, along with a method of manufacturing the device, are disclosed. The device includes: a substrate having a display area and a non-display area; a thin film transistor (TFT) in the display area; a wiring portion in the non-display area; an intermediate layer electrically connected to the TFT and including an organic light emitting layer; and a counter electrode on the intermediate layer. The TFT includes an active layer, a gate electrode, and source/drain electrodes electrically connected to the active layer. The source/drain electrodes include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked. The wiring portion includes the same material as the first conductive layer. One of the source/drain electrodes is longer than the other, to function as a pixel electrode, and is electrically connected to the intermediate layer. | 2011-05-26 |
20110121303 | THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY HAVING THE SAME - A thin film transistor (TFT) substrate includes: a plurality of gate lines extending in one direction, a plurality of data lines extending in a direction intersecting the gate lines, a pixel electrode formed in a pixel region defined by an intersection of the gate line and the data line, and with one side of the pixel electrode overlapping a portion of one data line and another side of the pixel electrode overlapping a portion of another data line. The TFT further includes a storage electrode line having a storage electrode disposed in a central portion of the pixel region. | 2011-05-26 |
20110121304 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREFOR - An active matrix substrate of a display device of the present invention includes a glass substrate ( | 2011-05-26 |
20110121305 | THIN FILM TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME - A thin film transistor device and method of making the same are provided. The thin film transistor device includes a crystalline semiconductor layer and a patterned heavily doped semiconductor layer. The patterned heavily doped semiconductor layer includes a first heavily doped semiconductor layer and a second heavily doped semiconductor layer. The first heavily doped semiconductor layer covers a first side surface and a portion of a top surface of the crystalline semiconductor layer; the second heavily doped semiconductor layer covers a second side surface and a portion of the top surface of the crystalline semiconductor layer. | 2011-05-26 |
20110121306 | Systems and Methods for Non-Periodic Pulse Sequential Lateral Solidification - The disclosed systems and method for non-periodic pulse sequential lateral solidification relate to processing a thin film. The method for processing a thin film, while advancing a thin film in a selected direction, includes irradiating a first region of the thin film with a first laser pulse and a second laser pulse and irradiating a second region of the thin film with a third laser pulse and a fourth laser pulse, wherein the time interval between the first laser pulse and the second laser pulse is less than half the time interval between the first laser pulse and the third laser pulse. In some embodiments, each pulse provides a shaped beam and has a fluence that is sufficient to melt the thin film throughout its thickness to form molten zones that laterally crystallize upon cooling. In some embodiments, the first and second regions are adjacent to each other. In some embodiments, the first and second regions are spaced a distance apart. | 2011-05-26 |
20110121307 | LIQUID CRYSTAL DISPLAY DEVICE - It is an object of the present invention to provide a liquid crystal display device which has a wide viewing angle and less color-shift depending on an angle at which a display screen is seen and can display an image favorably recognized both outdoors in sunlight and dark indoors (or outdoors at night). The liquid crystal display device includes a first portion where display is performed by transmission of light and a second portion where display is performed by reflection of light. Further, a liquid crystal layer includes a liquid crystal molecule which rotates parallel to an electrode plane when a potential difference is generated between two electrodes of a liquid crystal element provided below the liquid crystal layer. | 2011-05-26 |
20110121308 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - Provided are a thin film transistor including a polycrystalline silicon layer having improved crystallinity by applying Joule heat to form stress gradient in a glass substrate that is disposed under an amorphous silicon layer from a surface to a predetermined depth of the glass substrate, thereby crystallizing the amorphous silicon layer into a polycrystalline silicon layer, and a method of fabricating the same. The film transistor includes a glass substrate having stress gradient from an upper surface to a predetermined depth, a semiconductor layer disposed on the glass substrate, and formed of a polycrystalline silicon layer crystallized by Joule heating, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes disposed on the interlayer insulating layer, and electrically connected to source and drain regions of the semiconductor layer. | 2011-05-26 |
20110121309 | METHOD OF FABRICATING POLYSILICON LAYER, THIN FILM TRANSISTOR, ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME - A method of fabricating an organic light emitting diode (OLED) display device having a thin film transistor including a polysilicon layer. The method of fabricating a polysilicon layer includes forming a buffer layer on a substrate, forming a metal catalyst layer on the buffer layer, diffusing a metal catalyst into the metal catalyst layer to the buffer layer, removing the metal catalyst layer, forming an amorphous silicon layer on the buffer layer, and annealing the substrate to crystallize the amorphous silicon layer into a polysilicon layer. The thin film transistor includes a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed above the substrate and on the semiconductor layer, a gate electrode disposed on the gate insulating layer, a source electrode and a drain electrode both electrically connected to the semiconductor layer, and a metal silicide disposed between the buffer layer and the semiconductor layer. | 2011-05-26 |
20110121310 | SOLID STATE LIGHTING DEVICES WITH SELECTED THERMAL EXPANSION AND/OR SURFACE CHARACTERISTICS, AND ASSOCIATED METHODS - Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an SSL (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (CTE), selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material of the interlayer structure based at least in part on the second material having a second material CTE less than the first material CTE. The method can further include forming the interlayer structure over the SSL formation structure by disposing (at least) a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material. The SSL formation structure supports an SSL emitter material, and the method further includes counteracting a force placed on the formation structure by the first material, by virtue of the difference between the second material CTE and the first material CTE. In other embodiments, the SSL formation structure can have an off-cut angle with a non-zero value of up to about 4.5 degrees. | 2011-05-26 |
20110121311 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - The present invention provides a method for manufacturing a semiconductor substrate including a low-resistance nitride layer laminated on a substrate, a method for manufacturing a semiconductor device, a semiconductor substrate, and a semiconductor device. A method for manufacturing a semiconductor substrate of the present invention includes the following steps: A nitride substrate having a principal surface and a back surface opposite to the principal surface is prepared. Vapor-phase ions are implanted into the back surface of the nitride substrate. The back surface of the nitride substrate is bonded to a dissimilar substrate to form a bonded substrate. The nitride substrate is partially separated from the bonded substrate to form a laminated substrate including the dissimilar substrate and a nitride layer. The laminated substrate is heat-treated at a temperature over 700° C. | 2011-05-26 |
20110121312 | OPTICAL SEMICONDUCTOR DEVICE HAVING UNEVEN SEMICONDUCTOR LAYER WITH NON-UNIFORM CARRIER DENSITY - In an optical semiconductor device including a first semiconductor layer of a first conductivity type, an active layer provided on the first semiconductor layer, a second semiconductor layer of a second conductivity type provided on the active layer, an insulating layer provided on a part of the second semiconductor layer, an uneven semiconductor layer of the second conductivity type provided on another part of the second semiconductor layer, and an electrode layer provided on the insulating layer and the uneven semiconductor layer, a density of carriers of the second conductivity type being larger at a tip portion of the uneven semiconductor layer than at a bottom portion of the uneven semiconductor layer. | 2011-05-26 |
20110121313 | Enhancement Mode III-Nitride Transistors with Single Gate Dielectric Structure - According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge. | 2011-05-26 |
20110121314 | ENHANCEMENT MODE GALLIUM NITRIDE POWER DEVICES - Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices. | 2011-05-26 |
20110121315 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A recess along a sidewall is formed in a pMOS region and an nMOS region. An SiC layer of which thickness is thicker than a depth of the recess is formed in the recess. A sidewall covering a part of the SiC layer is formed at both lateral sides of a gate electrode in the pMOS region. A recess is formed by selectively removing the SiC layer in the pMOS region. A side surface of the recess at the gate insulating film side is inclined so that the upper region of the side surface, the closer to the gate insulating film in a lateral direction at a region lower than the surface of the silicon substrate. An SiGe layer is formed in the recess in the pMOS region. | 2011-05-26 |
20110121316 | SILICON CARBIDE SEMICONDUCTOR DEVICE - The area of each body region is minimized, and the gate oxide films at the bottoms of the trenches are more effectively protected by depletion layers extending from the body regions. | 2011-05-26 |
20110121317 | ANNEALING METHOD FOR SEMICONDUCTOR DEVICE WITH SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE - In an atmosphere in which a silicon carbide (SiC) substrate implanted with impurities is annealed to activate the impurities, by setting a partial pressure of H | 2011-05-26 |
20110121318 | Silicon Carbide Switching Devices Including P-Type Channels - Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 1×10 | 2011-05-26 |
20110121319 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MAKING SAME - Light emitting devices and methods of fabricating the same are disclosed. The light emitting device includes a light emitting diode (LED) that emits blue or UV light and is attached to a semiconductor construction. The semiconductor construction includes a re-emitting semiconductor construction that includes at least one layer of a II-VI compound and converts at least a portion of the emitted blue or UV light to longer wavelength light. The semiconductor construction further includes an etch-stop construction that includes an AlInAs or a GaInAs compound. The etch-stop is capable of withstanding an etchant that is capable of etching InP. | 2011-05-26 |
20110121320 | WHITE ORGANIC LIGHT EMITTING DEVICE - A white organic light emitting device having a dual stack structure is disclosed, in which an electron transport layer adjacent to a blue light emitting layer includes an electron transport catalyst layer including metal to improve blue light emitting efficiency, and a greenish yellow dopant is used to improve white display efficiency, increase lifespan, and reduce power consumption. | 2011-05-26 |
20110121321 | SEMICONDUCTOR LIGHT EMITTING DEVICE MEMBER, METHOD FOR MANUFACTURING SUCH SEMICONDUCTOR LIGHT EMITTING DEVICE MEMBER AND SEMICONDUCTOR LIGHT EMITTING DEVICE USING SUCH SEMICONDUCTOR LIGHT EMITTING DEVICE MEMBER - A semiconductor light-emitting device member excellent in transparency, light resistance, and heat resistance and capable of sealing a semiconductor light-emitting device without causing cracks and peeling even after a long-time use is provided wherein the semiconductor light-emitting device member contains (A) in a solid state Si-nuclear magnetic resonance spectrum, at least one peak selected from (a) peaks whose peak top position is in an area of a chemical shift of −40 ppm to 0 ppm inclusive, and whose full width at half maximum is 0.3 ppm to 3.0 ppm inclusive, and (b) peaks whose peak top position is in an area of the chemical shift of −80 ppm or more and less than −40 ppm, and whose full width at half maximum is 0.3 ppm to 5.0 ppm inclusive, wherein (B) silicon content is 20 weight % or more and (C) silanol content is 0.1 weight % to 10 weight % inclusive. | 2011-05-26 |
20110121322 | Radiation-Emitting Thin-Film Semiconductor Chip and Method of Producing a Radiation-Emitting Thin Film Semiconductor Chip - A radiation-emitting thin film semiconductor chip is herein described which comprises a first region with a first active zone, a second region, separated laterally from the first region by a space, with a second active zone which extends parallel to the first active zone in a different plane, and a compensating layer, which is located in the second region at the level of the first active zone, the compensating layer not containing any semiconductor material. | 2011-05-26 |
20110121323 | Packaging device for matrix-arrayed semiconductor light-emitting elements of high power and high directivity - A packaging device for matrix-arrayed semiconductor light-emitting elements of high power and high directivity comprises a metal base, an array chip and a plurality of metal wires. The metal base is of highly heat conductive copper or aluminum, and a first electrode area and at least one second electrode area which are electrically isolated are disposed on the metal base. The array chip is disposed on the first electrode area, on which multiple matrix-arranged semiconductor light-emitting elements and at least one wire bond pad adjacent to the light-emitting elements are disposed. The light-emitting element is a VCSEL element, an HCSEL element or an RCLED element. The metal wires are connected between the wire bond pad and the second electrode area to transmit power signals. Between the bottom surface and the first electrode area is disposed a conductive adhesive to bond and facilitate electrical connection between the two. | 2011-05-26 |
20110121324 | LED Chip-Based Lighting Products And Methods Of Building - Light-emitting diode (LED) chip-based lighting products and methods of manufacture include patterning conductors on an inside surface of a panel, mounting a plurality of unpackaged LED chips directly on the conductors, and integrating the panel with support structure to form the lighting product such that an outside surface of the panel forms an exterior surface of the lighting product. A light emitting diode (LED)-based lighting product includes a panel having an inner surface and an outer surface, the outer surface forming an external surface of the lighting product, conductors patterned on the inner surface, and a plurality of LEDs mounted directly to the conductors. | 2011-05-26 |
20110121325 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - There are disclosed TFTs having improved reliability. An interlayer dielectric film forming the TFTs is made of a silicon nitride film. Other interlayer dielectric films are also made of silicon nitride. The stresses inside the silicon nitride films forming these interlayer dielectric films are set between −5×10 | 2011-05-26 |
20110121326 | Submount Having Reflective Cu-Ni-Ag Pads Formed Using Electroless Deposition - A submount for an LED has relatively large copper pads formed on its top surface using an electroless process so that no electrical bias circuitry is required for the submount. The copper pads are then coated with nickel using an electroless process. The nickel layer is then coated with silver using an electroless process, such as an immersion silver process. In one embodiment, the silver layer is less than one micron thick. The Ni layer prevents a reduction in reflectivity of the Ag after long periods of use while conducting the high current (300 mA to >1 amp) needed for high power LEDs. The silver layer surrounds at least 75% of the periphery of the LED die and extends at least 1 mm around the periphery of the die to reflect the LED light. | 2011-05-26 |
20110121327 | ORGANIC LIGHT-EMITTING DIODE THREE-DIMENSIONAL IMAGE DISPLAY DEVICE - Disclosed herein is an organic light-emitting diode three-dimensional image display device which comprises a first substrate, a cathode formed on the first substrate, an electron injection layer formed on the cathode, an electron transfer layer formed on the electron injection layer, an emission layer formed on the electron transfer layer, a hole transfer layer formed on the emission layer, a hole injection layer formed on the hole transfer layer, an anode formed on the hole injection layer, a wire grid polarizer formed on the anode and composed of a metal thin film pattern formed at a first angle and a method thin film pattern formed at a second angle perpendicular to the first angle, which are alternately arranged, and a second substrate arranged on the wire grid polarizer. | 2011-05-26 |
20110121328 | LED package structure - An LED package structure includes a heatsink slug, a positive-electrode frame, a negative-electrode frame, and an LED module electrically connected with the positive-electrode frame and the negative-electrode frame. The LED module includes a plurality of LED chips. The heatsink slug is provided, at its surface, with a plurality of cup-like recesses. The plural LED chips are each bonded, correspondingly, on a plane in the cup-like recess. Each of the LED chips is covered with a fluorescent colloidal layer having a curved and convex contour. As a result, a specific proportion for the color lights emitted from all the LED chips and from the fluorescent material in every direction of a space can be maintained, and that a better spatial color uniformity can be achieved. | 2011-05-26 |
20110121329 | AC LED Structure - An AC LED structure includes an insulating substrate, an LED set, a first metal layer and a second metal layer. The LED set has a first light-emitting diode and a second light-emitting diode, which are deposited on the insulating substrate and insulated from each other. The first metal layer and the second metal layer commonly have a first profile and serve to electrically connect the first light-emitting diode and the second light-emitting diode in an inverse parallel connection. In virtue of the first metal layer and the second metal layer of the first profile deposited on the first light-emitting diode and the second light-emitting diode, the LED set is allowed to be connected in series or in parallel with another LED set according to practical needs, so as to be able to endure high current density or high voltage operation. | 2011-05-26 |
20110121330 | Gallium nitride light emitting devices and methods of manufacturing the same - A gallium nitride (GaN) light emitting device and a method of manufacturing the same are provided, the method including sequentially forming a buffer layer and a first nitride layer on a silicon substrate, and forming a plurality of patterns by dry etching the first nitride layer. Each pattern includes a pair of sidewalls facing each other. A reflective layer is deposited on the first nitride layer so that one sidewall of the pair is exposed by the reflective layer. An n-type nitride layer that covers the first nitride layer is formed by horizontally growing an n-type nitride from the exposed sidewall, and a GaN-based light emitting structure layer is formed on the n-type nitride layer. | 2011-05-26 |
20110121331 | WAVELENGTH CONVERTED SEMICONDUCTOR LIGHT EMITTING DEVICE - A device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. A luminescent material is positioned in a path of light emitted by the light emitting layer. A thermal coupling material is disposed in a transparent material. The thermal coupling material has a thermal conductivity greater than a thermal conductivity of the transparent material. The thermal coupling material is positioned to dissipate heat from the luminescent material. | 2011-05-26 |
20110121332 | III-V LIGHT EMITTING DEVICE WITH THIN N-TYPE REGION - A device includes a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. A transparent, conductive non-III-nitride material is disposed in direct contact with the n-type region. A total thickness of semiconductor material between the light emitting layer and the transparent, conductive non-III-nitride material is less than one micron. | 2011-05-26 |
20110121333 | Solid State Light Emitting Apparatus with Thermal Management Structures and Methods of Manufacturing - Provided are apparatus and methods corresponding to a solid state light emitting element. Such methods include mounting, to a thermally conductive component, a solid state light emitting element that includes first and second electrical connection points that are configured to be conductively engaged on a first side of a circuit structure. The solid state light emitting element is electrically insulated from the thermally conductive component to provide that electrical connections are arranged on the first side of the circuit structure and heat is conducted to a second side of the circuit structure that is opposite the first side of the circuit structure. | 2011-05-26 |
20110121334 | SEMICONDUCTOR LIGHT-EMITTING DEVICES - A semiconductor light-emitting device includes a substrate having an upper surface and a plurality of bumps positioned on the upper surface, a first conductive type semiconductor layer positioned on the substrate, a light-emitting structure positioned on the first conductive type semiconductor layer, and a second conductive type semiconductor layer positioned on the light-emitting structure. In one embodiment of the present disclosure, each of the bumps has a top plane substantially parallel to the upper surface, the first conductive type semiconductor layer has a plurality of protrusions each facing a portion of the substrate between the bumps, and the protrusions are spaced apart from the bumps. | 2011-05-26 |
20110121335 | LIGHT EMITTING MODULE AND MANUFACTURING METHOD THEREOF - Provided are a light emitting module and a manufacturing method thereof, the light emitting module having improved heat radiation properties and improved adhesion between a sealing resin for sealing a light emitting element and other members. A light emitting module | 2011-05-26 |
20110121336 | Arrangement Comprising at Least one Optoelectronics Semiconductor Component - The invention relates to an arrangement comprising at least one optoelectronic semiconductor component ( | 2011-05-26 |
20110121337 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - The present invention provides a nitride semiconductor light-emitting device capable of preventing shortening of the device lifetime due to increase in the driving voltage of the device and internal heat generation, and also providing uniform laser characteristics, even if the device has a ridge stripe structure. On a GaN substrate | 2011-05-26 |
20110121338 | FLUORO GROUP-CONTAINING COMPOUND, FLUORO GROUP-CONTAINING POLYMER, ORGANIC LIGHT EMITTING DEVICE INCLUDING THE POLYMER, AND METHOD OF MANUFACTURING THE DEVICE - A fluoro group-containing compound, a fluoro group-containing polymer, an organic light emitting device including the polymer, and a method of manufacturing the organic light emitting device are provided. | 2011-05-26 |
20110121339 | LIGHT-EMITTING DIODE MODULE AND MANUFACTURING METHOD THEREOF - A light-emitting diode (LED) module includes a substrate, an LED, a first encapsulation element and a second light-pervious encapsulation element. The substrate has a first surface, a second surface, a circuit layer and an opening, wherein the opening penetrates through the first surface and the second surface, and the circuit layer includes at least one first conductive contact disposed on the first surface. The LED is disposed in the opening and is electrically connected to the first conductive contact. The first encapsulation element and the second light-pervious encapsulation element are respectively disposed on the first surface and the second surface, for encapsulating the LED and the first conductive contact. The aforementioned LED module may output light from the back of the LED, thereby improving the light output efficiency of the LED module. A manufacturing method of the aforementioned LED module is also herein disclosed. | 2011-05-26 |
20110121340 | LIGHT EMITTING DEVICE PACKAGE - Disclosed is a light emitting device package. The light emitting device package includes a package body, a light emitting device installed in a cavity of the package body, an encapsulation layer to seal the light emitting device, and an electrode connected to the light emitting device. The package body includes a material having thermal conductivity lower than thermal conductivity of a material constituting the encapsulation layer. | 2011-05-26 |
20110121341 | LIGHT EMITTING APPARATUS - Provided is a light emitting apparatus. The light emitting apparatus includes a substrate; a light emitting device on the substrate; a fluorescent layer formed on the substrate and the light emitting device to surround the light emitting device; an encapsulant resin layer formed on the substrate and the fluorescent layer to surround the fluorescent layer; and a lens disposed on the light emitting device and supported by the substrate, wherein the lens includes a lens body having a first recess formed at a center of a top surface of the lens body and a second recess formed at a center of a bottom surface of the lens body, and a lens supporter provided at the bottom surface of the lens body to support the lens body such that the lens body is spaced apart from the substrate. | 2011-05-26 |
20110121342 | ORGANIC LIGHT EMITTING DIODE LIGHTING APPARATUS - An organic light emitting diode lighting apparatus includes: a substrate; a semi-transmissive resonance layer formed on the substrate and including multilayer films having different refractive indexes; a first electrode formed on the semi-transmissive resonance layer; a first emission layer formed on the first electrode; a second emission layer formed on the first emission layer and emitting light of a different color from that emitted by the first emission layer; and a second electrode formed on the second emission layer. | 2011-05-26 |
20110121343 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, a second electrode layer under the second conductive semiconductor layer, and a transmissive conductive layer at least one part between the second conductive semiconductor layer and the second electrode layer. | 2011-05-26 |
20110121344 | COLOR CORRECTION FOR WAFER LEVEL WHITE LEDs - A method for fabricating a plurality of LED chips comprises providing a plurality of LEDs and forming a plurality of spacers each of which is on at least one of the LEDs. Coating the LEDs with a conversion material, each of the spacers reducing the amount of conversion material over its one of the LEDs. This reduction causes the plurality of LED chips to emit a wavelength of light in response to an electrical signal that is within a standard deviation of a target wavelength. LEDs, LED chips and LED chip wafers are fabricated using the method according to the present invention. One embodiment of an LED chip wafer according to the present invention comprises a plurality of LEDs on a wafer and a plurality of a spacers, each of which is on a respective one of the LEDs. A conversion material at least partially covers the LEDs and spacers, with at least some light from the LEDs passing through the conversion material and is converted. The spacers cause the LED chips to emit light having a wavelength within a standard deviation compared to the similar LED chips without the spacers where at least some of the LED chips emit light a wavelength of light outside the standard deviation. | 2011-05-26 |
20110121345 | POWER SURFACE MOUNT LIGHT EMITTING DIE PACKAGE - A light emitting die package is provided which includes a metal substrate having a first surface and a first conductive lead on the first surface. The first conductive lead is insulated from the substrate by an insulating film. The first conductive lead forms a mounting pad for mounting a light emitting device. The package includes a metal lead electrically connected to the first conductive lead and extending away from the first surface. | 2011-05-26 |
20110121346 | LIGHT-EMITTING ELEMENT AND ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE - Provided is a light-emitting element in the structure and configuration of causing no possibility of a short circuit between first and second electrodes even if there is any foreign substance or a protrusion on the first electrode. Such a light-emitting element is configured to include, in order, a first electrode | 2011-05-26 |
20110121347 | SYSTEMS AND METHODS FOR MANAGING HEAT FROM AN LED - Light-emitting devices and particularly light-emitting device assemblies that include light-emitting diodes (LEDs) as light sources are described. The methods and systems of at least some of the embodiments described herein increase the removal of thermal energy generated by the light-emitting devices. | 2011-05-26 |
20110121348 | SEMICONDUCTOR LIGHT-EMITTING DEVICES - A semiconductor light-emitting device includes a substrate having an upper surface and a plurality of bumps positioned on the upper surface in a periodic manner, a first conductive type semiconductor layer positioned on the substrate, a light-emitting structure positioned on the first conductive type semiconductor layer, and a second conductive type semiconductor layer positioned on the light-emitting structure. The first conductive type semiconductor layer includes a plurality of protrusions each facing a portion of the substrate between the bumps, the protrusions are positioned in a ring manner at a peripheral region of the first conductive type semiconductor layer, and the protrusions are spaced apart from the bumps. | 2011-05-26 |
20110121349 | LIGHT-EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light-emitting diode (LED) and manufacturing method thereof are disclosed. The LED includes a transparent substrate, a plurality of transparent conductive layers, a plurality of metal circuits, and a LED chip. The LED chip is suitable for emitting a light and a portion of the light emits toward the transparent substrate. The manufacturing method of LED includes the following steps. First, a transparent conductive layer is formed on the transparent substrate. Next, a conductive pattern is fromed by etching transparent conductive layer. The intersection metal circuit is formed by disposing the metal on a portion of the transparent conductive layer. Finally, the LED chip is disposed on the metal circuit so tat the LED chip is electrically connected to the metal circuit. | 2011-05-26 |
20110121350 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an organic light-emitting display apparatus contemplates preparing a first substrate, preparing a second substrate, forming a first sealant and a second sealant on the second substrate, the first sealant having a height different from a height of the second sealant, injecting a filling material into a space surrounded by the first sealant and the second sealant, adhering the first substrate to the second substrate, and radiating an energy beam onto at least one of the first sealant and the second sealant. | 2011-05-26 |
20110121351 | Organic light emitting diode device and method of manufacturing the same - An organic light emitting diode (OLED) device and a method of manufacturing the same, the OLED device including a substrate, a first electrode on the substrate, a buffer layer on the first electrode, an emission layer on the buffer layer, and a second electrode on the emission layer, wherein the buffer layer includes a transparent conductive oxide, and a metal or metal oxide having a work function lower than a work function of the transparent conductive oxide. | 2011-05-26 |
20110121352 | Organic Photoelectric Device - An organic photoelectric device includes a substrate, a base electrode, an electrode terminal, a roof electrode, an organic functional layer, and a self-supporting cover member. The base electrode is configured above a first surface of the substrate, and the electrode terminal is accessible from above the first surface of the substrate. The self-supporting cover member serves to encapsulate the organic functional layer, which is arranged between the substrate and the self-supporting cover member, the self-supporting cover member being formed from conductive material or being coated with a conductive material on a side facing the substrate. The conductive material is locally coupled, in an electrically conductive manner, to the base electrode or the roof electrode at laterally distributed locations, and is further coupled to the electrode terminal in an electrically conductive manner. | 2011-05-26 |
20110121353 | OPTOELECTRONIC ARCHITECTURE HAVING COMPOUND CONDUCTING SUBSTRATE - Optoelectronic device modules, arrays optoelectronic device modules and methods for fabricating optoelectronic device modules are disclosed. The device modules are made using a starting substrate having an insulator layer sandwiched between a bottom electrode made of a flexible bulk conductor and a conductive back plane. An active layer is disposed between the bottom electrode and a transparent conducting layer. One or more electrical contacts between the transparent conducting layer and the back plane are formed through the transparent conducting layer, the active layer, the flexible bulk conductor and the insulating layer. The electrical contacts are electrically isolated from the active layer, the bottom electrode and the insulating layer. | 2011-05-26 |
20110121354 | Method for Producing an Electronic Component and Electronic Component - A method for producing an electronic component comprising barrier layers for the encapsulation of the component comprises, in particular, the following steps: providing a substrate ( | 2011-05-26 |
20110121355 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD OF MANUFACTURING THE SAME - An organic light emitting diode (OLED) display and a method of manufacturing the same are provided. The OLED display includes: a substrate main body; an OLED that is formed on the substrate main body; a hydrophilic polymer layer that is formed on the substrate main body to cover the OLED and that includes a hydrophilic surface having an angle of contact within a range of larger than 0° and smaller than or equal to 50°; and an inorganic protective layer that is formed on the hydrophilic surface of the hydrophilic polymer layer. | 2011-05-26 |
20110121356 | METHOD FOR ENCAPSULATING AN ELECTRONIC ARRANGEMENT - Method for encapsulating an electronic arrangement against permeates wherein a pressure-sensitive adhesive mass based on butylene block copolymers is applied to and around the areas of the electronic arrangement to be encapsulated. | 2011-05-26 |
20110121357 | LED with Improved Injection Efficiency - A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device. | 2011-05-26 |
20110121358 | P-TYPE LAYER FOR A III-NITRIDE LIGHT EMITTING DEVICE - A semiconductor structure includes a light emitting region, a p-type region disposed on a first side of the light emitting region, and an n-type region disposed on a second side of the light emitting region. At least 10% of a thickness of the semiconductor structure on the first side of the light emitting region comprises indium. Some examples of such a semiconductor light emitting device may be formed by growing an n-type region, growing a p-type region, and growing a light emitting layer disposed between the n-type region and the p-type region. The difference in temperature between the growth temperature of a part of the n-type region and the growth temperature of a part of the p-type region is at least 140° C. | 2011-05-26 |
20110121359 | Multi-Layer Reconfigurable Switches - Embodiments of the present invention are directed to reconfigurable two-terminal electronic switch devices ( | 2011-05-26 |
20110121360 | METHOD OF PRODUCING A SEMICONDUCTOR DEVICE WITH AN ALUMINUM OR ALUMINUM ALLOY ELECTRODE - A semiconductor device includes a silicon substrate having a first major surface and a second major surface opposite to the first major surface, a drift layer and a collector layer formed in sequence in the silicon substrate from the first major surface, and an aluminum silicon film formed on the second major surface. The drift layer is of a first conductivity type, and is surrounded by a semiconductor layer of a second conductivity type including the collector layer. | 2011-05-26 |
20110121361 | DEVICE FOR ELECTROSTATIC DISCHARGE AND METHOD OF MANUFACTURING THEREOF - The present invention provides a device for electrostatic discharge and the method of manufacturing thereof. P-well is formed on the substrate, and a first N | 2011-05-26 |
20110121362 | RF Circuits Including Transistors Having Strained Material Layers - Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance. | 2011-05-26 |
20110121363 | STRAINED ULTRA-THIN SOI TRANSISTOR FORMED BY REPLACEMENT GATE - A semiconductor structure is described. The structure includes a transistor formed in a semiconductor substrate, the semiconductor substrate having a semiconductor-on-insulator (SOI) layer; a channel associated with the transistor and formed on a first portion of the SOI layer; and a source/drain region associated with the transistor and formed in a second portion of the SOI layer and in a recess at each end of the channel, where the second portion of the SOI layer is substantially thicker than the first portion of the SOI layer. A method of fabricating the semiconductor structure is also described. The method includes forming a dummy gate in a semiconductor substrate; performing a SIMOX process to form a SOI layer such that a first portion of the SOI layer under the dummy gate is substantially thinner than a second portion of the SOI layer; forming a source/drain extension in the SOI layer; and recessing the source/drain extension for forming a source/drain region; epitaxially growing the second portion of the SOI layer; forming an insulating layer over the epitaxial growth; removing the dummy gate for forming a gate opening; and filling the gate opening with a gate dielectric material and a gate conductor material. | 2011-05-26 |
20110121364 | HETEROJUNCTION BIPOLAR TRANSISTOR - According to an example embodiment, a heterostructure bipolar transistor, HBT, includes shallow trench isolation, STI, structures around a buried collector drift region in contact with a buried collector. A gate stack including a gate oxide and a gate is deposited and etched to define a base window over the buried collector drift region and overlapping the STI structures. The etching process is continued to selectively etch the buried collector drift region between the STI structures to form a base well. SiGeC may be selectively deposited to form epitaxial silicon-germanium in the base well in contact with the buried collector drift region and poly silicon-germanium on the side walls of the base well and base window. Spacers are then formed as well as an emitter. | 2011-05-26 |
20110121365 | HYBRID INTEGRATED CIRCUIT DEVICE, AND METHOD FOR FABRICATING THE SAME, AND ELECTRONIC DEVICE - A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals. | 2011-05-26 |
20110121366 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device includes a first single crystal silicon layer including first transistors, a first alignment mark, and at least one metal layer overlying the first single crystal silicon layer for interconnecting the first transistors; a second layer overlying the at least one metal layer, wherein the second layer includes a plurality of second transistors; and a connection path connecting the first transistors and the second transistors and including at least a first strip, a second strip, and a through via connecting the first strip and the second strip, wherein the second strip is substantially orthogonal to the first strip and wherein the through via is substantially away from both ends of the first strip and both ends of the second strip. | 2011-05-26 |
20110121367 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including transistors B on an output side of a current mirror, arranged uniformly in a surrounding area of a transistor A on an input side of the current mirror. The transistors B are arranged at equal distances, adjacently to the transistor A, on both sides of the transistor A. | 2011-05-26 |
20110121368 | Gas-sensitive semiconductor device - A gas-sensitive semiconductor device having a semiconductive channel ( | 2011-05-26 |
20110121369 | INTEGRATED CIRCUIT INCLUDING FINFET RF SWITCH ANGLED RELATIVE TO PLANAR MOSFET AND RELATED DESIGN STRUCTURE - An integrated circuit (IC) includes a fin field effect transistor (FinFET) radio frequency (RF) switch; and a planar complementary metal-oxide semiconductor field effect transistor (MOSFET). The planar MOSFET has a channel on a <100> wafer plane and the FinFET RF switch has a channel on a <100> fin plane. The FinFET RF switch and the planar MOSFET can be oriented at approximately 45° with respect to one another. | 2011-05-26 |
20110121370 | EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES - A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material. | 2011-05-26 |
20110121371 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC APPARATUS - A solid-state imaging device includes a plurality of photoelectric conversion units configured to receive light and generate signal charge, the plurality of photoelectric conversion units being provided in such a manner as to correspond to a plurality of pixels in a pixel area of a semiconductor substrate; and pixel transistors configured to output the signal charge generated by the photoelectric conversion units as electrical signals. Each of the pixel transistors includes at least a transfer transistor that transfers the signal charge generated in the photoelectric conversion unit to a floating diffusion corresponding to a drain. A gate electrode of the transfer transistor is formed in such a manner as to extend with a gate insulating film in between from a channel formed area to a portion where the photoelectric conversion unit has been formed on the surface of the semiconductor substrate. | 2011-05-26 |
20110121372 | EDRAM Architecture - A process for manufacturing an eDRAM device comprises fabricating semiconductor features on a semiconductor substrate, the semiconductor substrate including a DRAM area and logic area. The process also includes fabricating a first conductive layer in the DRAM area and in the logic area, the first conductive layer in communication with a first group of the semiconductor features. After fabricating the first conductive layer, a storage component is fabricated in communication with a second group of the semiconductor features within the DRAM area. | 2011-05-26 |
20110121373 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern. The patterned second gate structure may include at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure. | 2011-05-26 |
20110121374 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A vertical transistor comprises a semiconductor region, a pillar region formed on the semiconductor region, a gate insulating film formed so as to cover a side surface of the pillar region, a gate electrode formed on the gate insulating film, a first impurity diffusion region formed in an upper portion of the pillar region, and a second impurity diffusion region formed in the semiconductor region so as to surround the pillar region. The first impurity diffusion region is formed so as to be spaced from the side surface of the pillar region. | 2011-05-26 |
20110121375 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a semiconductor substrate having a transistor formed thereon; a multi-layered interconnect formed on the semiconductor substrate, and having a plurality of interconnect layers, respectively composed of an interconnect and an insulating film, stacked therein; and a capacitance element having a lower electrode (lower electrode film), a capacitor insulating film, and an upper electrode (upper electrode film), all of which being embedded in the multi-layered interconnect, so as to compose a memory element, and further includes at least one layer of damascene-structured copper interconnect (second-layer interconnect) formed between the capacitance element and the transistor; the upper surface of one of the interconnects (second-layer interconnect) and the lower surface of the capacitance element are aligned nearly in the same plane; and at least one layer of copper interconnect (plate line interconnect) is formed over the capacitance element. | 2011-05-26 |
20110121376 | Dielectric Layers and Memory Cells Including Metal-Doped Alumina - A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process. | 2011-05-26 |
20110121377 | RESERVOIR CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a reservoir capacitor of a semiconductor device where a first peripheral circuit region and a second peripheral circuit region are defined comprises: forming a gate on an upper portion of a semiconductor substrate of the second peripheral circuit region; forming an interlayer insulating film on the entire upper portion of the semiconductor substrate including the gate; etching the interlayer insulating film of the second peripheral circuit region to form a bit line contact hole; forming a bit line material and a sacrificial film on the upper portion of the interlayer insulating film including the bit line contact hole; and etching the sacrificial film of the first peripheral circuit region to form a trench that exposes the bit line material. | 2011-05-26 |
20110121378 | ZrXHfYSn1-X-YO2 FILMS AS HIGH K GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO | 2011-05-26 |
20110121379 | Three-Terminal Single Poly NMOS Non-Volatile Memory Cell With Shorter Program/Erase Times - A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. | 2011-05-26 |
20110121380 | NON-VOLATILE ELECTRICALLY ALTERABLE MEMORY CELL FOR STORING MULTIPLE DATA - A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns. | 2011-05-26 |
20110121381 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer. | 2011-05-26 |
20110121382 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - Over the top of a semiconductor substrate, a lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed. Over the top of the semiconductor substrate, a memory gate electrode adjacent to the lamination pattern is formed. Between the control gate electrode and the semiconductor substrate, a third insulation film for gate insulation film is formed. Between the memory gate electrode and the semiconductor substrate, and between the lamination pattern and the memory gate electrode, a fourth insulation film including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film is formed. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded. | 2011-05-26 |
20110121383 | MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES - A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration. | 2011-05-26 |
20110121384 | TRENCH-GATE SEMICONDUCTOR DEVICE - A trench-gate semiconductor device is disclosed, in which the p-layer ( | 2011-05-26 |
20110121385 | RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) STRUCTURES AND METHOD OF FORMATION - Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure. | 2011-05-26 |
20110121386 | Trench MOSFET with trenched floating gates as termination - A trench MOSFET comprising a plurality of transistor cells with a plurality of wide trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. Each body region between two adjacent said trenched floating gates has floating voltage. | 2011-05-26 |
20110121387 | INTEGRATED GUARDED SCHOTTKY DIODE COMPATIBLE WITH TRENCH-GATE DMOS, STRUCTURE AND METHOD - A plurality of transistor cells, each of which can include a transistor P-body region and a Schottky diode, wherein the transistor P-body region can be formed below the Schottky diode to provide a semiconductor device having desirable electrical characteristics. | 2011-05-26 |
20110121388 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a device isolation structure, a recess channel structure, a first lower gate conductive layer conformal to the recess channel structure and defining a recess, a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, and a second lower gate conductive layer over the first lower gate conductive layer and the holding layer. The holding layer is configured to hold a shift of the seam occurring in the recess channel structure. | 2011-05-26 |
20110121389 | LDMOS HAVING A FIELD PLATE - Laterally diffused metal oxide semiconductor transistor for a radio frequency-power: amplifier comprising a drain finger ( | 2011-05-26 |
20110121390 | Semiconductor substrates and manufacturing methods of the same - Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is disposed on the insulation region. The substrate region and the floating body region are formed of materials having identical characteristics. The method of manufacturing the semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region. | 2011-05-26 |
20110121391 | METHOD FOR MANUFACTURING A SUSPENDED MEMBRANE AND DUAL-GATE MOS TRANSISTOR - A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring. | 2011-05-26 |
20110121392 | PROCESSES AND APPARATUS HAVING A SEMICONDUCTOR FIN - A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to recede to a greater degree in the lateral direction than the vertical direction. The process may include second etching the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded hard mask. The thinned semiconductor fin may have a characteristic dimension that can exceed photolithography limits. Electronic devices may include the thinned semiconductor fin as part of a field effect transistor. | 2011-05-26 |
20110121393 | FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION - A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode. | 2011-05-26 |
20110121394 | CHIP AND ELECTROSTATIC DISCHARGE PROTECTION DEVICE THEREOF - An ESD protection device is provided, which includes a P-type doped region, an N-type doped region, a first P+ doped region, a first N+ doped region, a second N+ doped region and a third N+ doped region. The N-type doped region is located in the P-type doped region. The first P+ doped region connected to a pad is located in the N-type doped region. A part of the first N+ doped region is located in the N-type doped region and the residue part thereof is located in the P-type doped region. The second and the third N+ doped regions are located in the P-type doped region and outside the N-type doped region, and are respectively electrically connected to a first power rail and a second power rail. In addition, the second N+ doped region is located between the first and the third N+ doped regions. | 2011-05-26 |
20110121395 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR HIGH VOLTAGE OPERATION - The present disclosure provides ESD protection devices that can effectively cope with electrostatic stress of microchips for high voltage operation. The ESD protection device includes protection device includes: a high voltage P well formed in a semiconductor substrate, an N-drift region formed in the high voltage P well, an anode N+ diffusion region and an anode P+ diffusion region formed in the N-drift region, a buffer N+ diffusion region formed in the N-drift region and separated a predetermined distant from the anode N+ diffusion region, a buffer N-ballistic region surrounding the buffer N+ diffusion region, an anode N-ballistic region surrounding the anode N+ diffusion region and the anode P+ diffusion region, a cathode N+ diffusion region and a cathode P+ diffusion region formed in the high voltage P well and separated a predetermined distance from the N-drift region, a MOSFET gate disposed on the semiconductor substrate between the cathode N+ diffusion region and the N-drift region, and a capacitor electrode disposed on the semiconductor substrate between the anode N+ diffusion region and the buffer N+ diffusion region. | 2011-05-26 |
20110121396 | PILLAR-TYPE FIELD EFFECT TRANSISTOR HAVING LOW LEAKAGE CURRENT - A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes: a semiconductor body, source and drain formed in a semiconductor pillar; a gate insulating layer formed on a surface of the semiconductor body; a gate electrode formed on a surface of the gate insulating layer. The gate electrode includes a first gate electrode and a second gate electrode being electrically connected with the first gate electrode. The first gate electrode has a work function higher than that of the second gate electrode. Accordingly, the gate induced drain leakage (GIDL) can be reduced, so that an off-state leakage current can be greatly reduced. | 2011-05-26 |
20110121397 | METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS - Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries. | 2011-05-26 |
20110121398 | TECHNIQUE FOR ENHANCING DOPANT PROFILE AND CHANNEL CONDUCTIVITY BY MILLISECOND ANNEAL PROCESSES - During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained in the adjacent channel region. | 2011-05-26 |
20110121399 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE HAVING METAL GATE STACK STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A complementary metal oxide semiconductor (CMOS) device including: a semiconductor substrate including a NMOS region and a PMOS region; a NMOS metal gate stack structure on the NMOS region and including a first high dielectric layer, a first barrier metal gate on the first high dielectric layer and including a metal oxide nitride layer, and a first metal gate on the first barrier metal gate; and a PMOS metal gate stack structure on the PMOS region and including a second high dielectric layer, a second barrier metal gate on the second high dielectric layer and including a metal oxide nitride layer, and a second metal gate on the second barrier metal gate. | 2011-05-26 |
20110121400 | METHOD FOR MAKING COMPLEMENTARY P AND N MOSFET TRANSISTORS, ELECTRONIC DEVICE INCLUDING SUCH TRANSISTORS, AND PROCESSOR INCLUDING AT LEAST ONE SUCH DEVICE - This method for making complementary p and n MOSFET transistors with Schottky source and drain electrodes controlled by a gate electrode, comprising: making source and drain electrodes from a single silicide for both p and n transistors; segregating first impurities from groups II and III of the periodic table at the interface between the silicide and the channel of the p transistor, the complementary n transistor being masked; and segregating second impurities from groups V and VI of the periodic table, at the interface between the silicide and the channel of the n transistor, and the complementary p transistor being masked. | 2011-05-26 |
20110121401 | Gate Effective-Workfunction Modification for CMOS - CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed. | 2011-05-26 |