21st week of 2013 patent applcation highlights part 52 |
Patent application number | Title | Published |
20130130385 | SURFACE MARKERS AND USES THEREOF FOR RAPID STABLE CELL LINE GENERATION AND GENE AMPLIFICATION - The present invention provides methods of producing recombinant cells, methods of large scale production of a gene expression product (such as protein), and methods of establishing a stable cell line using the surface markers. Also provided are expression vectors encoding the surface markers and cells comprising the expression vectors. Further provided are gene expression products (such as proteins) and cells obtained using methods described herein, as well as kits useful for carrying out methods described herein. | 2013-05-23 |
20130130386 | MODIFIED DENDRITIC CELLS HAVING ENHANCED SURVIVAL AND IMMUNOGENICITY AND RELATED COMPOSITIONS AND METHODS - Modified antigen presenting cells provided herein have improved lifespan and immunogenicity compared to unmodified antigen presenting cells, and are useful for immunotherapy. The modified antigen presenting cells express an altered protein kinase, referred to herein as “Akt.” The altered Akt associates with the cell membrane with greater frequency than unaltered Akt, and is referred to herein as “membrane-targeted Akt.” | 2013-05-23 |
20130130387 | METHOD FOR GENERATING INDUCED PLURIPOTENT STEM CELLS FROM KERATINOCYTES DERIVED FROM PLUCKED HAIR FOLLICLES - A method for generating induced pluripotent stem (iPS) cells from isolated hair follicles is disclosed. The method comprises:
| 2013-05-23 |
20130130388 | Methods of Modifying Eurakyotic Cells - A method for engineering and utilizing large DNA vectors to target, via homologous recombination, and modify, in any desirable fashion, endogenous genes and chromosomal loci in eukaryotic cells. These large DNA targeting vectors for eukaryotic cells, termed LTVECs, are derived from fragments of cloned genomic DNA larger than those typically used by other approaches intended to perform homologous targeting in eukaryotic cells. Also provided is a rapid and convenient method of detecting eukaryotic cells in which the LTVEC has correctly targeted and modified the desired endogenous gene(s) or chromosomal locus (loci) as well as the use of these cells to generate organisms bearing the genetic modification. | 2013-05-23 |
20130130389 | NOVEL PROMOTER FOR USE IN TRANSFORMATION OF ALGAE - The problem to be solved by the present invention is to provide a highly-efficient transformation technology, specifically, a highly-efficient promoter used for transforming algae, a vector comprising the promoter, and a method for transforming algae by using the vector. The promoter according to the present invention is characterized in comprising a polynucleotide constituting a non-coding region located upstream of a gene encoding a structural protein of a ClorDNA virus, and the like. | 2013-05-23 |
20130130390 | MODULAR CHEMISTRY ANALYZER - An automated chemistry analysis method is disclosed. In one general aspect, the method includes receiving a modular chemistry analysis test unit that includes one or more vessels for one or more reagents, and a machine-readable test specification coupled with the vessels. The method also includes defining a test that defines a test including a series of operations that employ the reagents for the vessels, and installing the chemistry analysis test unit in a first chemistry analyzer that includes one or more analysis tools and sequencing logic for sequencing instructions to be carried out by the analysis tools. The machine-readable test specification is automatically received from the chemistry analysis test module and stored for access by the sequencing logic to allow the sequencing logic to instruct the analysis tools to carry out the test defined by the test specification. | 2013-05-23 |
20130130391 | METHOD OF ANALYZING HEMOGLOBINS - An object of the present invention is to provide a method for analyzing hemoglobins which can accurately separate hemoglobins in a short time by liquid chromatography. | 2013-05-23 |
20130130392 | GOLD AND SILVER QUANTUM CLUSTERS IN MOLECULAR CONTAINERS AND METHODS FOR THEIR PREPARATION AND USE - A composition includes a quantum cluster of Ag | 2013-05-23 |
20130130393 | METHOD OF ANALYZING A PLURALITY OF FERROMAGNETIC PARTICLES - The invention relates to a method of analyzing a plurality of ferromagnetic particles (1). The method comprises the following steps:
| 2013-05-23 |
20130130394 | DEVICES AND METHODS FOR CONTROLLING ACTIN FILAMENTS GROWTH AND ORGANIZATION USING MICROPATTERNED NUCLEATION SITES - The present invention concerns devices and methods for controlling actin filaments growth and organization with micro patterned nucleation sites, their uses for studying actin network formation, for screening of drugs or for preparing complex structures. | 2013-05-23 |
20130130395 | AQUEOUS RADIATION PROTECTING FORMULATIONS AND METHODS FOR MAKING AND USING THEM - Medical devices are typically sterilized in processes used to manufacture such products and their sterilization by exposure to radiation is a common practice. Radiation has a number of advantages over other sterilization processes including a high penetrating ability, relatively low chemical reactivity, and instantaneous effects without the need to control temperature, pressure, vacuum, or humidity. Unfortunately, radiation sterilization can compromise the function of certain components of medical devices. For example, radiation sterilization can lead to loss of protein activity and/or lead to bleaching of various dye compounds. Embodiments of the invention provide methods and materials that can be used to protect medical devices from unwanted effects of radiation sterilization. | 2013-05-23 |
20130130396 | Detection of Nicotine Metabolites - The present invention relates to assays for detection of nicotine metabolites, in particular cotinine, in fluid samples and uses of these assays in quantification of smoking habits. The assays comprise contacting a body fluid sample with a cyanogen halide and a pyrazolone compound and detecting a change in light absorbance of the pyrazolone compound which is associated with the presence of nicotine metabolites. Also provided are assay kits including a cyanogen halide or cyanogen halide-precursor(s) and a pyrazolone compound. | 2013-05-23 |
20130130397 | COMPOSITIONS AND METHODS FOR SIMULTANEOUS DETECTION OF VOLATILE SULFUR COMPOUNDS AND POLYAMINES - Disclosed are compositions and methods useful for the rapid and facile simultaneous detection of malodorous bacterial metabolites in samples of expired breath and other fluids. The invention enables estimation, by simple visual inspection and comparison against standards, of the concentration of polyamines and volatile sulfur compounds in the micromolar to millimolar range. | 2013-05-23 |
20130130398 | SENSORS AND METHODS FOR DETECTING PEROXIDE BASED EXPLOSIVES - Methods, compositions, and systems for detecting explosives is disclosed and described. A sensor for detecting explosives can comprise a porous hydrophilic material modified with a titanium oxo compound having the following structure (I) where L is a ligand. Additionally, the porous hydrophilic material can be capable of detecting hydrogen peroxide vapor by complexing the titanium oxo compound and the hydrogen peroxide to provide a color change. | 2013-05-23 |
20130130399 | CO2 Indicator - A chemical indicator or ink, and methods for manufacture thereof, comprises at least one carbon dioxide-sensitive reactive dye which is capable of detecting changes in carbon dioxide concentration in a fluid under fluid and/or gas phase pressure of carbon dioxide above approximately (1) bar. The present chemical indicators or inks are useful in the monitoring of relatively high carbon dioxide pressure environments, such as in carbonated drinks. The present invention also relates to containers for holding a carbonated liquid, and closures therefore, comprising a carbon dioxide indicator or a carbon dioxide-sensitive ink, wherein the carbon dioxide indicator and/or the ink comprises at least one carbon dioxide-sensitive reactive dye which is capable of detecting changes in carbon dioxide concentration in a fluid under fluid and/or gas phase pressure of carbon dioxide above approximately (1) bar. | 2013-05-23 |
20130130400 | INCREASING THE USABLE DYNAMIC RANGE IN PHOTOMETRY - An optical device for determining the presence and/or concentration of analytes in a sample is presented. The optical device comprises a detector and a detection unit comprising optical path components. The detection unit has wavelength-dependent responsivity. The optical device further comprises a light source for emitting light of different respective usable wavelength ranges. The light is guidable through the optical path to the detector to generate baseline signals and response signals relative to the baseline signal indicative of the presence and/or concentration of analytes in the optical path. The intensity of the light reaching the detector is adjusted inverse to the wavelength-dependent responsivity with respect to at least two respective usable wavelength ranges so that a reduction of the ratio between the maximum baseline signal at one of the selected usable wavelength ranges and the minimum baseline signal at another of the selected usable wavelength ranges is obtained. | 2013-05-23 |
20130130401 | Biological Sample Pretreatment Method and Apparatus - A sample treatment apparatus is disclosed that allows a filtrate after reaction to be supplied to a solid phase extraction treatment without temporary collection. A necessary amount of a solid phase extracting agent is added to a solid phase extraction device for conditioning. An aqueous solution is added to the extracting agent and supernatants are discarded. A filter device is attached to an opening of the extraction and a sample is added into a filter reservoir. A hemolyzing agent is added to the sample, and they are stirred sufficiently to cause disruption of blood cells. A protein-denaturing solution is added to the mixture, and they stirred sufficiently to denature proteins contained in the sample. They are centrifuged to leave aggregate in the filter device, and the filtrate is supplied to the solid phase extracting agent through a filter unit without collecting the filtrate. | 2013-05-23 |
20130130402 | FLUORESCENT COMPOUNDS, COMPOSITIONS, AND METHODS FOR USING THE COMPOUNDS AND COMPOSITIONS - Low pKa fluorescent compounds, compositions that include the compounds, bioconjugates made from the compounds, and methods for making and using the compounds and bioconjugates. | 2013-05-23 |
20130130403 | Highly Sensitive System and Method for Analysis of Troponin - The invention provides methods, compositions, kits, and systems for the sensitive detection of cardiac troponin. Such methods, compositions, kits, and systems are useful in diagnosis, prognosis, and determination of methods of treatment in conditions that involve release of cardiac troponin. | 2013-05-23 |
20130130404 | SIGNAL AMPLIFICATION IN LATERAL FLOW AND RELATED IMMUNOASSAYS - The present invention provides methods, devices, compositions (e.g., capture complexes), and kits useful for enhancing the detection of antibodies in a test sample. The methods, devices, and compositions utilize detectable Fc-binding molecules such as Protein A, Protein G, and/or an Fc-specific antibody to amplify the signal of a detected antibody in immunoassays, such as lateral flow assays. | 2013-05-23 |
20130130405 | APPARATUS AND METHODS FOR SILICON OXIDE CVD RESIST PLANARIZATION - Embodiments of the present invention provide methods and apparatus for forming a patterned magnetic layer for use in magnetic media. According to embodiments of the present application, a silicon oxide layer formed by low temperature chemical vapor deposition is used to form a pattern in a hard mask layer, and the patterned hard mask is used to form a patterned magnetic layer by plasma ion implantation. | 2013-05-23 |
20130130406 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer. | 2013-05-23 |
20130130407 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a capacitor, the capacitor includes a lower electrode, which includes platinum, provided above a semiconductor substrate; a first ferroelectric film, which includes lead zirconate titanate added with La, provided on the lower electrode; a second ferroelectric film, which includes lead zirconate titanate added with La, Ca, and Sr, provided directly on the first ferroelectric film, the second ferroelectric film having a thickness smaller than that of the first ferroelectric film and includes amounts of Ca and Sr greater than amounts of Ca and Sr that may be present in the first ferroelectric film; and an upper electrode, which includes a conductive oxide, provided on the second ferroelectric film. | 2013-05-23 |
20130130408 | MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED DEVICE - In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape. | 2013-05-23 |
20130130409 | ETCH RATE DETECTION FOR REFLECTIVE MULTI-MATERIAL LAYERS ETCHING - A method and apparatus for etching a photomask substrate with enhanced process monitoring, for example, by providing for optical monitoring at different regions of the photomask to obtain desired etch rate or thickness loss is provided. In one embodiment, the method includes performing an etching process on a reflective multi-material layer that includes at least one molybdenum layer and one silicon layer through a patterned mask, directing radiation having a wavelength from about 170 nm and about 800 nm to an area of the multi-material layer uncovered by the patterned mask, collecting an optical signal reflected from the area uncovered by the patterned mask, analyzing a waveform obtained from the reflected optical signal, and determining a first endpoint of the etching process when an intensity of the reflected optical signal is between about 60 percent and about 90 percent less than an initial reflected optical signal. | 2013-05-23 |
20130130410 | METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING - A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask. | 2013-05-23 |
20130130411 | Interleaf for Leadframe Identification - A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets. The interleaf members include indicia that identifies the leadframes sheets. The stack of leadframe sheets is loaded onto an assembly machine. A first interleaf member is removed from the first leadframe sheet. The first leadframe sheet is transferred onto a mounting surface of the assembly machine. Semiconductor die are attached to leadframes on the first leadframe sheet. The method can include reading the indicia from the first interleaf member to determine a part number and lead finish for the first leadframe sheet, verifying the part number for the first leadframe sheet by comparing to a build list, and transferring the first leadframe sheet onto a mounting surface of the assembly machine only if the part number is verified. | 2013-05-23 |
20130130412 | LIGHT EMITTING DIODE MODULE WITH THREE PART COLOR MATCHING - A light emitting diode module is produced using at least one LED and at least two selectable components that form a light mixing chamber. First and second selectable components have first and second types of wavelength converting materials with different wavelength converting characteristics. The first and second wavelength converting characteristics alter the spectral power distribution of the light produced by the LED to produce light with a color point that is a predetermined tolerance from a predetermined color point. Moreover, a set of LED modules may be produced such that each LED module has the same color point within a predetermined tolerance. The LED module may be produced by pre-measuring the wavelength converting characteristics of the different components selecting components with wavelength converting characteristics that convert the spectral power distribution of the LED to a color point that is a predetermined tolerance from a predetermined color point. | 2013-05-23 |
20130130413 | APPARATUS AND METHOD FOR IN-SITU ENDPOINT DETECTION FOR SEMICONDUCTOR PROCESSING OPERATIONS - An endpoint detection method includes processing an outer surface of a substrate, directing an incident light beam through a window in an opaque metal body onto the surface being processed, receiving at a detector a reflected light beam from the substrate and generating a signal from the detector, and generating a signal based on the reflected light beam received at the detector, and detecting a processing endpoint. The signal is a time-varying cyclic signal that varies as the thickness of the layer varies over time, and detecting the processing endpoint includes detecting that a portion of a cycle of the cyclic signal has passed, the portion being less than a full cycle of the cyclic signal. | 2013-05-23 |
20130130414 | HIGH PRODUCTIVITY COMBINATORIAL WORKFLOW FOR PHOTORESIST STRIP APPLICATIONS - Electrical testing of metal oxide semiconductor (MOS) high-k capacitor structures is used to evaluate photoresist strip or cleaning chemicals using a combinatorial workflow. The electrical testing can be able to identify the damages on the high-k dielectrics, permitting a selection of photoresist strip chemicals to optimize the process conditions in the fabrication of semiconductor devices. The high productivity combinatorial technique can provide a compatibility evaluation of photoresist strip chemicals with high-k devices. | 2013-05-23 |
20130130415 | METHODS OF TESTING INTEGRATED CIRCUIT DEVICES USING FUSE ELEMENTS - Methods of fabricating integrated circuit devices utilize fuse elements to support sequential testing of vertically-integrated test elements during fabrication. These methods include forming a first test element, a first fuse and a first test pad electrically connected by the first fuse to the first test element, on a substrate. The first test element is tested by passing a first current between the first test element and first test pad and through the first fuse. The first fuse is then “cut” by increasing an impedance of the first fuse, which may include breaking the first fuse to create an electrical “open” (infinite impedance) or greatly increasing a resistance of the first fuse (e.g., by narrowing the fuse through electromigration). A second test element and a second test pad, which is electrically connected to the second test element and the first test pad, are then formed on the substrate. | 2013-05-23 |
20130130416 | METHOD OF FABRICATING A MICRO DEVICE TRANSFER HEAD - A micro device transfer head and head array are disclosed. In an embodiment, the micro device transfer head includes a base substrate, a mesa structure with sidewalls, an electrode formed over the mesa structure, and a dielectric layer covering the electrode. A voltage can be applied to the micro device transfer head and head array to pick up a micro device from a carrier substrate and release the micro device onto a receiving substrate. | 2013-05-23 |
20130130417 | MANUFACTURING METHOD OF A LIGHT-EMITTING DEVICE - A method for manufacturing a light-emitting device includes steps of: providing a substrate comprising an upper surface and a lower surface opposite to the upper surface; processing the upper surface to be an uneven surface; forming a light-emitting structure on the upper surface of the substrate; and forming a hole through the substrate by radiating a coherent laser beam to the lower surface of the substrate for a predetermined time; wherein the band gap energy of the coherent laser beam is higher than the band gap energy of the substrate thereby the substrate is etched away by the laser beam. | 2013-05-23 |
20130130418 | METHOD FOR PRODUCING LARGE LIGHTING WITH POWER LED - The present invention relates to a method for manufacturing large lighting which uses a power LED, such as for large LED lighting for street lamps, which incorporates a heat dissipation device that has the ability to dissipate heat with natural convection to maintain ambient temperature. The disclosed method is novel applied technology for producing a large LED lighting, such as for street lamps, which has a power LED device with a unique, rear heat dissipation capability. In addition to maximum thermal efficiency by heat dissipation, the present LED lighting system also increases luminous efficiency by providing high light emission with only a small quantity of LED power. | 2013-05-23 |
20130130419 | NIGHT VISION IMAGING SYSTEM (NVIS) COMPATIBLE LIGHT EMITTING DIODE - The present disclosure is directed to a LED assembly that is compatible for use with a night vision imaging system, Such LEDs may emit energy between 400 and 600 nm of the electromagnetic spectrum while limiting energy emissions between 600 and 1200 nanometers. Near infrared photochemistry is incorporated directly into the lens or encapsulant of an LED with an opaque package that limits transmission of visible and near infrared energy. | 2013-05-23 |
20130130420 | METHOD OF LASER LIFT-OFF FOR LEDS - A laser lift-off method for LEDs forms an elevation difference structure on a conversion substrate corresponding to one isolation zone of an epitaxial layer before epitaxy is formed on the conversion substrate to form the epitaxial layer. The elevation difference structure can release stress between the material interfaces, thus can reduce broken probability while lifting off the conversion substrate and epitaxial layer via laser and further improve production yield. | 2013-05-23 |
20130130421 | Method of Manufacturing Oxide Thin Film Transistor and Display Device - A method of manufacturing oxide thin film transistor and display device are provided. In the method of manufacturing an oxide thin film transistor, the method includes: forming an active layer of an oxide semiconductor on a substrate, and performing surface treatment with plasma for the active layer to permeate oxygen into the active layer. | 2013-05-23 |
20130130422 | FABRICATING METHOD OF LIGHT EMITTING DEVICE AND FORMING METHOD OF ORGANIC LAYER - A fabricating method of a light emitting device is provided. In the fabricating method, a substrate having a first electrode layer is provided. An organic film solution that includes an organic material, a solid medium, and a solvent is provided. The solid medium is capable of sublimation, and the organic material and the solid medium are mixed into the solvent. An organic film is formed on the first electrode layer by using the organic film solution. The solvent and the solid medium are removed to form an organic functional layer that has the organic material. A second electrode layer is formed on the organic functional layer. | 2013-05-23 |
20130130423 | Method of Making a Flexible Optoelectronic Device Having Inverted Electrode Structure - A flexible optoelectronic device having inverted electrode structure is disclosed. The flexible optoelectronic device having inverted electrode structure includes a flexible plastic substrate having a cathode structure, an n-type oxide semiconductor layer, an organic layer, and an anode. The n-type oxide semiconductor layer is disposed on the cathode structure. The organic layer is disposed on the n-type oxide semiconductor layer. The anode is electrically connected with the organic layer. | 2013-05-23 |
20130130424 | PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER - A method for separating a plurality of dies on a Micro-Electro-Mechanical System (MEMS) wafer comprising scribing a notch on a first side of the wafer between at least two of the plurality of dies on a first surface and depositing a metal on the first surface of the plurality of dies. The method further comprises scribing a second side of the wafer between at least two of the plurality of dies from a second surface thereof through the notch. The first side and second side are substantially parallel and opposite each other and the first surface and the second surface are substantially parallel and opposite each other. In a process in accordance with the present invention, a method to minimize chipping of the bonding portion of a MEMs device during sawing of the wafer is provided, which minimally affects the process steps associated with separating the die on a wafer. | 2013-05-23 |
20130130425 | Method and Machine for Producing a Semiconductor, of the Photovoltaic or Similar Electronic Component Type - The invention relates to a method for producing a semiconductor, of the photovoltaic cell type, or similar electronic components. According to the invention, at least one silicon wafer is cut from the cross-section of a silicon rod and, after doping, a substrate is assembled on either side of the silicon wafer and the latter is cut into two parts through the thickness of the silicon, so as to form two semiconductor units each comprising a substrate and a thin silicon film. | 2013-05-23 |
20130130426 | METHOD OF MANUFACTURING AN OPTICAL MEMBER HAVING STACKED HIGH AND LOW REFRACTIVE INDEX LAYERS - A method of making an optical member including high refractive index layers and low refractive index layers, which are each relatively thin as compared with an optical length, and disposed alternately in the lateral direction with respect to an optical axis. Each width of the high refractive index layers and the low refractive index layers is equal to or smaller than the wavelength order of incident light. | 2013-05-23 |
20130130427 | METHOD FOR INCREASING THE TRANSLUCENCY OF A SUBSTRATE - A method for increasing a translucency of a substrate is provided, whereby a scattering layer is deposited on the light exit side by means of chemical vapor deposition at atmospheric pressure using a flamer of a plasma, the scattering layer contains either zinc oxide or aluminum and/or aluminum oxide, more particularly aluminum-doped zinc oxide or silicon oxide. | 2013-05-23 |
20130130428 | METHOD OF MAKING A SPATIALLY SENSITIVE APPARATUS - A spectrometer for use with a desired wavelength range includes an array of filters. Each filter outputs at least two non-contiguous wavelength peaks within the desired wavelength range. The array of filters is spectrally diverse over the desired wavelength range, and each filter in the array of filters outputs a spectrum of a first resolution. An array of detectors has a detector for receiving an output of a corresponding filter. A processor receives signals from each detector, and outputs a reconstructed spectrum having a second resolution, the second resolution being higher than any of the first resolution of each filter. Filters and detectors may be arranged into a plurality of imaging units, each imaging unit including first and second filters and first and second photosensing regions. A processor receives signals from each imaging unit, and generates a reconstructed spatial image comprised of discrete spatial units corresponding to each imaging unit. | 2013-05-23 |
20130130429 | IMAGE SENSOR WITH IMPROVED COLOR CROSSTALK - An image sensor comprises a substrate of a first conductivity type. First and second pixels are arrayed over the substrate. A potential barrier is formed in a region of the substrate corresponding to the first pixel but not in a region of the substrate corresponding to the second pixel. The second pixel is responsive to a color having a wavelength longer than the color to which the first pixel is responsive. The potential barrier is doped with dopants by a high energy ion implantation dopants or by an ion implantation or diffusion during epitaxial growth of the P-type epitaxial layer. | 2013-05-23 |
20130130430 | SPATIALLY SELECTIVE LASER ANNEALING APPLICATIONS IN HIGH-EFFICIENCY SOLAR CELLS - Various laser processing schemes are disclosed for producing various types of hetero-junction emitter and homo-junction emitter solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero-junction solar cells. Laser ablation techniques are disclosed that leave the underlying silicon substantially undamaged. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, or other cleavage techniques such as ion implantation and heating, that are either planar or textured/three-dimensional. These techniques are highly suited to thin crystalline semiconductor, including thin crystalline silicon films. | 2013-05-23 |
20130130431 | Lattice Matchable Alloy for Solar Cells - An alloy composition for a subcell of a solar cell is provided that has a bandgap of at least 0.9 eV, namely, Ga | 2013-05-23 |
20130130432 | RAPID THERMAL PROCESSING SYSTEM AND SULFIDATION METHOD THEREOF - A rapid thermal processing system includes a rapid thermal processing furnace, a back electrode substrate, and a cover. The rapid thermal processing furnace includes a reaction chamber and a heating device. The heating device is capable of generating heat energy. The back electrode substrate is adapted to dispose in the reaction chamber and has a precursor layer and a selenium layer formed on the precursor layer. The cover is disposed at a position corresponding to the selenium layer on the back electrode substrate and has a sulfur in solid form formed thereon, so as to make the sulfur in solid form opposite to the selenium layer. After the sulfur in solid form absorbs the heat energy generated by the heating device, the sulfur in solid form reacts with the selenium layer and the precursor layer to form a photoelectric transducing layer. | 2013-05-23 |
20130130433 | METHOD AND APPARATUS PROVIDING SINGLE STEP VAPOR CHLORIDE TREATMENT AND PHOTOVOLTAIC MODULES - A method and apparatus are disclosed in which cadmium chloride is deposited on a cadmium telluride layer while simultaneously heat treating the cadmium telluride layer. | 2013-05-23 |
20130130434 | Method for Producing a Photovoltaic Element Comprising a Silicon Dioxide Layer - Production of a photovoltaic element, more particularly of a solar cell. In this case, an additional silicon dioxide layer is used, which is produced by UV irradiation with a wavelength of less than 200 nm and can improve the interface properties on the silicon and can help to reduce disturbances known by the expression “background plating”. | 2013-05-23 |
20130130435 | THICK FILM CONDUCTIVE COMPOSITION AND USE THEREOF - The invention relates to a thick film conductive composition comprising metal particles wherein the specific surface area of the silver particles measured by BET according to ISO 9277 is equal to or more than 1.8 m | 2013-05-23 |
20130130436 | DYE-SENSITIZED SOLAR CELL WITH HYBRID NANOSTRUCTURES AND METHOD FOR FABRICATING WORKING ELECTRODES THEREOF - A dye-sensitized solar cell with hybrid nanostructures comprises a negative-polarity conductive substrate, a metal oxide layer, a positive-polarity conductive substrate and an electrolyte. The metal oxide layer has a plurality of nanoparticles and a plurality of nanotubes. The metal oxide layer and the electrolyte are arranged between the negative-polarity conductive substrate and the positive-polarity conductive substrate. The nanoparticles increase contact area with dye and thus enhance power generation efficiency. The nanotubes increase carrier mobility and thus effectively transfer electricity to electrodes. The solar cell integrates the advantages of nanoparticles and nanotubes and offsets the disadvantages thereof to effectively enhance the photovoltaic conversion efficiency of dye-sensitized solar cells. | 2013-05-23 |
20130130437 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided. | 2013-05-23 |
20130130438 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers. | 2013-05-23 |
20130130439 | FORMED METALLIC HEAT SINK SUBSTRATE, CIRCUIT SYSTEM, AND FABRICATION METHODS - A thermally conductive substrate for suitable for use as a three dimensional heat sink for electrical device systems. The substrate comprises a base element with a cavity comprising a recessed device mounting site. Associated device systems include one or more devices arranged in the three dimensional heat sink which can be encapsulated into a device package and associated construction methodologies. | 2013-05-23 |
20130130440 | METHOD OF FABRICATING AND TRANSFERRING A MICRO DEVICE AND AN ARRAY OF MICRO DEVICES UTILIZING AN INTERMEDIATE ELECTRICALLY CONDUCTIVE BONDING LAYER - A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, an electrically insulating layer is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes. In an embodiment, an electrically conductive intermediate bonding layer is utilized during the formation and transfer of the micro devices to the receiving substrate. | 2013-05-23 |
20130130441 | CHIP-SCALE SEMICONDUCTOR DIE PACKAGING METHOD - A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die. | 2013-05-23 |
20130130442 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area. | 2013-05-23 |
20130130443 | METHOD FOR PACKAGING ULTRA-THIN CHIP WITH SOLDER BALL THERMO-COMPRESSION IN WAFER LEVEL PACKAGING PROCESS - The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip. | 2013-05-23 |
20130130444 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region. | 2013-05-23 |
20130130445 | ACTIVE AREA BONDING COMPATIBLE HIGH CURRENT STRUCTURES - A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer. | 2013-05-23 |
20130130446 | TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES - A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel. | 2013-05-23 |
20130130447 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - At least part of a semiconductor layer or a semiconductor substrate includes a semiconductor region having a large energy gap. The semiconductor region having a large energy gap is preferably formed from silicon carbide and is provided in a position at least overlapping with a gate electrode provided with an insulating layer between the semiconductor region and the gate electrode. By making a structure in which the semiconductor region is included in a channel formation region, a dielectric breakdown voltage is improved. | 2013-05-23 |
20130130448 | METHOD FOR FORMING AND CONTROLLING MOLECULAR LEVEL SiO2 INTERFACE LAYER - The present disclosure provides a method for forming and controlling a molecular level SiO | 2013-05-23 |
20130130449 | STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE - Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region. | 2013-05-23 |
20130130450 | LOW LEAKAGE CAPACITOR FOR ANALOG FLOATING-GATE INTEGRATED CIRCUITS - An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. | 2013-05-23 |
20130130451 | Semiconductor Device with Reliable High-Voltage Gate Oxide and Method of Manufacture Thereof - A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a substrate infused to create a neighboring wells, and N-well over which the capacitor will be formed, and P-well to be overlaid by the HV gate. The boron-barrier helps to reduce or eliminate the harmful effects of boron diffusion from the P-well during TEOS deposition of the gate oxide material. | 2013-05-23 |
20130130452 | MULTI-LEVEL CHARGE STORAGE TRANSISTORS AND ASSOCIATED METHODS - Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described. | 2013-05-23 |
20130130453 | Method for manufacturing semiconductor device with first and second gates over buried bit line - A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate. | 2013-05-23 |
20130130454 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer. | 2013-05-23 |
20130130455 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to a method of manufacturing a semiconductor device including a buried gate, after a recess is formed by etching a semiconductor substrate, since an etching back process is not performed on a gate electrode material buried within the recess, variability in the depth of the gate electrode material can be reduced. In addition, GIDL can be improved by a selective oxidation process and control of a thickness of a spacer and data retention time can be increased. | 2013-05-23 |
20130130456 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region. | 2013-05-23 |
20130130457 | SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced. | 2013-05-23 |
20130130458 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes forming a gate pattern on a semiconductor substrate, performing a C ion implantation process for suppressing diffusion of dopants in the semiconductor substrate, and performing a halo ion implantation process including P ions. Therefore, a hot carrier effect due to change of a dopant profile and degradation caused by GIDL can be improved. | 2013-05-23 |
20130130459 | MOS P-N JUNCTION DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance. | 2013-05-23 |
20130130460 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer. | 2013-05-23 |
20130130461 | EPITAXIAL PROCESS FOR FORMING SEMICONDUCTOR DEVICES - A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching step to define the pillars, an epitaxial silicon film is grown on the substrate between the pillars prior to forming recesses in the substrate for the source/drain regions of the transistor. The epitaxial silicon film compensates for substrate material that may be lost during formation of the gate electrode pillars, thereby producing source/drain recesses having a configuration amenable to be filled uniformly with silicon for later forming the source/drain regions in the substrate. | 2013-05-23 |
20130130462 | TUNABLE SEMICONDUCTOR DEVICE - Embodiments of the present invention include a method for forming a tunable semiconductor device. In one embodiment, the method comprises: forming a semiconductor substrate; patterning a first mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector; removing the first mask; patterning a second mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector; removing the second mask; and forming a single continuous collector above the second discontinuous subcollector. | 2013-05-23 |
20130130463 | MANUFACTURING METHOD OF CHARGING CAPACITY STRUCTURE - A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes. | 2013-05-23 |
20130130464 | PLASMA PROCESSING OF METAL OXIDE FILMS FOR RESISTIVE MEMORY DEVICE APPLICATIONS - In some embodiments, the present invention discloses plasma processing at interfaces of an ALD metal oxide film with top and bottom electrodes to improve the ReRAM device characteristics. The interface processing can comprise an oxygen inhibitor step with a bottom polysilicon electrode to prevent oxidation of the polysilicon layer, enhancing the electrical contact of the metal oxide film with the polysilicon electrode. The interface processing can comprise an oxygen enrichment step with a top metal electrode to increase the resistivity of the metal oxide layer, providing an integrated current limiter layer. | 2013-05-23 |
20130130465 | METHODS OF FORMING INTEGRATED CIRCUIT CAPACITORS HAVING COMPOSITE DIELECTRIC LAYERS THEREIN CONTAINING CRYSTALLIZATION INHIBITING REGIONS - Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers. | 2013-05-23 |
20130130466 | Methods of Forming Electrical Components and Memory Cells - Some embodiments include methods of forming electrical components. First and second exposed surface configurations are formed over a first structure, and material is then formed across the surface configurations. The material is sub-divided amongst two or more domains, with a first of the domains being induced by the first surface configuration, and with a second of the domains being induced by the second surface configuration. A second structure is then formed over the material. The first domains of the material are incorporated into electrical components. The second domains may be replaced with dielectric material to provide isolation between adjacent electrical components, or may be utilized as intervening regions between adjacent electrical components. | 2013-05-23 |
20130130467 | RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES - A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided. | 2013-05-23 |
20130130468 | Method For Fabricating Passive Devices For 3D Non-Volatile Memory - A method for fabricating passive devices such as resistors and capacitors for a 3D non-volatile memory device. In a peripheral area of a substrate, alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide are provided in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are formed above the stack. Contact structures are formed which extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel or serially by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. The passive device can be fabricated concurrently with a 3D memory array using common processing steps. | 2013-05-23 |
20130130469 | VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME - A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells can be arranged in parallel with a corresponding series of control gates. A select gate can also be disposed in series with the variable-resistance material memory cells. Writing/reading/erasing to a given variable-resistance material memory cell can include turning off the corresponding control gate, while turning on all other control gates. Various devices can include such a variable-resistance material memory array. | 2013-05-23 |
20130130470 | NONVOLATILE MEMORY ELEMENT AND PRODUCTION METHOD THEREOF AND STORAGE MEMORY ARRANGEMENT - A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form. | 2013-05-23 |
20130130471 | MANUFACTURING METHOD OF VERTICAL CHANNEL TRANSISTOR ARRAY - A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts. | 2013-05-23 |
20130130472 | SEMICONDUCTOR CHIPS HAVING GUARD RINGS AND METHODS OF FABRICATING THE SAME - Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer. | 2013-05-23 |
20130130473 | SEMICONDUCTOR ON GLASS SUBSTRATE WITH STIFFENING LAYER AND PROCESS OF MAKING THE SAME - A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film. | 2013-05-23 |
20130130474 | Quantum Well Device - An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer, The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor. | 2013-05-23 |
20130130475 | VAPOR TRANSPORT DEPOSITION METHOD AND SYSTEM FOR MATERIAL CO-DEPOSITION - An improved feeder system and method for continuous vapor transport deposition that includes at least two vaporizers couple to a common distributor through an improved seal for separately vaporizing and collecting at least any two vaporizable materials for deposition as a material layer on a substrate. Multiple vaporizer provide redundancy and allow for continuous deposition during vaporizer maintenance and repair. | 2013-05-23 |
20130130476 | METHOD FOR CLEANING FILM FORMATION APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for cleaning a hot-wall type film formation apparatus having a batch processing system with industrially high mass productivity is provided. In the method, a carbon film deposited on an inner wall or the like of a reaction chamber of the apparatus is removed efficiently in a short time. To remove the carbon film deposited on the inner wall of the reaction chamber by a thermal CVD method, the reaction chamber is heated at a temperature higher than or equal to 700° C. and lower than or equal to 800° C., and oxygen is introduced into the reaction chamber. | 2013-05-23 |
20130130477 | METHOD FOR PRODUCING GALLIUM TRICHLORIDE GAS AND METHOD FOR PRODUCING NITRIDE SEMICONDUCTOR CRYSTAL - According to the invention, there is provided a method for producing a gallium trichloride gas, the method including: a first step of reacting a metallic gallium and a chlorine gas to produce a gallium monochloride gas; and a second step of reacting the produced gallium monochloride gas and a chlorine gas to produce a gallium trichloride gas. | 2013-05-23 |
20130130478 | Non-Volatile Memory Device And Method Of Manufacturing The Same - A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers. | 2013-05-23 |
20130130479 | Semiconductor-on-Insulator with Back Side Body Connection - Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region. | 2013-05-23 |
20130130480 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - Disclosed is a method for manufacturing a semiconductor device having a multilayer structure. The method for manufacturing a semiconductor device according to the present invention comprises the loading of a substrate into the chamber of a chemical vapor deposition apparatus and the forming of a multilayer structure in which a plurality of doped amorphous silicon layers and a plurality of insulation layers are alternately stacked. Said layers are stacked by alternately and repetitively forming the doped amorphous silicon layer on the substrate by supplying a conductive dopant and silicon precursor into the chamber where the substrate is loaded, and forming the insulation layer containing silicon on the substrate by introducing the silicon precursor and a reaction gas into the chamber where the substrate is loaded. | 2013-05-23 |
20130130481 | METHOD AND APPARATUS FOR ATOMIC HYDROGEN SURFACE TREATMENT DURING GaN EPITAXY - Methods and apparatus for generating and delivering atomic hydrogen to the growth front during the deposition of a III-V film are provided. The apparatus adapts HWCVD technology to a system wherein the Group III precursor and the Group V precursor are delivered to the surface in isolated processing environments within the system. Multiple HWCVD units may be incorporated so that the atomic hydrogen parameters may be varied in a combinatorial manner for the development of III-V films. | 2013-05-23 |
20130130482 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - On a substrate, a silicon carbide layer provided with a main surface is formed. A mask is formed to cover a portion of the main surface of the silicon carbide layer. The main surface of the silicon carbide layer on which the mask is formed is thermally etched using chlorine-based gas so as to provide the silicon carbide layer with a side surface inclined relative to the main surface. The step of thermally etching is performed in an atmosphere in which the chlorine-based gas has a partial pressure of 50% or smaller. | 2013-05-23 |
20130130483 | ELECTRO-STATIC DISCHARGE PROTECTION DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING ELECTRO-STATIC DISCHARGE PROTECTION DEVICE - An electro-static discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first silicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode. | 2013-05-23 |
20130130484 | ION IMPLANTER AND ION IMPLANT METHOD THEREOF - An ion implanter and an ion implant method are disclosed. Essentially, the wafer is moved along one direction and an aperture mechanism having an aperture is moved along another direction, so that the projected area of an ion beam filtered by the aperture is two-dimensionally scanned over the wafer. Thus, the required hardware and/or operation to move the wafer may be simplified. Further, when a ribbon ion beam is provided, the shape/size of the aperture may be similar to the size/shape of a traditional spot beam, so that a traditional two-dimensional scan may be achieved. Optionally, the ion beam path may be fixed without scanning the ion beam when the ion beam is to be implanted into the wafer, also the area of the aperture may be adjustable during a period of moving the aperture across the ion beam. | 2013-05-23 |