21st week of 2009 patent applcation highlights part 48 |
Patent application number | Title | Published |
20090130758 | Gene Cry7ba1 Encoding and Insecticidal Crystal Protein of Bacillus Thuringiensis - The present invention discloses the isolation, cloning and use of insecticidal crystal proteins from | 2009-05-21 |
20090130759 | Culture Medium Containing Kinase Inhibitor, and Use Thereof - Pluripotent cells are maintained in a self-renewing state in serum-free culture medium comprising a gp130 agonist (LIF) and a GSK3 inhibitor. | 2009-05-21 |
20090130760 | METHOD FOR THE UBIQUITINATION OF COMMON SUBUNIT OF RNA POLYMERASES - The present invention provides a method for ubiquitinating RNA polymerases, comprising bringing the RNA polymerases into contact with BRCA1-BARD1. | 2009-05-21 |
20090130761 | Freeze-Dried Product for Introducing Nucleic Acid, Oligonucleic Acid or Derivative Thereof - A freeze-dried product is provided which, together with demonstrating satisfactory ability to express function when used to introduce a gene or antisense nucleic acid and the like, enables concentration to be adjusted easily, offers easy handling and has superior storage performance. | 2009-05-21 |
20090130762 | Activation of HCV-specific T cells - The invention provides a method of activating hepatitis C virus (HCV)-specific T cells, including CD4 | 2009-05-21 |
20090130763 | Method of Controlling Degradation of Protein by Tetracycline Antibiotic - The present invention provides a fusion protein comprising a variant protein of a protein binding to an antibiotic and a target protein having fused thereto, wherein the variant protein is degraded when the antibiotic is not bound but stabilized when the antibiotic is bound in a cell, and the fusion protein is degraded when the antibiotic is not bound but stabilized when the antibiotic is bound in a cell. | 2009-05-21 |
20090130764 | METHODS OF TREATING METAL CONTAINING HAZARDOUS WASTE USING CORN ASH CONTAINING ORTHOPHOSPHATES - A method of treating a waste material or soil by contacting the waste material or soil with an effective amount of corn ash to lower metal leaching in a Toxicity Characteristics Leaching Procedure test to below the hazardous waste characteristic criteria producing a treated waste material or soil, wherein the corn ash contains an effective amount of one or more orthophsophates. Preferably, the corn ash is substantially free of polyphosphates. The waste material or soil is a hazardous waste containing one or more metals being Cd, Pb and Zn. The waste material is generated by a foundry or steel mill. | 2009-05-21 |
20090130765 | SYSTEM AND A METHOD FOR MANAGING INFORMATION RELATING TO SAMPLE TEST REQUESTS WITHIN A LABORATORY ENVIRONMENT - A system and method for managing information relating to requests for a number of tests to be made of at least one sample within a laboratory environment are disclosed. The system may include a sample reception unit, a pre-analytical unit to scan, sort and/or aliquot the sample on request according to respective test requirements included within a respective sample order, an analytical unit to run at least one test on a sorted and/or aliquoted sample, and at least one decision unit. The decision unit acts as a connecting component for interconnecting the sample reception unit, the pre-analytical unit and the analytical unit as both an intermediary and coordinator such that tests can be performed via a recursive workflow until the sample is completely measured. The decision unit is further configured to collate the test results appropriately with the sample and to give a respective report towards a host component. | 2009-05-21 |
20090130766 | FLUID SAMPLE TRANSPORT DEVICE WITH REDUCED DEAD VOLUME FOR PROCESSING, CONTROLLING AND/OR DETECTING A FLUID SAMPLE - The present invention relates to a fluid sample transport device ( | 2009-05-21 |
20090130767 | ORGANOSILANES AND SUBSTRATES COVALENTLY BONDED WITH SAME AND METHODS FOR SYNTHESIS AND USE - The present invention provides novel silicon compounds, methods for making these novel silicon compounds, compositions comprising these novel silicon compounds attached to substrates, methods for attaching the novel silicon compounds to substrates and methods for using the compositions in a variety of chromatographic applications. | 2009-05-21 |
20090130768 | VAPOCHROMIC COORDINATION POLYMERS FOR USE IN ANALYTE DETECTION - This application relates to vaprochromic coordination polymers useful for analyte detection. The vapochromism may be observed by visible color changes, changes in luminescence, and/or spectroscopic changes in the infrared (IR) signature. One or more of the above chromatic changes may be relied upon to identify a specific analyte, such as a volatile organic compound or a gas. The chromatic changes may be reversible to allow for successive analysis of different analytes using the same polymer. The polymer has the general formula M | 2009-05-21 |
20090130769 | Novel Cross-Linkers For Obtaining Structure Information On Molecule Complexes - The present invention describes a novel cross-linker, a method for preparing one or more cross-linked biomolecules, biomolecular complexes of two or more biomolecules, a method for preparing cross-linked fragments from such cross-linked biomolecules and/or biomolecular complexes, a method for cleavage and reduction of such cross-linked biomolecules and/or biomolecular complexes, a method for identifying cross-links in such cross-linked biomolecules and/or biomolecular complexes, as well as a method for determining relative amounts of cross-links in a biomolecule or biomolecular complex in two or more samples. | 2009-05-21 |
20090130770 | BIOMARKER FOR FARNESYL PATHWAY - The present invention relates to a novel biomarker which can be used to determine the extent of interference of a substance with the farnesyl pathway. | 2009-05-21 |
20090130771 | Assay device and method - An assay device includes a first reagent including a magnetic particle and a second reagent including detectable component. The first and second reagent can each independently bind to an analyte in a sample. Applying a magnetic field can selectively concentrate the detectable component in a detection zone, where a detectable change ca be measured and related to the amount of analyte in the sample. | 2009-05-21 |
20090130772 | Apparatus and method for collecting data on light-emitting reactions - The invention concerns an apparatus and a method for collecting data on a set of light-emitting molecular reactions. The apparatus comprises a holder for a reaction vessel comprising a plurality of reaction spaces containing first reaction substance, feeder for supplying second reaction substance to said reaction spaces for initiating said reaction set, and a plurality of light detectors for measuring light emitted from said reaction spaces in synchronized relationship with said feeding. According to the invention, at least two of said light detectors are arranged on opposing sides of the reaction vessel and being adapted to simultaneously measure different properties of the reaction set, that is, different wells or wavelengths, for example. The invention allows doubling the measurement speed in aequorin-based intracellular Ca-measurements. | 2009-05-21 |
20090130773 | Method of Enhancing a Fluorescent Signal - A composition comprising a hydrogel particle and a fluorophore; wherein said composition produces an enhanced fluorescent signal when excited by an energy source capable of exciting the fluorophore. | 2009-05-21 |
20090130774 | Elisa assays using prion-specific peptide reagents - Peptide reagents that interact preferentially with the PrPsc form of the prion protein are described for use in detecting PrPsc in biological samples. In particular, ELISA assays are described. | 2009-05-21 |
20090130775 | METHOD FOR CLINICAL STAGING OF ULCERATIVE COLITIS OR INTERSTITIAL PNEUMONIA AND REAGENT KIT FOR THE SAME - The invention provides a method capable of readily discriminating pathologic conditions and judging selection of a therapeutic drug, the degree of the therapeutic effect, discontinuation of medication, etc., wherein stages quantitatively judged by digitizing substances contained in urine, which is different from conventional methods for judging stages of an ulcerative colitis and an interstitial pneumonitis which are performed by observation of mucous lesions with endoscopy requiring the skill or by analysis of histological samples collected from the living body. | 2009-05-21 |
20090130776 | BINDING PROTEIN MOLECULE - A binding protein molecule, characterized in that it has a first domain having a binding site to an inhibitor of non-specific adsorption in which the domain comprises a part of the variable region of an antibody as the binding site and a second domain having a binding site to a target substance in which the domain comprises a part of the variable region of an antibody as the binding site, wherein the first and second domains are bound via a linker. | 2009-05-21 |
20090130777 | METHOD FOR EVALUATING ANALYTE - In an analyte evaluation method for evaluating an analyte, AC voltage is applied between a substrate electrode on a substrate and a counter electrode, and signals obtained from a marker provided on an analyte bound to the substrate electrode are observed, wherein the frequency of the AC voltage is changed and the behavior of the average value of the marker signals is observed. A novel, highly-selective, low-noise method of evaluating a object of evaluation is thus achieved. | 2009-05-21 |
20090130778 | Water-Soluble Polymeric Substrate Having Metallic Nanoparticle Coating - A metallic nanoparticle coated water-soluble polymeric substrate and the process for preparing and using the same is described. | 2009-05-21 |
20090130779 | Method of Forming a Magnetic Tunnel Junction Structure - In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) structure including a conductive layer on a substrate. The method also includes depositing a sacrificial layer on the conductive layer before depositing a patterning film layer. | 2009-05-21 |
20090130780 | SEMICONDUCTOR PROCESSING SYSTEM AND METHOD OF PROCESSING A SEMICONDUCTOR WAFER - A method of processing semiconductor wafers includes applying reactive gas through a plurality of inlets to the semiconductor wafers. The method further includes removing exhaust gas resulting from the step of applying reactive gas. The removing of the exhaust gas is through a plurality of outlets coupled to a manifold. The manifold combines the exhaust gas from the plurality of outlets. The method further includes measuring a pressure in each outlet of the plurality of outlets during the step of removing. | 2009-05-21 |
20090130781 | METHOD FOR SIMULTANEOUSLY PRODUCING MULTIPLE WAFERS DURING A SINGLE EPITAXIAL GROWTH RUN AND SEMICONDUCTOR STRUCTURE GROWN THEREBY - HVPE method for simultaneously fabricating multiple Group III nitride semiconductor structures during a single reactor run. A HVPE reactor includes a reactor tube, a growth zone, a heating element and a plurality of gas blocks. A substrate holder is capable of holding multiple substrates and can be a single or multi-level substrate holder. The gas delivery blocks are independently controllable. Gas flows from the delivery blocks are mixed to provide a substantially uniform gas environment within the growth zone. The substrate holder can be controlled, e.g., rotated and/or tilted, for uniform material growth. Multiple Group III nitride semiconductor structures can be grown on each substrate during a single fabrication run of the HVPE reactor. Growth on different substrates is substantially uniform and can be performed on larger area substrates, such as 3-12″ substrates. | 2009-05-21 |
20090130782 | METHOD AND LINE FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method is provided for manufacturing a semiconductor device that includes a multilayer wiring structure in which insulating layers and wiring layers each with a plurality of conductor lines are alternately stacked on each other. The method includes steps of forming a first wiring layer on a first insulating layer, detecting a defect in the first wiring layer on the first insulating layer, and determining whether or not the defect is to be irradiated with a focused ion beam, according to a detection result. If it is determined that the defect is to be irradiated, the defect is irradiated with a focused ion beam and then a second insulating layer is formed on the first wiring layer disposed on the first insulating layer. If it is determined that the defect is not to be irradiated with a focused ion beam, the second insulating layer is formed on the first wiring layer disposed on the first insulating layer without irradiating the defect. | 2009-05-21 |
20090130783 | METHOD OF FABRICATING AN ULTRA-SMALL CONDENSER MICROPHONE - In the present invention, a semiconductor substrate wherein a plurality of MEMS microphones is formed is disposed opposed to a discharge electrode in a state of being stuck on a sheet. Electretization of a dielectric film provided in the MEMS microphone is performed by irradiating the dielectric film between a fixed electrode and a vibration film provided in the MEMS microphone with ions resulting from a corona discharge of the discharge electrode in a state that a predetermined potential difference is applied to the fixed electrode and the vibration film and fixing charges based on the ions to the dielectric film. The electretization is successively performed to each MEMS microphone on the semiconductor substrate by relatively moving the semiconductor substrate and the discharge electrode. Therefore, electretization of the dielectric film in the MEMS microphone chip is realized using a low-cost and simple fabricating equipment and productivity can be enhanced. | 2009-05-21 |
20090130784 | Method for determining the position of the edge bead removal line of a disk-like object - A method for determining the position of an edge bead removal line of a disk-like object having an edge area and an alignment mark on the edge area is disclosed, wherein the edge area including the edge bead removal line is imaged on a line-by-line basis, an intensity profile I of the imaged edge area including the edge bead removal line is obtained with a camera on a line-by-line basis, and the edge area and the alignment mark are detected, wherein the local intensity maxima I′ | 2009-05-21 |
20090130785 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - As the thickness of the card holder for preventing warping of a multilayered wiring substrate | 2009-05-21 |
20090130786 | Organic electroluminescent display device and method of fabricating the same - An organic electroluminescent display device includes an array element layer formed on a substrate, the array element layer including a switching element, a driving element, a first electrode, an organic luminescent layer, and a second electrode, and a ground line formed on the substrate, the ground line directly contacting the second electrode. | 2009-05-21 |
20090130787 | Method for fabricating a plurality of electromagnetic radiation emitting semiconductor chips - Method for fabricating a semiconductor chip which emits electromagnetic radiation, wherein to improve the light yield of semiconductor chips which emit electromagnetic radiation, a textured reflection surface is integrated on the p-side of a semiconductor chip. The semiconductor chip has an epitaxially produced semiconductor layer stack based on GaN, which comprises an n-conducting semiconductor layer, a p-conducting semiconductor layer and an electromagnetic radiation generating region which is arranged between these two semiconductor layers. The surface of the p-conducting semiconductor layer which faces away from the radiation-generating region is provided with three-dimensional pyramid-like structures. A mirror layer is arranged over the whole of this textured surface. A textured reflection surface is formed between the mirror layer and the p-conducting semiconductor layer. | 2009-05-21 |
20090130788 | FLAT PANEL DISPLAY DEVICE AND FABRICATING METHOD THEREOF - A top-emitting organic light-emitting device can prevent a voltage drop by electrically coupling a cathode bus line to a cathode electrode. A method for fabricating the same is also disclosed. The flat panel display device comprises an insulating substrate having a pixel region and a non-pixel region, a first electrode arranged in the pixel region. a second electrode arranged in the pixel region and the non-pixel region, an organic emission layer and a charge transporting layer formed between the first electrode and the second electrode of the pixel region, and an electrode line formed in the pixel region and the non-pixel region. The electrode line and the second electrode are electrically and directly coupled to each other in the non-pixel region. | 2009-05-21 |
20090130789 | SIGNAL LINE FOR DISPLAY DEVICE AND THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SIGNAL LINE - A thin film transistor (TFT) array panel with signal lines that have low resistivity is presented. The TFT array panel includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer formed on the gate line, a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode facing the source electrode with a gap, and a pixel electrode connected to the drain electrode. In one embodiment, at least one of the gate line, the data line, and the drain electrode includes a first conductive layer made of a Mo-containing conductor, a second conductive layer made of a Cu-containing conductor, and a third conductive layer made of a MoN-containing conductor. | 2009-05-21 |
20090130790 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A method for manufacturing a nitride semiconductor light-emitting element comprises: forming a semiconductor laminated structure wherein an n-type nitride semiconductor epitaxial layer, an active layer, and a p-type nitride semiconductor epitaxial layer are laminated on a substrate; forming a p-type electrode having a first electrode layer containing Pd and a second electrode layer containing Ta on the p-type nitride semiconductor epitaxial layer; heat treating at a temperature between 400° C. and 600° C. in an ambient containing oxygen after forming the p-type electrode; and forming a pad electrode containing Au on the p-type electrode after the heat treating. | 2009-05-21 |
20090130791 | CAMERA MODULES AND METHODS OF FABRICATING THE SAME - Provided are camera modules capable of effectively shielding electromagnetic (EM) waves and methods of fabricating the same. A method of fabricating a camera module includes, preparing a first wafer including an array of lens units. Then, a second wafer including an array of image sensor CSPs (chip-scale packages) is prepared. Each of the image sensor CSPs includes an image sensor chip corresponding to one of the lens units. The first wafer is stacked on the second wafer. The first wafer and the second wafer are cut to form a trench exposing the top surface of the image sensor chip at the interface between adjacent lens units. The trench is filled with a first material used for forming a housing. The first material and the image sensor chip are cut at the interface between the adjacent lens units. | 2009-05-21 |
20090130792 | Method of fabricating image sensor - A method of fabricating an image sensor includes forming a photoelectric transformation device on a substrate and forming a dielectric layer structure on the substrate. The dielectric layer structure includes multi-layer interlayer dielectric layers and multi-layer metal interconnections which are located between the multi-layer interlayer dielectric layers. A cavity which penetrates the multi-layer interlayer dielectric layers on the photoelectric transformation device is formed. A heat treatment is performed on the substrate on which the cavity is formed. | 2009-05-21 |
20090130793 | PHOTO DIODE AND METHOD FOR MANUFACTURING THE SAME - A method of fabricating a photo diode includes sequentially forming a buried layer of a first conductivity type, a first epitaxial layer of the first conductivity type, and a second epitaxial layer of a second conductivity type on a semiconductor substrate; forming a doped oxide film, including impurities of the second conductivity type, on the second epitaxial layer; forming a silicon nitride film on the oxide film; and patterning the oxide film and the silicon nitride film to sequentially form an oxide film pattern of the second conductivity type and a silicon nitride film pattern, respectively. The second conductivity type impurities are diffused from the oxide film pattern into the second epitaxial layer using a heat diffusion process to form a doped shallow junction layer of the second conductivity type, which converts the oxide film pattern into a non-conductive oxide film pattern. | 2009-05-21 |
20090130794 | THERMAL EVAPORATION APPARATUS, USE AND METHOD OF DEPOSITING A MATERIAL - Thermal evaporation apparatus for depositing of a material on a substrate, comprising material storage means; heating means to generate a vapour of the material in the material storage means; vapour outlet means comprising a vapour receiving pipe having vapour outlet passages, and emission reducing means arranged such that an external surface of the vapour outlet means directed to said substrate exhibits low emission, and wherein the apparatus further comprises pipe heating means in the interior of said vapour outlet means, wherein at least the surfaces of the material storage means, heating means, and emission reducing means and pipe heating means arranged to come into contact with the material vapour are of a corrosion-resistant material. Further a thermal evaporation apparatus for depositing a material on a substrate comprising a vapour outlet means arranged to receive in its interior the vapour of the material heated in a material storage means and having vapour outlet passages, wherein said vapour outlet means basically consist of a corrosion-resistant material and are gastight to such an extent that sufficient dynamic pressure of said material vapour is achievable for homogenous deposition of said material on said substrate. Also the use of the apparatus, and a method of depositing a material onto a substrate by thermal evaporation. | 2009-05-21 |
20090130795 | SYSTEMS AND METHODS FOR PREPARATION OF EPITAXIALLY TEXTURED THICK FILMS - The disclosed subject matter relates to the use of laser crystallization of thin films to create epitaxially textured crystalline thick films. In one or more embodiments, a method for preparing a thick crystalline film includes providing a film for crystallization on a substrate, wherein at least a portion of the substrate is substantially transparent to laser irradiation, said film including a seed layer having a predominant surface crystallographic orientation; and a top layer disposed above the seed layer; irradiating the film from the back side of the substrate using a pulsed laser to melt a first portion of the top layer at an interface with the seed layer while a second portion of the top layer remains solid; and re-solidifying the first portion of the top layer to form a crystalline laser epitaxial with the seed layer thereby releasing heat to melt an adjacent portion of the top layer. | 2009-05-21 |
20090130796 | Sulfurization and Selenization of Electrodeposited Cigs Films by Thermal Annealing - The invention relates to a method for production of thin layers of semiconductor alloys of the I-III-VI | 2009-05-21 |
20090130797 | METHODS OF FORMING PHASE-CHANGEABLE MEMORY DEVICES USING GROWTH-ENHANCING AND GROWTH-INHIBITING LAYERS FOR PHASE-CHANGEABLE MATERIALS - Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer to guide the formation of a phase-changeable material region within a memory cell (e.g., PRAM cell). In particular, methods of forming an integrated circuit memory device include forming an interlayer insulating layer having an opening therein, on a substrate, and then lining sidewalls of the opening with a seed layer (i.e., growth-enhancing layer) that supports growth of a phase-changeable material thereon. An electrically insulating growth-inhibiting layer is then selectively formed on a portion of the interlayer insulating layer surrounding the opening. The formation of the growth-inhibiting layer is followed by a step to selectively grow a phase-changeable material region in the opening, but not on the growth-inhibiting layer. | 2009-05-21 |
20090130798 | Process for Making a Semiconductor System - Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device. | 2009-05-21 |
20090130799 | Stacked dual MOSFET package - A method of fabricating a stacked dual MOSFET die package is disclosed. The method includes the steps of (a) forming a first conductive tab, (b) stacking a high side MOSFET die on the first conductive tab such that a drain contact of the high side MOSFET die is coupled to the first conductive tab, (c) stacking a second conductive tab in overlaying relationship to the high side MOSFET die such that a source contact of the high side MOSFET die is coupled to the second conductive tab, and (d) stacking a low side MOSFET die on the second conductive tab such that a drain contact of the low side MOSFET die is coupled to the second conductive tab. | 2009-05-21 |
20090130800 | Manufacturing method of semiconductor device - A method of manufacturing a semiconductor device includes the steps of bonding a semiconductor chip to a first side of a circuit board, bonding a metal base for dissipating heat produced by the semiconductor chip to a second side of the circuit board, and forming a dam on the metal base by a dam material so as to restrict flow of a solder used in bonding a plurality of the circuit boards to the metal base. | 2009-05-21 |
20090130801 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND LEAD FRAME, AND METHOD FOR MANUFACTURING THE SAME - There are provided a lead frame including a plurality of first external terminal portions | 2009-05-21 |
20090130802 | SUBSTRATE BASED UNMOLDED PACKAGE - A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. | 2009-05-21 |
20090130803 | STRESSED FIELD EFFECT TRANSISTOR AND METHODS FOR ITS FABRICATION - A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate. | 2009-05-21 |
20090130804 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes first providing an insulation substrate. A patterned conductive layer is formed over the insulation substrate, and the patterned conductive layer includes a channel region and a number of protruding regions. A gate structure layer is formed over the insulation substrate. The gate structure layer covers a part of the patterned conductive layer, and each of the protruding regions has an exposed region. A doping process is performed to dope at least the exposed region of the patterned conductive layer to form a number of S/D regions. | 2009-05-21 |
20090130805 | ADVANCED CMOS USING SUPER STEEP RETROGRADE WELLS - The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer ( | 2009-05-21 |
20090130806 | POWER SEMICONDUCTOR COMPONENT WITH CHARGE COMPENSATION STRUCTURE AND METHOD FOR THE FABRICATION THEREOF - A semiconductor component with charge compensation structure has a semiconductor body having a drift path between two electrodes. The drift path has drift zones of a first conduction type, which provide a current path between the electrodes in the drift path, while charge compensation zones of a complementary conduction type constrict the current path of the drift path. For this purpose, the drift path has two alternately arranged, epitaxially grown diffusion zone types, the first drift zone type having monocrystalline semiconductor material on a monocrystalline substrate, and a second drift zone type having monocrystalline semiconductor material in a trench structure, with complementarily doped walls, the complementarily doped walls forming the charge compensation zones. | 2009-05-21 |
20090130807 | Trench DRAM Cell with Vertical Device and Buried Word Lines - A DRAM array having trench capacitor cells of potentially 4F | 2009-05-21 |
20090130808 | METHOD OF FABRICATING FLASH MEMORY - A method of fabricating a flash memory includes successively forming a floating gate insulating layer, a floating gate material layer, a dielectric layer, a control gate material layer, a silicide layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer, removing portions of the silicide layer, the control gate material layer, the dielectric layer, and the floating gate material layer not covered by the hard mask layer to form a stacked structure, forming a silicon cap layer covering the surface of the stacked structure, and performing a thermal process. | 2009-05-21 |
20090130809 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes first and second element isolation insulating films, first and second gate insulating films, first and second gate wiring and first and second mask layer. First and second upper surfaces of the first and second element isolation insulating films are higher than an upper surface of the substrate, first and second bottom surfaces of the first and second element isolation insulating films are lower than the upper surface of the substrate, a second height from the upper surface of the substrate to the second upper surface is larger than a first height from the upper surface of the substrate to the first upper surface. A height from the upper surface of the substrate to an upper surface of the first mask layer equals a height from the upper surface of the substrate to an upper surface of the second mask layer. | 2009-05-21 |
20090130810 | Fabrication method - A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region, is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer. | 2009-05-21 |
20090130811 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH UNIFORM CONCENTRATION ION DOPING IN RECESS GATE CHANNEL REGION - A semiconductor device is manufactured by defining a groove in a semiconductor substrate, where the groove includes an upper portion and a lower portion, among other steps. A sacrificial layer is then formed to selectively fill the lower portion of the groove. Impurity ions are implanted into the semiconductor substrate while the lower portion of the groove is filled with the sacrificial layer. The sacrificial layer is then removed, and a gate is formed on the groove. In the method for manufacturing the semiconductor device, impurities can be doped at a uniform concentration in the channel area of the semiconductor device. | 2009-05-21 |
20090130812 | Creating High Voltage FETs with Low Voltage Process - An integrated circuit (IC) includes a high voltage first-conductivity type field effect transistor (HV-first-conductivity FET) and a high voltage second-type field effect transistor (HV-second-conductivity FET). The HV first-conductivity FET has a second-conductivity-well and a field oxide formed over the second-conductivity-well to define an active area. A first-conductivity-well is formed in at least a portion of the active area, wherein the first-conductivity-well is formed to have the capability to operate as a first-conductivity− drift portion of the HV-first-conductivity FET. The HV second-conductivity FET has a first-conductivity-well and a field oxide formed over the first-conductivity-well to define an active area. A channel stop region I s formed in at least a portion of the active area, wherein the channel stop region is formed to have the capability to operate as second-conductivity− drift portions of the HV-second-conductivity FET. | 2009-05-21 |
20090130813 | Method and System to Provide a Polysilicon Capacitor with Improved Oxide Integrity - A system and method in accordance with the present invention allows for an improved oxide integrity of a polysilicon capacitor compared to capacitors manufactured using conventional semiconductor processing techniques. This is accomplished by moving the capacitor implant step to a time after the deposition of the polysilicon. As an additional benefit, a separate capacitor oxide growth does not need to be performed. | 2009-05-21 |
20090130814 | SEMICONDUCTOR METHODS - A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor. | 2009-05-21 |
20090130815 | Semiconductor device and method for fabricating the same - The semiconductor device comprises a capacitor formed over a semiconductor substrate | 2009-05-21 |
20090130816 | METHOD FOR MANUFACTURING SIMOX WAFER AND SIMOX WAFER MANUFACTURED THEREBY - This method for manufacturing a SIMOX wafer, includes: implanting oxygen ions in a silicon wafer; cleaning said silicon wafer into which said oxygen ions are implanted; and forming a buried oxide film within an interior of said silicon wafer by subjecting said cleaned silicon wafer to a heat treatment, wherein said method further includes immersing said silicon wafer in an aqueous solution of hydrofluoric acid and etching a SiO | 2009-05-21 |
20090130817 | METHOD TO ELIMINATE RE-CRYSTALLIZATION BORDER DEFECTS GENERATED DURING SOLID PHASE EPITAXY OF A DSB SUBSTRATE - A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect. | 2009-05-21 |
20090130818 | METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR PREPARING RECESSED GATE STRUCTURE USING THE SAME - A method for preparing a recessed gate structure comprises the steps of: forming a shallow trench isolation structure surrounding an active area in a silicon substrate, wherein an etching barrier layer is formed on the surface of the shallow trench isolation structure; forming a plurality of gate trenches in the active area of the silicon substrate by performing an etching process; and forming a recessed gate structure by filling the gate trench with a predetermined height. | 2009-05-21 |
20090130819 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes a device isolation layer. In the method, a hard mask may be formed on a semiconductor substrate, and the semiconductor substrate may be etched using the hard mask as a mask to form a trench. The hard mask may be removed, and a device isolation layer may be formed in the trench. A shallow trench isolation pattern having an excellent layer quality may be formed by reducing an aspect ratio of the trench in the semiconductor device and gap-filling a dielectric. Thus, the number of defects may be decreased. | 2009-05-21 |
20090130820 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a shallow trench isolation trench in a semiconductor substrate, and then forming a first oxide layer over the semiconductor substrate including the trench by exposing the semiconductor substrate including the shallow trench isolation trench to oxygen, and then implanting boron ions on the surface of the trench by performing an ion implantation on the STI trench process using BF | 2009-05-21 |
20090130821 | THREE DIMENSIONAL PACKAGING WITH WAFER-LEVEL BONDING AND CHIP-LEVEL REPAIR - A method, a system and a computer readable medium for three dimensional packaging with wafer-level bonding and chip-level repair. A first wafer is provided having a first plurality of chips. A second wafer is provided having a second plurality of chips. At least one chip is removed from the second wafer while retaining the relative alignment of the remaining chips in the second wafer. The first and second wafers are aligned and joined with wafer-to-wafer techniques. Where a bad chip having a relative physical position within the second wafer corresponding to a relative physical position within the first wafer of a good chip is removed, a good chip may be aligned and bonded to the first wafer using die-to-wafer techniques. | 2009-05-21 |
20090130822 | PROCESS FOR COLLECTIVE MANUFACTURING OF SMALL VOLUME HIGH PRECISION MEMBRANES AND CAVITIES - The invention relates to a process for collective manufacturing of cavities and/or membranes ( | 2009-05-21 |
20090130823 | METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING TRENCH GATE STRUCTURE - A method of forming a semiconductor device is provided, which may include, but is not limited to, the following processes. Grooves may be formed in an insulating region and in a semiconductor region, while forming burrs near the boundary between the insulating region and the semiconductor region. Protection films may be selectively formed on inside walls of the grooves except on bottom walls of the grooves. A selective thermal process may be carried out in the presence of the protection films, thereby removing the burrs. | 2009-05-21 |
20090130824 | ARSENIC AND PHOSPHORUS DOPED SILICON WAFER SUBSTRATES HAVING INTRINSIC GETTERING - A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates. | 2009-05-21 |
20090130825 | Joined Assembly, Wafer Holding Assembly, Attaching Structure Thereof and Method for Processing Wafer - The object of the present invention is to provide an assembly, wafer holding assembly and attaching structure thereof, wherein sufficient air-tightness is assured during prolonged cycles of temperature rises and uninstallations and replacements of the assemblies are possible. | 2009-05-21 |
20090130826 | Method of Forming a Semiconductor Device Having a Strained Silicon Layer on a Silicon-Germanium Layer - A method of forming a semiconductor device having a strained silicon (Si) layer on a silicon germanium (SiGe) layer is provided. The method includes preparing a silicon substrate. A SiGe layer is formed on the silicon substrate. At least a part of the SiGe layer has a first dislocation density. A strained Si layer having a second dislocation density lower than the first dislocation density is formed on the SiGe layer. | 2009-05-21 |
20090130827 | INTRINSIC AMORPHOUS SILICON LAYER - Embodiments of the present invention may include an improved thin film solar cell device that is formed by sequentially depositing an intrinsic amorphous silicon layer and an intrinsic microcrystalline silicon layer during the p-i-n or n-i-p junction formation process. Embodiments of the invention also generally provide a method and apparatus for forming the same. The present invention may be used to advantage to form other single junction, tandem junction, or multi-junction thin film solar cell devices. | 2009-05-21 |
20090130828 | Method for Forming Voltage Sustaining Layer with Opposite-Doped Islands for Semiconductor Power Devices - A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage. | 2009-05-21 |
20090130829 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Provided are a manufacturing method of a semiconductor device and a substrate processing apparatus. The manufacturing method of the semiconductor device includes: loading a plurality of substrates into a reaction vessel, which is configured by a process tube and a manifold that supports the process tube, and arranging the loaded substrates within the reaction vessel; pre-processing the plurality of substrates by supplying a pre-process gas from the manifold side toward the process tube side within the reaction vessel; main-processing the plurality of pre-processed substrates by supplying a main-process gas from the manifold side toward the process tube side within the reaction vessel; and unloading the plurality of main-processed substrates from the reaction vessel, wherein in pre-processing the plurality of substrates, the pre-process gas is supplied from at least one position in an area corresponding to the manifold, and at least one position in an upper area of an area corresponding to a substrate arrangement area. | 2009-05-21 |
20090130830 | Method for fabricating optical semiconductor device - In the method of fabricating an optical semiconductor device, a semiconductor layer is formed on an InP region, and includes semiconductor films. A first etching mask is formed on the semiconductor layer. The semiconductor layer is etched through the first etching mask to form a semiconductor mesa and a first marking mesa, each mesa includes an active layer and an InP cladding layer, the InP cladding layer being provided on the active layer. The active layer is made of semiconductor material different from InP. An InP burying region is grown through the first etching mask on a side of the semiconductor mesa and a side of the first marking mesa to bury the semiconductor mesa and the first marking mesa. A second etching mask is formed on the InP burying region after removing the first etching mask, and has an opening located above the first marking mesa. InP in the InP burying region and the first marking mesa is etched through the second etching mask to form a second marking mesa. The alignment mark includes the second marking mesa, and the active layer is exposed on the top of the second marking mesa. | 2009-05-21 |
20090130831 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for fabricating a semiconductor device having a CMOS transistor including a gate electrode with low resistance. In the CMOS transistor in accordance with embodiments, the impurities implanted into the gate electrode have a higher density than the impurities implanted into the source/drain region. Embodiments also reduce the amount of impurities included in channel regions. | 2009-05-21 |
20090130832 | SILICON SURFACE STRUCTURING METHOD - A method for the structuring of multicrystalline silicon substrate surfaces and emitter diffusion into said surfaces comprises the following steps: providing a texturing solution which comprises at least a portion of phosphoric acid, providing a semiconductor substrate with a surface to be structured, coating the surface to be structured with the texturing solution, heating the texturing solution to a heating temperature T | 2009-05-21 |
20090130833 | INSULATING BUFFER FILM AND HIGH DIELECTRIC CONSTANT SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode. | 2009-05-21 |
20090130834 | METHODS OF FORMING IMPURITY CONTAINING INSULATING FILMS AND FLASH MEMORY DEVICES INCLUDING THE SAME - Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak. | 2009-05-21 |
20090130835 | METHOD OF MANUFACTURING INVERTED T-SHAPED FLOATING GATE MEMORY - A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T-shape, a U-shape, a trapezoid shape, or a double inverted T-shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T-shape, such that a top contour is a non-flat segment. | 2009-05-21 |
20090130836 | METHOD OF FABRICATING FLASH CELL - A method of fabricating a flash cell of a semiconductor device includes depositing a damage-prevention film on and/or over a hard mask pattern to prevent damage to an ONO film of a gate pattern when removing the hard mask using a vapor process chamber (VPC) process. | 2009-05-21 |
20090130837 | IN SITU DEPOSITION OF A LOW K DIELECTRIC LAYER, BARRIER LAYER, ETCH STOP, AND ANTI-REFLECTIVE COATING FOR DAMASCENE APPLICATION - The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier layers, and etch stops, and ARCs. The invention may also utilize a plasma containing a reducing agent, such as ammonia, to reduce any oxides that may occur, particularly on metal surfaces such as copper filled features. This particular SiC material is useful in complex structures, such as a damascene structure and is conducive to in situ deposition, especially when used in multiple capacities for the different layers, such as the barrier layer, the etch stop, and the ARC and can include in situ deposition of the associated dielectric layer(s). | 2009-05-21 |
20090130838 | METHOD OF FORMING CONDUCTIVE BUMPS - A method of forming a conductive bump of the present invention, includes the steps of, preparing a substrate including a connection pad and a protection insulating layer, in which an opening portion is provided on the connection pad, on a surface layer side, arranging a first conductive ball, at least an outer surface portion of which is made of solder, on the connection pad in the opening portion of the protection insulating layer, filling a solder layer in the opening portion by applying a reflow heating to the first conductive ball, arranging a second conductive ball on the solder layer, and obtaining a conductive bump which protrudes from an upper surface of the protection insulating layer, by joining the solder layer and the second conductive ball by a reflow heating. | 2009-05-21 |
20090130839 | MANUFACTURING METHOD OF REDISTRIBUTION CIRCUIT STRUCTURE - A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is formed on the passivation layer. The first patterned photoresist layer has a plurality of second openings exposing a portion of each of the pads. A plurality of first bumps is formed in the second openings, respectively. An under ball metal (UBM) material layer is formed over the substrate to cover the first patterned photoresist layer and the first bumps. A plurality of conductive lines is formed on the UBM material layer. The UBM material layer is patterned to form a plurality of UBM layers using the conductive lines as a mask. | 2009-05-21 |
20090130840 | Protected Solder Ball Joints in Wafer Level Chip-Scale Packaging - Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress. | 2009-05-21 |
20090130841 | METHOD FOR FORMING CONTACT IN SEMICONDUCTOR DEVICE - A method for forming a contact in a semiconductor device, comprises providing a substrate, forming a plurality of conductive patterns and a passivation layer surrounding the conductive patterns over the substrate, forming an insulation layer covering the conductive patterns and passivation layer, forming a mask pattern for a contact over the insulation layer, forming a first opening by performing an isotropic etch process on the insulation layer using the mask pattern as an etch mask, wherein the isotropic etch process is performed until the insulation layer meets the passivation layer, forming a barrier layer over a resultant structure of the first opening, exposing the insulation layer by performing an anisotropic etch process using the mask pattern as an etch mask, and forming a second opening exposing the substrate by performing a self aligned contact (SAC) process using the mask pattern and barrier layer as an etch mask. | 2009-05-21 |
20090130842 | Method of forming contact hole and method of manufacturing semiconductor memory device using the same - A contact hole forming method and a method of manufacturing semiconductor device using the same may include forming a layer on a substrate; anisotropically etching the layer to form a dummy contact hole exposing the substrate; isotropically etching a sidewall of the dummy contact hole to form a contact hole by alternatively and repeatedly supplying an etching solution including a fluoride salt in a low-polarity organic solvent and deionized water to the dummy contact hole. The methods increase reliability of semiconductor memory devices. | 2009-05-21 |
20090130843 | METHOD OF FORMING LOW-RESISTIVITY RECESSED FEATURES IN COPPER METALLIZATION - A method is provided for forming low-resistivity recessed features containing a ruthenium (Ru) film integrated with bulk copper (Cu) metal. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film in the recessed feature in a barrier film deposition chamber, transferring the patterned substrate from the barrier film deposition chamber to a Ru metal deposition chamber, heat-treating the barrier film in the presence of a H | 2009-05-21 |
20090130844 | Method of Forming Metal Line of Semiconductor Device - A method of forming metal lines of a semiconductor device, comprising providing a semiconductor substrate in which a plurality of gates and junctions formed between the gates are included in a cell area and a peripheral area; forming an insulating layer over the semiconductor substrate including the gates; forming an etch protection layer over the insulating layer; etching he etch protection layer and the insulating layer, and gap-filling conductive material to form contact plugs contacting the junctions of the cell area; and, forming first metal lines contacting the contact plugs and forming second metal lines contacting the junctions of the peripheral area by etching the etch protection layer and the insulating layer. | 2009-05-21 |
20090130845 | DIRECT ELECTRODEPOSITION OF COPPER ONTO TA-ALLOY BARRIERS - A method of depositing copper directly onto a tantalum alloy layer of an on-chip copper interconnect structure, which includes electrodepositing copper from a neutral or basic electrolyte onto a surface of a tantalum alloy layer, in which the tantalum alloy layer is deposited on a substrate of the on-chip copper interconnect structure, and in which the copper nucleates onto the surface of the tantalum alloy layer without use of a seed layer to form a copper conductor. | 2009-05-21 |
20090130846 | SEMICONDUCTOR DEVICE FABRICATION METHOD - Methods of fabricating a semiconductor device including a through-silicon via that is electrically insulated from the semiconductor substrate. An exemplary method includes preparing a semiconductor wafer including a semiconductor substrate, a semiconductor element, an interlayer insulating, pads that are electrically connected to the semiconductor element, and a protective film; forming upper terminals electrically connected to the pads; forming annular grooves below the pads and extending to the interlayer insulating film; forming an annular insulating layer in the annular grooves and forming a bottom insulating film on the bottom surface of the semiconductor substrate; forming electrode-forming extending to the pads; filling the electrode-forming holes with a conductive material to form through-silicon vias electrically connected to the pads; and forming lower terminals on the bottom insulating film electrically connected to the through-silicon vias. | 2009-05-21 |
20090130847 | METHOD OF FABRICATING METAL PATTERN WITHOUT DAMAGING INSULATION LAYER - Provided is a method of fabricating a metal pattern so that an insulation layer between a wafer and the metal pattern can be prevented from being damaged in a planarization procedure when the metal pattern having a trench structure is fabricated on the wafer. The method includes operations of forming a first insulation layer on a surface of the wafer; selectively etching the surface of the wafer and the first insulation layer so as to form a plurality of trenches; forming a second insulation layer on a bottom and side walls of the plurality of trenches by using a thermal oxidation method; filling a metal inside the plurality of trenches; and performing planarization by removing the metal deposited outside the plurality of trenches. | 2009-05-21 |
20090130848 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION THEREOF - A semiconductor device having a silicon substrate, an element isolating film, an active region, a gate electrode provided via a gate insulating film, a diffusion layer provided on the active region on opposite sides of the gate electrode, an interlayer insulating film, and a plug filled in a hole formed on the interlayer insulating film, wherein the semiconductor device further has a contact forming region surrounded by the element isolating film, and a conductive layer formed on the contact forming region, the gate electrode extends so as to overlap with a portion of the contact forming region and is connected to the conductive layer at the overlapping portion, and the plug contacts the conductive layer at another portion of the contact forming region and is electrically connected to the gate electrode via the conductive layer. | 2009-05-21 |
20090130849 | CHEMICAL MECHANICAL POLISHING AND WAFER CLEANING COMPOSITION COMPRISING AMIDOXIME COMPOUNDS AND ASSOCIATED METHOD FOR USE - A composition and associated method for chemical mechanical planarization (or other polishing) is described. The composition contains an amidoxime compound and water. The composition may also contain an abrasive and a compound with oxidation and reduction potential. The composition is useful for attaining improved removal rates for metal, including copper, barrier material, and dielectric layer materials in metal CMP. The composition is particularly useful in conjunction with the associated method for metal CMP applications. | 2009-05-21 |
20090130850 | Semiconductor Devices and Method of Fabricating the Same - A method of fabricating a semiconductor device is provided. A contact hole with a finer width can be formed by solving an exposure limit of KrF exposure apparatuses. The fabrication method includes forming a first insulation layer on a substrate; forming a photoresist pattern on the first insulation layer; forming a second insulation layer covering the photoresist pattern; forming a second insulation layer spacer in a sidewall of the photoresist pattern by etching the second insulation layer; forming a contact hole by etching the first insulation layer using the photoresist pattern and the second insulation layer spacer as a mask; removing the photoresist pattern; and removing the second insulation layer spacer. A contact hole with a finer width can be formed using a KrF exposure apparatus, and furthermore, contact resistance can be lowered and device characteristics can be improved | 2009-05-21 |
20090130851 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, comprises forming a first film above a pattern forming material, patterning the first film to form a core material pattern, forming a second film above the pattern forming material so as to cover a side surface and an upper surface of the core material pattern, forming a third film above the second film as a protective material for the second film, etching the second and third films so that side wall sections including the second film and the third film are formed on both sides of the core material pattern and the second film and the third film of an area other than the side wall sections are removed, removing the core material pattern between the side wall sections, and transferring patterns corresponding to the side wall sections on the pattern forming material by using the side wall sections as a mask. | 2009-05-21 |
20090130852 | PROCESS FOR IMPROVING CRITICAL DIMENSION UNIFORMITY OF INTEGRATED CIRCUIT ARRAYS - Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined. | 2009-05-21 |
20090130853 | METHOD FOR FABRICATING A DEEP TRENCH IN A SUBSTRATE - The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate. | 2009-05-21 |
20090130854 | PATTERNING STRUCTURE AND METHOD FOR SEMICONDUCTOR DEVICES - Methods for forming a pattern layer over a target layer are disclosed. The methods use a novel low temperature spacer structure which results in a pattern layer having a decreased pattern pitch versus conventional patterning using photolithography. The decreased pattern pitch allows the target layer to be divided into multiple regions separated by a small distance, which in turn allows for greater density and device miniaturization. The structure and methods may be applied to patterning a word line layer in a memory device. | 2009-05-21 |
20090130855 | Phase change alloy etch - A method of forming devices is provided. A phase change layer is provided. The phase change layer is etched by providing an etch gas comprising a bromine containing compound and forming a plasma from the etch gas. The phase change layer is of a material that may be heated by a current and then when cooled, either forms an amorphous material or a crystalline material, depending on how fast the material is cooled. In addition, the amorphous material has a resistance at least several times greater than the crystalline material. | 2009-05-21 |
20090130856 | METHOD FOR MONITORING PROCESS DRIFT USING PLASMA CHARACTERISTICS - Methods for monitoring process drift using plasma characteristics are provided. In one embodiment, a method for monitoring process drift using plasma characteristics includes obtaining metrics of current and voltage information of a first waveform coupled to a plasma during a plasma process formed on a substrate, obtaining metrics of current and voltage information of a second waveform coupled to the plasma during the plasma process formed on the substrate, the first and second waveforms having different frequencies, determining at least one characteristic of the plasma using the metrics obtained from each different frequency waveform, and adjusting the plasma process in response to the determined at least one characteristic of the plasma. | 2009-05-21 |
20090130857 | METHOD OF MANUFACTURING A STRUCTURE BASED ON ANISOTROPIC ETCHING, AND SILICON SUBSTRATE WITH ETCHING MASK - A method of manufacturing a structure includes a first step of forming, on a monocrystal silicon substrate having a (100) surface as a principal surface, a basic etching mask corresponding to a target shape and having at least a first structure with a projecting corner and a second structure adjoining the first structure with an opening intervening therebetween, and a correction etching mask extending from the projecting corner of an etching mask of the first structure and connected to an etching mask of the second structure, and a second step of performing anisotropic etching of the monocrystal silicon substrate having the basic etching mask and the correction etching mask to form the target shape. | 2009-05-21 |