20th week of 2013 patent applcation highlights part 32 |
Patent application number | Title | Published |
20130121000 | LIGHT EMITTING DEVICE AND LIGHTING APPARATUS HAVING THE SAME - Disclosed are a light emitting device and a lighting apparatus having the same. The light emitting device includes a plurality of lead frames, a first body having reflectance, disposed on top surfaces of the lead frames and having an open region at a predetermined region of the top surfaces of the lead frames, a second body having transmittance, having a first opening corresponding to the open region of the first body, and disposed on a top surface of the first body, a light emitting chip on at least one of the lead frames exposed in the first opening of the second body, and a first resin layer disposed in the first opening of the second body to cover the light emitting chip. | 2013-05-16 |
20130121001 | ILLUMINATION APPARATUS CONFINING LIGHT BY TOTAL INTERNAL REFLECTION AND METHODS OF FORMING THE SAME - In various embodiments, an illumination apparatus includes an air gap between a sub-assembly and a waveguide attached thereto at a plurality of discrete attachment points, as well as a bare-die light-emitting diode encapsulated by the waveguide. | 2013-05-16 |
20130121002 | ILLUMINATION APPARATUS - This disclosure discloses an illumination apparatus. The illumination apparatus comprises a cover comprising a second portion and a first portion, and a light source disposed within the cover. An average thickness of the first portion is greater than that of the second portion. | 2013-05-16 |
20130121003 | Illumination Device for Providing Synchronous Forward and Backward Lighting - An illumination device for providing synchronous forward and backward lighting is disclosed. The illumination device includes a light housing of a predetermined shape and an illumination light source provided in the light housing. Also provided in the light housing is a reflector having a front section and a rear section, each of which sections forms a flared reflective area. Light emitted by the illumination light source in the light housing is reflected by the reflective areas of the front and rear sections of the reflector and hence directed both forward and backward, so as for the illumination device to provide wide-range lighting when in use. | 2013-05-16 |
20130121004 | HIGH EFFICIENCY DIRECTIONAL LIGHT SOURCE USING LENS OPTICS - At least one embodiment in the disclosure describes a high efficiency directional light engine. The light engine comprises a light emitter emitting light and a collimation lens. The collimation lens has a cone-shaped sidewall, a base surface and a curved top surface. The height of the cone-shaped sidewall is at least three times more than the diameter of the base surface. The light emitter is optically coupled to and disposed in close proximity to the base surface. One or more first reflection images of the light emitter result from first reflection of the light off a surface of the cone-shaped sidewall. The diameter of the light emitter is substantially close to the diameter of the base surface so that the light emitter and the first reflection images form a virtual point light source with minimal gap(s) or without any gap between the light emitter and the first reflection images. | 2013-05-16 |
20130121005 | ILLUMINATING LENS, OBSERVATION DEVICE AND METHOD FOR PRODUCING AN ILLUMINATING LIGHT BEAM - An illuminating lens for a medical headlamp, endoscope or exoscope, to generate an illuminating light beam with variable light distribution includes a liquid lens with variable focal length to modify a focusing of the illuminating light beam. The invention also relates to an observation device with an illuminating lens of this type as well as a method to generate an illuminating light beam with variable light distribution. | 2013-05-16 |
20130121006 | Low profile heat sink with attached LED light source - An LED light source with an attached heat sink includes larger fins, smaller fins, a mounting platform and light emitting diodes attached to the mounting platform. The larger fins are oriented parallel to the smaller fins. The larger fins are integrally formed with a first base, and the smaller fins are integrally formed with a second base. The bottom surface of the second base contacts the larger fins, which are more than twice as tall as the smaller fins. There are more than twice as many smaller fins than larger fins per distance perpendicular to the fins. Ducts are formed between the larger fins and the bottom surface of the second base. Intake holes pass through the first base into each duct near the end of the duct that is blocked by an end wall. The mounting platform with the LEDs is attached to the bottom of the first base. | 2013-05-16 |
20130121007 | Manufacture Method for a Surface Mounted Power LED Support and its Product - A manufacture method for a surface mounted power LED support comprises providing a wiring board having both sided metal layers. In addition, the method comprises forming a hole. Further, the method comprises setting a metal layer in the surface of the hole. Still further, the method comprises thickening the metal layer of the wiring board. The method also comprises etching the metal layer of the wiring board. Moreover, the method comprises cutting the wiring board to form single support unit. A surface mounted power LED support comprises a both sided wiring board, a hole formed in the wiring board and wiring layers set on the surface of the wiring board. | 2013-05-16 |
20130121008 | Grip Device, In Particular for a Vehicle - The invention relates to a grip device ( | 2013-05-16 |
20130121009 | Light Emitting Device - A light emitting device is provided with a semiconductor light emitting element and a wavelength conversion portion. The wavelength conversion portion includes an outer peripheral portion between an input surface and an output surface. The outer peripheral portion includes a first inclined part at a side of the input surface and a second inclined part at a side of the output surface. The first inclined part and the second inclined part define a projecting portion that is projected on the outer peripheral portion. | 2013-05-16 |
20130121010 | Automobile Light Covering Device and Method - Disclosed is a vehicular communication method and device that displays a message when a vehicle light source is energized, sending the message to nearby motorists. The device increases good-will between drivers or alternatively provides a directed message to other drivers. A vehicle light, such as a rear brake light, turn signal or emergency vehicle light includes a housing having an outer translucent panel. The panel includes an etched or overlaid message such that a message is visualized when the internal light is energized. The message is readily visualized without compromising the luminosity of the lamp or the amount of light required under state and federal vehicle regulations. An embodiment includes a message that is adhered over an existing vehicle light housing using an adhesive film, while another embodiment contemplates the outer panel including the message in its construction. | 2013-05-16 |
20130121011 | VEHICLE LAMP WITH LIGHT-EMITTING DIODE AS LIGHT SOURCE - A vehicle lamp having a housing and an illumination unit arranged within the housing is provided. The illumination unit comprises at least one light-emitting diode as light source. The at least one light-emitting diode is thermally coupled to a cooling element. The cooling element has a surface region arranged within the housing. On the surface region a decorative element is arranged. | 2013-05-16 |
20130121012 | VEHICLE HEADLIGHT - A vehicle headlight can facilitate an earlier awareness with peripheral vision under dark environment (such as during nighttime, tunnel, or adverse weather driving). The light source can include a plurality of white LEDs. The plurality of white LEDs include a first white LED and a second white LED. The first white LED has an S/P ratio, which is represented by (S(λ)*V′(λ))/(S(λ)*V(λ)) in which S(λ) is a spectrum of the first light source, V′(λ) is a relative luminosity factor in scotopic vision, and V(λ) is a relative luminosity factor in photopic vision, lower than that of the second white LED. | 2013-05-16 |
20130121013 | VEHICULAR HEADLAMP AND REPLACEMENT METHOD FOR LEVELING ACTUATOR OF THE VEHICULAR HEADLAMP - A vehicular headlamp includes: a bracket having an actuator attaching portion that has a first fixation portion and a second fixation portion and part of which is a cuttable portion; a first actuator that is attached to the actuator attaching portion from one direction and is fixed via the first fixation portion; and a lamp unit that is supported by the bracket and that is capable of being tilted relative to the bracket by drive force of the first actuator. The actuator attaching portion is configured so that the cuttable portion can be cut off to detach the first actuator from the bracket in another direction than the one direction and a second actuator can be attached to the actuator attaching portion from the another direction and fixed to the actuator attaching portion via the second fixture portion. | 2013-05-16 |
20130121014 | CARBODIIMIDE PHOSPHORS - The invention relates to carbodiimide compounds of the general formula (I) EA | 2013-05-16 |
20130121015 | Wearable Band With Variable Light Display - Various wearable bands capable of being illuminated are disclosed. A wearable band includes a band strip defining multiple openings therein, a light source, and multiple optical fibers. Each optical fiber has a first end and a second end, with the first end of each optical fiber operably coupled to the light source. Each optical fiber is configured to transmit light originating from the light source toward the second end. Light transmitted along each optical fiber is visible through a corresponding opening of the wearable band. The openings may be arranged to form at least one letter or symbol, may be arranged along an outline of a decoration on the band strip, may be arranged to fill a region within at least one letter or symbol located on the band strip, and/or may be arranged to enhance and be conformal with a graphical design located on the band strip. | 2013-05-16 |
20130121016 | OPTICAL FILM HAVING IMPROVED OPTICAL PERFORMANCE, AND BACKLIGHT UNIT COMPRISING THE SAME - The present invention relates to an optical film having improved optical performance and to a backlight unit comprising the same. More particularly, the present invention relates to a microlens array (MLA) sheet which comprises a base unit and a lens unit formed on one side of the base unit, wherein the lens unit consists of a plurality of conical lenses. Existing hemispherical microlens array sheets have limitations in terms of improving luminance, and therefore cannot replace prism sheets in high luminance products. However, the microlens array sheet consisting of conical lenses of the present invention can improve both luminance and viewing angle characteristics. | 2013-05-16 |
20130121017 | ILLUMINANT KEYBOARD DEVICE - A illuminant keyboard device includes a bottom frame having a plurality of latch parts, a plurality of keying units disposed on the bottom frame, a membrane switch interposed between the bottom frame and the keying units, a first light guide plate interposed between the membrane switch and the bottom frame, a least a light source disposed on predetermined position of the first light guide plate, a second light guide plate interposed between the membrane switch and the first light guide plate and a light-shielding plate interposed between the membrane switch and the keying units. The first light guide plate has a plurality of first holes and the second light guide plate has a plurality of second holes, an aperture of the first holes is larger than an aperture of the second holes. | 2013-05-16 |
20130121018 | DIFFUSION SHEET, BACKLIGHT, LIQUID CRYSTAL DISPLAY APPARATUS, AND METHOD OF PRODUCING A DIFFUSION SHEET - A diffusion sheet includes a light-transmissive substrate, a plurality of structures, and a flat portion. The light-transmissive substrate includes a first main surface, and a second main surface. The plurality of structures have convex shapes and are randomly formed on the first main surface. The flat portion is formed among the plurality of structures on the first main surface and has a surface roughness (Ra) of no less than 0.9 μm. | 2013-05-16 |
20130121019 | Frontlight unit for reflective displays - The frontlight unit is intended for enhancing illumination of a reflective display having pixels arranged in a matrix pattern and using monochromatic laser lights as light sources. The unit contains a network of light-distribution planar ridge waveguides with holograms arranged in a matrix pattern that corresponds to the matrix pattern of the reflective display when it is applied onto this display and emits light in the downward direction in the form of diverging beams that fall onto the pixels of the reflective display and in the upward direction onto mirrors wherefrom light is reflected also in the form of diverging beams onto the reflective display. Thus, all of the light reflected from the holograms of the light-distribution planar ridge waveguides is not lost and is used entirely for illumination of the reflective display. The mirrors occupy no more than 5% of the display surface area. | 2013-05-16 |
20130121020 | BACK-LIGHT MODULE - A back-light module including a light guide plate (LGP), first light-emitting devices, and second light-emitting devices is provided. The LGP has a top-emitting surface, a bottom surface and a side surface. The LGP has at least one indentation. The indentation has a first light-incident sidewall and a pair of second light-incident sidewalls. The second light-incident sidewalls are located on two sides of the first light-incident sidewall and adjacent to the first light-incident sidewall. Normal vectors of the second light-incident sidewalls and the first light-incident sidewall are not parallel. The first light-emitting devices are located in the indentation, and a first light beam propagating toward the first light-incident sidewall is emitted from each of the first light-emitting devices. The second light-emitting devices are located in the indentation, and a second light beam propagating toward one of the second light-incident sidewalls is emitted from each of the second light-emitting devices. | 2013-05-16 |
20130121021 | COMPOSITE OPTICAL FILM AND BACKLIGHT MODULE USING THE SAME - The present disclosure provides a composite optical film including a brightness enhancement film, a high refractive-index layer, and an intermediate layer. The brightness enhancement film has a plurality of brightness enhancement structures parallel to each other, and a top surface and a bottom surface opposite to each other. The brightness structures are disposed on the top surface. The high refractive-index layer is disposed on the bottom surface, and includes a film and a plurality of inorganic nano-particles disposed within the film. The intermediate layer is disposed between the brightness enhancement film and the high refractive-index layer. | 2013-05-16 |
20130121022 | OPTICAL SHEET HAVING IMPROVED DURABILITY, AND BACKLIGHT UNIT COMPRISING SAME - A durability-enhanced optical sheet and an edge-type backlight unit having the optical sheet. The edge-type backlight unit includes a light source unit that includes a plurality of light sources, a light guide unit that is disposed adjacently to the light source unit and controls a path of light generated from the light source unit, a diffusion sheet disposed on the light guide plate, and an optical sheet that is disposed on the diffusion sheet and includes a lens unit and a non-lens unit, wherein the non-lens unit includes a first base unit, a second base unit, and a bonding layer for bonding the first and second base units. The optical sheet includes two base unit layers, and thus, sheet waves that can be caused due to heat can be prevented, modulus can be increased, and durability of the optical sheet can be enhanced. | 2013-05-16 |
20130121023 | BACKLIGHT UNIT AND DISPLAY APPARATUS THEREOF - A backlight unit and a display device having the same are provided. The backlight unit includes a light source, a reflector arranged on and under the light source to totally reflect at least a part of light emitted from the light source in a lateral direction, a reflective sheet arranged under the reflector, and a diffusion sheet arranged on the reflector. | 2013-05-16 |
20130121024 | PLANAR LIGHT GUIDE AND LIGHTING DEVICE - A planar light guide includes a main body with a back face and a radiation outcoupling face opposite thereto, a main direction of light guidance parallel to the radiation outcoupling face, at least one plurality of identically shaped and identically oriented outcoupling structures formed on at least one of the main faces, and at least one structure main face per outcoupling structure, wherein an angle-dependent emission characteristic is provided asymmetrically in a first plane parallel to the main direction of light guidance and perpendicular to the radiation outcoupling face. | 2013-05-16 |
20130121025 | BACKLIGHT MODULE - A backlight module includes a light guide plate and a light emitting unit. The light guide plate has a first side surface, a second side surface, and a third side surface. The first side surface is located opposite to the second side surface. A height of the first side surface is greater than a height of the second side surface. The third side surface is located between the first side surface and the second side surface and has a light entrance surface and a light exit surface. The light entrance surface is connected to the first side surface and the light exit surface. The light exit surface is connected to the second side surface. An included angle is formed between the light entrance surface and the light exit surface. The light emitting unit is disposed on the light entrance surface. | 2013-05-16 |
20130121026 | DISPLAY DEVICE - According to one embodiment, a display device includes: a plurality of light guide units; a light source; a support substrate; a first electrode transmissive to light provided on the second major surface; a counter substrate opposed to the second major surface and provided away from the first electrode; a second electrode transmissive to light provided on a surface of the counter substrate opposed to the second major surface; and a plurality of spacers provided between the support substrate and the counter substrate and arranged between adjacent ones of the plurality of light guide units when projected onto a plane parallel to the first direction and the second direction. Optical characteristics in a region which is surrounded by adjacent ones of the spacers, the first electrode and the second electrode are changed by a voltage which is applied between the first electrode and the second electrode. | 2013-05-16 |
20130121027 | LIGHT SOURCE DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPARATUS - A light source device includes: a first light source emitting first illumination light; a light guide plate including a plurality of scattering areas each allowing the first illumination light that has entered the light guide plate through a side surface thereof to be scattered and to exit therethrough; a second light source disposed to face the light guide plate, and emitting second illumination light toward the light guide plate from a direction different from a light emitting direction of the first light source; and light shields arranged between the light guide plate and the second light source at positions other than positions corresponding to the plurality of scattering areas, each of the light shields blocking the second illumination light. | 2013-05-16 |
20130121028 | LIGHT GUIDE PLATE WITH MICRO-DOTS - A light guide plate includes an incident surface, an emergent surface substantially perpendicular to the incident surface, a bottom surface opposite to the emergent surface, and a number of micro-dots positioned on the bottom surface. The micro-dots have similar shape and size. A density of the micro-dots gradually increases from a near-end to a far-end of the incident surface. | 2013-05-16 |
20130121029 | Connecting an Inverter in a Solar Power Plant with Shifted Potential Center Point - The invention relates to a process of connecting an AC output of a transformerless inverter of a solar power plant to an internal AC power grid at an input side of a galvanic isolation, while an offset voltage for shifting a potential center point of a photovoltaic generator connected to the inverter is applied. The process includes: (i) synchronizing the inverter with the power grid; (ii) essentially matching a potential center point of the current-carrying lines of the AC output and a potential center point of the power grid, while only one of the potential center points of the current-carrying lines and the power grid is yet shifted by the offset voltage; and (iii) galvanically connecting all current-carrying lines of the AC output with the power grid only after the steps of synchronizing and essentially matching. | 2013-05-16 |
20130121030 | APPARATUS AND METHOD FOR SOFT SWITCHING IN A MEDIUM VOLATAGE TO LOW VOLTAGE CONVERTER - A switching and control arrangement are provided along with a transformer arrangement such that semiconductor-based switches can be used in a medium DC voltage to AC inverter in a medium voltage to low voltage DC to DC converter. The switching arrangement on the secondary side of the transformer arrangement controls a current ramp up or down of switches on the primary side of the transformer that are used to convert DC to AC, thereby permitting for soft switching of those switches. | 2013-05-16 |
20130121031 | MANAGEMENT OF COMMON MODE NOISE FREQUENCIES IN PORTABLE ELECTRONIC DEVICES - The disclosed embodiments provide a system that facilitates the use of a portable electronic device. During operation, the system detects a coupling of a power supply to the portable electronic device through a set of wires. Next, the system uses the set of wires to identify a type of the power supply. The system then periodically determines a switching frequency of the power supply based on the type of the power supply and a current drawn from the power supply. Finally, the system uses the switching frequency to facilitate the operation of a touch control in the portable electronic device. For example, if the switching frequency corresponds to a sensing frequency of the touch control, the system may change the sensing frequency to an alternative sensing frequency. | 2013-05-16 |
20130121032 | POWER SUPPLY REGULATION FOR ULTRA-LOW LOAD AND NO-LOAD OPERATION - A controller of a switching power converter employs a dynamically adaptive power supply regulation approach that improves low-load and no-load regulation to achieve ultra-low standby power in a switching power converter. Under ultra-low load conditions when a deep-deep pulse width modulation (DDPWM) is applied, the controller decreases the actual on-time of the power switch of the switching power converter by decreasing the “on” duration of the control signal used to turn on or off the power switch, until the “on” duration of the control signal reaches a minimum value. To further reduce the on-time of the power switch, the controller reduces the power applied to the power switch to turn on the switch more slowly, while maintaining the “on” duration of the control signal at a minimum value. The minimum value of the “on” duration of the control signal and the minimum power applied to the switch are dynamically controlled. | 2013-05-16 |
20130121033 | DC-DC CONVERTER CIRCUIT USING LLC CIRCUIT IN THE REGION OF VOLTAGE GAIN ABOVE UNITY - The present invention provides a series of DC-DC converter circuit designs, and DC-DC converters based on such circuit design, that provide high input-to-output voltage conversion. The converters include a resonant tank and a means for interrupting the tank current to produce a near zero-loss “hold” state wherein zero current and/or zero voltage switching is provided, while providing control over the amount of power transfer. A resonant DC-DC converter for high voltage step-up ratio in accordance with the circuit design includes: (a) a low voltage DC-AC converter, (b) a resonant tank, (c) a high voltage AC-DC converter, (d) a (i) common ground on an input and an output without use of a transformer and/or (ii) a single high voltage controllable switch within the resonant tank. | 2013-05-16 |
20130121034 | DC-DC Converter - A DC-DC converter is configured with a voltage-source power converter at a primary side of a transformer, a current-source power converter at a secondary side of the transformer, and a controller. First and second voltage detection circuits respectively detect first and second voltages of the voltage-source and the current-source power converters. A current detection circuit detects an input-output current of the current-source power converter. The controller controls the voltage-source and the current-source power converters to transfer power between the primary side and the secondary side of the transformer. The controller includes a calculation unit that performs calculations based on the first voltage, the second voltage and the input-output current, and a table unit that include a plurality of parameter sets. The calculation unit performs the calculations based on one of the plurality of parameter sets that is selected from the table unit. | 2013-05-16 |
20130121035 | ULTRA LOW STANDBY CONSUMPTION IN A HIGH POWER POWER CONVERTER - A power converter includes a dc input having first and second terminals. A main converter is coupled to the first terminal of the dc input. A standby circuit coupled to the second terminal of the dc input and the main converter. The main converter is coupled to control a transfer of energy from the dc input through the standby circuit to a main output of the main converter during a normal operating condition of the power supply. The standby circuit is coupled to decouple the main converter from the second terminal of the dc input during a standby operating condition of the power converter. A standby converter is coupled to the first and second terminals of the dc input to control a transfer of energy from the dc input to a standby output of the standby converter during the standby operating condition of the power converter. | 2013-05-16 |
20130121036 | RESONANT CONVERTING CIRCUIT AND RESONANT CONTROLLER - The resonant converting circuit comprises a resonant circuit, a current detecting circuit and the resonant controller. The resonant controller controls a power conversion of the resonant circuit for converting an input voltage into an output voltage and the resonant controller comprises an over current judgment unit and an over current protection unit. The over current judgment unit determines whether the resonant current is higher than an over current value according to a current detecting signal generated by the current detecting circuit. The over current protection unit generates a protection signal in response to a determined result of the over current judgment unit and an indication signal indicative of an operating state of the resonant controller. The resonant controller executes a corresponding protecting process in response to the protection signal. | 2013-05-16 |
20130121037 | Resonant Converting Circuit and Resonant Controller - A current detecting circuit detects a resonant current in a primary side of a resonant converting circuit to generate a current detecting signal. An output detecting circuit generates a feedback signal according to the output voltage. A resonant controller generates a clock signal and adjusts an operating frequency of the clock signal in response to the feedback signal for modulating the output voltage of the resonant circuit. The resonant controller includes a resonance deviation protection unit which detects the current detecting signal according to a phase of the clock signal to determine whether the resonant circuit enters a region of zero current switching or not. When the resonant circuit enters the region of zero current switching, the resonant controller executes a corresponding protection process in response to that the resonant controller operates in a starting mode or a normal operating mode. | 2013-05-16 |
20130121038 | CONVERTER, METHOD FOR CONTROLLING THE SAME, AND INVERTER - Disclosed herein are a converter, a method for controlling the same, and an inverter. The converter includes: an input terminal having power input thereto; a first converter unit converting the power input to the input terminal to thereby output the converted power to an output terminal; and a second converter unit connected between the input terminal and the output terminal while being in parallel with the first converter unit, wherein each of the first and second converter units includes an active clamp unit provided at a primary side thereof and a synchronous rectifying unit provided at a secondary side thereof. | 2013-05-16 |
20130121039 | SWITCHING AMPLIFIER WITH PULSED CURRENT SUPPLY - A switching amplifying method or a switching amplifier for obtaining one or more than one linearly amplified replicas of an input signal, is highly efficient, and does not have the disadvantage of “dead time” problem related to the class D amplifiers. Said switching amplifying method comprises the steps of: receiving the input signal; pulse modulating the input signal for generating a pulse modulated signal; switching a pulsed current from a direct current (DC) voltage according to the pulse modulated signal; conducting said pulsed current positively or negatively to a filter according to the polarity of the input signal; filtering said pulsed current positively or negatively conducted to the filter for outputting an output signal by the filter. | 2013-05-16 |
20130121040 | METHOD AND APPARATUS TO REGULATE AN OUTPUT VOLTAGE OF A POWER CONVERTER AT LIGHT/NO LOAD CONDITIONS - An example controller for a primary side control power converter includes a feedback circuit, a driver circuit, and an adjustable voltage reference circuit. The feedback circuit compares a feedback signal representative of a bias winding voltage of the power converter with a voltage reference. The driver circuit outputs a switching signal having a switching period to control a switch to regulate an output of the power converter in response to the feedback signal and enables or disables a switching period based on the output of the feedback circuit. The adjustable voltage reference circuit adjusts the voltage reference by a first amount in response to a first number of disabled switching periods indicating a first load condition at the output of the power converter and by a second amount in response to a second number of disabled switching periods indicating a second load condition at the output of the power converter. | 2013-05-16 |
20130121041 | POWER CONVERTER BASED ON H-BRIDGES - A power converter includes an active front end (AFE) that is coupled by a dc link stage to a plurality of H-bridge inverters. One or more multi-phase electro-magnetic energy conversion devices, such as transformers or electric machines, with open windings that are connected to only the AFE or only the H-bridge inverters or to both the AFE and H-bridge inverters, provide a regenerative or partial regenerative power converter. | 2013-05-16 |
20130121042 | CASCADED H-BRIDGE MEDIUM VOLTAGE DRIVE, POWER CELL AND BYPASS MODULE THEREOF - The present application relates to a cascaded H-Bridge medium voltage drive, a power cell, and a bypass module thereof, wherein the bypass module is configured for bypassing a major circuit module of the power cell, while the major circuit module comprises a fuse, a rectifier, a bus capacitor and an H-Bridge inverter, two points led from the H-Bridge inverter being configured as a first output end and a second output end; a bypass circuit comprises a first bridge arm and a second bridge arm; a point led from the first bridge arm is configured as a first input end of the bypass circuit, a point led from the second bridge arm is configured as a second input end of the bypass circuit, and the first input end is electrically connected with the first output end, the second input end is electrically connected with the second output end. | 2013-05-16 |
20130121043 | HARMONIC CANCELLING INTERPHASE MAGNETIC DEVICE - A harmonic cancelling interphase magnetic device ( | 2013-05-16 |
20130121044 | Power Converter Controller IC Having Pins with Multiple Functions - A controller integrated circuit (IC) for controlling a power converter uses one or more IC pins having plurality of functions such as configuration of a parameter supported by the controller IC and shutdown protection. Several different functions may be supported by a single IC pin, thereby reducing the number of pins required in the controller IC and also reducing the cost of manufacturing the controller IC. The controller IC may also share a comparison circuit among different pins and the different functions provided by those pins. Use of a shared comparison circuit further reduces the cost of manufacturing the controller IC without sacrificing the performance of the IC. | 2013-05-16 |
20130121045 | POWER CONVERSION APPARATUS - An inverter circuit is connected in series to an AC power supply, and at the subsequent stage, a smoothing capacitor is connected via a converter circuit including semiconductor switching devices. A control circuit controls the converter circuit by providing a short-circuit period for bypassing the smoothing capacitor in each cycle, and controls the inverter circuit to improve the power factor of the AC power supply by using a current instruction such that the voltage of the smoothing capacitor becomes a target voltage. When the voltage of a DC voltage source of the inverter circuit has exceeded a predetermined upper limit, the control circuit increases the current instruction to control the inverter circuit, thereby increasing the discharge amount of the DC voltage source. Thus, even if the voltage variation of the DC voltage source of the inverter circuit increases, it is possible to stably continue the control. | 2013-05-16 |
20130121046 | PHASE LOCKING SYSTEM FOR THREE-PHASE ALTERNATING CURRENT ELECTRIC GRID AND METHOD THEREOF - A phase locking system for a three-phase alternating current (AC) electric grid and a method thereof are disclosed. The method includes: receiving a three-phase voltage of the AC electric grid and converting the three-phase voltage to a two-phase voltage signal, each of which including a positive and a negative sequence components; obtaining a pure positive sequence component by subtracting the negative sequence component from the voltage signal of each phase and using αβ/dq coordinate transformation and low-pass filtering, and phase locking the pure positive sequence component; and obtaining an error signal by subtracting a disturbance variable and subsequently subtracting the positive sequence component from the voltage signal of each phase, wherein the disturbance variable includes the negative sequence component, and obtaining a signal including the negative sequence component by performing a α-β/d-q coordinate transformation on the error signal and adjusting the error signal through a regulator. | 2013-05-16 |
20130121047 | ACTIVE POWER FACTOR CORRECTION CIRCUIT AND RELATED PFC CONTROLLER - An active power factor correction (PFC) circuit for calibrating a power factor of an AC-to-DC converter when the active PFC circuit is coupled with the AC-to-DC converter is disclosed including: a piecewise linear gain circuit, an error amplifier, a PWM controller, and a PWM signal generator. The piecewise linear gain circuit is for receiving a feed forward signal and generating a corresponding gain signal, wherein the gain signal and the feed forward signal have a broken line relation with respect to magnitude. The error amplifier is for generating an error signal according to an output voltage of the AC-to-DC converter. The PWM controller is for generating a control signal according to the gain signal and the error signal. The PWM signal generator is for generating a PWM signal for controlling a power switch of the AC-to-DC converter according to the control signal. | 2013-05-16 |
20130121048 | Wide Input Voltage Range Power Supply Circuit - A wide input voltage power supply circuit for a load includes a first regulation stage and a second regulation stage. The first regulation stage includes a linear regulator circuit configured to maintain a bus voltage within a predefined voltage range when an input voltage exceeds a predefined input level. A second regulation stage includes a buck converter circuit configured to regulate an average bus voltage to a predetermined load level. The second regulation stage includes an under voltage lockout configuration, with the under voltage lockout configured to set a minimum turn-on voltage for the load. | 2013-05-16 |
20130121049 | EMI Frequency Spreading Method for Switching Power Converter - A controller of a switching power converter sets an actual turn-on time of a switch in the switching power converter in each switching cycle by selecting one of a plurality of valley points of the output voltage of the switching power converter occurring subsequent to the desired turn-on time of the switch. The desired turn-on time of the switch may be calculated according to the regulation scheme employed by the switching power converter. The controller selects one of the plurality of valley points randomly from switching cycle to switching cycle. The controller generates a control signal to turn on the switching power converter at the selected one of the plurality of valley points of the output voltage occurring subsequent to the desired turn-on time. | 2013-05-16 |
20130121050 | INTEGRATED MAGNETIC DEVICE FOR LOW HARMONICS THREE-PHASE FRONT-END - An integrated magnetic for a low harmonics three-phase bidirectional front-end and also for AC/DC and DC/AC power converters. Its use enables reduction of the harmonics of the currents absorbed or injected to three-phase power line by using only one device which integrates a splitter and an inductor function. Compared to known solutions, cost, material and dimensions of the integrated magnetic device are reduced thanks to the magnetic core comprising three closed sub-assemblies and one or more jokes, separated by air-gaps from the sub-assemblies. | 2013-05-16 |
20130121051 | DC PRE-CHARGE CIRCUIT - Systems and methods are provided for pre-charging the DC bus on a motor drive. Pre-charging techniques involve pre-charge circuitry including a manual switch, an automatic switch, and pre-charge control circuitry to switch the automatic switch between pre-charge and pre-charge bypass modes in response to an initialized pre-charge operation, input voltage sags, and so forth. In some embodiments, the pre-charge operation may be initialized by switching the manual switch closed. In some embodiments, the pre-charge operation may also be initialized by a detected voltage sag on the DC bus. The pre-charge circuitry may also be configured to disconnect to isolate a motor drive from the common DC bus under certain fault conditions. | 2013-05-16 |
20130121052 | ELECTRIC POWER CONVERTER HAVING PLURALITY OF SEMICONDUCTOR MODULES ARRAYED IN SUCCESSIVE LAYERS - In an electric power converter, a stacked-layer unit has a plurality of semiconductor modules arrayed as layers along a stacking direction, each semiconductor module containing a semiconductor element and a pair of power terminals protruding outward in a protrusion direction at right angles to the stacking direction, each pair consisting of an AC terminal and a positive-polarity or negative-polarity power terminal. The semiconductor modules are arranged with the positive-polarity and negative-polarity power terminals in a single column at one side of the stacked-layer unit, and respectively connected to a positive-polarity busbar and negative-polarity busbar which are located at that side and which are separated by a fixed spacing in the protrusion direction, while the AC terminals of each layer-adjacent pair of semiconductor modules are connected in common to a corresponding one of a plurality of AC busbars. | 2013-05-16 |
20130121053 | METHODS AND CIRCUITS FOR LIMITING BIT LINE LEAKAGE CURRENT IN A CONTENT ADDRESSABLE MEMORY (CAM) DEVICE - A content addressable memory (CAM) device can include a number of bit lines. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data values. An isolation circuit car have a controllable impedance path connected between the bit line and a precharge voltage node and can be controlled by application of a potential at a control node. A control circuit can be coupled to the control node and can switch the isolation circuit from a high impedance state to a low impedance state prior to, and for a duration of at least of a portion of an access operation. | 2013-05-16 |
20130121054 | THREE-DIMENSIONAL INTEGRATED CIRCUIT - A three-dimensional integrated circuit comprising a submicroscale integrated-circuit substrate and n nanoscale layers stacked above the submicroscale integrated-circuit substrate, a nanowire-junction memory element in each of which is independently controlled by two submicroscale subcomponents within the submicroscale integrated-circuit substrate, the first submicroscale subcomponent coupled through a first set of switches to each of the n nanowire-junction memory elements and the second submicroscale subcomponent coupled through a second set of switches to each of the n nanowire-junction memory elements, the total number of switches in the first and second sets of switches less than 2n, and n greater than or equal to 2. | 2013-05-16 |
20130121055 | WORD LINE DRIVER CELL LAYOUT FOR SRAM AND OTHER SEMICONDUCTOR DEVICES - A word line driver cell suitable for RAM devices such as SRAM, static random access memory devices, is provided. The word line driver cell is compatible with double pattern processing techniques and enables the formation of all word lines from a single metal layer which, in turn, enables overlying and underlying metal levels to be used for other features such as signal lines for word line decoders. A power mesh is formed using multiple metal layers and the formation of all the word lines from a single metal layer enables VDD and VSS power lines that are formed from an overlying layer to extend orthogonal to the cell direction and include wider widths reducing metal line resistance and increasing the deliverable power. | 2013-05-16 |
20130121056 | APPARATUSES AND OPERATION METHODS ASSOCIATED WITH RESISTIVE MEMORY CELL ARRAYS WITH SEPARATE SELECT LINES - The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line. | 2013-05-16 |
20130121057 | RESISTOR THIN FILM MTP MEMORY - An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell. | 2013-05-16 |
20130121058 | CIRCUIT AND METHOD FOR CONTROLLING WRITE TIMING OF A NON-VOLATILE MEMORY - A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching. | 2013-05-16 |
20130121059 | MULTI-VALUED LOGIC DEVICE HAVING NONVOLATILE MEMORY DEVICE - A multi-valued logic device having an improved reliability includes a conversion unit configured to convert a multi level signal into a plurality of partial signals; and a plurality of nonvolatile memory devices configured to individually store the plurality of partial signals, wherein a number of bits of each of the plurality of partial signals individually stored in the plurality of nonvolatile memory devices is less than the number of bits of the multi level signal. | 2013-05-16 |
20130121060 | NON-VOLATILE MEMORY ELEMENTS AND MEMORY DEVICES INCLUDING THE SAME - Non-volatile memory elements, memory devices including the same, and methods for operating and manufacturing the same may include a memory layer between a first electrode and a second electrode spaced apart from the first electrode. The memory layer may include a first material layer and a second material layer, and may have a resistance change characteristic due to movement of ionic species between the first material layer and the second material layer. At least the first material layer of the first and second material layers may be doped with a metal. | 2013-05-16 |
20130121061 | NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL - A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state, wherein the second programmed resistivity state stores a data state of the memory cell. Numerous other aspects are provided. | 2013-05-16 |
20130121062 | REWRITING A MEMORY ARRAY - A method for rewriting a memory array ( | 2013-05-16 |
20130121063 | MEMORY DEVICE, SEMICONDUCTOR STORAGE DEVICE, METHOD FOR MANUFACTURING MEMORY DEVICE, AND READING METHOD FOR SEMICONDUCTOR STORAGE DEVICE - A memory device that can prevent degradation in characteristics of a diode and the destruction due to the miniaturization includes: a substrate; first electrodes, a second electrode, and a third electrode that are stacked above the substrate; a variable resistance layer between the first and second electrodes; and a non-conductive layer between the second and third electrodes. The variable resistance layer includes a high-concentration variable resistance layer closer to the first electrodes, and a low-concentration variable resistance layer closer to the second electrode and having an oxygen concentration lower than that of the high-concentration variable resistance layer. The second and third electrodes and the non-conductive layer comprise the diode, and the first and second electrodes and the variable resistance layer comprise variable resistance elements, a total number of which is equal to that of the first electrodes. | 2013-05-16 |
20130121064 | Memory Based Illumination Device - The invention contained herein provides electrical circuits and driving methods to operate a memory cell comprising a capacitance coupled to a breakover conduction switch such as a thyristor, DIAC or one or more complementary transistor pairs. The memory cell comprises a cell capacitance for storing a memory state and for capacitively coupling an applied voltage to the switch. During operation, pulses are applied to write, read or maintain the cell's memory state. An illumination cell comprises an LED, OLED or electroluminescent material in series with each memory cell. Breakover conduction charge passes through the switch and the emissive element to charge the cell capacitance. A memory array of breakover conduction memory cells may be organized into rows and columns for reading and writing an addressable array memory cells. An organic light emitting display memory array may be fabricated using organic light emitting devices and/or materials. | 2013-05-16 |
20130121065 | DYNAMIC WORDLINE ASSIST SCHEME TO IMPROVE PERFORMANCE TRADEOFF IN SRAM - A dynamic wordline assist circuit for improving performance of an SRAM. An SRAM is disclosed that includes a plurality of memory cells, wherein each memory cell is coupled to a wordline and a pair of bitlines; and a wordline assist circuit coupled to the wordline, wherein the wordline assist circuit includes a first input for activating the wordline assist circuit during a read or write cycle and includes a second input for deactivating the wordline assist circuit during the read or write cycle after a delay. | 2013-05-16 |
20130121066 | CIRCUIT AND METHOD FOR GENERATING A REFERENCE LEVEL FOR A MAGNETIC RANDOM ACCESS MEMORY ELEMENT - A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a first value indicative of a resistance between the first node and the second node, and setting the reference level based at least in part on the measured value. Also an associated reference circuit. | 2013-05-16 |
20130121067 | HIGH SPEED LOW POWER MAGNETIC DEVICES BASED ON CURRENT INDUCED SPIN-MOMENTUM TRANSFER - A high speed, low power method to control and switch the magnetization direction and/or helicity of a magnetic region in a magnetic device for memory cells using spin polarized electrical current. The magnetic device comprises a reference magnetic layer with a fixed magnetic helicity and/or magnetization direction and a free magnetic layer with a changeable magnetic helicity and/or magnetization direction. The fixed magnetic layer and the free magnetic layer are preferably separated by a non-magnetic layer. The fixed and free magnetic layers may have magnetization directions at a substantially non-zero angle relative to the layer normal. A current can be applied to the device to induce a torque that alters the magnetic state of the device so that it can act as a magnetic memory for writing information. The resistance, which depends on the magnetic state of the device, is measured to read out the information stored in the device. | 2013-05-16 |
20130121068 | MAGNETIC MEMORY CELL - The disclosed subject matter relates to a non-volatile memory bit cell ( | 2013-05-16 |
20130121069 | INTERNAL VOLTAGE GENERATING CIRCUIT OF PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD THEREOF - An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal. | 2013-05-16 |
20130121070 | Memory Device - A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor. | 2013-05-16 |
20130121071 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while a well containing the memory cells receives a positive voltage. A selected memory cell in the well can be biased with a negative voltage while the well is at the positive voltage then the selected memory cell bias transitions to a positive programming voltage when the well returns to a ground potential. | 2013-05-16 |
20130121072 | METHOD FOR NON-VOLATILE MEMORY WITH BACKGROUND DATA LATCH CACHING DURING READ OPERATIONS - Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles. | 2013-05-16 |
20130121073 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. | 2013-05-16 |
20130121074 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. | 2013-05-16 |
20130121075 | SYSTEMS AND METHODS FOR OPERATING MULTI-BANK NONVOLATILE MEMORY - A non-volatile memory system that has multiple memory banks initially assigns logical addresses to memory banks according to an assignment scheme, maintains this assignment for a period of time, then identifies frequently-written data (“hot-data”) assigned to a memory bank that is heavily worn over that period of time and reassigns it to a less worn memory bank. | 2013-05-16 |
20130121076 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block. | 2013-05-16 |
20130121077 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential higher than the read potential is applied to the word line in the first block in a state that a ground potential is applied to a channel of a memory cell existing nearer to the bit line side than a memory cell in the second cell unit to which the read potential is applied, after which all the memory cells in the second cell unit are cut off from the bit line, the bit line is set to a precharge potential, and read is performed to the a memory cell to be read in the first cell unit. | 2013-05-16 |
20130121078 | THREE-DIMENSIONAL ARRAY OF RE-PROGRAMMABLE NON-VOLATILE MEMORY ELEMENTS HAVING VERTICAL BIT LINES AND A SINGLE-SIDED WORD LINE ARCHITECTURE - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line. | 2013-05-16 |
20130121079 | NOR FLAH MEMORY CELL AND STRUCTURE THEREOF - The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a first transistor, a second transistor and at least one third transistor. The first transistor has a control terminal, a first terminal and a second terminal. The control terminal used to receive a word line signal and the first terminal used to receive a bit line signal. A gate of the first transistor comprises a silicon-rich nitride layer and an oxide layer, wherein the silicon-rich nitride layer is buried in the oxide layer. A control terminal of the second transistor used to receive a read signal. A second terminal of the second transistor used to transport a source line signal according to the read signal. The third transistor coupled between the first transistor and the bit line signal, and a control terminal of the third transistor receives a midway control signal. | 2013-05-16 |
20130121080 | Adaptive Estimation of Memory Cell Read Thresholds - A method for operating a memory ( | 2013-05-16 |
20130121081 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; an inner insulating film provided between the memory layer and the semiconductor pillar; an outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In an erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential. | 2013-05-16 |
20130121082 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes determining whether a program operation is performed on even memory cells coupled to even bit lines of a selected page, setting a coupling resistance value between odd bit lines of the selected page and page buffers depending on whether the program operation for the even memory cells is performed, performing a program operation on the odd memory cells coupled to the odd bit lines, and coupling the odd bit line to the page buffer based on the set coupling resistance value and performing an verification operation for verifying whether threshold voltages of the odd memory cells on which the program operation is performed are a target voltage or more. | 2013-05-16 |
20130121083 | NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME - In one embodiment, the method includes detecting a noise level of a common source line, and adjusting a frequency of program-verify operations on a memory cell during a programming loop based on the detected noise level. | 2013-05-16 |
20130121084 | METHOD AND APPARATUS TO PROVIDE DATA INCLUDING HARD BIT DATA AND SOFT BIT DATA TO A RANK MODULATION DECODER - A method includes providing data including hard bit data and soft bit data to a rank modulation decoder. | 2013-05-16 |
20130121085 | Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate - A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions. | 2013-05-16 |
20130121086 | Memory Configured to Provide Simultaneous Read/Write Access to Multiple Banks - A memory includes at least first and second banks of single-port memory elements, a first local controller adapted to send read and write instructions to the first memory bank, and a second local controller adapted to send read and write instructions to the second memory bank. A global controller is configured to receive first and second memory addresses and a first indication of an operation to be performed at the first memory addresses and a second indication of an operation to be performed at the second memory address and to instruct the first local controller to perform the first indicated operation at the first memory address and to instruct the second local controller to perform the second indicated operation at the second memory address at the same time. | 2013-05-16 |
20130121087 | SEMICONDUCTOR MANUFACTURING METHOD - A memory bit cell includes a latch, a write port coupled to the latch, and a read port coupled to the latch. The write port includes a first set of devices having a first threshold voltage and a second set of devices having a second threshold voltage that is greater than the first threshold voltage. The read port includes a third set of devices having a third threshold voltage that is less than the first threshold voltage. | 2013-05-16 |
20130121088 | MEMORY WORD LINE BOOST USING THIN DIELECTRIC CAPACITOR - A memory including a boost circuit configured to supply a voltage higher than a supply voltage to a word line. The boost circuit includes a first capacitor having a first capacitor dielectric thickness. The boost circuit further includes a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness. | 2013-05-16 |
20130121089 | SYSTEMS AND METHODS FOR REDUCING PEAK POWER CONSUMPTION IN A SOLID STATE DRIVE CONTROLLER - In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power consumption in a device. The first signal is combined with the second signal to generate a combined signal, and at least a portion of the second signal is shifted in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal. | 2013-05-16 |
20130121090 | SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE APPARATUS INCLUDING THE SAME - A semiconductor memory device includes memory cells arranged at regions where word lines and bit lines cross each other; a randomizing and de-randomizing circuit configured to perform a first randomizing operation on data to be programmed to the memory cells, based on a seed value, so as to generate first randomized data; a data reading/writing circuit configured to perform a second randomizing operation on the first randomized data using a data inverting operation so as to generate second randomized data and program the second randomized data to the memory cells; and a control logic configured to control the randomizing and de-randomizing circuit and the data reading/writing circuit. | 2013-05-16 |
20130121091 | SYSTEM WITH CONTROLLER AND MEMORY - According to the system of the present invention, data (DQ) signals are outputted/received between a controller | 2013-05-16 |
20130121092 | SEMICONDUCTOR DEVICE INCLUDING PLURAL SEMICONDUCTOR CHIPS STACKED TO ONE ANOTHER - Disclosed herein is a device that includes a first semiconductor chip outputting a read command and a clock signal, a plurality of second semiconductor chips stacked to the first semiconductor chip, and a signal path electrically connected between the first and second semiconductor chips. Each of the second semiconductor chips performs a read operation to read out a data signal stored therein in response to the read command. Each of the second semiconductor chips includes a counter circuit performing a count operation in response to the clock signal to generate a count signal, and an output control circuit outputs the data signal to the signal path when the count signal indicates a predetermined value. The predetermined values of the second semiconductor chips are different from one another. | 2013-05-16 |
20130121093 | MEMORY ACCESS CONTROL DEVICE AND MANUFACTURING METHOD - A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length. | 2013-05-16 |
20130121094 | INTEGRATED CIRCUIT COMPRISING A DELAY-LOCKED LOOP - Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry. | 2013-05-16 |
20130121095 | MEMORY CONTROLLER, SYSTEM INCLUDING THE CONTROLLER, AND MEMORY DELAY AMOUNT CONTROL METHOD - A DRAM coupled to a system LSI, the DRAM receiving a test pattern from the system LSI to store the test pattern, if a power source of the system LSI is turned on, outputting the stored test pattern to the system LSI, receiving a delay set value from the system LSI, the delay set value being based on the test pattern, storing the delay set value after the power source of the system LSI is turned off and outputting the stored delay set value to the system LSI, if the power source of the system LSI is turned on again. | 2013-05-16 |
20130121096 | Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory - A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal. | 2013-05-16 |
20130121097 | ADDRESS OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a signal generation unit configured to generate a toggling signal and first and second pulse signals in response to a test signal and a burst pulse signal. An address output unit may be configured to receive first to fourth input addresses and output sequentially first to fourth output addresses in response to the toggling signal and the first and second pulse signals. A repair unit may be configured to perform a repair operation on a word line selected by the first to fourth output addresses. | 2013-05-16 |
20130121098 | Serial Memory with Fast Read with Look-Ahead - A serial memory may have memory arranged in a plurality of memory blocks, a serial interface for receiving a read instruction and associated memory address; and a controller configured to only store a plurality of most significant bits from each memory block which are accessed in parallel before an entire address has been received through the serial interface. The controller is further configured to stream out one of the plurality of most significant bits upon full reception of the memory address while retrieving the remaining bits from memory using the entire address and stream out the remaining bits after the most significant bits have been streamed out. | 2013-05-16 |
20130121099 | AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - An amplifier circuit includes an amplification unit and a back-bias voltage providing unit. The amplification unit amplifies input data. The back-bias voltage providing unit provides selectively back-bias voltages of different levels to the amplification unit in an initial operation period of the amplification unit and a period after the initial operation period. | 2013-05-16 |