20th week of 2013 patent applcation highlights part 16 |
Patent application number | Title | Published |
20130119400 | SELF-ALIGNED SIDEWALL GATE GaN HEMT - A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length. | 2013-05-16 |
20130119401 | LARGE AREA NITRIDE CRYSTAL AND METHOD FOR MAKING IT - Techniques for processing materials in supercritical fluids including processing in a capsule disposed within a high-pressure apparatus enclosure are disclosed. The disclosed techniques are useful for growing crystals of GaN, AlN, InN, and their alloys, including InGaN, AlGaN, and AlInGaN for the manufacture of bulk or patterned substrates, which in turn can be used to make optoelectronic devices, lasers, light emitting diodes, solar cells, photoelectrochemical water splitting and hydrogen generation devices, photodetectors, integrated circuits, and transistors. | 2013-05-16 |
20130119402 | LIGHT EMITTING DEVICE - Disclosed is a method for fabricating a light emitting device. The method includes forming an oxide including gallium aluminum over a gallium oxide substrate, forming a nitride including gallium aluminum over the oxide including gallium aluminum and forming a light emitting structure over the nitride including gallium aluminum. | 2013-05-16 |
20130119403 | Semiconductor Structure and a Method of Forming the Same - Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate. | 2013-05-16 |
20130119404 | DEVICE STRUCTURE INCLUDING HIGH-THERMAL-CONDUCTIVITY SUBSTRATE - Methods and apparatuses for forming a device structure including a high-thermal-conductivity substrate are disclosed herein. A method forming such a device structure may comprise forming an active layer over a first substrate in a manner such that a frontside of the active layer faces the first substrate and a backside of the active layer faces away from the first substrate, forming a second substrate over the backside of the active layer, and removing the first substrate to expose the frontside of the active layer. Other embodiments are described and claimed. | 2013-05-16 |
20130119405 | SEMICONDUCTOR DEVICE WITH ENHANCED STRAIN - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner. | 2013-05-16 |
20130119406 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEM - A silicon carbide substrate includes a base layer made of silicon carbide, silicon carbide layers made of single-crystal silicon carbide and arranged side by side on the base layer when viewed in plan view, and a filling portion made of silicon carbide and filling a gap formed between the adjacent silicon carbide layers. The filling portion has a surface roughness of not more than 50 μm in RMS value. | 2013-05-16 |
20130119407 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, in the substrate, a trench opened on one main surface side of the substrate; and forming an oxide film in a region including a surface of the trench. In the step of forming the oxide film, the substrate is heated at a temperature of not less than 1250° C. in an atmosphere containing oxygen. | 2013-05-16 |
20130119408 | Display Device and Method for Fabricating the Same - An inexpensive display device, as well as an electrical apparatus employing the same, can be provided. In the display device in which a pixel section and a driver circuit are included on one and the same insulating surface, the driver circuit includes a decoder | 2013-05-16 |
20130119409 | Semiconductor DC Transformer - A semiconductor DC transformer is provided. The semiconductor DC transformer comprises: a plurality of semiconductor electricity-to-light conversion structures connected in series for converting input electric energy into optical energy; and a plurality of semiconductor light-to-electricity conversion structures connected in series for converting input optical energy into electric energy, in which a number of the semiconductor electricity-to-light conversion structures is different from that of the semiconductor light-to-electricity conversion structures so as to realize a DC transformation, and a working light spectrum of the semiconductor electricity-to-light conversion structures is matched with that of the semiconductor light-to-electricity conversion structures. | 2013-05-16 |
20130119410 | WHITE LIGHT EMITTING DIODE (LED) LIGHTING DEVICE DRIVEN BY PULSE CURRENT - A white LED lighting device driven by a pulse current is provided, which consists of blue, violet or ultraviolet LED chips, blue afterglow luminescence materials A and yellow luminescence materials B. Wherein the weight ratio of the blue afterglow luminescence materials A to the yellow luminescence materials B is 10-70 wt %:30-90 wt %. The white LED lighting device drives the LED chips with a pulse current having a frequency of not less than 50 Hz. Because of using the afterglow luminescence materials, the light can be sustained when an excitation light source disappears, thereby eliminating the influence of LED light output fluctuation caused by current variation on the illumination. At the same time, the pulse current can keep the LED chips being at an intermittent work state, so as to overcome the problem of chip heating. | 2013-05-16 |
20130119411 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - A light emitting diode package structure includes a substrate, LED bare chips and a lens. The substrate has an upper surface, a lower surface and a side surface between the upper surface and the lower surface. The upper surface is provided with a circuit pattern. The side surface is provided with a groove. The LED bare chips are fixed on the upper surface and electrically connected with the circuit pattern. The lens covers the LED bare chips, the upper surface and the circuit pattern by an injection molding process so as to be inserted into the groove. With this arrangement, the connecting strength between the substrate and the lens can be enhanced, thereby achieving waterproof and anti-electrostatic effects. Further, material cost of the present invention is reduced greatly. | 2013-05-16 |
20130119412 | PIXEL CIRCUIT, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS - An electro-optical device formed on a semiconductor substrate, includes: a first transistor controlling a current level according to a voltage between a gate and a source; a second transistor electrically connected between a data line and the gate of the first transistor; a third transistor electrically connected between the gate and a drain of the first transistor; and a light-emitting element emitting light at a luminance according to the current level, in which one of a source and a drain of the second transistor and one of a source and a drain of the third transistor are formed by a common diffusion layer. | 2013-05-16 |
20130119413 | LIGHT-EMITTING ELEMENT, DISPLAY DEVICE, AND METHOD FOR PRODUCING LIGHT-EMITTING ELEMENT - A light-emitter including: a transparent first electrode; a charge injection transport layer; a light-emitting layer; and a transparent second electrode, layered in this order. The light-emitting layer is defined by a bank. The charge injection transport layer has a recessed structure including: an inner bottom surface in contact with a bottom surface of the light-emitting layer; and an inner side surface continuous with the inner bottom surface. The inner side surface includes: a lower edge continuous with the inner bottom surface; and an upper edge continuous with the lower edge. The upper edge is aligned with a bottom periphery of the bank, or has contact with a bottom surface of the bank. The charge injection transport layer has contact with a side surface of the light-emitting layer. | 2013-05-16 |
20130119414 | LIGHT-EMITTING DEVICES WITH VERTICAL LIGHT-EXTRACTION MECHANISM - A light-emitting device comprises a lattice structure to minimize the horizontal waveguide effect by reducing light traveling distance in the light-absorption medium of the light-emitting devices, and to enhance light extraction from the light-emitting layer. The lattice structure includes sidewalls and/or rods embedded in the light-absorption medium and dividing the light-absorption medium into a plurality of area units. The area units are completely isolated or partially separated from each other by the sidewalls. Also provided is a method of fabricating a light-emitting device that comprises a lattice structure, which lattice structure includes sidewalls and/or rods embedded in the light-absorption medium and dividing the light-absorption medium into a plurality of area units. | 2013-05-16 |
20130119415 | LED PACKAGE STRUCTURE FOR ENHANCING MIXED LIGHT EFFECT - An LED package structure for enhancing mixed light effect comprises: at least one first light emitting chip; at least one second light emitting chip, a frame structure having a first containing portion, a second containing portion, a spacing portion and a light mixing area; a first colloid, doped with a green-light phosphor and filled into the first containing portion; a second colloid, filled into the second containing portion; and an encapsulating colloid, packaged and filled into the light mixing area. This design can enhance the light emission efficiency and achieve a uniform light-mixing dot light source. | 2013-05-16 |
20130119416 | LIGHT-EMITTING DIODE AND DISPLAY APPARATUS USING SAME - To provide a light-emitting diode enabling improvements to color purity as well as to luminous efficiency, a light-emitting diode comprises a reflective electrode and a transparent electrode having functional layers therebetween, the functional layers being a transparent conductive layer, a hole injection layer, and a hole transport layer, and further comprises a light-emitting layer emitting blue light and having an electron transport layer layered thereon, such that a total optical layer thickness of the functional layers sandwiched between the reflective electrode and the light-emitting layer is in a range of 455.4 nm to 475.8 nm, inclusive. | 2013-05-16 |
20130119417 | LIGHT EMITTING DIODE (LED) PACKAGES AND RELATED METHODS - Light emitting diode (LED) packages and methods are disclosed herein. In one aspect, a light emitting package is disclosed. The light emitting package includes one or more areas of conductive material having a thickness of less than approximately 50 microns (μm). The package can further include at least one light emitting diode (LED) electrically connected to the conductive material and at least one thin gap disposed between areas of conductive material. | 2013-05-16 |
20130119418 | METHODS OF FORMING OPTICAL CONVERSION MATERIAL CAPS AND LIGHT EMITTING DEVICES INCLUDING PRE-FORMED OPTICAL CONVERSION MATERIAL CAPS - A method of forming can be provided by applying an optical conversion material to a mold to form a unitary layer of optical conversion material and removing the unitary layer of optical conversion material from the mold. | 2013-05-16 |
20130119419 | MAGNETICALLY ADJUSTING COLOR-CONVERTING MATERIALS WITHIN A MATRIX AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS - Magnetically adjusting color-converting particles within a matrix and associated devices, systems, and methods are disclosed herein. A magnetic-adjustment process can include applying a magnetic field to a mixture including a non-solid matrix and a plurality of color-converting particles (e.g. magnetically anisotropic color-converting particles). The magnetic field can cause the plurality of color-converting particles to move into a generally non-random alignment (e.g., a generally non-random magnetic alignment and/or a generally non-random shape alignment) within the non-solid matrix. The non-solid matrix then can be solidified to form a solid matrix. A magnetic-adjustment process can be performed in conjunction with testing and/or product binning of solid-state radiation transducer devices. For example, a position, direction, strength, or duration of a magnetic field used to perform a magnetic-adjustment process can be controlled according to optical output collected from a solid-state radiation transducer device. Measuring the optical output and performing the magnetic-adjustment process can be at least partially concurrent. | 2013-05-16 |
20130119420 | LIGHT EMITTING DEVICE - A light emitting device is disclosed. The light emitting device includes an electrode, which includes a reflective electrode layer disposed over a second semiconductor layer and a bonding electrode layer disposed in at least a partial region of an outer side surface of the reflective electrode layer while coming into contact with the second semiconductor layer. Thus, it may be possible to enhance bonding reliability between the electrode and the semiconductor layer. | 2013-05-16 |
20130119421 | LIGHT EMITTING DIODE EPITAXIAL STRUCTURE AND MANUFACTURING METHOD OF THE SAME - An LED epitaxial structure includes a substrate, a buffer layer, a functional layer and a light generating layer. The buffer layer is located on a top surface of the substrate. The functional layer includes a plurality of high-temperature epitaxial layers and low-temperature epitaxial layers alternatively arranged between the buffer layer and light generating layer. A textured structure is formed in the low-temperature epitaxial layer. A SiO2 layer including a plurality of convexes is located on the textured structure to increase light extraction efficiency of the LED epitaxial structure. A manufacturing method of the LED epitaxial structure is also disclosed. | 2013-05-16 |
20130119422 | SEMICONDUCTOR LIGHT EMITTING DEVICE, LIGHT EMITTING MODULE, LIGHTING APPARATUS AND DISPLAY ELEMENT - A semiconductor light emitting device has a multilayer epitaxial structure for emitting light by a light emitting layer located between a first conductive layer and a second conductive layer. The multilayer epitaxial structure can be grown directly on a base substrate. A reflective layer can be provided in the multilayer epitaxial structure between the base substrate and the first conductive layer. A distributive Bragg reflector can be positioned adjacent the substrate. A surface of the multilayer epitaxial structure can be conformed to provide improved light extraction. A phosphorus film encapsulates the multilayer epitaxial structure and its respective side surfaces. | 2013-05-16 |
20130119423 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND PACKAGE - A semiconductor light emitting device and package containing the same include: a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A light extraction layer is disposed on the light emitting structure and includes a light-transmissive thin film layer having light transmittance, a nano-rod layer including nano-rods disposed on the light-transmissive thin film layer, and a nano-wire layer including nano-wires disposed on the nano-rod layer. | 2013-05-16 |
20130119424 | LIGHT EMITTING DEVICE AND LIGHT EMITTING APPARATUS HAVING THE SAME - A light emitting device is provided a transmissive substrate; a first pattern portion including a protrusions; a second pattern portion including a concaves having a width smaller than a width of each protrusion; a light emitting structure under the transmissive substrate and including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer; a first electrode under the first conductive semiconductor layer; a reflective electrode layer under the second conductive semiconductor layer; a second electrode under the reflective electrode layer; a first connection electrode under the first electrode; a second connection electrode under the second electrode; and an insulating support member around the first electrode and the first connection electrode and around the second electrode and the second connection electrode and including a ceramic-based thermal diffusion agent. | 2013-05-16 |
20130119425 | LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE USING THE SAME - An object of the present invention is to provide a light emitting element having slight increase in driving voltage with accumulation of light emitting time. Another object of the invention is to provide a light emitting element having slight increase in resistance value with increase in film thickness. A light emitting element of the invention includes a first layer for generating holes, a second layer for generating electrons and a third layer comprising a light emitting substance between first and second electrodes. The first and third layers are in contact with the first and second electrodes, respectively. The second and third layers are connected to each other so as to inject electrons generated in the second layer into the third layer when applying the voltage to the light emitting element such that a potential of the second electrode is higher than that of the first electrode. | 2013-05-16 |
20130119426 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREFOR - A low-cost and productivity-oriented surface mount light-emitting device is provided. The light-emitting device includes an insulating film | 2013-05-16 |
20130119427 | LED SUBSTRATE, LED CHIP AND METHOD FOR MANUFACTURING THE SAME - An LED substrate may comprise a base including a first surface and a second surface; and a conductive structure formed on at least a part of the first surface and at least a part of the second surface, the part of the conductive structure formed on the first surface electrically connected to the part of the conductive structure formed on the second surface. A method for forming an LED substrate, a method for forming an LED chip, and an LED chip manufactured therefrom may be provided as well. | 2013-05-16 |
20130119428 | LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, AND ELECTRONIC DEVICE - The present invention provides a light-emitting element, a light-emitting device and an electronic device in which an optical path length through which generated light goes can be changed easily. The present invention provides a light-emitting element including a light-emitting layer between a first electrode and a second electrode, and a mixed layer in contact with the first electrode; in which the light-emitting layer includes a light-emitting substance; the mixed layer includes a hole transporting substance and a metal oxide showing an electron accepting property to the hole transporting substance, and has a thickness of 120 to 180 nm, and when a voltage is applied between the first electrode and the second electrode such that a potential of the first electrode is higher than that of the second electrode, the light-emitting substance emits light. | 2013-05-16 |
20130119429 | LIGHT-EMITTING ELEMENT AND THE MANUFACTURING METHOD THEREOF - A light-emitting element includes a light-emitting stack includes: a first semiconductor layer; an active layer formed on the first semiconductor layer; and a second semiconductor layer formed on the active layer; a recess structure formed through the second semiconductor layer, the active layer, and extended in the first semiconductor layer, wherein the first semiconductor layer includes a contact region defined by the recess structure; a first electrode structure including a first contact portion on the contact region of the first semiconductor layer, and a second contact portion laterally extended from the first contact portion into the first semiconductor layer; and a dielectric layer formed on side surfaces of the second semiconductor layer and the active layer to insulate the second semiconductor layer and the active layer from the first contact portion. | 2013-05-16 |
20130119430 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a vertical-type light emitting device and a method of manufacturing the same. The light emitting device includes a p-type semiconductor layer, an active layer, and an n-type semi-conductor layer that are stacked, a cover layer disposed on a p-type electrode layer to surround the p-type electrode layer, a conductive support layer disposed on the cover layer, and an n-type electrode layer disposed on the n-type semiconductor layer. | 2013-05-16 |
20130119431 | LIGHT EMITTING MODULE, METHOD FOR MANUFACTURING LIGHT EMITTING MODULE, AND VEHICULAR LAMP - Provided is a light emitting module in which an LED device is mounted and power is supplied to the LED device by a gold wire. The light emitting module includes a first resin (sealing material) that seals the gold wire and a second resin (dam wall) that surrounds at least a portion of the outer peripheral of the first resin. The first resin has a lower viscosity and a lower elastic modulus compared to the second resin, and protects the gold wire mechanically and chemically. The second resin suppresses the first resin from being flowed out toward the peripherals, and, as a result, the sealing state of the gold wire by the first resin may be maintained. | 2013-05-16 |
20130119432 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device having a p+ collector region in the surface of an n− drift region. The p+ collector region forms a p-n junction with the n− drift region. A collector electrode is in contact with the p+ collector region. A low-lifetime region having a carrier lifetime shorter than in other regions is provided, extending from the n− drift region to the p+ collector region, at the interface between the n− drift region and p+ collector region. The low-lifetime region, being partially activated in accordance with the concentration distribution of a p-type impurity implanted in order to form the p+ collector region, is in a barely activated state. The low-lifetime region has an activation rate lower than that of the p+ collector region. The p+ collector region is completely electrically activated as far as a depth of, for example, 0.5 μm-0.8 μm, from the surface on the collector electrode side. | 2013-05-16 |
20130119433 | ISOLATION STRUCTURE FOR ESD DEVICE - Among other things, an electrostatic discharge (ESD) device is provided. The ESD device comprises a dielectric isolation structure that is formed between an emitter and a collector of the ESD device. During an ESD event, current flows from the emitter, substantially under the dielectric isolation structure, to the collector, to protect associated circuitry. The dielectric isolation structure is formed to a depth that is less than a depth of at least one of the emitter or the collector, or doped regions thereof, thereby decreasing a length of a current path from the emitter to the collector, because the current is not obstructed by the dielectric isolation structure. Accordingly, the ESD device can carry higher current during the ESD event because the shorter current path has less resistance than a longer path that would otherwise be traveled if the dielectric isolation structure was not formed at the shallower depth. | 2013-05-16 |
20130119434 | BIPOLAR TRANSISTOR WITH A COLLECTOR HAVING A PROTECTED OUTER EDGE PORTION FOR REDUCED BASED-COLLECTOR JUNCTION CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance C | 2013-05-16 |
20130119435 | DIELECTRIC DUMMIFICATION FOR ENHANCED PLANARIZATION WITH SPIN-ON DIELECTRICS - An integrated device includes a lower layer pattern on a semiconductor substrate. The lower layer pattern includes a first region including first electrical devices and a second region including second electrical devices and electrically nonconductive dummy devices. A first device density of the first electrical devices in the first region is substantially greater than a second device density of the second electrical devices in the second region. A partially-planarizing dielectric layer is disposed on the lower layer pattern so as to cover the first electrical devices, the second electrical devices, and the electrically nonconductive dummy devices. The average height of the partially-planarizing dielectric layer in the first region is approximately the same as the average height in the second region. Through-holes are formed in the first region, and an electrically conductive material is disposed in the through-holes. | 2013-05-16 |
20130119436 | INTERFACE CONTROL IN A BIPOLAR JUNCTION TRANSISTOR - Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer. | 2013-05-16 |
20130119437 | SEMICONDUCTOR DEVICE - A semiconductor device having small leakage current and high breakdown voltage during reverse blocking, small on-state resistance and large output current at forward conduction, short reverse recovery time at shutoff, and high peak surge current value is provided. An n-type layer is made of a group-III nitride, and a p-type layer is made of a group-IV semiconductor material having a smaller band gap than the group-III nitride. The energy level at the top of the valence band of the n-type layer is lower than the energy level at the top of the valence band of the p-type layer, so that a P-N junction semiconductor device satisfying the above requirements is obtained. Further, a combined structure of P-N junction and Schottky junction by additionally providing an anode electrode to be in Schottky contact with the n-type layer also achieves the effect of decreasing voltage at the rising edge of current resulting from the Schottky junction. | 2013-05-16 |
20130119438 | PIXEL FOR DEPTH SENSOR AND IMAGE SENSOR INCLUDING THE PIXEL - A unit pixel of a depth sensor including a light-intensity output circuit configured to output a pixel signal according to a control signal, the pixel signal corresponding to a first electric charge and a second electric charge, a first light-intensity extraction circuit configured to generate the first electric charge and transmit the first electric charge to the light-intensity output circuit, the first electric charge varying according to an amount of light reflected from a target object and a second light-intensity extraction circuit configured to generate the second electric charge and transmit the second electric charge to the light-intensity output circuit, the second electric charge varying according to the amount of reflected light. The light-intensity output circuit includes a first floating diffusion node. Accordingly, it is possible to minimize waste of a space, thereby manufacturing a small-sized pixel. | 2013-05-16 |
20130119439 | METHOD OF PRODUCING A SOLID-STATE IMAGE PICKUP APPARATUS, SOLID-STATE IMAGE PICKUP APPARATUS, AND ELECTRONIC APPARATUS - A method of producing a solid-state image pickup apparatus, including the steps of: forming a plurality of light-receiving portions on a substrate; forming a plurality of transfer gates to be connected to the plurality of light-receiving portions formed on the substrate; forming an insulation film on the substrate; exposing a base by etching the insulation film so that the etched part of the insulation film between the adjacent transfer gates tapers away; and injecting an impurity into the exposed part using the insulation film that has remained after the etching as a mask to thus form an impurity injection portion. | 2013-05-16 |
20130119440 | BIOSENSORS INTEGRATED WITH A MICROFLUIDIC STRUCTURE - A biosensor with a microfluidic structure surrounded by an electrode and methods of forming the electrode around the microfluidic structure of the biosensor are provided. A method includes forming a gate or electrode in a first layer. The method further includes forming a trench in a second layer. The method further includes forming a first metal layer in the trench such that the first metal layer is in electrical contact with the gate or the electrode. The method further includes forming a sacrificial material in the trench. The method further includes forming a second metal layer over the sacrificial material and in contact with the first metal layer. The method further includes removing the sacrificial material such that a microfluidic channel is formed surrounded by the first and the second metal layers. | 2013-05-16 |
20130119441 | MICROELECTRONIC DEVICE AND MEMS PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF - A microelectronic device including a substrate, at least a semi-conductor element, an anti metal ion layer, a non-doping oxide layer and a MEMS structure is provided. The substrate has a CMOS circuit region and a MEMS region. The semi-conductor element is configured within the CMOS circuit region of the substrate. The anti metal ion layer is disposed within the CMOS circuit region of the substrate and covers the semi-conductor element. The non-doping oxide layer is disposed on the substrate within the MEMS region. The MEMS structure is partially suspended above the non-doping oxide layer. The present invention also provides a MEMS package structure and a fabricating method thereof. | 2013-05-16 |
20130119442 | JUNCTION FIELD-EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN REGIONS FORMED BY SELECTIVE EPITAXY - Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate. | 2013-05-16 |
20130119443 | SEMICONDUCTOR STRUCTURE FOR AN ELECTRONIC INTERRUPTOR POWER SWITCH - The invention relates to a structure comprising an n-type substrate ( | 2013-05-16 |
20130119444 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess. | 2013-05-16 |
20130119445 | CMOS DEVICE FOR REDUCING RADIATION-INDUCED CHARGE COLLECTION AND METHOD FOR FABRICATING THE SAME - A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced. | 2013-05-16 |
20130119446 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS - An electrical device in which an interface layer comprising arsenic is disposed between and in contact with a conductor and a semiconductor. In some cases, the interface layer may be a monolayer of arsenic. | 2013-05-16 |
20130119447 | NON-UNIFORM GATE DIELECTRIC CHARGE FOR PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING - A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric. | 2013-05-16 |
20130119448 | MEMORY LAYOUT STRUCTURE AND MEMORY STRUCTURE - A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each first doped region is disposed in a middle region; a plurality of second doped region, wherein each second doped region is disposed in a distal end region respectively; a plurality of recessed gate structures; a plurality of word lines electrically connected to each recessed gate structure respectively; a plurality of digit lines electrically connected to the first doped region respectively; and a plurality of capacitors electrically connected to each second doped region respectively. | 2013-05-16 |
20130119449 | SEMICONDUCTOR DEVICE WITH SEAL RING WITH EMBEDDED DECOUPLING CAPACITOR - A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to V | 2013-05-16 |
20130119450 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - Provided is a non-volatile semiconductor storage device including a memory cell which is disposed on a semiconductor substrate and where a control gate electrode is disposed on a charge storage layer, a select gate transistor where a select gate electrode is disposed between a source region and a drain region and which shares the source region with the memory cell, a first air gap which is disposed between the charge storage layers and between the source regions adjacent to each other in a word line direction and which is formed continuously over the memory cell and the select gate transistor adjacent to each other in a bit line direction so as to be concealed under the word line and under the select gate electrode, and a back-filling insulating film which back-fills an air gap between the drain electrodes adjacent to each other in the word line direction. | 2013-05-16 |
20130119451 | INTERLAYER POLYSILICON DIELECTRIC CAP AND METHOD OF FORMING THEREOF - In some embodiments, an interlayer polysilicon dielectric cap disposed atop a substrate having a first floating gate, a second floating gate and an isolation layer disposed between the first floating gate and the second floating gate may include: a first nitrogen containing layer disposed atop an upper portion and sidewalls of the first floating gate and second floating gate; a first oxygen containing layer disposed atop the first nitrogen containing layer and an upper surface of the isolation layer; a second nitrogen containing layer disposed atop an upper portion and sidewalls of the first oxygen containing layer; and a second oxygen containing layer disposed atop the second nitrogen containing layer and an upper surface of the first oxygen containing layer. | 2013-05-16 |
20130119452 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PRODUCING THE SAME - Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell | 2013-05-16 |
20130119453 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - A non-volatile memory unit cell includes a transistor pair, and first, second, third and fourth control gates. The transistor pair has a first transistor and a second transistor that are connected in parallel and of opposite types. The first transistor and the second transistor have a first floating polysilicon gate and a second floating polysilicon gate, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated. The first control gate is capacitively coupled to the first floating polysilicon gate through a first coupling junction. The second control gate is capacitively coupled to the second floating polysilicon gates through a second coupling junction. The third control gate is capacitively coupled to the first floating polysilicon gate through a first tunneling junction. The fourth control gate is capacitively coupled to the second floating polysilicon gates through a second tunneling junction. | 2013-05-16 |
20130119454 | NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE - A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided. | 2013-05-16 |
20130119455 | NAND FLASH WITH NON-TRAPPING SWITCH TRANSISTORS - A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures. | 2013-05-16 |
20130119456 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes: a substrate; a stacked body provided above the substrate, including a selector gate and an insulating layer provided on the selector gate; an insulating film provided on a sidewall of a hole formed by penetrating the stacked body in the stacking direction; a channel body and a semiconductor layer. The channel body is provided on a sidewall of the insulating film in the hole, that blocks the hole near an end of the insulating layer side in the selector gate, and that encloses a cavity below a part that blocks the hole. The semiconductor layer is formed of a same material as the channel body and is embedded continuously in the hole above the part where the channel body blocks the hole. | 2013-05-16 |
20130119457 | MEMORY DEVICE, MANUFACTURING METHOD AND OPERATING METHOD OF THE SAME - A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element. | 2013-05-16 |
20130119458 | NOR FLASH MEMORY CELL AND STRUCTURE THEREOF - The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a a substrate, an active area, a first gate structure, a second gate structure and at least one third gate structure. The first gate structure covers a first partial region of the active area and is formed by a silicon-rich nitride material. The second gate structure covers a second partial region of the active area. The third gate structure covers a third partial region between a first opening and the first gate structure. The active area has the first opening, the first opening disposed on a first side of the first gate structure and the first side is not neighbor to the second gate structure. The NOR flash memory cell further comprises a first conducting structure for covering the first opening to form a bit line signal receiving terminal. | 2013-05-16 |
20130119459 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, which form a bit line only at one side of a line pattern by partially etching a semiconductor substrate in a vertical gate structure, such that a body tied structure for reducing the floating body effect can be implemented. A semiconductor device includes a line pattern formed over a semiconductor substrate, a bit line buried in a bottom part of one side of the line pattern, and a gate formed over the bit line, and located perpendicular to the bit line. | 2013-05-16 |
20130119460 | TRENCH TYPE POWER TRANSISTOR DEVICE AND FABRICATING METHOD THEREOF - The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region. | 2013-05-16 |
20130119461 | SEMICONDUCTOR DEVICE HAVING A BURIED GATE AND METHOD FOR FORMING THEREOF - A semiconductor device includes: a first interlayer insulating layer in first and second regions of a semiconductor substrate, a second interlayer insulating layer over the first interlayer insulating layer in first and second regions, a hard mask provided between the first and the second interlayer insulating layers in the second region and not extending to the first region, a first metal contact formed through the second interlayer insulating layer and the hard mask in the second region, and a first storage node contact formed through the first interlayer insulating layer in the first region. | 2013-05-16 |
20130119462 | SEMICONDUCTOR DEVICE FOR INCREASING BIT LINE CONTACT AREA, AND MODULE AND SYSTEM INCLUDING THE SAME - A semiconductor device including a buried gate is disclosed. In the semiconductor device, a bit line contact contacts a top surface and lateral surfaces of an active region, such that a contact area between a bit line contact and the active region is increased and a high-resistivity failure is prevented from occurring in a bit line contact. | 2013-05-16 |
20130119463 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate. | 2013-05-16 |
20130119464 | SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench. | 2013-05-16 |
20130119465 | DUAL CHANNEL TRENCH LDMOS TRANSISTORS AND TRANSISTORS INTEGRATED THEREWITH - A dual channel trench LDMOS transistor includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the second conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the first conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain drift region of the first conductivity type formed in the semiconductor layer and in electrical contact with a drain electrode. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor. | 2013-05-16 |
20130119466 | High Voltage Device with Reduced Leakage - A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity. | 2013-05-16 |
20130119467 | DEVICES, METHODS, AND SYSTEMS WITH MOS-GATED TRENCH-TO-TRENCH LATERAL CURRENT FLOW - A DMOS transistor is fabricated with its source/body/deep body regions formed on the walls of a first set of trenches, and its drain regions formed on the walls of a different set of trenches. A gate region that is formed in a yet another set of trenches can be biased to allow carriers to flow from the source to the drain. Lateral current low from source/body regions on trench walls increases the active channel perimeter to a value well above the amount that would be present if the device was fabricated on just the surface of the wafer. Masking is avoided while open trenches are present. A transistor with a very low on-resistance per unit area is obtained. | 2013-05-16 |
20130119468 | THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME - A thin-film transistor may include a drain electrode, a source electrode, an active layer, a gate electrode, and a gate insulating layer. In a vertical sectional view, the gate insulating layer may be disposed between the active layer and the gate electrode to include a first inorganic layer, an organic layer, and a second inorganic layer sequentially stacked. According to a method of fabricating the thin-film transistor, the gate insulating layer may be formed between the steps of forming the active layer and the second electrode layer or between the steps of forming the first electrode layer and the second electrode layer. | 2013-05-16 |
20130119469 | SEMICONDUCTOR DEVICE - Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor. | 2013-05-16 |
20130119470 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region. | 2013-05-16 |
20130119471 | DISPLAY PANEL, COLOR FILTER SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A display panel includes; a substrate, and a light blocking structure surrounding an ink filling region on the substrate, the light blocking structure including; a first layer pattern having an ink affinity characteristic disposed on the substrate, and a second layer pattern positioned on the first layer pattern and including an organic material having a light blocking characteristic. | 2013-05-16 |
20130119472 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer. | 2013-05-16 |
20130119473 | GATE STRUCTURES AND METHODS OF MANUFACTURE - A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material. | 2013-05-16 |
20130119474 | TRENCH SILICIDE AND GATE OPEN WITH LOCAL INTERCONNECT WITH REPLACEMENT GATE PROCESS - A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate. | 2013-05-16 |
20130119475 | METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE INCLUDING STRESS FILMS - A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region. | 2013-05-16 |
20130119476 | Integrated Circuit Including Gate Electrode Level Region Including Cross-Coupled Transistors Having Gate Contacts Located Over Inner Portion of Gate Electrode Level Region and Offset Gate Level Feature Line Ends - A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. The first and second p-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. The first and second n-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions. | 2013-05-16 |
20130119477 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first fin formed of a first semiconductor material and a second fin comprising a layer formed of a second semiconductor material. The first semiconductor material is silicon, and the second semiconductor material is silicon-germanium (SiGe). The second fin further includes a layer of the first semiconductor material below the layer of the second semiconductor material. The semiconductor device also includes a hard mask layer on the first and second fins and an insulator layer that is disposed below the first and second fins. The first and second fins are used to form an N-channel and a P-channel semiconductor device, respectively. | 2013-05-16 |
20130119478 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is described as including a first fin having a layer formed of a first semiconductor material and a second fin that is formed of a second semiconductor material. The first and second semiconductor materials are different. The second semiconductor material may have a mobility of P-type carriers that is greater than a mobility of P-type carriers of the first semiconductor material. The second fin includes a layer formed of the first semiconductor material below the layer formed of the second semiconductor material. The semiconductor device further includes a hard mask layer disposed on the first and second fins and an insulator layer disposed below the first and second fins. The first and second semiconductor materials include silicon and germanium, respectively. The first and second fins are used to form respective N-channel and a P-channel semiconductor devices. | 2013-05-16 |
20130119479 | TRANSISTOR STRUCTURE - A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer. | 2013-05-16 |
20130119480 | INTEGRATED CIRCUIT RESISTOR - A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided. | 2013-05-16 |
20130119481 | FINFET DEVICE - A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and removing a portion of the gate stack portion to expose a portion of the substrate. | 2013-05-16 |
20130119482 | FIN FIELD EFFECT TRANSISTORS AND METHODS FOR FABRICATING THE SAME - The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric. | 2013-05-16 |
20130119483 | SILICIDE CONTACTS HAVING DIFFERENT SHAPES ON REGIONS OF A SEMICONDUCTOR DEVICE - A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications. | 2013-05-16 |
20130119484 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method of manufacturing a semiconductor device comprising: providing a semiconductor substrate, on which a high-k dielectric layer and a patterned gate are formed sequentially; nitridating portions of the high-k dielectric layer on the semiconductor substrate which are not covered by the gate; and forming spacers around the gate. Accordingly, the present invention further provides a semiconductor device. Portions of the high-k dielectric layer on the semiconductor substrate, which are not covered by the gate or the spacers positioned thereon, are nitridated, such that an oxygen diffusion barrier layer is formed on the surface of the high-k dielectric layer, thereby oxygen diffusion in the lateral direction into the high-k dielectric layer under the gate is prevented, and the operation performance of the semiconductor device is optimized. | 2013-05-16 |
20130119485 | Transistor Performance Improving Method with Metal Gate - The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode. | 2013-05-16 |
20130119486 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a nitride semiconductor multilayer including an active region, and first and second electrodes, each having a finger-like structure and formed on the active region to be spaced from each other. A first electrode interconnect is formed on the first electrode. A second electrode interconnect is formed on the second electrode. A second insulating film is formed to cover the first and second electrode interconnects. A first metal layer is formed on the second insulating film. The first metal layer is formed above the active region with the second insulating film interposed therebetween, and is coupled to the first electrode interconnect. | 2013-05-16 |
20130119487 | Structure and Method for MOSFETS with High-K and Metal Gate Structure - The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure. | 2013-05-16 |
20130119488 | THINNED FINGER SENSOR AND ASSOCIATED METHODS - An electronic device may include a housing with a connector member opening therein, electronic circuitry within the housing, and a finger sensor assembly carried by the housing. The finger assembly may include a thinned finger sensing integrated circuit (IC) secured to the housing that has a thickness less than 200 microns. The finger sensor assembly may also include a connector member extending through the connector member opening in the housing and coupling together the thinned finger sensing IC and the electronic circuitry. The thinned finger sensing IC may be adhesively secured to the housing, such as using a pressure sensitive adhesive, and the thinned finger sensing IC may conform to a non-planar surface. | 2013-05-16 |
20130119489 | METHOD AND APPARATUS FOR WAFER-LEVEL SOLDER HERMETIC SEAL ENCAPSULATION OF MEMS DEVICES - A plurality of MEMS devices are formed on a substrate, a sacrificial layer is formed to cover each of the MEMS devices and a protective cap layer is formed on the sacrificial layer. A release hole is formed through the protective cap layer to the underlying sacrificial layer, and a releasing agent is introduced through the release hole to remove the sacrificial layer under the protective cap layer and expose a MEMS device. Optionally, the MEMS device can be released with the same releasing agent or, optionally, with a secondary releasing agent. The release hole is solder sealed, to form a hermetic seal of the MEMS device. Optionally, release holes are formed at a plurality of locations, each over a MEMS device and the releasing forms a plurality of hermetic sealed MEMS devices on the wafer substrate, which are singulated to form separate hermetically sealed MEMS devices. | 2013-05-16 |
20130119490 | INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE - Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method further includes providing a coating of insulator material over the single crystalline beam. The method further includes forming a via through the insulator material. The method further includes providing a sacrificial material in the via and over the insulator material. The method further includes providing a lid on the sacrificial material. The method further includes providing further sacrificial material in a trench of a lower wafer. The method further includes bonding the lower wafer to the insulator, under the single crystalline beam. The method further includes venting the sacrificial material and the further sacrificial material to form an upper cavity above the single crystalline beam and a lower cavity, below the single crystalline beam. | 2013-05-16 |
20130119491 | INTEGRATED SEMICONDUCTOR DEVICES WITH AMORPHOUS SILICON BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE - Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS processes, methods of manufacture and design structures are disclosed. The method includes forming at least one beam comprising amorphous silicon material and providing an insulator material over and adjacent to the amorphous silicon beam. The method further includes forming a via through the insulator material and exposing a material underlying the amorphous silicon beam. The method further includes providing a sacrificial material in the via and over the amorphous silicon beam. The method further includes providing a lid on the sacrificial material and over the insulator material. The method further includes venting, through the lid, the sacrificial material and the underlying material to form an upper cavity above the amorphous silicon beam and a lower cavity below the amorphous silicon beam, respectively. | 2013-05-16 |
20130119492 | Miniaturized Electrical Component Comprising an MEMS and an ASIC and Production Method - The invention relates to a miniaturized electrical component comprising an MEMS chip and an ASIC chip. The MEMS chip and the ASIC chip are disposed on top of each other; an internal mounting of MEMS chip and ASIC chip is connected to external electrical terminals of the electrical component by means of vias through the MEMS chip or the ASIC chip. | 2013-05-16 |
20130119493 | MICROELECTRO MECHANICAL SYSTEM ENCAPSULATION SCHEME - A microelectro mechanical system (MEMS) assembly includes a carrier and a MEMS device disposed over the carrier. A buffer layer is disposed over the MEMS device. The Young's modulus of the buffer layer is less than that of the MEMS device. | 2013-05-16 |
20130119494 | MTJ STRUCTURE AND INTEGRATION SCHEME - A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack. | 2013-05-16 |
20130119495 | MAGNETIC TUNNEL JUNCTION DEVICES HAVING MAGNETIC LAYERS FORMED ON COMPOSITE, OBLIQUELY DEPOSITED SEED LAYERS - Semiconductor stack structures such as magnetic tunnel junction structures having a magnetic free layer that is grown on composite, obliquely deposited seed layers to induce an increased in-plane magnetic anisotropy Hk of the magnetic free layer. In one aspect, a semiconductor device includes a composite seed layer formed on a substrate, and a magnetic layer formed on the composite seed layer. The composite seed layer includes a first seed layer obliquely formed with an incident angle from a surface normal of the substrate along a first direction of the substrate, and a second seed layer obliquely formed with the incident angle on the first seed layer along a second direction of the substrate, opposite the first direction. | 2013-05-16 |
20130119496 | Semiconductor Magnetoresistive Random-access Memory (MRAM) Device and Manufacturing Method thereof - The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the sidewalls of the magnetic tunnel junction unit. The method for manufacturing a semiconductor device comprises: forming a magnetic tunnel junction unit, depositing an isolation dielectric layer to cover the top and the sidewall of the magnetic tunnel junction unit, and depositing a magnetic shielding material layer on the isolation dielectric layer. | 2013-05-16 |
20130119497 | MAGNETIC TUNNEL JUNCTION STRUCTURE - A magnetic tunnel junction (MTJ) device is formed by a process that includes forming a trench in a substrate and depositing an MTJ structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The process includes applying reverse photo etching to remove material that is not directly over the trench. The process also includes plagiarizing the MTJ structure without performing a photo-etch process on the MTJ structure. | 2013-05-16 |
20130119498 | MEMORY SYSTEM HAVING THERMALLY STABLE PERPENDICULAR MAGNETO TUNNEL JUNCTION (MTJ) AND A METHOD OF MANUFACTURING SAME - A spin-torque transfer magnetic random access memory (STTMRAM) element employed to store a state based on the magnetic orientation of a free layer, the STTMRAM element is made of a first perpendicular free layer (PFL) including a first perpendicular enhancement layer (PEL). The first PFL is formed on top of a seed layer. The STTMRAM element further includes a barrier layer formed on top of the first PFL and a second perpendicular reference layer (PRL) that has a second PEL, the second PRL is formed on top of the barrier layer. The STTMRAM element further includes a capping layer that is formed on top of the second PRL. | 2013-05-16 |
20130119499 | Nanoengineered Biophotonic Hybrid Device - Apparatus, compositions, methods, and articles of manufacture are disclosed relating to the design and production of biological components and/or their incorporation in devices and systems, including biohybrid photosensitive devices and systems. In some embodiments, biological components include light antenna structures that collect light and emit Stokes-shifted light to a photoactive non-biological component. In some embodiments, the characteristics of biological components are engineered via force-adaptation of an organism or adaptive system. In some embodiments, biological components are modified by removing reaction centers or other structure not contributing to desired performance. | 2013-05-16 |