19th week of 2010 patent applcation highlights part 64 |
Patent application number | Title | Published |
20100121991 | METHOD OF CONTROLLING MOBILE TERMINAL ON EXTERNAL DEVICE BASIS AND EXTERNAL DEVICE OPERATING SYSTEM USING THE SAME - A method of controlling a mobile terminal on an external device basis and an external device operation system using the same are provided. The system includes a connector for connecting an external device, a switch for determining a type of the external device connected to the connector and switching according to the type thereof, a transceiver to be connected, if the external device is an external device which requires a high speed data transmission, to the external device according to switching of the switch, and a USB switch to be connected, if the external device is an external device which does not require a high speed data transmission, to the external device according to switching of the switch. | 2010-05-13 |
20100121992 | METHOD, DEVICE AND SYSTEM FOR STORING DATA IN CACHE IN CASE OF POWER FAILURE - A method, device and system for storing data in a cache in case of power failure are disclosed. The method includes: in case of power failure of a storage system, receiving configuration information from a central processing unit (CPU); establishing a mapping relationship between an address of data in the cache and an address in a storage device according to the configuration information; sending a signaling message that carries the mapping relationship to the cache, so that the cache migrates the data to the storage device according to the signaling message. | 2010-05-13 |
20100121993 | STORAGE ROUTER AND METHOD FOR PROVIDING VIRTUAL LOCAL STORAGE - A storage router and storage network provide virtual local storage on remote storage devices. A plurality of devices are connected to a first transport medium. In one embodiment, a storage router maintains a map to allocate storage space on the remote storage devices to devices connected to the first transport medium by associating representations of the devices connected to the first transport medium with representations of storage space on the remote storage devices. The storage router controls access from the devices connected to the first transport medium to the storage space on the remote storage devices in accordance with the map and allows access from devices connected to the first transport medium to the remote storage devices using native low level block protocol. | 2010-05-13 |
20100121994 | STACKED MEMORY ARRAY - A memory subsystem, array controller, method, and design structure are provided for a stacked memory array. The memory subsystem includes an array controller and at least one memory array. The array controller includes a primary and secondary buffer interface to communicate with a memory controller via a cascade interconnected bus. The array controller also includes an array access controller to process memory access commands received via one of the primary and secondary buffer interfaces. The at least one memory array includes a memory cell array die separately packaged with respect to the array controller and coupled to the array controller in a stacked configuration via memory core data lines using through silicon vias (TSVs). | 2010-05-13 |
20100121995 | SYSTEM AND METHOD FOR SUPPORTING TCP OUT-OF-ORDER RECEIVE DATA USING GENERIC BUFFER - A method and system for handling received out-of-order network data using generic buffers for non-posting TCP applications is disclosed. When incoming out-of-order data is received and there is no application buffer posted, a TCP data placement may notify a TCP reassembler to terminate a current generic buffer, allocate a new current generic buffer, and DMA the incoming data into the new current generic buffer. The TCP data placement may notify the TCP reassembler the starting TCP sequence number and the length of the new current generic buffer. Moreover, the TCP data placement may add entries into a TCP out-of-order table when the incoming data creates a new disjoint area. The TCP data placement may adjust an existing disjoint area to reflect any updates. When a TCP application allocates or posts a buffer, then the TCP reassembler may copy data from a linked list of generic buffers into posted buffers. | 2010-05-13 |
20100121996 | AUTOMATICALLY SWITCHING CONSOLE CONNECTION - A method and system for configuring a network device is provided. In one implementation the method and system may include directing, via a multiplexer, a group of signals defined by a serial communication format from a primary serial configuration interface to a communication port in a CPU. A universal-serial-bus-to-serial (USB) signal may be detected at a USB interface and converted by a USB-to-serial converter circuit to the serial communication format and directed, via the same multiplexer, to the universal-asynchronous-receiver-transmitter instead of the serial signals from the primary serial configuration interface. A detection signal may be communicated from the USB-to-serial converter circuit to the multiplexer. Alternatively, the detection signal may be directed to the CPU, which may then communicate a selection signal to the multiplexer. | 2010-05-13 |
20100121997 | METHOD FOR WRITING DIGITAL CONTENTS TO A PLURALITY OF STORAGE CARDS AND THE SYSTEM FOR THE SAME - A method for writing digital contents to a plurality of storage card by using a mina console comprises the following steps of: placing a storage card to a respective one of a plurality of card writing devices; writing digital contents to a storage card through a Hub by using a main console; a plurality of cards can be recorded by serially connection or parallel connection so as to increase the writing speed; and placing the storage cards into card readers; and whether the process of writing digital contents is successful being displayed. A system for the same is also included. | 2010-05-13 |
20100121998 | COMPUTER OPERATING DEVICE - An operating device ( | 2010-05-13 |
20100121999 | Generating of a Device Description for a Measuring Device - A method for generating a device description for a measuring apparatus in a target field bus protocol is described. The method comprises the reception of a first device description of the apparatus. The first device description of the apparatus comprises at least one variable. The at least one variable is related to a storage cell of the apparatus. The target field bus protocol is selected from a plurality of field bus protocols, and at least one block is formed from the at least one variable. The at least one block has a maximum block size that corresponds to the smallest maximum block size of at least two field bus protocols of the plurality of field bus protocols. The maximum block size can be transmitted via a field bus with a single request when the respective field bus protocol is used. Subsequently, the at least one block is provided as device description for the apparatus in the target field bus protocol. | 2010-05-13 |
20100122000 | Method for Accessing a Data Transmission Bus, Corresponding Device and System - The invention relates to a bus, which is connectable to a primary master and to secondary masters, the bus being suitable for the transmission of data between the peripherals. In order to ensure a minimum rate and/or maximum latency between the secondary masters, when the primary master uses a small time fraction available on the bus, said primary master is provided with the highest priority and comprises means for wirelessly accessing to a medium. The inventive method for accessing to the bus consists in authorising the primary master to access to the bus upon the request thereof and in selecting the access to the bus for the secondary masters when the primary master peripheral does not request said access to the bus. | 2010-05-13 |
20100122001 | TECHNIQUE FOR INTERCONNECTING INTEGRATED CIRCUITS - Two integrated circuit die each having a processing core and on-board memory are interconnected and packaged together to form a multi-chip module. The first die is considered primary and the second die is considered secondary are connected through an interposer. The first and second die may be the same design and thus have the same resources such as peripherals and memory and preferably have a common system interconnect protocol. The core of the second die is disabled or at least placed in a reduced power mode. The first die includes minimal circuit for interconnecting to the second die. The second die has some required interface circuitry and an address translator. The result is that the core of the first die can perform transactions with the memory and other resources of the second integrated circuit as if the memory and other resources were on the first die. | 2010-05-13 |
20100122002 | AUTOMATIC ON-DEMAND PRESCALE CALIBRATION ACROSS MULTIPLE DEVICES WITH INDEPENDENT OSCILLATORS OVER AN I2C BUS INTERFACE - A system and method for synchronizing otherwise independent oscillators private to I | 2010-05-13 |
20100122003 | RING-BASED HIGH SPEED BUS INTERFACE - A communication system management interface includes a control master; and one or more slaves under management by the control master; wherein each device, either the control master or slave, has at least an input signal connected to an output signal of another device to form a daisy-chain. | 2010-05-13 |
20100122004 | MESSAGE SWITCHING SYSTEM - The message switching system comprises at least two inputs and at least one output, first arbitration means dedicated to said output, and management means designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system and having sent requests for the assignment of said output, and designed to assign said output. Said management means comprise storage means designed to store said relative orders OR(i,j), initialization means designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means designed to update all of said relative orders when a new request arrives at said first arbitration means, or when said output is assigned to one of said inputs. | 2010-05-13 |
20100122005 | Method and System for Detecting Interrups From Detachable Electronic Accessories Or Peripherals - Aspects of a method and system for detecting interrupts from detachable electronic accessories or peripherals are provided. In this regard, a hardware audio CODEC may be operable to compare a voltage on one or more biased pins of an accessory or peripheral port to one or more reference voltages and filter one or more output signals generated from the comparison. When an accessory or peripheral is coupled to the accessory or peripheral port, interrupts from the accessory or peripheral may be detected based on results of the comparison and/or the filtering. An interrupt may be detected when the voltage on the one or more pins may be below the one or more reference voltages. An interrupt may be detected when the voltage on the one or more pins may be below the one or more reference voltages for a plurality of consecutive clock cycles. | 2010-05-13 |
20100122006 | INTERRUPT DETECTION APPARATUS AND INFORMATION PROCESSING SYSTEM - An interrupt detection apparatus includes a detection address region storing unit configured to store an address region, as a detection address region, to be detected in accordance with a first interrupt message having address information, an issuance interrupt information storing unit configured to store address information of a second interrupt message as issuance interrupt information, an interrupt message detection unit configured to determine that the first interrupt message corresponds to the detection address region, and an interrupt issuing unit configured to issue the second interrupt message having the issuance interrupt information when it is determined that the first interrupt message corresponds to the detection address region. | 2010-05-13 |
20100122007 | MICROCONTROLLER WITH CONFIGURABLE LOGIC ARRAY - A microcontroller may have a central processing unit (CPU); a programmable logic device receiving input signals and having input/outputs coupled with external pins, and an interrupt control unit receiving at least one of the internal input signals or being coupled with at least one of the input/outputs and generating an interrupt signal fed to the CPU. | 2010-05-13 |
20100122008 | INTERRUPT MORPHING AND CONFIGURATION, CIRCUITS, SYSTEMS, AND PROCESSES - An electronic configuration circuit includes a processing circuit ( | 2010-05-13 |
20100122009 | I/O SPACE REQUEST SUPPRESSING METHOD FOR PCI DEVICE - To minimize the restriction on the number of available PCI devices although the assignable size of I/O space is limited, an arithmetic unit is provided with a configuration information acquisition device for acquiring the configuration information about PCI devices, an available space determination device for determining available space for each PCI device, and a configuration information notification device for notifying an operating system of the configuration information. | 2010-05-13 |
20100122010 | USB SHARING SWITCH WITH AUTOMATIC SWITCHING CAPABILITIES - A USB printer sharing switch device with automatic switching capabilities is provided for multiple computers to share a USB printer. The sharing switch device transfers USB data between the computers and the printer without changing the data format. The automatic switching function is performed by hardware and firmware of the sharing switch device in cooperation with driver software on the computers. In one implementation, the sharing switch device includes multiple USB device controllers corresponding to the multiple computers, and employs multiple switches and a USB hub so that each computer is connected to its corresponding controller and the computer that is currently connected to the printer can communicate with its controller while printing. The current computer transmits a spooling finished command to its controller when spooling is finished. After receiving the spooling finished command, the sharing switch device automatically switches the printer to another computer. | 2010-05-13 |
20100122011 | Method and Apparatus for Supporting Multiple High Bandwidth I/O Controllers on a Single Chip - An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers. | 2010-05-13 |
20100122012 | SYSTOLIC NETWORKS FOR A SPIRAL CACHE - Systolic networks within a tiled storage array provide for movement of requested values to a front-most tile, while making space for the requested values at the front-most tile by moving other values away. A first and second information pathway provide different linear pathways through the tiles. The movement of other values, requests for values and responses to requests is controlled according to a clocking logic that governs the movement on the first and second information pathways according to a systolic duty cycle. The first information pathway may be a move-to-front network of a spiral cache, crossing the spiral push-back network which forms the push-back network. The systolic duty cycle may be a three-phase duty cycle, or a two-phase duty cycle may be provided if the storage tiles support a push-back swap operation. | 2010-05-13 |
20100122013 | DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES - A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state. | 2010-05-13 |
20100122014 | Method For Protecting Memory Proprietary Commands - A method for protecting memory proprietary command is provided. By using the logic block area (LBA) address in the header of the LBA mode, the device end can determine whether the data sector in the LBA mode includes a proprietary command. Also, by using the pre-defined computation function to establish a relation among the values stored in a plurality of characteristic point addresses and a specific point address so that he device end can determine whether a proprietary command is received. As the operating system will not filter out the proprietary command wrapped in this manner, the proprietary command can pass the operating system and be executed by the device end. | 2010-05-13 |
20100122015 | SOFTWARE ADAPTED WEAR LEVELING - A subset of software objects stored in a first segment of non-volatile memory are identified as requiring frequent write operations or otherwise associated with a high endurance requirement. The subset of software objects are move to a second segment of non-volatile memory with a high endurance capacity, due to the application of wear leveling techniques to the second segment of non-volatile memory. The first and second segments of memory can be located in the same memory device or different memory devices. | 2010-05-13 |
20100122016 | DYNAMIC SLC/MLC BLOCKS ALLOCATIONS FOR NON-VOLATILE MEMORY - Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode. | 2010-05-13 |
20100122017 | MEMORY CONTROLLER, NON-VOLATILE MEMORY SYSTEM, AND HOST DEVICE - Provided is a nonvolatile memory system which can be used for a boot program storage and easily controlled by a host device. At the time of reading a boot code | 2010-05-13 |
20100122018 | BACKUP METHOD, BACKUP DEVICE, AND VEHICLE CONTROLLER - A backup method includes the following processes. Backup data is temporarily stored in a volatile memory. An erased area is saved in a flash memory for the backup data. The erased area is free of data. The backup data is written in the erased area. | 2010-05-13 |
20100122019 | APPARATUS, SYSTEM, AND METHOD FOR MANAGING PHYSICAL REGIONS IN A SOLID-STATE STORAGE DEVICE - An apparatus, system, and method are disclosed for managing physical regions in a solid-state storage device. The definition module defines a physical storage region on solid-state storage media of a solid-state storage device. The physical storage region includes a subset of total physical storage capacity on the solid-state storage media. The storage controller performs memory operations within the physical storage region such that the memory operations are bounded to the physical storage region. The implementation module implements the physical storage region definition with respect to the storage controller for the solid-state storage media. | 2010-05-13 |
20100122020 | DYNAMIC PERFORMANCE VIRTUALIZATION FOR DISK ACCESS - A storage control system includes performance monitor logic configured to track performance parameters for different volumes in a storage array. Service level enforcement logic is configured to assign target performance parameters to the different volumes and generate metrics for each of the different volumes identifying how much the performance parameters change for the different volumes responsive to changes in the amounts of tiering media allocated to the different volumes. Resource allocation logic is configured to allocate the tiering media to the different volumes according to the performance parameters, target performance parameters, and metrics for the different volumes. | 2010-05-13 |
20100122021 | USB-Attached-SCSI Flash-Memory System with Additional Command, Status, and Control Pipes to a Smart-Storage Switch - An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access. | 2010-05-13 |
20100122022 | SSD WITH IMPROVED BAD BLOCK MANAGMENT - In some embodiments, a memory controller includes a plurality of processors of a first type and a processor of a second type coupled to the processors of the first type. Each of the plurality of processors of the first type is configured to determine a bad block rate of a memory channel of a solid state memory device to which it is configured to be coupled. The processor of the second type is configured to receive the bad block data rates from each of the plurality of processors of the first type and to report one of a total capacity or a bad block rate of the solid state memory device to a host device. The total capacity and the bad block rate of the solid state memory device are based on the bad block rates received from each of the plurality of processors of the first type. | 2010-05-13 |
20100122023 | PORTABLE ELECTRONIC DEVICE AND METHOD FOR PROTECTING DATA OF THE PORTABLE ELECTRONIC DEVICE - A portable electronic device includes a random access memory, a non-volatile random access memory, a detecting unit, and a processing unit. The detecting unit is configured to detect an acceleration of the portable electronic device. The processing unit is configured to compare a value of the acceleration of the portable electronic device with a predetermined parameter. If the value of the acceleration is greater or equal to the predetermined parameter, data is copied from the random access memory to the non-volatile random access memory. | 2010-05-13 |
20100122024 | METHODS AND SYSTEMS FOR DIRECTLY CONNECTING DEVICES TO MICROCONTROLLERS - Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller. In another embodiment, the device may include a bus translator and a self-selecting bus decoder. The bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses. A microcontroller may be coupled to a selected one of the plurality of different types of buses of the bus translator. | 2010-05-13 |
20100122025 | LOW COST IMPLEMENTATION FOR SMALL CONTENT-ADDRESSABLE MEMORIES - A content-addressable memory (CAM) for managing the reallocation of erasable objects within a non-volatile memory is conceptually separated into two tables: a first table provides verification of whether or not a logical address has been reallocated and, if so, a second table provides the physical address of the reallocated erasable object. | 2010-05-13 |
20100122026 | SELECTIVELY READING DATA FROM CACHE AND PRIMARY STORAGE - Techniques are provided for using an intermediate cache to provide some of the items involved in a scan operation, while other items involved in the scan operation are provided from primary storage. Techniques are also provided for determining whether to service an I/O request for an item with a copy of the item that resides in the intermediate cache based on factors such as a) an identity of the user for whom the I/O request was submitted, b) an identity of a service that submitted the I/O request, c) an indication of a consumer group to which the I/O request maps, d) whether the I/O request is associated with an offloaded filter provided by the database server to the storage system, or e) whether the intermediate cache is overloaded. Techniques are also provided for determining whether to store items in an intermediate cache in response to the items being retrieved, based on logical characteristics associated with the requests that retrieve the items. | 2010-05-13 |
20100122027 | Storage controller - A storage controller of the present invention enables a larger number of storage devices to be mounted while keeping the installation size small. A plurality of sub-storage units are disposed inside a high density-type storage unit. The respective sub-storage units comprise a plurality of hard disk drives, controller, memory, power supply device, and display part. The respective sub-storage units operate independently of one another. A controller creates a management table based on management data acquired from the respective sub-storage units. The user is notified when there is an error in the table contents. A display part lights up in accordance with an indication from a storage unit specification part, notifying the user of the location of the sub-storage unit. | 2010-05-13 |
20100122028 | METHOD AND SYSTEM FOR CONTROLLING INFORMATION OF LOGICAL DIVISION IN A STORAGE CONTROLLER - A storage controller is realized in which validity/invalidity of functions is settable in a unit of logical division in conformity with logical division of logical groups control is performed such that operation has the influence upon only the inside of a range defined by resource groups of logical division and an Inband I/F for accessing functions is made to match with the logical division. Further, access control cooperative with information on the user side (information of server, user and application) is realized by causing a management server to manage information in the storage controller and user information. | 2010-05-13 |
20100122029 | MEMORY CONTROL DEVICE AND METHOD FOR CONTROLLING THE SAME - The present invention provides a storage control device which enables the time between failures to prolong as much as possible, though it uses HDD's whose mean time between failures is relatively short. The storage control device controls spindle motors in a manner that a spindle motor is rotated regarding the HDD of data which can access from a host computer and a spindle motor is stopped regarding the HDD of data which are clearly judged that a host computer does not access the data. Whether the host computers can access the HDD or not is judged by the fact that whether the memory region (internal logical volume) provided by the HDD is in mapped to the host logical volume or not which is recognized by the host computer and is able to access thereby. | 2010-05-13 |
20100122030 | COMPUTER SYSTEM AND PROCESS FOR TRANSFERRING MULTIPLE HIGH BANDWIDTH STREAMS OF DATA BETWEEN MULTIPLE STORAGE UNITS AND MULTIPLE APPLICATIONS IN A SCALABLE AND RELIABLE MANNER - Multiple applications request data from multiple storage units over a computer network. The data is divided into segments and each segment is distributed randomly on one of several storage units, independent of the storage units on which other segments of the media data are stored. At least one additional copy of each segment also is distributed randomly over the storage units, such that each segment is stored on at least two storage units. This random distribution of multiple copies of segments of data improves both scalability and reliability. When an application requests a selected segment of data, the request is processed by the storage unit with the shortest queue of requests. Random fluctuations in the load applied by multiple applications on multiple storage units are balanced nearly equally over all of the storage units. This combination of techniques results in a system which can transfer multiple, independent high-bandwidth streams of data in a scalable manner in both directions between multiple applications and multiple storage units. | 2010-05-13 |
20100122031 | SPIRAL CACHE POWER MANAGEMENT, ADAPTIVE SIZING AND INTERFACE OPERATIONS - A spiral cache memory provides low access latency for frequently-accessed values by self-organizing to always move a requested value to a front-most storage tile of the spiral. If the spiral cache needs to eject a value to make space for a value moved to the front-most tile, space is made by ejecting a value from the cache to a backing store. A buffer along with flow control logic is used to prevent overflow of writes of ejected values to the generally slow backing store. The tiles in the spiral cache may be single storage locations or be organized as some form of cache memory such as direct-mapped or set-associative caches. Power consumption of the spiral cache can be reduced by dividing the cache into an active and inactive partition, which can be adjusted on a per-tile basis. Tile-generated or global power-down decisions can set the size of the partitions. | 2010-05-13 |
20100122032 | SELECTIVELY PERFORMING LOOKUPS FOR CACHE LINES - Embodiments of the present invention provide a system that selectively performs lookups for cache lines. During operation, the system by maintains a lower-level cache and a higher-level cache in accordance with a set of rules that dictate conditions under which cache lines are held in the lower-level cache and the higher-level cache. The system next performs a lookup for cache line A in the lower level cache. The system then discovers that the lookup for cache line A missed in the lower-level cache, but that cache line B is present in the lower-level cache. Next, in accordance with the set of rules, the system determines, without performing a lookup for cache line A in the higher-level cache, that cache line A is guaranteed not to be present and valid in the higher-level cache because cache line B is present in the lower-level cache. | 2010-05-13 |
20100122033 | MEMORY SYSTEM INCLUDING A SPIRAL CACHE - An integrated memory system with a spiral cache responds to requests for values at a first external interface coupled to a particular storage location in the cache in a time period determined by the proximity of the requested values to the particular storage location. The cache supports multiple outstanding in-flight requests directed to the same address using an issue table that tracks multiple outstanding requests and control logic that applies the multiple requests to the same address in the order received by the cache memory. The cache also includes a backing store request table that tracks push-back write operations issued from the cache memory when the cache memory is full and a new value is provided from the external interface, and the control logic to prevent multiple copies of the same value from being loaded into the cache or a copy being loaded before a pending push-back has been completed. | 2010-05-13 |
20100122034 | STORAGE ARRAY TILE SUPPORTING SYSTOLIC MOVEMENT OPERATIONS - A tile for use in a tiled storage array provides re-organization of values within the tile array without requiring sophisticated global control. The tiles operate to move a requested value to a front-most storage element of the tile array according to a global systolic clock. The previous occupant of the front-most location is moved or swapped backward according to the systolic clock, and the new occupant is moved forward according to the systolic clock, according to the operation of the tiles, while providing for multiple in-flight access requests within the tile array. The placement heuristic that moves the values is determined according to the position of the tiles within the array and the behavior of the tiles. The movement of the values can be performed via only next-neighbor connections of adjacent tiles within the tile array. | 2010-05-13 |
20100122035 | SPIRAL CACHE MEMORY AND METHOD OF OPERATING A SPIRAL CACHE - A spiral cache memory provides reduction in access latency for frequently-accessed values by self-organizing to always move a requested value to a front-most central storage element of the spiral. The occupant of the central location is swapped backward, which continues backward through the spiral until an empty location is swapped-to, or the last displaced value is cast out of the last location in the spiral. The elements in the spiral may be cache memories or single elements. The resulting cache memory is self-organizing and for the one-dimensional implementation has a worst-case access time proportional to N, where N is the number of tiles in the spiral. A k-dimensional spiral cache has a worst-case access time proportional to N | 2010-05-13 |
20100122036 | METHODS AND APPARATUSES FOR IMPROVING SPECULATION SUCCESS IN PROCESSORS - Methods and apparatuses are disclosed for improving speculation success in processors. In some embodiments, the method may include executing a plurality of threads of program code, the plurality of threads comprising a first speculative load request, setting an indicator bit corresponding to a cache line in response to the first speculative load request, and in the event that a second speculative load request from the plurality of threads refers to a first cache line with the indicator bit set, determining if a second cache line is available. | 2010-05-13 |
20100122037 | DEVICE AND METHOD FOR GENERATING CACHE USER INITIATED PRE-FETCH REQUESTS - A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate. | 2010-05-13 |
20100122038 | METHODS AND APPARATUSES FOR IMPROVING SPECULATION SUCCESS IN PROCESSORS - Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue. | 2010-05-13 |
20100122039 | Memory Systems and Accessing Methods - Memory systems and accessing methods are disclosed. In one embodiment, a method of accessing a memory device includes accessing a first end of the memory device regarding a first data type, and accessing a second end of the memory device regarding a second data type. | 2010-05-13 |
20100122040 | ACCESS CONTROLLER - The present invention aims to provide an access control apparatus that can improve responsiveness to an access request of a processor compared with a conventional technology. | 2010-05-13 |
20100122041 | MEMORY CONTROL APPARATUS, PROGRAM, AND METHOD - A memory control apparatus which controls access to a shared memory for each transaction. The apparatus includes a management unit that stores versions of data stored in the shared memory, a log storage unit that stores an update entry including a version of data subjected to an update operation in response to execution of an update operation on the shared memory in processing each transaction, and a control unit that writes a result of processing corresponding to execution of a relevant update operation to the shared memory when a request to commit a transaction has been given, and a relevant update entry version matches a corresponding version stored in the management unit, or re-executes the update operation and writes a result of re-execution to the shared memory when the update entry version does not match the corresponding version in the management unit. | 2010-05-13 |
20100122042 | Multi-windows color adjustment system and method - The invention provides a multi-windows color adjustment system and method that divides the picture frame of a display screen into three or more windows so that the user can compare the color tones of the windows and then select the preferred window. The multi-windows color adjustment system includes a memory read/write controller coupled to an image data input for temporarily storing an input image data and executing read/write control, a window control unit coupled to the memory read/write controller for executing size, data flow and color tone controls of the windows, a line buffer coupled to the memory read/write controller and the window control unit for storing a line data, and a color adjustment unit coupled to the window control unit and the line buffer for executing the processing of color adjustment of the image data in the windows subject to the control of the window control unit. | 2010-05-13 |
20100122043 | MEMORY AND METHOD APPLIED IN ONE PROGRAM COMMAND FOR THE MEMORY - A memory and a method applied in one program command for the memory are provided. The memory includes a buffer and at least one program unit. The method includes the following steps. First, enter the program command to the memory. Next, enter user data to the buffer. Read the data of the program unit. Determine whether the user data fill the buffer. Fill the part of the buffer unoccupied by the user data with the data of the program unit if the user data do not fill the buffer. Erase the program unit if the program unit is not empty. Finally, program the data of the buffer into the program unit. | 2010-05-13 |
20100122044 | Data dependency scoreboarding - A parallel processing technique is described for performing parallel processing operations upon N-dimensional arrays of data elements for which a corresponding N-dimensional Scoreboard of status data is held. Hazard checking for data dependencies upon data elements within the N-dimensional array of data elements is performed by looking up the corresponding status value within the Scoreboard. The status data for a given data element within the Scoreboard is located at a position which can be derived from the position of the data elements within its N-dimensional array. Thus, a two-dimensional array of video macroblocks can have a corresponding two-dimensional Scoreboard of status data indicating whether individual macroblocks have, for example, either already been deblocked or have not already been deblocked. | 2010-05-13 |
20100122045 | Method for processing data using triple buffering - The present invention relates to a method for processing data. A data block to be processed is written to a memory area in a first interval of time. The data block is processed in the same memory area (A, B, C) in a second interval of time. The processed data block is returned from the same memory area in a third interval of time. | 2010-05-13 |
20100122046 | Memory Micro-Tiling - According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel. | 2010-05-13 |
20100122047 | SYSTEMS AND METHODS FOR ENHANCING A DATA STORE | 2010-05-13 |
20100122048 | MANAGING MEMORY PAGES - A method, and corresponding software and system, is described for paging memory used for one or more sequentially-accessed data structure. The method includes providing a data structure representing an order in which memory pages are to be reused; and maintaining the data structure according to a history of access to a memory page associated with one of the sequentially-accessed data structures. A position of the memory page in the order depends on a transition of sequential access off of the memory page. | 2010-05-13 |
20100122049 | SYSTEM AND METHOD FOR MANAGING AN ELECTRONIC STORAGE VOLUME - A system and method for managing an electronic storage volume is described. The method includes assigning a threshold to a constrained storage space to define a first state in which an amount of data stored in the constrained storage space exceeds the threshold and a second state in which the amount of data stored in the confined storage space does not exceed the threshold. The method also includes comparing the amount of data to be stored in the constrained storage space and the threshold, and performing a predefined action if the comparison indicates that the amount data to be in the confined storage space would cause a transition between the first state and the second state. | 2010-05-13 |
20100122050 | VIRTUAL STORAGE MIGRATION TECHNIQUE TO MINIMIZE SPINNING DISKS - A method, and system for employing the method, for virtual data storage migration providing a plurality of data storage devices communicating with at least one computer system. A plurality of data being managed by the computer system and an archive data storage device is selected from the plurality of data storage devices. Specified data is selected for archiving in the archive data storage device when the archive data meets a specified archive criteria. After the archived specified data is accessed in the archive data storage device at a predetermined frequency, the archive data is migrated to an active data storage device in a powered up state. The archive data storage device is then powering down. | 2010-05-13 |
20100122051 | REMOTE COPYING MANAGEMENT SYSTEM, METHOD AND APPARATUS - A management system for managing storage systems, having first correspondence information concerned with correspondence of copy pairs with copy groups as setting of remote copying of data in logical volumes of the storage systems, and second correspondence information concerned with correspondence of physical paths and logical paths between the storage systems with the copy groups, wherein when failure information designating a certain physical path is received, a copy group affected by failure in the certain physical path is specified and displayed by referring to the first correspondence information and the second correspondence information. Consequently, physical paths can be monitored from the viewpoint of remote copying. | 2010-05-13 |
20100122052 | Generating and Using Checkpoints in a Virtual Computer System - To generate a checkpoint for a virtual machine (VM), first, while the VM is still running, a copy-on-write (COW) disk file is created pointing to a parent disk file that the VM is using. Next, the VM is stopped, the VM' s memory is marked COW, the device state of the VM is saved to memory, the VM is switched to use the COW disk file, and the VM begins running again for substantially the remainder of the checkpoint generation. Next, the device state that was stored in memory and the unmodified VM memory pages are saved to a checkpoint file. Also, a copy may be made of the parent disk file for retention as part of the checkpoint, or the original parent disk file may be retained as part of the checkpoint. If a copy of the parent disk file was made, then the COW disk file may be committed to the original parent disk file. | 2010-05-13 |
20100122053 | SYSTEMS AND METHODS FOR PERFORMING DATA REPLICATION - Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is configured to process a copy of the log and consistency point entries to replicate data in a replication volume, the replicated data being a copy of the application data on the source system. When the replicated data represents a known good state of the application, as determined by the consistency point entries, the destination system(s) may perform a storage operation (e.g., snapshot, backup) to copy the replicated data and to logically associate the copied data with a time information (e.g., time stamp) indicative of the source system time when the application was in the known good state. | 2010-05-13 |
20100122054 | COPY SAFE STORAGE - A data storage device provides information to an application while protecting the information from being copied. Particularly, the data storage device may include a detector to detect an access to an indicator. The indictor may be integrated with the information in such a way that a copy application will access the indicator when copying the information but another application using the information (e.g. a database application) will not access the indicator. The data storage device may further be configured to undertake a defensive response when access to the indicator is detected. Defensive responses may include terminating the access, issuing a report, or sending spurious data to the host. The configuration of the indicator and timing of the response may be chosen to impede separation of the indicator from the data. | 2010-05-13 |
20100122055 | DATA INTEGRITY VALIDATION USING HIERARCHICAL VOLUME MANAGEMENT - A method for reading data from a data storage system is provided. The method comprises requesting a virtual data volume to access data from one or more data blocks in the data storage system; requesting a virtual protection information volume to access protection information associated with the data blocks; validating the data using the protection information; and providing the data to the host interface, in response to successful validation of the data. A method for writing data to a data storage system is also provided. The method comprises receiving data to be written to one or more data blocks in the data storage system, wherein the data is stored in a cache; generating protection information to be stored on a virtual protection information volume; requesting a virtual data volume to update the data blocks with the data; and requesting the virtual protection information volume to store the protection information. | 2010-05-13 |
20100122056 | Method and Device for Securely Storing and Securely Reading User Data - User data is stored in at least one record in at least one predefined, logic data storage area. One respective record ID is assigned to the at least one record. The record ID includes a uniqueness stamp that is unique in the respective predefined data storage area, a unique ID of the predefined data storage area in which the respective record is stored, and a logic position of the respective record within the respective predefined data storage area. A record test value is determined and stored for the user data and the respective associated record ID of the respective record. Data storage area information containing the ID of the respective predefined data storage area and data on at least one value range of the uniqueness stamps of the records currently stored in the respective predefined data storage area is assigned to the respective predefined data storage area. | 2010-05-13 |
20100122057 | TILED STORAGE ARRAY WITH SYSTOLIC MOVE-TO-FRONT REORGANIZATION - A tiled storage array provides reduction in access latency for frequently-accessed values by re-organizing to always move a requested value to a front-most storage element of array. The previous occupant of the front-most location is moved backward according to a systolic pulse, and the new occupant is moved forward according to the systolic pulse, preserving the uniqueness of the stored values within the array, and providing for multiple in-flight access requests within the array. The placement heuristic that moves the values according to the systolic pulse can be implemented by control logic within identical tiles, so that the placement heuristic moves the values according to the position of the tiles within the array. The movement of the values can be performed via only next-neighbor connections of adjacent tiles within the array. | 2010-05-13 |
20100122058 | Memory page eviction based on present system operation - Systems, methods, and other embodiments associated with selecting a memory page for removal from a buffer pool based on the operating conditions of a computing system. | 2010-05-13 |
20100122059 | Memory Command Delay Balancing In A Daisy-Chained Memory Topology - A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel. A separate DIMM-specific response delay unit in the DIMM may also be programmed to provide DIMM-specific delay compensation in the response path, further allowing the memory controller to accurately ascertain the timing of receipt of a response thereat, and, hence, to better manage further processing of the response. | 2010-05-13 |
20100122060 | SYSTEM AND METHOD FOR ALLOCATING AND DEALLOCATING MEMORY WITHIN TRANSACTIONAL CODE - Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed. | 2010-05-13 |
20100122061 | TECHNIQUES FOR IMPLEMENTING ACCURATE DEVICE PARAMETERS STORED IN A DATABASE - Systems, memory modules and methods of configuring systems including memory modules are provided. The memory modules include device parameters specifically corresponding to memory devices of the memory module. The device parameters may be retrieved from a database, and the system may be configured in accordance with the device parameters retrieved from the database. | 2010-05-13 |
20100122062 | Using an IOMMU to Create Memory Archetypes - In one embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory and control logic coupled to the memory. The memory is configured to store translation data corresponding to one or more I/O translation tables stored in a memory system of a computer system that includes the IOMMU. The control logic is configured to translate an I/O device-generated memory request using the translation data. The translation data includes a type field indicating one or more attributes of the translation, and the control logic is configured to control the translation responsive to the type field. | 2010-05-13 |
20100122063 | INFORMATION PROCESSING APPARATUS AND METHOD - A read-only memory (ROM) includes storage areas used as a processing setting data storage unit, a successful detection rate storage unit, and a processing time storage unit. A central processing unit (CPU) can function as a calculation unit by executing a calculation program stored on the ROM. The successful detection rate storage unit stores a predetermined successful detection rate (the probability of executing subsequent processing based on a result of a current processing). The processing time storage unit stores a predetermined processing time of each processing. The calculation unit calculates a module configuration for executing each processing according to the successful detection rate stored on the successful detection rate storage unit and the processing time stored on the processing time storage unit. The processing setting data storage unit stores setting data of a characteristic amount and a setting data of positional information about image data (the address of the image data). | 2010-05-13 |
20100122064 | METHOD FOR INCREASING CONFIGURATION RUNTIME OF TIME-SLICED CONFIGURATIONS - A device may include a data processing logic cell field and one or more sequential CPUs. The logic cell field and the CPUs may be configured to be coupled to each other for data exchange. The data exchange may be in block form using lines leading to a cache memory. In a method for operating a reconfigurable unit having runtime-limited configurations, the configurations may be able to increase their maximum allowed runtime, e.g., by triggering a parallel counter. An increase in configuration runtime by the configurations may be suppressed in response to an interrupt. | 2010-05-13 |
20100122065 | System and Method for Large-Scale Data Processing Using an Application-Independent Framework - A large-scale data processing system and method for processing data in a distributed and parallel processing environment. The system includes an application-independent framework for processing data having a plurality of application-independent map modules and reduce modules. These application-independent modules use application-independent operators to automatically handle parallelization of computations across the distributed and parallel processing environment when performing user-specified data processing operations. The system also includes a plurality of user-specified, application-specific operators, for use with the application-independent framework to perform a user-specified data processing operation on a user-specified set of input files. The application-specific operators include: a map operator and a reduce operator. The map operator is applied by the application-independent map modules to input data in the user-specified set of input files to produce intermediate data values. The reduce operator is applied by the application-independent reduce modules to process the intermediate data values to produce final output data. | 2010-05-13 |
20100122066 | INSTRUCTION METHOD FOR FACILITATING EFFICIENT CODING AND INSTRUCTION FETCH OF LOOP CONSTRUCT - Instruction set techniques have been developed to identify explicitly the beginning of a loop body and to code a conditional loop-end in ways that allow a processor implementation to efficiently manage an instruction fetch buffer and/or entries in an instruction cache. In particular, for some computations and processor implementations, a machine instruction is defined that identifies a loop start, stores a corresponding loop start address on a return stack (or in other suitable storage) and directs fetch logic to take advantage of the identification by retaining in a fetch buffer or instruction cache the instruction(s) beginning at the loop start address, thereby avoiding usual branch delays on subsequent iterations of the loop. A conditional loop-end instruction can be used in conjunction with the loop start instruction to discard (or simply mark as no longer needed) the loop start address and the loop body instructions retained in the fetch buffer or instruction cache. | 2010-05-13 |
20100122067 | ACROSS-THREAD OUT-OF-ORDER INSTRUCTION DISPATCH IN A MULTITHREADED MICROPROCESSOR - Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel. | 2010-05-13 |
20100122068 | MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD - A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines. | 2010-05-13 |
20100122069 | Macroscalar Processor Architecture - A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel. Other methods and apparatuses are also described. | 2010-05-13 |
20100122070 | Combined associative and distributed arithmetics for multiple inner products - Subvector slices x(i,r,s) of a first vector x(i) are stored (e.g., in a CAM array) in a bit-parallel word-serial manner. For each of the stored subvector slices and in parallel on bits of said each subvector slice, an operation is executed that outputs a pre-calculated inner product result of the said bits and a second vector a. If the subvector slices x(i,r,s) of the first vector x(i) are initially stored in a bit-serial word-serial manner, there is a transform to store them in the bit-parallel word serial manner by copying relevant bits of each of the subvector slices from a 0 | 2010-05-13 |
20100122071 | SEMICONDUCTOR DEVICE AND DATA PROCESSING METHOD - A semiconductor device includes a first circuit that executes a first calculation, a second circuit that includes a first storage unit therein and executes a second calculation, a controller that outputs a first address for specifying a first execution circuit for the first calculation and a second execution circuit for the second calculation, to the first circuit and the second circuit, and controls input of data into the first circuit, and a bus that transfers a result of the first calculation executed by the first circuit to the second circuit, wherein the result of the first calculation can be conditionally used as an address for specifying the second execution circuit. | 2010-05-13 |
20100122072 | Debugging system, debugging method, debugging control method, and debugging control program - A debugging system according to an exemplary embodiment of the present invention includes: a plurality of arithmetic processing units ( | 2010-05-13 |
20100122073 | HANDLING EXCEPTIONS IN SOFTWARE TRANSACTIONAL MEMORY SYSTEMS - A method and apparatus for handling exceptions during execution of a transaction is herein described. A compiler associates a transaction exception handler (TEH) with a transaction in program code, such as through insertion of a call to the TEH. The TEH is also associated with an exception data structure, such as an unwind table, that is utilized during runtime to call an appropriate handler in response to an exception. Additionally, the TEH code is generated by the compiler and inserted into the program code. Upon encountering an exception during execution of the transaction, the TEH is capable of dynamically resizing the transaction to the point of the exception through an attempted commit. | 2010-05-13 |
20100122074 | Blood Glucose Tracking Apparatus and Methods - A measurement module for glucose testing includes a glucose testing measurement module housing, a test strip receptacle formed in the housing, and a connector portion formed in the housing and shaped to permit mechanical removable attachment of the housing to a hand-held computer. Electronics determine the amount of glucose present in a sample of body fluid, when the test strip is positioned in the receptacle and the body fluid is placed on a test strip, and communicate the glucose amount to the hand-held computer via the connector portion. | 2010-05-13 |
20100122075 | METHOD FOR CONTROLLING BOOT SEQUENCE OF SERVER - A method for controlling a boot sequence of a server includes the following steps. A boot image is created, and a first proxy server program is placed into the boot image. The first proxy server program communicates with a management server. The boot image is restored on a rewritable removable storage device, so as to enable the rewritable removable storage device to boot a managed target server. A second proxy server program is installed and executed in the management server. A basic input/output system (BIOS) of the target server is set to enable the rewritable removable storage device to act as a first boot device. Boot files in the rewritable removable storage device are modified through the first proxy server program or the second proxy server program according to a boot instruction received from the management server, thereby controlling a boot sequence of the target server. | 2010-05-13 |
20100122076 | SECURITY METHOD - A security method for verifying a client device comprising: loading and executing a boot loader at the client device which establishes a connection to a boot compliance server; sending a first cryptographic element from the boot compliance server to the client device; generating a first cryptographic response with the first cryptographic element based on at least part of the boot loader and sending the first cryptographic response to the boot compliance server for verification; and continuing the boot process upon successful verification of the first cryptographic response. | 2010-05-13 |
20100122077 | SWITCHING BETWEEN MULTIPLE OPERATING SYSTEMS (OSes) USING SLEEP STATE MANAGEMENT AND SEQUESTERED RE-BASEABLE MEMORY - Embodiments of switching between multiple operating systems (OSes) using sleep state management and sequestered re-baseable memory are generally described herein. Embodiments of the invention allow one OS to be suspended into S3 or sleep mode, saving its state to memory and turning off its devices. Then, another sleeping OS can be resumed from another location in memory by switching a memory base addressed to a sequestered memory region and restoring its device state. Other embodiments may be described and claimed. | 2010-05-13 |
20100122078 | SYSTEMS AND METHODS FOR CREATING A CODE INSPECTION SYSTEM - A code inspection system produces a dynamic decoy machine that closely parallels one or more protected systems. The code inspection system can analyze and monitor one or more protected systems, and as those protected systems are updated, altered or modified, the dynamic decoy machine, in which potentially malicious code is tested, can also be updated. Thus, the dynamic decoy machine can accurately reflect the current state of the one or more protected systems such that the potentially destructive nature, if any, of suspicious code can be evaluated as if it were in the actual environment of the protected system, without jeopardizing the security of the protected system. | 2010-05-13 |
20100122079 | COPYRIGHT PROTECTION SYSTEM, REPRODUCTION APPARATUS AND METHOD - The object of the present invention is to provide a reproduction apparatus that is capable of preventing personal information of users from being transmitted to an external apparatus that is under management of a malicious person. | 2010-05-13 |
20100122080 | PSEUDONYM CERTIFICATE PROCESS SYSTEM BY SPLITTING AUTHORITY - The present invention can't independently know real name information of a user unless a server of an authority treating real name certificate and a server of an authority treating pseudonym certificate collaborate mutually, so that privacy of a user isn't infringed. The present invention can acquire real name information of a user with collaboration of real name certification sever and pseudonym certification sever only if you need real name information for a user. | 2010-05-13 |
20100122081 | METHOD OF VALIDATION PUBLIC KEY CERTIFICATE AND VALIDATION SERVER - In response to a validation request that includes second information identifying the certificate authority, key information of the certificate authority at issuance of the public key certificate, and information identifying the public key certificate, if the second information identifying the certificate authority included in the validation request corresponds to the first information identifying the certificate authority included in the authority certificate, and the information identifying the public key certificate included in the validation request does not exist in the revocation information, the validation server creates a validation result indicating that the public key certificate corresponding to the information identifying the public key certificate included in the validation request is valid. | 2010-05-13 |
20100122082 | USER IDENTITY VALIDATION SYSTEM AND METHOD - An identity validation system and method for the Internet provides user accountability while supporting user privacy to counter SPAM, Internet vandalizers, and predators, as well as cyber bullies who use the Internet to communicate with actual or potential victims. The system includes network authority software that issues a permanent identity and secret code to a user and disseminates different hashed versions of the permanent identity and secret code to different agents. A user hardware Internet passport generates hashed versions of the permanent identity and secret code as well as a passcode that is generated from the hashed secret code and user software generates a temporary identity from the hashed permanent identity. The user software transmits the temporary identity and passcode to a selected agent that performs the actual identity validation. | 2010-05-13 |
20100122083 | METHOD AND APPARATUS FOR SECURELY COMMUNICATING PERSONAL HEALTH INFORMATION - A method of securely communicating personal health information between a user terminal and a health care server. The method includes receiving an encryption key from a security key issuing device through a local communication between a user terminal and the security key issuing device; obtaining health information of a user; encrypting the health information by using the encryption key; and transmitting the encrypted health information to a health care server through a network communication between the user terminal and the health care server. | 2010-05-13 |
20100122084 | METHOD, APPARATUS AND SYSTEM FOR REGISTERING NEW MEMBER IN GROUP KEY MANAGEMENT - A method for registering a new member in group key management is disclosed. An agent is deployed on the local network that requires the automatic group key management service; the agent receives an original registration request message sent by a new member in the local network, encapsulates the original registration request message and an information indicating the new member into a first request message, and sends the first request message to a Group Controller Key Server (GCKS); and the agent receives a first response message returned by the GCKS, extracts the information indicating the new member and the original response message carrying the processing result of request from the first response message, and sends the original response message to the new member according to the information indicating the new member. Apparatuses and system for registering a new member in group key management are also disclosed. According to the present invention, a new member that joins a network can be registered automatically. | 2010-05-13 |
20100122085 | SYSTEM AND METHOD FOR PROVIDING VARIABLE SECURITY LEVEL IN A WIRELESS COMMUNICATION SYSTEM - A system and method for providing variable security levels in a wireless communication network. The present invention optimizes the often conflicting demands of highly secure wireless communications and high speed wireless communications. According to a preferred embodiment of the present invention, various security sensors are scanned to determine the likely presence of an intruder within a predetermined trust zone. If an intruder is likely present, the security level is changed to the highest setting, and consequently a lower data rate, while the intruder is identified. If the identified intruder is in fact a trusted node, the security level is returned to a lower setting. If the identified intruder is not a trusted node, the security level is maintained at an elevated state while the intruder is within the trust zone. | 2010-05-13 |
20100122086 | METHOD FOR COMBINING DATA TO BE PROCESSED WITH A DATA-SPECIFIC APPARATUS, AND APPARATUS AND COMPUTER PROGRAM FOR IMPLEMENTING THE METHOD - The invention discloses a method and a system for combining data with an apparatus which is provided for processing the data, with the following steps: (a) determining an identifier associated with the apparatus; (b) generating a first key by using the identifier and a second secret key, which is independent of the identifier; (c) generating a decryption algorithm to be used for the second key and providing the decryption algorithm to the apparatus; (d) encrypting a rights object, which allows access to the data, using the first key and the second secret key; (e) transmitting the data and the rights object to the apparatus; (f) decrypting the rights object with the apparatus by using the identifier associated with the apparatus and the decryption algorithm associated with the apparatus; and (g) decrypting the data using a key selected by a rights owner and included in the decrypted rights object. | 2010-05-13 |
20100122087 | METHOD AND APPARATUS FOR LOGGING IN A HEALTH INFORMATION TELE-MONITORING DEVICE BY USING A PERSONAL PORTABLE DEVICE - A method of logging in a health information tele-monitoring device by using a personal portable device. The method includes issuing a security key embedded in a health information tele-monitoring device to a personal portable device, storing the security key issued by the health information tele-monitoring device in the user's personal portable device; requesting the user's personal portable device to authenticate the health information tele-monitoring device in order to connect the health information tele-monitoring device to a healthcare server; and authorizing access of the health information tele-monitoring device to the healthcare server. | 2010-05-13 |
20100122088 | METHOD AND SYSTEM FOR CONTROL OF CODE EXECUTION ON A GENERAL PURPOSE COMPUTING DEVICE AND CONTROL OF CODE EXECUTION IN A RECURSIVE SECURITY PROTOCOL - Embodiments of systems and methods which provide highly specific control over the execution of general-purpose code block are disclosed. These embodiments may allow the exact circumstances under which a given code block is allowed to execute to be determined with specificity. Such a control mechanism may be coupled with embodiments of a data hiding system and method, based for example, on an ordered execution of a set of code segments implemented via recursive execution. When embodiments of these systems and methods are utilized together an unencumbered generality as well as a level of protection against attack that surpasses many other security systems may be obtained. | 2010-05-13 |
20100122089 | SYSTEM AND METHOD FOR COMPRESSING SECURE E-MAIL FOR EXCHANGE WITH A MOBILE DATA COMMUNICATION DEVICE - A system and method are provided for pre-processing encrypted and/or signed messages at a host system before the message is transmitted to a wireless mobile communication device. The message is received at the host system from a message sender. There is a determination as to whether any of the message receivers has a corresponding wireless mobile communication device. For each message receiver that has a corresponding wireless mobile communication device: the message is processed so as to modify the message with respect to encryption and/or authentication aspect. The processed message is transmitted to a wireless mobile communication device that corresponds to the first message receiver. The system and method may include post-processing messages sent from a wireless mobile communications device to a remote system. Authentication and/or encryption message processing is performed upon the message. The processed message may then be sent through the remote system to one or more receivers. | 2010-05-13 |
20100122090 | Secure Bytecode Instrumentation Facility - A secure bytecode instrumentation facility, wherein a new code fragment is registered in an encrypted registry by first extracting a digital certificate from a specified code fragment location. A certification authority (CA) in the digital certificate is compared against a list of registered trusted certification authorities in the registry. If the CA is in the registry list, the code fragment origin in the digital certificate is compared against a list of registered trusted origins in the registry. If the code fragment origin is in the registry list, a determination is made as to whether the code fragment is authentic. If so, the information of the code fragment is recorded into the registry. The injection of code fragments may begin upon the initialization of the instrumentation facility if the encrypted registry has not been corrupted since last accessed, and if the code fragment content matches code fragment information in the registry. | 2010-05-13 |