19th week of 2010 patent applcation highlights part 30 |
Patent application number | Title | Published |
20100118581 | MAGNETIC MEMORY DEVICE - The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed. | 2010-05-13 |
20100118582 | MEMORY MODULE AND MEMORY SYSTEM HAVING THE SAME - A memory module comprises of a plurality of memory chips arranged in a rank and configured to input and output data in response to at least one of a command signal and an address signal. The memory module also comprises of a plurality of chip select pin terminals configured to transfer a plurality of chip select signals provided from an external device to the plurality of memory chips. | 2010-05-13 |
20100118583 | MAGETIC SHIFT REGISTER AND DATA ACCESSING METHOD - A magnetic shift register memory includes at least a magnetic memory track, in which multiple domain walls separate the memory track into multiple magnetic domains to serve as magnetic memory cells. A fixed number of the magnetic memory cells forms a memory unit to store a burst data. A read/write device is implemented between the memory units to read or write the burst data to the magnetic memory cells passing the read/write device. A flag unit records a flag value for each memory track or each memory unit to indicate whether the burst data is located at a first side or a second side of the read/write device. A current unit provides an operation current to the magnetic memory track according to the flag value to move the domain walls to pass the read/write device. After the read/write device reads or writes the burst data, the flag value is updated. | 2010-05-13 |
20100118584 | MEMORY DEVICE USING ANTIFUSES - Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory. | 2010-05-13 |
20100118585 | HIGH DENSITY SPIN TORQUE THREE DIMENSIONAL (3D) MEMORY ARRAYS ADDRESSED WITH MICROWAVE CURRENT - One embodiment of the present invention includes a three dimensional memory array having a plurality of memory elements coupled to form the array through a single top lead and a single bottom lead, each memory element including a magnetic free layer in which non-volatile data can be stored, wherein each memory element possesses unique resonant frequencies associated with each digital memory state, thereby enabling frequency addressing during parallel write and read operations, each memory element further including a fixed layer and a spacer formed between the free layer and the fixed layer. | 2010-05-13 |
20100118586 | FERROELECTRIC MEMORY - A ferroelectric memory of an embodiment of the present invention includes a plurality of units, in each of which a ferroelectric capacitor and a transistor are connected to each other in parallel. The memory includes first and second memory cell arrays, first and second bit lines arranged in the first and second memory cell arrays, respectively, first and second blocks connected to the first bit line, and including N | 2010-05-13 |
20100118587 | RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY - Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data. | 2010-05-13 |
20100118588 | VOLTAGE REFERENCE GENERATION FOR RESISTIVE SENSE MEMORY CELLS - Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage for a resistive sense memory (RSM) cell, such as an STRAM cell. A dummy reference cell used to generate a reference voltage to sense a resistive state of an adjacent RSM cell. The dummy reference cell comprises a switching device, a resistive sense element (RSE) programmed to a selected resistive state, and a dummy resistor coupled to the RSE. A magnitude of the reference voltage is set in relation to the selected resistive state of the RSE and the resistance of the dummy resistor. | 2010-05-13 |
20100118589 | Non-Volatile Memory Cell with Multiple Resistive Sense Elements Sharing a Common Switching Device - A non-volatile memory cell array and associated method of use are disclosed. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs. | 2010-05-13 |
20100118590 | Bidirectional Non-Volatile Memory Array Architecture - A bidirectional memory array architecture for non-volatile memory is disclosed. In accordance with some embodiments, a plurality of memory cells are arranged into an M number of rows and an N number of columns with each memory cell having a resistive sense element (RSE) and a switching device. A total number of M+N+1 control lines extend adjacent to and are connected with the memory cells to facilitate bi-directional programming of resistive states to each memory cell. | 2010-05-13 |
20100118591 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: an oxide resistance change element, a constant current source circuit supplying a write current to the oxide resistance change element, and a voltage clamper clamping a voltage in a path in which a write current flows. The voltage clamper is arranged in parallel with the path between the constant current source circuit and the oxide resistance change element. | 2010-05-13 |
20100118592 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - Provided is a nonvolatile semiconductor memory device capable of performing a writing action for a memory cell at high speed. The device comprises: a memory cell array having a first sub-bank and a second sub-bank each having a plurality of nonvolatile memory cells arranged in a form of a matrix; a row decoder shared by the first sub-bank and the second sub-bank; a first column decoder and a second column decoder provided in the first sub-bank and the second sub-bank, respectively; and a control circuit arranged to execute alternately a first action cycle to perform a programming action in the first sub-bank and a reading action for a programming verifying action in the second sub-bank and a second action cycle to perform the reading action for the programming verifying action in the first sub-bank and the programming action in the second sub-bank. | 2010-05-13 |
20100118593 | VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM THEREOF - A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit. | 2010-05-13 |
20100118594 | METHOD AND APPARATUS PROVIDING A CROSS-POINT MEMORY ARRAY USING A VARIABLE RESISTANCE MEMORY CELL AND CAPACITANCE - The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is a capacitor. | 2010-05-13 |
20100118595 | RESISTANCE VARIABLE MEMORY DEVICES AND READ METHODS THEREOF - A resistance-variable memory device includes memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell may, for example, include a resistance-variable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline using the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage. | 2010-05-13 |
20100118596 | Embedded DRAM with bias-independent capacitance - An embedded memory system that includes DRAM cells and logic transistors. The capacitor of the embedded memory responds to a positive bias voltage of ½ Vdd. The wordline driver of a p-channel access transistor applying the positive power supply voltage when the p-channel access FET is not being accessed and a voltage lower than the threshold voltage of the p-channel access FET is being accessed. For DRAM cells containing an n-channel access FET, the wordline driver applies either a negative voltage or the ground voltage to the n-channel access FET when the DRAM cell is not being accessed. A second voltage composed of Vdd and a boosted voltage is applied to the n-channel FET when the DRAM cell is being accessed. | 2010-05-13 |
20100118597 | Multiple valued dynamic random access memory cell and thereof array using single electron transistor - Provided is a multi-valued dynamic random access memory (DRAM) cell using a single electron transistor (SET). The multi-valued DRAM cell using the SET applies different refresh signals to a load current transistor for controlling current supply to the SET and a voltage control transistor for controlling a terminal voltage of the SET and refreshes a data value stored in the SET by a predetermined period to reduce standby current and stably supply a voltage low enough to satisfy a coulomb-blockade condition to the terminal of the SET. | 2010-05-13 |
20100118598 | Phosphonium Ionic Liquids, Compositions, Methods of Making and Electronic Devices Formed There From - The invention generally encompasses phosphonium ionic liquids and compositions and their use in many applications, including but not limited to: as electrolytes in electronic devices such as memory devices including static, permanent and dynamic random access memory, as battery electrolytes, as a heat transfer medium, fuel cells and electrochromatic devices, among other applications. In particular, the invention generally relates to phosphonium ionic liquids, compositions and molecules possessing structural features, wherein the molecules exhibit superior combination of thermodynamic stability, low volatility, wide liquidus range and ionic conductivity. The invention further encompasses methods of making such phosphonium ionic liquids, compositions and molecules, and operational devices and systems comprising the same. | 2010-05-13 |
20100118599 | PROCESS FOR FORMING BOTH SPLIT GATE AND COMMON GATE FINFET TRANSISTORS AND INTEGRATED CIRCUITS THEREFROM - A method to fabricate an integrated circuit (IC) that includes a plurality of MOSFETs including at least one common gate FinFET device and at least one split gate FinFET device. A substrate having a semiconductor surface is provided. A plurality of fins are formed from the semiconductor surface including at least one taller fin of a first height and at least one shorter fin of a second height, wherein the first height is at least 10% greater than the second height. Gate slacks are formed on the taller and shorter fins such that a gate electrode for the taller fin is a split gate electrode and a gate electrode for the shorter fin is a common gate electrode. Fabrication of the IC is completed, wherein the split gate FinFET includes the split gate electrode and the common gate FinFET device includes the common gate electrode. An IC includes a substrate having a semiconductor surface, a plurality of semiconductor fins including at least one taller fin of a first height and at least one shorter fin of a second height, wherein the first height is at least 10% greater than the second height, and at least one common gate FinFET device formed from the shorter fin and at least one split gate FinFET device providing a parallel gate transistor pair comprising a first and a second transistor formed from the taller fin. | 2010-05-13 |
20100118600 | MAGNETORESISTIVE ELEMENT - A magnetoresistive element which records information by supplying spin-polarized electrons to a magnetic material, includes a first pinned layer which is made of a magnetic material and has a first magnetization directed in a direction perpendicular to a film surface, a free layer which is made of a magnetic material and has a second magnetization directed in the direction perpendicular to the film surface, the direction of the second magnetization reversing by the spin-polarized electrons, and a first nonmagnetic layer which is provided between the first pinned layer and the free layer. A saturation magnetization Ms of the free layer satisfies a relationship 0≦Ms<√{square root over ( )}{Jw/(6πAt)}. Jw is a write current density, t is a thickness of the free layer, A is a constant. | 2010-05-13 |
20100118601 | PHASE CHANGE RANDOM ACCESS MEMORY DEVICE - In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another. | 2010-05-13 |
20100118602 | DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF - A memory array includes a plurality of first and second source, lines overlapping a plurality of bit lines, and a plurality of magnetic storage elements, each coupled to a corresponding first and second source line and to a corresponding bit line. Current may be driven, in first and second directions, through each magnetic element, for example, to program the elements. Diodes may be incorporated to avert sneak paths in the memory array. A first diode may be coupled between each magnetic element and the corresponding first source line, the first diode being biased to allow read and write current flow through the magnetic element, from the corresponding first source line; and a second diode may be coupled between each magnetic element and the corresponding second source line, the second diode being reverse-biased to block read and write current flow through the magnetic element, from the corresponding second source line. | 2010-05-13 |
20100118603 | DEVICE AND METHOD OF PROGRAMMING A MAGNETIC MEMORY ELEMENT - The present disclosure provides a non-volatile memory device. A memory device includes a first magnetic element having a fixed magnetization. The memory device also includes a second magnetic element having a non-fixed magnetization. The memory device further includes a barrier layer between the first and second magnetic elements. A unidirectional current source is electrically coupled to the first and second magnetic elements. The current source is configured to provide a first current to the first and second memory elements. The first current has a first current density and is in a first direction. The current source is also configured to provide a second current to the first and second magnetic elements. The second current has a second current density, different than the first current density, and is in the first direction. The first and second currents cause the non-fixed magnetization of the second magnetic element to toggle between substantially parallel to the fixed magnetization of the first magnetic element and between substantially antiparallel to the fixed magnetization of the first magnetic element. | 2010-05-13 |
20100118604 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING NON-SELECTED WORD LINES ADJACENT TO SELECTED WORD LINES BEING CHARGED AT DIFFERENT TIMING FOR PROGRAM DISTURB CONTROL - A non-volatile semiconductor memory device includes a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during data writing, a high voltage for writing is applied to a selected word line, and an intermediate voltage for writing is applied to at least two of non-selected word lines. The beginning of charging a first word line located between the selected word line and a source line to a first intermediate voltage for writing is followed by the beginning of charging a second word line located between the selected word line and a bit line contact to a second intermediate voltage for writing. | 2010-05-13 |
20100118605 | SEMICONDUCTOR STORAGE DEVICE ADAPTED TO PREVENT ERRONEOUS WRITING TO NON-SELECTED MEMORY CELLS - A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the potentials on the word lines and the bit lines in accordance with input data to write data to the memory cells. The control circuit is adapted to, at the write time, first apply a first potential to a well region or substrate in which the memory cells are formed, then set the well region or substrate to a second potential lower than the first potential, and next apply a predetermined voltage to the word lines to thereby perform a write operation. | 2010-05-13 |
20100118606 | Methods of programming non-volatile memory devices and memory devices programmed thereby - In a method of programming a non-volatile memory device, and in a device incorporating the same, the memory device includes: a plurality of memory cell transistors arranged in a plurality of transistor strings, wherein a transistor string includes a plurality of memory cell transistors arranged in series; a plurality of word lines, each word line connected to a corresponding memory cell transistor of each of the different transistor strings; and a plurality of bit lines, each bit line connected to one of the transistor strings. The method comprises: applying a first voltage to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; and applying a second voltage to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor. | 2010-05-13 |
20100118607 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ADAPTED TO STORE A MULTI-VALUED DATA IN A SINGLE MEMORY CELL - A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell. | 2010-05-13 |
20100118608 | NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM, AND METHOD DETERMINING READ VOLTAGE IN SAME - A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit. | 2010-05-13 |
20100118609 | Nonvolatile semiconductor memory, and method for reading data - A nonvolatile semiconductor memory includes a memory cell, a first gate control circuit that is coupled to the memory cell, and a second gate control circuit that is coupled to the memory cell. The memory cell includes a first gate electrode that is formed above a channel region in a semiconductor substrate, a second gate electrode that is formed beside the first gate electrode, and that is capacitively coupled with the first gate electrode through a first insulating layer, and a charge trapping layer that is formed between the channel region and the second gate electrode, and that includes a second insulating layer for trapping a charge. Data stored in a memory cell transistor including the second gate electrode changes depending on an amount of the charge trapped in the charge trapping layer. The first gate control circuit applies a potential to the first gate electrode, when reading the data stored in the memory cell transistor. The second gate control circuit brings the second gate electrode into a floating state, when the potential is applied to the first gate electrode. | 2010-05-13 |
20100118610 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A stacked body with a plurality of dielectric films and electrode films alternately stacked therein is provided. The electrode film is divided into a plurality of control gate electrodes extending in one direction. The stacked body is provided with a U-pillar penetrating through the select gate electrodes and the control gate electrodes, having one end connected to a source line, and having the other end connected to a bit line. Moreover, a different potential is applied to uppermost one of the control gate electrodes than that applied to the other control gate electrodes. | 2010-05-13 |
20100118611 | DELAYED ACTIVATION OF SELECTED WORDLINES IN MEMORY - Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in the array. | 2010-05-13 |
20100118612 | SEMICONDUCTOR MEMORY DEVICE AND READ ACCESS METHOD THEREOF - The semiconductor memory device includes a plurality of memory cell arrays and a control circuit that outputs a first signal and a second signal. The first signal instructs start of precharging of each memory cell array. The second signal instructs completion of the precharging and transition to a read access. The first signal is wired through one or more delay circuits to arrive at each memory cell array with a time difference, and the second signal is wired not through the one or more delay circuits. | 2010-05-13 |
20100118613 | Method of erasing data in flash memory device - A method of erasing data in a flash memory device, including erasing data in at least one flash memory cell using a first erase voltage; detecting whether the at least one flash memory cell has a threshold voltage less than a first voltage; programming the at least one flash memory cell by varying the threshold voltage of the at least one flash memory cell using a second voltage that is greater than the first voltage if the detecting step detects the threshold voltage is less than the first voltage; maintaining the threshold voltage of the at least one flash memory cell if the detecting step detects the threshold voltage is greater than the first voltage; and verifying the at least one flash memory cell using a first verification voltage. | 2010-05-13 |
20100118614 | SEMICONDUCTOR APPARATUS, DATA WRITE CIRCUIT OF SEMICONDUCTOR APPARATUS, AND METHOD OF CONTROLLING DATA WRITE CIRCUIT - A data write circuit of a semiconductor apparatus includes a plurality of latches configured to latch a plurality of data in response to activation of a plurality of control signals and output the latched data to data lines; and a control unit configured to generate the plurality of control signals to be activated at different timings, such that partial data input at relatively earlier timing among the plurality of data is latched at earlier timing than the other data by a portion of the plurality of latches. | 2010-05-13 |
20100118615 | Semiconductor memory device - A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line. | 2010-05-13 |
20100118616 | Semiconductor memory device - A semiconductor memory device having shared sense amplifiers is provided. The semiconductor memory device has a bit-line selector disposed closer to a memory cell array than a column decoder. When the column decoder outputs a bit-line indication signal corresponding to the number of bit lines, the bit-line selector selects a plurality of bit lines in response to the bit-line indication signal. Thus, it is possible to reduce the number of signals output from the column decoder. | 2010-05-13 |
20100118617 | MEMORIES WITH IMPROVED WRITE CURRENT - A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level. | 2010-05-13 |
20100118618 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH DATA BUS INVERSION FUNCTION - A semiconductor integrated circuit includes a data bus inversion (DBI) flag generating unit to generate DBI flag signals using a plurality of output data sets, a data inverting unit to invert the plurality of output data sets according to the DBI flag signals and transmit the plurality of output data sets through global transmission lines, and a plurality of data output units to output the plurality of output data sets, which are transmitted through the global transmission lines by pads. | 2010-05-13 |
20100118619 | BUFFER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A buffer circuit of a semiconductor memory apparatus includes a compensation voltage generation unit configured to generate a compensation voltage in response to a level of a reference voltage; and a buffering unit configured to generate an output signal by buffering an input signal depending on the reference voltage and control a transition section of the output signal depending on a level of the compensation voltage. | 2010-05-13 |
20100118620 | Semiconductor Device - A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored in the memory circuit is analyzed in advance. In the case where “high” is the majority data, memory cells storing “high” are formed with vacant cells in which a semiconductor element is not formed. | 2010-05-13 |
20100118621 | Implementing Variation Tolerant Memory Array Signal Timing - A method and signal timing adjustment circuit for implementing variation tolerant memory array signal timing, and a design structure on which the subject circuit resides are provided. A logic circuit generates a first delay signal based upon logic devices forming the logic circuit. A memory cell circuit receives the first delay signal and generates control signals responsive to the first delay signal and based upon memory cell devices forming the memory cell circuit. A programmable logic delay circuit receives the control signals and generates a timing adjustment signal. | 2010-05-13 |
20100118622 | 1-TRANSISTOR TYPE DRAM CELL, A DRAM DEVICE AND MANUFACTURING METHOD THEREFORE, DRIVING CIRCUIT FOR DRAM, AND DRIVING METHOD THEREFOR - The present invention relates to an 1-transistor DRAM cell, a DRAM device and a manufacturing method therefor, a driving circuit for a DRAM, a driving method therefore, and a driving method for an 1-transistor DRAM, and a double-gate type 1-transistor DRAM. The present invention comprises a data hold process biasing a word line at a negative voltage level and biasing a sensing line and a bit line at a first constant voltage level; a data purging process resetting data by biasing the word line and the bottom word line at a second constant voltage level and biasing the sensing line and the bit line at the first constant voltage level; and a data write process biasing the word line and the bottom word line at the second constant voltage level and supplying a write data to the bit line. | 2010-05-13 |
20100118623 | Method of operating semiconductor devices - A method of operating a semiconductor device including a memory cell of a 1-T DRAM is provided in which a gate voltage level in a hold mode is adjusted to adjust a data sensing margin of the semiconductor device. | 2010-05-13 |
20100118624 | READ CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - Provided is a read circuit for a semiconductor memory device which may have a reduced circuit scale, and a semiconductor memory device. In a plurality of sense amplifiers of the read circuit of the semiconductor memory device, for serially reading data from a serial output terminal, if a number of byte selectors which may be selected to determine an address at a predetermined time before determination of the address is four, only four sense amplifiers are required in total, and hence the read circuit and the semiconductor memory device are reduced in circuit scale. | 2010-05-13 |
20100118625 | CHARGE PUMP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A charge pump circuit includes a first charge pump unit that includes a first capacitor and a second capacitor connected in parallel and generates a first charge pump voltage in the second capacitor by pumping the first capacitor, and a second charge pump unit that includes a third capacitor connected to the second capacitor in series and generates a second charge pump voltage in the second capacitor by further pumping the first charge pump voltage charged in the second capacitor via the third capacitor. In this manner, by pumping the latter stage capacitor from among the capacitors connected in parallel by a parallel connection method, the voltage applied between the capacitor electrodes of the latter stage capacitor is lowered. | 2010-05-13 |
20100118626 | Delay device for shifting phase of strobe signal - A delay apparatus includes a DLL circuit including a delay element, the DLL circuit generating a first control signal for controlling the delay element in order that the delay element delays a reference clock inputted into the delay element by one cycle, and a strobe delay element having a configuration identical to a configuration of the delay element, the strobe delay element delaying the strobe signal inputted from an outside by an amount of delay corresponding to a second control signal. The delay apparatus further includes a strobe delay controlling circuit obtaining the second control signal, from the first control signal and an expectation value for the amount of delay to be made by the strobe delay element, and a clock supplying circuit supplying the DLL circuit with the reference clock having a frequency higher than a frequency of the strobe signal. | 2010-05-13 |
20100118627 | STROBE-OFFSET CONTROL CIRCUIT - A strobe offset control circuit is disclosed. The control circuit comprises a strobe signal input to receive a strobe signal and a data receiver to receive a data signal in response to a sample signal derived from the strobe signal. A calibration enable input is provided to receive a calibration enable signal. The calibration enable signal places the strobe offset control circuit in one of a calibration mode or a receiver mode. In the calibration mode, a phase offset between the data signal and the sample signal is adjusted based on output from the receiver. In the receiver mode, the phase offset between the data signal and the sample signal is not adjusted based on output from the receiver. | 2010-05-13 |
20100118628 | MEMORY CIRCUIT AND TRACKING CIRCUIT THEREOF - The invention provides a tracking circuit of a memory circuit. The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect data bits output by a memory cell array. In one embodiment, the tracking circuit comprises a plurality of dummy cells, a dummy bit line, and an inverter. At least one of the plurality of dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for pulling down the voltage of the dummy bit line when the word-line pulse signal is enabled. The dummy bit line is coupled between the dummy cells and the inverter. The inverter inverts the voltage of the dummy bit line to generate the sense amplifier enable signal. | 2010-05-13 |
20100118629 | APPARATUS FOR CONTROLLING I/O STROBE SIGNAL IN SEMICONDUCTOR MEMORY APPARATUS - A sensing enable signal control circuit determines a driving timing of an I/O sense amplifier based on a read-out result of data, which is stored in a dummy cell of a semiconductor memory apparatus. The sensing enable signal control circuit in a semiconductor memory apparatus includes a detection code generating unit configured to output a detection code according to a voltage level of dummy cell data, which are read out from a dummy cell through at least one read operation, in response to a column select enable signal, and a multiplexer configured to receive the detection code and a default code and output a delay code to delay a sensing enable signal. | 2010-05-13 |
20100118630 | Method and Apparatus for Synchronizing Data From Memory Arrays - According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 2010-05-13 |
20100118631 | Semiconductor memory devices with mismatch cells - A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily. | 2010-05-13 |
20100118632 | CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING SIMULTANEOUS SWITCHING OUTPUT NOISE, POWER NOISE, OR COMBINATIONS THEREOF - Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal. | 2010-05-13 |
20100118633 | SEMICONDUCTOR MEMORY DEVICE HAVING DUMMY SENSE AMPLIFIERS AND METHODS OF UTILIZING THE SAME - A semiconductor memory device having dummy sense amplifiers and a method of utilizing the same are provided. Embodiments of the semiconductor memory device may include at least one dummy cell block including dummy cells and memory cells. Normal bit lines connecting the memory cells in the dummy cell block in a first direction and dummy bit lines connecting the dummy cells in the first direction. A dummy sense amplifier is also included for connecting any two of the normal bit lines and the dummy bit lines. Some of the embodiments may improve the sensing margin and refresh margin in sensing memory cells in the dummy cell, as well as increasing the redundancy efficiency and utilization of the dummy cells. | 2010-05-13 |
20100118634 | Semiconductor apparatuses and methods of operating the same - A method of operating a semiconductor device is provided including applying a constant source voltage to a source line. | 2010-05-13 |
20100118635 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device is capable of performing a stable high-speed operation while inputting/outputting data. The semiconductor memory device includes an inversion output circuit configured to output a clocking pattern in a clocking mode, and an inversion pin to which the inversion output circuit is connected. | 2010-05-13 |
20100118636 | Methods and Systems Involving Electrically Reprogrammable Fuses - An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. | 2010-05-13 |
20100118637 | Circuts and methods for reducing minimum supply for register file cells - A register file employing a shared supply structure to improve the minimum supply voltage. | 2010-05-13 |
20100118638 | SEMICONDUCTOR MEMORY APPARATUS HAVING DECREASED LEAKAGE CURRENT - A semiconductor memory apparatus includes a MOS transistor configured to be supplied with a first voltage through a bulk terminal thereof. The semiconductor memory apparatus also includes a current control unit configured to be connected to a source terminal of the MOS transistor, receive a power down mode enable signal and a self refresh mode enable signal, apply a second voltage to the source terminal during a power down mode or a self refresh mode, and apply the first voltage to the source terminal during modes other than the power down mode and the self refresh mode. | 2010-05-13 |
20100118639 | SEMICONDUCTOR MEMORY APPARATUS - A reference voltage selecting unit selectively outputs a first external reference voltage and a second external reference voltage as a selection reference voltage in accordance with whether to perform a wafer test. An address buffer generates an internal address by buffering an external address in accordance with the selection reference voltage. A command buffer generates an internal command by buffering an external command in accordance with the selection reference voltage. A data buffer generates internal data by buffering an external data in accordance with the second external reference voltage. | 2010-05-13 |
20100118640 | MOBILE CONCRETE MIXING PLANT - A transportable concrete mixing plant is provided and includes a frame, a mixing drum for mixing concrete, a rail positioned above the mixing drum, and a carriage assembly mounted to the rail for positioning containers of dry premix concrete so that the premix may be dispensed from the containers into the drum. The concrete pump dispenses liquid concrete from the mixing drum and pumps it to a remote location, such as a work site. | 2010-05-13 |
20100118641 | METHOD AND APPARATUS FOR CONTROLLING A STREAM OF SOLIDS - A method for controlling at least one of a level of solids and an inventory of solids in a solids tank includes withdrawing a stream of solids from the solids tank via a downer. The stream of solids withdrawn from the solids tank is fluidized at a bottom of the downer by supplying a conveying gas so as to convey the withdrawn stream of solids upward via a riser branching off from the downer, a size of the conveyed stream of solids being adjusted by the supplying of the conveying gas. At least one of the level and the inventory of the solids in the solids tank is used as an adjustment variable of a control circuit and a volume flow of the conveying gas is used as an actuating variable of the control circuit. | 2010-05-13 |
20100118642 | Airfoil-Shaped Micro-Mixers for Reducing Fouling on Membrane Surfaces - An array of airfoil-shaped micro-mixers that enhances fluid mixing within permeable membrane channels, such as used in reverse-osmosis filtration units, while minimizing additional pressure drop. The enhanced mixing reduces fouling of the membrane surfaces. The airfoil-shaped micro-mixer can also be coated with or comprised of biofouling-resistant (biocidal/germicidal) ingredients. | 2010-05-13 |
20100118643 | AGITATOR FOR ABRASIVE MEDIA - Disclosed is a agitator ( | 2010-05-13 |
20100118644 | METHOD AND SYSTEM FOR CONTROLLING STREAMERS - A method and system for controlling the shape and separation of an arrangement of streamers towed behind a survey vessel. Each streamer is steered laterally by lateral steering devices positioned along its length at specific nodes. Each streamer is driven by its lateral steering devices to achieve a specified separation from a neighboring streamer. One of these actual streamers, used as a reference by the other actual streamers, is steered to achieve a specified separation from an imaginary, or ghost, streamer virtually towed with the actual streamers. | 2010-05-13 |
20100118645 | COIL SHOOTING MODE - The technique disclosed herein includes a method and apparatus for controlling streamer steering devices to maintain a coil streamer shape that gives coverage for a coil shooting plan. The technique uses solved positions and a target coil streamer shape identified in the shooting plan to determine steering instructions to the streamer steering devices along the streamer. | 2010-05-13 |
20100118646 | Seismic vibrator array and method for using - A method for generating seismic energy for subsurface surveying includes operating a first seismic vibrator and operating at least a second seismic vibrator substantially contemporaneously with the operating the first seismic vibrator. A driver signal to each of the first and the at least a second seismic vibrators that are substantially uncorrelated with each other. | 2010-05-13 |
20100118647 | Method for optimizing energy output of from a seismic vibrator array - A method for generating seismic energy for subsurface surveying includes operating a first seismic vibrator and operating at least a second seismic vibrator in a body of water substantially contemporaneously with the operating the first seismic vibrator. Each vibrator has a different selected frequency response, and the vibrators each are operated at a depth in the water such that a surface ghost amplifies a downward output of each vibrator within a selected frequency range. A signal used to drive each vibrator has a frequency range corresponding to the frequency range of each vibrator. | 2010-05-13 |
20100118648 | EMAT Acoustic Signal Measurement Using Modulated Gaussian Wavelet and Hilbert Demodulation - Casing signals generated by an EMAT in a borehole are processed using one or more band-limited Gaussian filters. By using the Hilbert transform, an envelope of the filtered signals is determined and amplitudes and arrival times of individual arrivals are estimated. These can be used to estimate casing and cement properties. | 2010-05-13 |
20100118649 | Method and Apparatus for Echo-Peak Detection for Circumferential Borehole Image Logging - Signals from an acoustic transducer used in a borehole include overlapping, ringing reflections from the casing walls, voids in the cement and the formation. By using the Hilbert transform, an envelope of the signals is determined and individual echoes are detected by using a Gauss-Laplace operator. | 2010-05-13 |
20100118650 | 4D SEISMIC SIGNAL ANALYSIS - Methods of seismic data collection are described that reduce the amount of data required, reduce noise in the data collected and collect more data in areas where data collection is required. This results in a dramatic reduction of datasets required and improves noise reduction in data collected. By reducing the amount of data collected and increasing the noise reduction, a more accurate seismic survey is conducted at a dramatically reduced cost. | 2010-05-13 |
20100118651 | METHOD FOR GENERATION OF IMAGES RELATED TO A SUBSURFACE REGION OF INTEREST - A method and system for generating images of a subsurface region of interest. In general, one embodiment of the present invention includes establishing boundary conditions utilizing seismic data and initial conditions which include excitation from source locations in an earth model. Source wavefields are then propagated forward through the earth model to a maximum time, and saved at a plurality of checkpoints sparsely in time and also corresponding boundary values of the source wavefields at each time step are saved. Source wavefields are also propagated backward through the earth model from the maximum time utilizing the plurality of checkpoints when available and the saved boundary values at each time step. Receiver wavefields are propagated backward concurrently through the earth model from the maximum time. Imaging conditions are applied at selected time steps to both the backward propagated source wavefields and receiver wavefields and those wavefields are utilized to generate images related to the subsurface region. | 2010-05-13 |
20100118652 | Determination of depth moveout and of residual radii of curvature in the common angle domain - A method is disclosed for processing seismic data. The method includes prestack depth migrating seismic measurements to compute common angle domain image gathers with an initial depth model. Residual moveout analysis is performed in the common angle domain, moveout corrections are derived in terms of the residual radii of curvature at zero reflection angle. Corrections for larger reflection angles are obtained from separate analyses for the coefficients of suitable series expansions. The residual radii of curvature at zero reflection angle can be used to improve the signal to noise ratio of the migrated data and to assess or improve the velocity model used for the prestack depth migration. | 2010-05-13 |
20100118653 | Vertical seismic profiling velocity estimation method - A method includes providing a first velocity model obtained from a VSP survey representative of an upper region of a subterranean formation. Wavefield equations from the first velocity model are datumed to a datum line between the upper region and a target area beneath the upper region to obtain datumed wavefield equations. The method further includes obtaining interferometric common shot data and interferometric common midpoint data from the datumed wavefield equations at the datum line. The first velocity model, the datumed wavefield equations, and the interferometric common midpoint data are then used to generate a second velocity model representative of velocities in the target area. | 2010-05-13 |
20100118654 | Vertical seismic profiling migration method - A method includes seismic wave field continuation, imaging and data analysis steps that are applied in a near well region. | 2010-05-13 |
20100118655 | Progressive 3D vertical seismic profiling method - A method includes providing a first data set representative of a first 3D VSP of a first region of a subterranean formation, and providing a second data set representative of a second 3D VSP of a second region of the subterranean formation. The first data set and the second data set define a common region of the subterranean formation. The first data set and the second data set are merged within the common region to produce a third data set representative of a third 3D VSP of the first and second regions of subterranean formation. The third data set is then stored on a computer readable medium. | 2010-05-13 |
20100118656 | RELIABLE BROADCAST DELIVERY OF COMMUNICATIONS IN LAND-BASED SEISMIC SURVEYING - A method for use in a land-based seismic survey includes: transmitting a plurality of source control commands to a plurality of seismic sources over a VHF/IP network; and managing congestion on the VHF/IP network while transmitting the source control commands. In other aspects, a program storage medium encoded with instructions that, when executed by a processor, perform such a method and a computer programmed to perform such a method. | 2010-05-13 |
20100118657 | Bit Based Formation Evaluation and Drill Bit and Drill String Analysis Using an Acoustic Sensor - A drill bit having a bit body includes one or more acoustic sensors that are configured to detect elastic waves when the drill bit is used for drilling a wellbore. The acoustic sensor may be configured to detect a sonic signature associated with a failure event. In further arrangements, the acoustic sensors may be configured to receive signals from a controlled acoustic source. | 2010-05-13 |
20100118658 | ACOUSTIC LOCATION OF GUNSHOTS USING COMBINED ANGLE OF ARRIVAL AND TIME OF ARRIVAL MEASUREMENTS - A gunshot location system computes candidate gunshot locations from angle-of-arrival information and time-of-arrival information provided by acoustic sensors. In addition to an angle, each sensor calculates an angular uncertainty from impulses received at four or more microphones having rotational symmetry. An intersection of one or more time-of-arrival hyperbolas with one or more angle-of-arrival beams is used to determine a candidate gunshot location. In simple environments, a location can be confirmed with just two sensors allowing sensor density to be significantly reduced, while in complex environments including reflections, blocking, and interfering acoustic events, the additional angle-of-arrival information improves location accuracy and confidence, allowing elimination of candidate locations inconsistent with the combined time-of-arrival and angle-of-arrival information. | 2010-05-13 |
20100118659 | Interval timer - The present invention is directed towards a device and method of use for ensuring that persons who need to stay on a schedule can do so without constantly looking at a clock. The device is a programmable electronic device wherein the user can set a schedule time, an interval time and a sub-interval time and wherein the device alerts the user when one or more of these times are reached. | 2010-05-13 |
20100118660 | TIME/DATE INFORMATION PROVIDING SYSTEM AND TIME/DATE INFORMATION PROVIDING METHOD - A time/date information providing system is provided which includes a time/date information providing server for managing time/date information which is registered by information providers for providing various items of information associated with time and date as the time/date information, a calendar service providing server for providing a calendar service of performing schedule management on a user's schedule in association with time and date, acquiring the time/date information registered in the time/date information providing server, and providing the time/date information to the user in the calendar service, and at least one or more information processing terminals for accessing the calendar service providing server or the time/date information providing server via a communication network to acquire the time/date information from the calendar service providing server or the time/date information providing server. | 2010-05-13 |
20100118661 | WATCH MOVEMENT AND WATCH - Watch or watch movement comprising a regulating member and a display mechanism for displaying time data from the movement. The watch or watch movement also comprises a hydraulic system using oil or liquid to transmit forces and/or to lubricate the mechanism. | 2010-05-13 |
20100118662 | CLOCK KIT WITH INDEPENDENTLY MOUNTABLE DIAL - A clock kit includes a clock mechanism having a plurality of clock hands and a sticker assembly having a plurality of stickers providing indicia corresponding to a plurality of positions for the plurality of clock hands and positioned between at least one liner sheet and at least one liner sheet. A first adhesive force between a first side of the stickers and the liner sheet is less than a second adhesive force between a second side opposing side of the stickers and the transfer sheet. A third adhesive force between the first side of the stickers and a surface on which the clock kit is to be mounted is greater than the second adhesive force. | 2010-05-13 |
20100118663 | METHOD AND APPARATUS FOR PROCESSING REQUEST FROM APPLICATION IN HOME NETWORK - A method is used by an Open Cable-Digital Media Player (OC-DMP) to process a request of an application with respect to content of an Open Cable-Digital Media Server (OC-DMS). The method includes determining validity of the request based on metadata of the content, and selectively transmitting the request to the OC-DMS based on a result of the determination. | 2010-05-13 |
20100118664 | NEAR FIELD LIGHT GENERATING DEVICE, OPTICALLY ASSISTED MAGNETIC RECORDING HEAD, OPTICALLY ASSISTED MAGNETIC RECORDING DEVICE, NEAR FIELD OPTICAL MICROSCOPE AND NEAR FIELD LIGHT EXPOSURE APPARATUS - Disclosed is a near field light generating device comprising a first medium layer which transmits light from a light source. This near field light generating device generates near field light by using light irradiating a plasmon probe through the first medium. This near field light generating device is characterized in that a second medium layer having a refractive index lower than that of the first medium layer is formed between the first medium layer and the plasmon probe. | 2010-05-13 |
20100118665 | DEVICE AND METHOD FOR RECORDING AND/OR REPRODUCING DATA ONTO/FROM INFORMATION RECORDING MEDIUM BY USING NEAR-FIELD LIGHT AND INFORMATION RECORDING MEDIUM - An apparatus | 2010-05-13 |
20100118666 | NEAR-FIELD LIGHT DETECTION ELEMENT AND INFORMATION RECORDING MEDIUM REPRODUCING METHOD - A near-field light detection element is provided with a light source ( | 2010-05-13 |
20100118667 | OPTICAL DISK DEVICE - This optical disk device includes a pickup, an offsetting means, a focus servo means, a layer jump means, and a shift means. The pickup irradiates laser light upon an optical disk having a plurality of recording layers via a correction lens and an objective lens, and detects light reflected back from the optical disk. The offsetting means generates a focus error (FE) signal on the basis of the reflected light, and applies an offset voltage to the focus error signal. The focus servo means performs focusing servo on the basis of the FE signal. And, before layer jumping is executed by the layer jump means, the focus servo means displaces the correction lens to an intermediate position after having adjusted the offset voltage to a balance value. Then the layer jump means performs layer jumping. | 2010-05-13 |
20100118668 | OPTICAL DISK DRIVE - Rotation synchronization detection means is provided which detects a specified rotational phase having a period of one revolution of an optical disk. An output of the rotation synchronization detection means is synchronized with an output of rotation phase detection means for detecting a rotation phase on the basis of a FG signal and thereafter, information of surface vibration component and eccentricity component is memorized in memories before a sleep process in accordance with the output of the rotation phase detection means or a timing until jump is determined in accordance with the output of the rotation phase detection means and during recovery from the sleep status of stopping the disk once, the output of the rotation synchronization detection means is again synchronized with the output of the rotation phase detection means adapted to detect the rotation phase on the basis of the FG signal. | 2010-05-13 |
20100118669 | OPTICAL DISK APPARATUS AND FOCUS JUMP METHOD FOR MULTILAYER OPTICAL DISK - The present invention provides an optical disk apparatus and a focus jump method capable of reliably performing a focus jump by appropriately obtaining the amplitude of a signal such as a focus error signal in a multilayer optical disk. An optical disk includes jump areas which are provided separately from data areas and at which a focus jump is performed. When a focus jump is performed, an optical pickup is moved to the jump area, and the laser power level of the optical pickup is changed and set in accordance with a target layer to which the focus is jumped. A focus position is allowed to reach the target layer by counting the number of times of intersecting with recording layers using a reflected light from the optical disk while performing a focus sweep of an objective lens in the optical pickup. | 2010-05-13 |
20100118670 | SERVO CONTROL SIGNAL GENERATION DEVICE AND AN OPTICAL DISK DEVICE USING THE SAME - A servo control signal generation device for discriminating a kind of an optical disk, changing over between top and bottom envelope signals of an RF signal, and generating a defect signal and a mirror signal includes an RF generator for generating the RF signal from reflected light of an optical disk, a disk discriminator for discriminating a kind of the optical disk from the RF signal, and a top envelope generator and a bottom envelope generator respectively for generating the top and bottom envelope signals of the RF signal. If the disk has reflectance after recording which is lower than that before recording, the defect and mirror signals are generated respectively from the top and bottom envelope signals. If the disk has reflectance after recording which is higher than that before recording, the defect and mirror signals are generated respectively from the bottom and top envelope signals. | 2010-05-13 |
20100118671 | TILT CONTROL METHOD, INTEGRATED CIRCUIT AND OPTICAL DISC DEVICE - There is provided an optical disc drive including a light axis deviation detection means ( | 2010-05-13 |
20100118672 | OPTICAL INFORMATION STORAGE MEDIUM, OPTICAL INFORMATION STORAGE MEDIUM PLAYBACK APPARATUS, METHOD OF CONTROLLING OPTICAL INFORMATION STORAGE MEDIUM PLAYBACK APPARATUS, CONTROL PROGRAM OF OPTICAL INFORMATION STORAGE MEDIUM PLAYBACK APPARATUS, AND STORAGE MEDIUM STORING THE PROGRAM THEREIN - A super resolution medium ( | 2010-05-13 |
20100118673 | METHOD FOR INSPECTING OPTICAL INFORMATION RECORDING MEDIUM, INSPECTION APPARATUS, OPTICAL INFORMATION RECORDING MEDIUM AND RECORDING METHOD - A method for inspecting an optical information storage medium includes the steps of: irradiating the storage medium with a laser beam and rotating the medium by a constant linear velocity control technique by reference to the radial location at which the laser beam forms a spot on the medium; changing the rotational velocities according to the radial location on the medium between at least two linear velocities that include a first linear velocity Lv | 2010-05-13 |
20100118674 | SYSTEM AND METHOD FOR COMBINING PRE-MASTERED ERRORS WITH MARKS OR PRINTED SPOTS ON OPTICAL MEDIA - An optical article for playback in a player, the optical article including at least one sector having data, and a mark disposed in a predetermined relationship with the at least one sector, wherein the mark renders a portion of the data generally unreadable. The optical article further includes error correction code associated with the at least one sector, wherein data within the error correction code is configured as partially corrupted. The inclusion of partially corrupted error correction code reduces the size of the mark or spot required to render the data sector uncorrectable. | 2010-05-13 |
20100118675 | RECORDING AND REPRODUCTION APPARATUS, REPRODUCTION APPARATUS, AND HOST APPARATUS - It is an object of the present invention to provide a universal drive capable of recording and reproducing high-image quality contents on and from various media, such as BD, HD-DVD, DVD and others according to the AACS. The drive ( | 2010-05-13 |
20100118676 | OPTICAL DISC DRIVE WITH DELAYED LAYER JUMP - An optical disc drive ( | 2010-05-13 |
20100118677 | Optical Disc Apparatus, Method of Adjusting Focus Offset for Optical Disc Apparatus, and Program for Executing Focus Offset Adjustment - In an optical disc apparatus, whether an unrecorded recording layer without information recorded thereon is included in the multiple recording layers of the optical disc mounted inside the apparatus is judged. then when the unrecorded recording layer is judged to be present, a signal for focus offset adjustment is recorded in a non-user data recording area of the unrecorded recording layer, and reproduction of the recorded focus offset adjusting signal is followed by its quality evaluation, which is further followed by calculation and setup of an appropriate focus offset value based on evaluation results. | 2010-05-13 |
20100118678 | METHOD FOR TESTING MAGNETIC RECORDING MEDIUM AND METHOD FOR PRODUCTION OF MAGNETIC RECORDING MEDIUM INCLUDING TESTING STEP - A method for testing a magnetic recording medium tests a magnetic recording medium provided on a non-magnetic substrate ( | 2010-05-13 |
20100118679 | MULTI-LAYER OPTICAL DISCS - An optical record carrier ( | 2010-05-13 |
20100118680 | OPTICAL RECORDING MATERIAL, OPTICAL RECORDING MEDIUM, AND RECORDING AND REPRODUCING METHOD OF OPTICAL RECORDING MEDIUM - The present invention provides an optical recording material allows for obtaining excellent recording signal properties even at high-speed recording and is excellent in durability in both a single-sided single layer optical recording medium and a single-sided two-layer optical recording medium having a first recording layer and a second recording layer. The optical recording material contains a cyanine compound having a specific structure and a squarylium compound as dyes for optical recording layers. | 2010-05-13 |