19th week of 2012 patent applcation highlights part 46 |
Patent application number | Title | Published |
20120115220 | Anti-MicroRNA Oligonucleotide Molecules - The invention relates to isolated anti-microRNA molecules. In another embodiment, the invention relates to an isolated microRNA molecule. In yet another embodiment, the invention provides a method for inhibiting microRNP activity in a cell. | 2012-05-10 |
20120115221 | SPARC-DERIVED TUMOR REJECTION ANTIGENIC PEPTIDES AND MEDICAMENTS COMPRISING THE SAME - It is an objective of the present invention to identify SPARC protein-derived peptides that are able to induce human killer T cells and helper T cells having cytotoxic activity to tumors, and to provide a means for carrying out a tumor immunotherapy of patients with various types of cancers overexpressing SPARC. The present invention provides a peptide of any of the following:
| 2012-05-10 |
20120115222 | COMPOSITION AND METHOD FOR MAINTENANCE, DIFFERENTIATION, AND PROLIFERATION OF STEM CELLS - Compositions and methods for the proliferation, differentiation, and maintenance of stem cells are described. Preferred are the use of hematopoietic stem cells in combination with a collagen matrix. | 2012-05-10 |
20120115223 | PREPARATION OF INACTIVATED ARTIFICIAL ANTIGEN PRESENTING CELLS AND THEIR USE IN CELL THERAPIES - Methods of processing inactivated artificial antigen presenting cells (aAPCs) and artificial antigen presenting cells with specificity for selected antigenic peptides are described, including their generation and use in cell therapy compositions comprising activated cytotoxic T lymphocytes. Inactivated aAPCs are advantageously generated through crosslinking, such as via a photoreaction involving a psoralen derivative and UVA irradiation. | 2012-05-10 |
20120115224 | CULTURE METHODS OF BONE MARROW STROMAL CELLS AND MESENCHYMAL STEM CELLS, AND MANUFACTURE METHOD OF GRAFT CELLS FOR CENTRAL NERVE SYSTEM DISEASES THERAPY - In a culture method of the present invention, by culturing bone marrow stromal cells or mesenchymal stem cells under a pseudo micro-gravity environment generated by multi-axis rotation, bone marrow stromal cells or mesenchymal stem cells having an average cell size smaller than that before the culture are obtained. The bone marrow stromal cells or mesenchymal stem cells thus cultured are suitable as graft cells for a central nerve diseases therapy. | 2012-05-10 |
20120115225 | REPROGRAMMING OF SOMATIC CELLS WITH PURIFIED PROTEINS - Purified somatic cell reprogramming factors are described herein. The factors are particularly useful alone or in combination with at least one effector of cellular metabolism, in order to generate at least one reprogramming somatic cell. Methods for using at least one somatic cell reprogramming factor and at least one somatic cell reprogramming enhancing factor are pro-vided. Additionally, the cells generated from the methods are also described. The methods and cells may find use in personalized medicine applications. | 2012-05-10 |
20120115226 | 3D CULTURING SYSTEMS FOR GROWTH AND DIFFERENTIATION OF HUMAN PLURIPOTENT STEM (hPS) CELLS - The present invention relates to the use of 3D culturing systems for the derivation of hepatocyte-like cells from human pluripotent stem cells (hPS). In particular, the invention concerns the directed differentiation and maturation of human pluripotent stem cells into hepatocyte like cells in 3D hollow fiber capillary bioreactors. | 2012-05-10 |
20120115227 | GENE TRANSFER VECTORS COMPRISING GENETIC INSULATOR ELEMENTS AND METHODS TO IDENTIFY GENETIC INSULATOR ELEMENTS - The present invention relates to a gene transfer vector (GTV) and in particular to an integrating gene transfer vector (IGTV), which comprises at least one genetic insulator element (GIE), wherein the each comprises at least two copies of an element selected from the group consisting of: a CTF binding site; a first CTCF binding site and a second CTCF binding site, wherein the first and the second CTCF binding sites are derived from the regulatory sequences of different genes. | 2012-05-10 |
20120115228 | OLIGOMERIC COMPOUNDS AND COMPOSITIONS FOR THE USE IN MODULATION OF MICRORNAS - Compounds, compositions and methods are provided for modulating the levels expression, processing and function of miRNAs. The compositions comprise oligomeric compounds targeted to small non-coding RNAs and miRNAs. The oligomeric compounds possess potent miRNA inhibitory activity, and further exhibit improved therapeutic index. Further provided are methods for selectively modulating miRNA activing in a cell. | 2012-05-10 |
20120115229 | EMBRYONIC STEM CELLS AND NEURAL PROGENITOR CELLS DERIVED THEREFROM - The present invention provides undifferentiated human embryonic stem cells, methods of cultivation and propagation and production of differentiated cells. In particular it relates to the production of human ES cells capable of yielding somatic differentiated cells in vitro, and committed progenitor cells such as neural progenitor cells capable of giving rise to mature somatic cells including neural cells and/or glial cells and uses thereof. The invention also provides methods that generate in vitro and in vivo models of controlled differentiation of ES cells towards the neural lineage. The model, and the cells that are generated along the pathway of neural differentiation may be used for the study of the cellular and molecular biology of human neural development, for the discovery of genes, growth factors, and differentiation factors that play a role in neural differentiation and regeneration, for drug discovery and for the development of screening assays for teratogenic, toxic and neuroprotective effects. | 2012-05-10 |
20120115230 | PHENYLPROPANOID RELATED REGULATORY PROTEIN-REGULATORY REGION ASSOCIATIONS - Materials and methods for identifying lignin regulatory region-regulatory protein associations are disclosed. Materials and methods for modulating lignin accumulation are also disclosed. | 2012-05-10 |
20120115231 | NOVEL LYSOPHOSPHOLIPID ACYLTRANSFERASE - The present invention provides novel lysophospholipid acyltransferases. The object of the present invention is attained by the nucleotide sequences of SEQ ID NOs: 1 and 6 and the amino acid sequences of SEQ ID NOs: 2 and 7 of the present invention. | 2012-05-10 |
20120115232 | METHOD FOR INDUCING DEGRADATION OF PROTEIN IN MAMMALIAN CELL - Provided is a system which can induce the degradation of a protein of interest in a mammalian cell system reliably and stably within a short time. A mammalian cell inducible for protein degradation, the degradation of a protein of interest being induced by an auxin, in which the mammalian cell has both a TIR1 family protein gene from rice and a chimeric gene expressing a protein of interest labeled with a plant Aux/IAA family protein. | 2012-05-10 |
20120115233 | Leafhopper Ecdysone Receptor Nucleic Acids, Polypeptides, and Uses Thereof - The present invention relates to a novel isolated leafhopper ecdysone receptor polypeptide. The invention also relates to an isolated nucleic acid encoding the leafhopper ecdysone receptor polypeptide, to vectors comprising them and to their uses, in particular in methods for modulating gene expression in an ecdysone receptor-based gene expression modulation system and methods for identifying molecules that modulate leafhopper ecdysone receptor activity. | 2012-05-10 |
20120115234 | DOWN-REGULATION OF GENE EXPRESSION USING ARTIFICIAL MICRORNAS - Isolated nucleic acid fragments comprising precursor miRNA, and artificial miRNAs and their use in down-regulating gene expression are described. | 2012-05-10 |
20120115235 | ENHANCED CELLULASE EXPRESSION IN S. DEGRADANS - The invention provides organisms and methods of using and making organisms with enhanced cellulase expression. | 2012-05-10 |
20120115236 | Device and Method For Indirect Electronic Condition Control in Biomolecule Detection Platforms - A system and method of indirectly modifying an environmental condition at a test site in one embodiment includes providing a test site on a substrate, providing a hydrogel composition loaded with a chemical factor at the test site, providing an actuator configured to activate the hydrogel composition to release a chemical factor at the test site, controlling the actuator to activate the hydrogel composition to release a chemical factor at the test site, and modifying the local chemical environment at the test site with the chemical factor. | 2012-05-10 |
20120115237 | ISOLATION OF RNA-PROTEIN COMPLEXES USING CROSS-LINKING REAGENTS AND OLIGONUCLEOTIDES - Provided herein is a method of sample analysis. In certain embodiments, the method comprises: a) cross-linking protein of a cell using a first compound to produce a first cross-linked product comprising cross-linked protein, and RNA; b) contacting the first cross-linked product and a second compound under conditions by which an oligonucleotide portion of the second compound hybridizes to the RNA; c) activating a reaction the first and second compound, thereby covalently crosslinking the oligonucleotide to the cross-linked protein to produce a second cross-linked product; d) isolating the second cross-linked product using an affinity tag; and e) analyzing the isolated second cross-linked product. Compounds for performing the method are also provided. | 2012-05-10 |
20120115238 | NUCLEIC ACID EXTRACTION KIT, NUCLEIC ACID EXTRACTION METHOD, AND NUCLEIC ACID EXTRACTION APPARATUS - A nucleic acid extraction kit, which enables the nucleic acid extraction operation to be accomplished safely without causing contamination, and in which the complex preparation of reagents and the disposal treatments that are performed before and after the nucleic acid extraction operation can be performed rapidly and simply, with the extraction performed in an automated manner. The nucleic acid extraction kit includes: a container including reagent wells | 2012-05-10 |
20120115239 | VAPOCHROMIC COORDINATION POLYMERS FOR USE IN ANALYTE DETECTION - Vapochromic coordination polymers useful for analyte detection are provided. The vapochromism may be observed by visible color changes, changes in luminescence, and/or spectroscopic changes in the infrared (IR) signature. One or more of the above chromatic changes may be relied upon to identify a specific analyte, such as a volatile organic compound or a gas. The chromatic changes may be reversible to allow for successive analysis of different analytes. The polymer has the general formula M | 2012-05-10 |
20120115240 | Treatment of ruminant exhalations - Methane gas in a ruminant exhalation may be oxidized to reduce the amount of methane gas output by the ruminant. | 2012-05-10 |
20120115241 | SYSTEMS, DEVICES, AND METHODS FOR REMOTELY INTERROGATED CHEMOSENSOR ELECTRONICS - Systems, devices and methods for remotely interrogating sensor electronics are described. In one embodiment, a system for detecting and localizing chemical analytes is described. This system includes a plurality of chemosensor electronic devices for detecting the presence of chemical analytes. Each of these devices includes a chemosensor for sensing chemical analytes, a transponder, and an electronic circuit for activating the transponder based on an output of the chemosensor. These devices may have a cross-section area of less than 1 square micrometer. The system also includes an interrogation device for interrogating the plurality of devices and for receiving information on the detected chemical analytes from devices with activated transponders, and a processor for determining the locations of the devices with activated transponders. These locations may be forwarded to a third party. | 2012-05-10 |
20120115242 | VITAMIN D METABOLITE DETERMINATION UTILIZING MASS SPECTROMETRY FOLLOWING DERIVATIZATION - The invention relates to the detection of vitamin D metabolites. In a particular aspect, the invention relates to methods for detecting derivatized vitamin D metabolites by mass spectrometry. | 2012-05-10 |
20120115243 | SAMPLE PORT, MULTI-LAYER FILTER, SAMPLING METHOD, AND USE OF A SAMPLE PORT IN SAMPLING - The invention relates to a sample port, filter, and sampling method. The sample port according to the invention comprises a body equipped with an internal cavity and two plungers arranged moveably in this, which can be pressed against each other in the internal cavity, in order to compress a sample, and at least one of which plungers can be moved into a reactor, in order to collect a sample. The sample port also comprises a sample chamber, which is formed by the space remaining between the internal cavity and the plungers, and at least one sample-container connection connected in connection with the internal cavity, in order to collect the sample from sample chamber. In addition, the sample port has filter means adapted to at least either plunger for separating the liquid component of the sample from the solid component and means for leading the liquid component of the sample out of the sample chamber. | 2012-05-10 |
20120115244 | MATERIALS AND METHODS FOR IMMUNOASSAY OF PTERINS - Methods of assaying for (i) a pterin by immunoassay employing a pterin as capture agent, (ii) neopterin by chemiluminescent microparticle immunoassay (CMIA) employing an anti-neopterin antibody (Ab) as capture agent, (iii) neopterin by an immunoassay (IA) employing an acridinium (Acr)-labeled anti-neopterin Ab as conjugate, and (iv) neopterin by an IA employing Acr-labeled neopterin as tracer; an Acr-labeled anti-neopterin Ab; a conjugate/complex comprising anti-neopterin Ab and a carrier scaffold; a conjugated pterin; a conjugate comprising an Acr-labeled pterin and a carrier scaffold; an immunogen comprising neopterin and a carrier protein; a conjugate comprising such an immunogen and an Acr compound; an immunogen comprising a carrier protein and a neopterin hapten; a conjugate comprising such an immunogen and an Acr compound; a kit for assaying a pterin comprising a pterin as a capture agent and instructions for IA; and a kit for assaying neopterin comprising an anti-neopterin Ab as a capture agent and instructions for CMIA, neopterin comprising an Acr-labeled anti-neopterin Ab as a conjugate and instructions for IA, or Acr-labeled neopterin as a tracer and instructions for IA. | 2012-05-10 |
20120115245 | ASSAYING SUBSTRATE WITH SURFACE-ENHANCED RAMAN SCATTERING ACTIVITY - A metal substrate obtained by agglomerating 5 nm to 100 nm metal nano-particles (including clusters) having SERS activity on a metal substrate having a lower electrode potential (higher ionization tendency) than the electrode potential of the metal nano-particles, and fixing the metal nano-particles in an optimally agglomerated state that acts as hot sites, when a detection specimen is adsorbed in a non-dried state, and a predetermined laser light is irradiated, the surface enhanced Raman scattered (SERS) light of antigen detection specimen can be detected by surface Raman resonance in an optimally agglomerated state. | 2012-05-10 |
20120115246 | MICROFLUIDIC DEVICE COMPRISING SENSOR - The invention relates to a microfluidic device for performing detection of a substance in a liquid sample, wherein a cavity ( | 2012-05-10 |
20120115247 | DRUG MONITORING ASSAY - A method for obtaining at least one binding agent which binds a pharmaceutically active form of the compound with a higher specificity than a pharmaceutically inactive form of the compound is described by using special derivatives of said parent compound. The invention also pertains to the respectively created binding agents and derivatives. Furthermore, drug monitoring assays using said binding agents for monitoring pharmaceutically active forms of said parent compound are provided. | 2012-05-10 |
20120115248 | METHODS OF DETERMINING THE PRESENCE AND/OR CONCENTRATION OF AN ANALYTE IN A SAMPLE - Compositions, methods, and systems for monitoring analyte levels are provided herein. The disclosure provides methods and systems for the real-time monitoring of analytes, such as citrate, calcium, phosphate and magnesium, in a biological fluid in a clinical setting. | 2012-05-10 |
20120115249 | Biomarker for Selecting Patients and Related Methods - The present invention concerns biomarkers and use thereof for determining whether a subject is or is not susceptible to developing a prophylactic or therapeutic immune response after such treatment. | 2012-05-10 |
20120115250 | CONCAVE-CONVEX PATTERN FORMING METHOD AND MAGNETIC TUNNEL JUNCTION ELEMENT FORMING METHOD - A method of forming a concave-convex pattern according to an embodiment includes: forming a guide pattern on a base material, the guide pattern having a convex portion; forming a formative layer on the guide pattern, the formative layer including a stacked structure formed by stacking a first layer and a second layer, the first layer including at least one element selected from a first metal element and a metalloid element, the second layer including a second metal element different from the first metal element; selectively leaving the formative layer only at side faces of the convex portions by performing etching on the formative layer; removing the guide pattern; and forming the concave-convex pattern in the base material by performing etching on the base material, with the remaining formative layer being used as a mask. | 2012-05-10 |
20120115251 | PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE - Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer. | 2012-05-10 |
20120115252 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film. | 2012-05-10 |
20120115253 | Semiconductor apparatus - A method for manufacturing a semiconductor apparatus includes forming a semiconductor device on a principal surface of a substrate, in which the semiconductor device includes an interconnect layer, forming a buffer film which covers the semiconductor device and prevents diffusion of a magnetic material, and forming a magnetic shielding film which covers the buffer film and includes the magnetic material. | 2012-05-10 |
20120115254 | HEATING PLATE WITH PLANAR HEATER ZONES FOR SEMICONDUCTOR PROCESSING - A heating plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar heater zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar heater zone includes one or more heater elements made of an insulator-conductor composite. A substrate support assembly in which the heating plate is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the heating plate include bonding together ceramic sheets having planar heater zones, power supply lines, power return lines and vias. | 2012-05-10 |
20120115255 | METHOD AND APPARATUS FOR DYNAMIC THIN-LAYER CHEMICAL PROCESSING OF SEMICONDUCTOR WAFERS - A semiconductor wafer processing and analysis apparatus ( | 2012-05-10 |
20120115256 | METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT - A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications. | 2012-05-10 |
20120115257 | FILM FORMING METHOD AND FILM FORMING APPARATUS - A film forming process is performed on a substrate in a deposition chamber. A first electrode is provided in the deposition chamber and is grounded. A second electrode is provided in the deposition chamber to face the first electrode. A radio frequency power supply supplies radio frequency power to the second electrode. A DC power supply supplies a DC bias voltage to the second electrode. A control unit adjusts a bias voltage to be less than the potential of the second electrode when the radio frequency power is supplied, but the bias voltage is not supplied. In this way, it is possible to improve film quality while preventing a reduction in the deposition rate of a film during deposition. | 2012-05-10 |
20120115258 | METHODS FOR MONITORING THE AMOUNT OF METAL CONTAMINATION IN A PROCESS - Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants. | 2012-05-10 |
20120115259 | METHOD FOR FABRICATING FLEXIBLE ELECTRONIC DEVICE AND ELECTRONIC DEVICE FABRICATED THEREBY - Disclosed are a method for fabricating a flexible electronic device using laser lift-off and an electronic device fabricated thereby. More particularly, disclosed are a method for fabricating a flexible electronic device using laser lift-off allowing for fabrication of a flexible electronic device in an economical and stable way by separating a device such as a secondary battery fabricated on a sacrificial substrate using laser, and an electronic device fabricated thereby. | 2012-05-10 |
20120115260 | ORGANIC LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A top emission OLED includes a driving TFT including a channel region and source and drain electrodes. A power supply, a ground line, and a light emitting diode are electrically coupled to the TFT and an auxiliary electrode is electrically coupled to the ground line and to the source electrode of the driver transistor. The auxiliary electrode resides between the light emitting diode and the channel region of the driver transistor and is configured to shield the channel region of the driver transistor from an electric field generated by the light emitting diode. | 2012-05-10 |
20120115261 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE PACKAGE AND FRAME FOR MANUFACTURING LIGHT EMITTING DEVICE PACKAGE - A method for manufacturing a light emitting device package includes: preparing a base frame including an annular base part, at least a pair of lead parts extending to an inner side of the base part, and at least one support part extending to the inner side of the base part in a direction different from that of the lead parts and having a step structure formed on at least one surface of an end thereof; forming a package main body such that the package main body is combined to the step structure of the support part; separating the lead parts from the base part; disposing a light emitting device on at least one of the lead parts; and separating the package main body from the support part. | 2012-05-10 |
20120115262 | LASER ASSISTED TRANSFER WELDING PROCESS - A method of printing transferable components includes pressing a stamp including at least one transferable semiconductor component thereon on a target substrate such that the at least one transferable component and a surface of the target substrate contact opposite surfaces of a conductive eutectic layer. During pressing of the stamp on the target substrate, the at least one transferable component is exposed to electromagnetic radiation that is directed through the transfer stamp to reflow the eutectic layer. The stamp is then separated from the target substrate to delaminate the at least one transferable component from the stamp and print the at least one transferable component onto the surface of the target substrate. Related systems and methods are also discussed. | 2012-05-10 |
20120115263 | CHIP-TYPE LED AND METHOD OF MANUFACTURING THE SAME - An embodiment of the present invention has an insulating substrate in which a first concave hole for mounting an LED chip and a second concave hole for connecting a metallic small-gauge wire are formed, where a metallic sheet that serves as a first wiring pattern is formed at a portion that includes the first concave hole, a metallic sheet that serves as a second wiring pattern is formed at a portion that includes the second concave hole, an LED chip is mounted upon the metallic sheet inside the first concave hole, the LED chip is electrically connected to the metallic sheet inside the second concave hole via a metallic small-gauge wire, and the chip-type LED is sealed with a clear resin. | 2012-05-10 |
20120115264 | PIXEL ELEMENT OF LIQUID CRYSTAL DISPLAY AND METHOD FOR PRODUCING THE SAME - The present invention provides a method for forming a pixel element. The method comprises: forming a first patterned metal layer within the pixel area; forming an insulation layer on the first patterned metal layer; forming a semiconductor layer on the insulation layer; patterning the semiconductor layer to form bend seed generation portion; and forming a second metal layer to connect the semiconductor layer. | 2012-05-10 |
20120115265 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A substrate comprising a thin-film-transistor (TFT) region, a pixel region, a gate-line region and a data-line region is provided. A transparent conductive layer and a first metal layer are orderly formed on the substrate. A conductive stack layer is formed within each of the TFT/pixel/gate-line regions and the end of the data-line region. Next, a first insulating layer and a semiconductor layer are orderly formed, and a patterned first insulating layer and a patterned semiconductor layer are formed above the conductive stack layer within the TFT region. Then, a second metal layer and a first photoresist layer are respectively formed. Afterwards, the second and the first metal layers are patterned by using the first photoresist layer as a photomask. Finally, the first photoresist layer is reflowed by heat, and part of the reflowed first photoresist layer covers a channel formed within the TFT region. | 2012-05-10 |
20120115266 | MANUFACTURING METHOD FOR ORGANIC OPTOELECTRONIC THIN FILM - Disclosed is a manufacturing method for an organic optoelectronic thin film comprising the steps of providing a substrate and a first electrode; forming a semiconductor layer on the substrate, wherein the semiconductor layer includes polyethylene glycol (PEG); forming a conductive polymer layer on the first electrode; disposing the substrate and the semiconductor layer on the conductive polymer layer and adhering the semiconductor layer to the conductive polymer layer; and removing the substrate; and forming a second electrode on the semiconductor layer. A first adhesion between the semiconductor layer and the substrate is generated. A second adhesion between the semiconductor layer and the conductive polymer layer is generated. The second adhesion is greater than the first adhesion so that while the substrate is removed, the semiconductor layer and the conductive polymer layer are still adhered. | 2012-05-10 |
20120115267 | METHOD FOR FABRICATING LIGHT EMITTING DEVICE - Disclosed is a method for fabricating a light emitting device. The method includes forming an oxide including gallium aluminum over a gallium oxide substrate, forming a nitride including gallium aluminum over the oxide including gallium aluminum and forming a light emitting structure over the nitride including gallium aluminum. | 2012-05-10 |
20120115268 | LASER LIFTOFF STRUCTURE AND RELATED METHODS - Light-emitting devices, and related components, systems, and methods associated therewith are provided. | 2012-05-10 |
20120115269 | SACRAFICIAL LAYERS MADE FROM AEROGEL FOR MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICE FABRIACTION PROCESSES - Systems and methods for processing sacrificial layers in MEMS device fabrication are provided. In one embodiment, a method comprises: applying a patterned layer of Aerogel material onto a substrate to form an Aerogel sacrificial layer; applying at least one non-sacrificial silicon layer over the Aerogel sacrificial layer, wherein the non-sacrificial silicon layer is coupled to the substrate through one or more gaps provided in the patterned layer of Aerogel material; and removing the Aerogel sacrificial layer by exposing the Aerogel sacrificial layer to a removal liquid. | 2012-05-10 |
20120115270 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD OF MANUFACTURING SAME - Disclosed herein is a solid-state image pickup device including: a photoelectric conversion section configured to convert incident light into a signal charge; a transfer transistor configured to read the signal charge from the photoelectric conversion section and transfer the signal charge; and an amplifying transistor configured to amplify the signal charge read by the transfer transistor, wherein a compressive stress film having a compressive stress is formed on the amplifying transistor. | 2012-05-10 |
20120115271 | LOW TEMPERATURE SINTERING OF DYE-SENSITISED SOLAR CELLS - This invention relates to the field of dye-sensitized solar cells and discloses a method for reducing the temperature necessary for sintering the metal oxide paste coating the electrode. | 2012-05-10 |
20120115272 | PRODUCTION METHOD AND PRODUCTION DEVICE FOR SOLAR BATTERY - When a solar battery configured by laminating a p-type layer, an i-type layer and an n-type layer in this order is produced, an n-type microcrystalline silicon thin film is formed as an n-type layer under film forming conditions wherein a ratio of the flow rate of an n-type dopant-containing gas to the flow rate of a silicon-containing gas is 0.03 or less, the ratio of the flow rate of a diluent gas to the flow rate of a silicon-containing gas is 70 or more, and the total pressure of a material gas is 200 Pa or more. | 2012-05-10 |
20120115273 | MANUFACTURING METHOD OF PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device has a structure that includes a first amorphous silicon layer and a second amorphous silicon layer that are in contact with a single crystalline silicon substrate, and a first microcrystalline silicon layer with one conductivity type and a second microcrystalline silicon layer with a conductivity type that is opposite the one conductivity type that are in contact with the first and second amorphous silicon layers, respectively. The first and second microcrystalline silicon layers are formed using a plasma CVD apparatus that is suitable for high pressure film formation conditions. | 2012-05-10 |
20120115274 | Plasma Deposition of Amorphous Semiconductors at Microwave Frequencies - Apparatus and method for plasma deposition of thin film photovoltaic materials at microwave frequencies. The apparatus inhibits deposition on windows or other microwave transmission elements that couple microwave energy to deposition species. The apparatus includes a microwave applicator with conduits passing therethrough that carry deposition species. The applicator transfers microwave energy to the deposition species to transform them to a reactive state conducive to formation of a thin film material. The conduits physically isolate deposition species that would react to form a thin film material at the point of microwave power transfer. The deposition species are separately energized and swept away from the point of power transfer to prevent thin film deposition. The invention allows for the ultrafast formation of silicon-containing amorphous semiconductors that exhibit high mobility, low porosity, little or no Staebler-Wronski degradation, and low defect concentration. | 2012-05-10 |
20120115275 | FORMING PHOTOVOLTAIC CONDUCTIVE FEATURES FROM MULTIPLE INKS - Photovoltaic conductive features and processes for forming photovoltaic conductive features are described. The process comprises (a) providing a substrate comprising a passivation layer disposed on a silicon layer; (b) depositing a surface modifying material onto at least a portion of the passivation layer; (c) depositing a composition comprising at least one of metallic nanoparticles comprising a metal or a metal precursor to the metal onto at least a portion of the substrate; and (d) heating the composition such that it forms at least a portion of a photovoltaic conductive feature in electrical contact with the silicon layer, wherein at least one of the composition or the surface modifying material etches a region of the passivation layer. When the surface modifying material is a UV-curable material, the process comprises the additional step of curing the UV-curable material. | 2012-05-10 |
20120115276 | AMORPHOUS OXIDE SEMICONDUCTOR AND THIN FILM TRANSISTOR USING THE SAME - There is provided an amorphous oxide semiconductor including hydrogen and at least one element of indium (In) and zinc (Zn), the amorphous oxide semiconductor containing one of hydrogen atoms and deuterium atoms of 1×10 | 2012-05-10 |
20120115277 | MULTI-CHIP STACKING METHOD TO REDUCE VOIDS BETWEEN STACKED CHIPS - A multi-chip stacking method to reduce voids between stacked chips is revealed. A first chip is disposed on a substrate, and a plurality of first bonding wires are formed by wire bonding to electrically connect the first chip and the substrate. A second chip is disposed on an active surface of the first chip where a FOW (film over wire) adhesive is formed on a back surface of the second chip. The FOW adhesive partially encapsulates the first bonding wires and adheres to the active surface of the first chip. Then, the substrate is placed in a pressure oven to provide a positive pressure greater than one atm during thermally curing the FOW adhesive with exerted pressures. Accordingly, voids can be reduced inside the FOW adhesive during the multi-chip stacked processes where issues of poor adhesion and popcorn between chips can be avoided. | 2012-05-10 |
20120115278 | STACKED SEMICONDUCTOR PACKAGE WITHOUT REDUCTION IN DATA STORAGE CAPACITY AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips with a semiconductor chip body having an upper surface, a lower surface, side surfaces coupling the upper surface and the lower surface, and a circuit part. The semiconductor chips include pads coupled to the circuit part and disposed at an edge of the upper surface. A recess parts are concavely formed in the side surfaces corresponding to each pad. Conductive connection patterns cover the recess parts, and each conductive connection pattern is electrically connected to a corresponding bonding pad. The is semiconductor chip module is disposed on a substrate, and the contact pads of the semiconductor substrate are electrically connected to the conductive connection patterns. The stacked semiconductor package provides an improved structure that can contain a plurality of stacked semiconductor chips with no reduction in data storage capacity. | 2012-05-10 |
20120115279 | CHIP-SCALE SEMICONDUCTOR DIE PACKAGING METHOD - A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism. | 2012-05-10 |
20120115280 | FILM FOR SEMICONDUCTOR AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A film for semiconductor includes a support film, a second adhesive layer, a first adhesive layer and a bonding layer which are laminated together in this order. This film for semiconductor is configured so that it supports a semiconductor wafer laminated on the bonding layer thereof when the semiconductor wafer is diced and the bonding layer is selectively peeled off from the first adhesive layer when a chip is picked up. This film for semiconductor is characterized in that in the case where peel strength at 23° C. of the chip is defined as “F | 2012-05-10 |
20120115281 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which is excellent in high-temperature high-humidity reliability without decreasing moldability and curability is provided. The method includes sealing a semiconductor element in resin using a semiconductor-sealing epoxy resin composition; and then performing a heating treatment. The semiconductor-sealing epoxy resin composition contains (A) an epoxy resin of formula (1): | 2012-05-10 |
20120115282 | INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE - A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions. | 2012-05-10 |
20120115283 | WIRING SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THEREOF - The present invention provides a thin wiring pattern such as wiring formed by discharging a droplet. In the present invention, a porous (including microporous) substance is formed as a base film in forming pattern by using a droplet discharge method (also referred to as an ink-jetting method). One feature of a wiring substrate according to the present invention provides a porous film and a conductive layer thereon. One feature of a semiconductor device of the present invention provides a thin film transistor in which a gate electrode is formed by the conductive layer having the above-described structure. | 2012-05-10 |
20120115284 | METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE - A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer. | 2012-05-10 |
20120115285 | METHOD FOR FORMING MICROCRYSTALLINE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A seed crystal which includes mixed phase grains including an amorphous silicon region and a crystallite which is a microcrystal that can be regarded as a single crystal is formed on an insulating film by a plasma CVD method under a first condition that enables mixed phase grains having high crystallinity and high uniformity of grain sizes to be formed at a low density, and then a microcrystalline semiconductor film is formed to be stacked on the seed crystal by a plasma CVD method under a second condition that enables the mixed phase grains to grow to fill a space between the mixed phase grains. | 2012-05-10 |
20120115286 | THIN-FILM TRANSISTOR PRODUCING METHOD - Provided is a thin film transistor manufacture method by which a thin film transistor provided with LDD regions can be produced without increasing the number of photo masks used. An etching stopper layer ( | 2012-05-10 |
20120115287 | MANUFACTURING METHOD OF SOI MOS DEVICE ELIMINATING FLOATING BODY EFFECTS - The present invention discloses a manufacturing method of SOI MOS device eliminating floating body effects. The active area of the SOI MOS structure according to the present invention includes a body region, a N-type source region, a N-type drain region, a heavily doped P-type region, wherein the N-type source region comprises a silicide and a buried insulation region and the heavily doped P-type region is located between the silicide and the buried insulation region. The heavily doped P-type region contacts to the silicide, the body region, the buried insulation layer and the shallow trench isolation (STI) structure respectively. The manufacturing method of the device comprises steps of forming a heavily doped P-type region via ion implantation method, forming a metal layer on a part of the surface of the source region, then obtaining a silicide by the heat treatment of the metal layer and the Si material below. The present invention utilizes the silicide and the heavily doped P-type region to form an ohmic contact in order to release the holes accumulated in the body region of SOI MOS device and eliminate SOI MOS floating body effects. Besides, the manufacturing process is simple and can be easily implement. Further, the manufacturing process according to the present invention will not increase chip area and is compatible with conventional CMOS process. | 2012-05-10 |
20120115288 | METHOD FOR FABRICATING ACTIVE DEVICE ARRAY SUBSTRATE - A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer. | 2012-05-10 |
20120115289 | TFT CHARGE STORAGE MEMORY CELL HAVING HIGH-MOBILITY CORRUGATED CHANNEL - Numerous other aspects are provided a method for making a nonvolatile memory cell. The method includes forming a non-planar dielectric structure, and conformally depositing a semiconductor layer over the dielectric structure. A portion of the semiconductor layer serves as a channel region for a transistor, and the channel region is non-planar in shape. | 2012-05-10 |
20120115290 | MANUFACTURING METHOD OF CRYSTALLINE SEMICONDUCTOR FILM AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The crystalline semiconductor film is formed following steps that supplying a film formation gas to a second gas diffusion area from a gas introduction port provided in an upper electrode; supplying the film formation gas to a first gas diffusion area from the second gas diffusion area through holes provided in a dispersion plate between the first gas diffusion area and the second gas diffusion area; supplying the film formation gas into a treatment room from the first gas diffusion area through holes in a shower plate between the first gas diffusion area and the treatment room; generating glow discharge plasma by supplying high frequency electricity from an electrode surface of the upper electrode; generating crystal nuclei on a substrate provided over a lower electrode facing the upper electrode; and growing the crystal nuclei. A portion of the dispersion plate which faces the gas introduction port has no hole. | 2012-05-10 |
20120115291 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first MISFET having a first conduction type channel and formed on a semiconductor substrate; a second MISFET having a second conduction type channel and formed on the semiconductor substrate; a first strain film having a first sign strain that covers a region where the second MISFET is disposed; and a second strain film having a second sign strain that covers a region where the first MISFET is disposed. In the semiconductor device, an edge of the second strain film closer to the second MISFET overlaps with part of the first strain film; and the second strain film at a portion where the second strain film overlaps with the first strain film and at a portion extending from the portion, is thinner than the second strain film at a portion that covers the first MISFET. | 2012-05-10 |
20120115292 | METHOD FOR INTEGRATING SONOS NON-VOLATILE MEMORY INTO A STANDARD CMOS FOUNDRY PROCESS FLOW - An embodiment of a method is disclosed to integrate silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a conventional complementary metal oxide semiconductor (CMOS) semiconductor foundry process flow. An embodiment of the method only adds a few additional steps to a standard CMOS foundry process flow and makes minor changes to the rest of the baseline CMOS foundry process flow to form a new process module that includes both CMOS devices and an embedded SONOS NVM. | 2012-05-10 |
20120115293 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively. | 2012-05-10 |
20120115294 | METHODS OF FORMING NONVOLATILE MEMORY DEVICES HAVING ELECTROMAGNETICALLY SHIELDING SOURCE PLATES - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors disposed at the cell array region, bitlines disposed on the memory cell transistors, and a source plate disposed between the memory cell transistors and the bitlines to veil the memory cell transistors thereunder. | 2012-05-10 |
20120115295 | GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP - A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene. | 2012-05-10 |
20120115296 | TUNNEL FIELD-EFFECT TRANSISTOR WITH GATED TUNNEL BARRIER - A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced). | 2012-05-10 |
20120115297 | METHOD FOR FABRICATING A TUNNELING FIELD-EFFECT TRANSISTOR - The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics. | 2012-05-10 |
20120115298 | METHOD OF FABRICATING GATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer. | 2012-05-10 |
20120115299 | BIPOLAR JUNCTION TRANSISTOR HAVING A HIGH GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND A METHOD FOR FORMING THE BIPOLAR JUNCTION TRANSISTOR - A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion subjected to the thermal oxidation. An emitter is formed overlying the germanium-enriched portion region. The germanium-enriched region imparts advantageous operating properties to the heterojunction bipolar transistor, including improved high-frequency/high-speed operation. | 2012-05-10 |
20120115300 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - In a method for manufacturing a semiconductor memory device, a three dimensional lower electrode including a titanium nitride film is formed on a semiconductor substrate, and a dielectric film is formed on the surface of the lower electrode. After a first upper electrode is formed at a temperature that the crystal of the dielectric film is not grown on the surface of the dielectric film, the first upper electrode and the dielectric film are heat-treated at a temperature that the crystal of the dielectric film is grown to convert at least a portion of the dielectric film into a crystalline state. Thereafter, a second upper electrode is formed on the surface of the first upper electrode. | 2012-05-10 |
20120115301 | METAL CAPACITOR AND METHOD OF MAKING THE SAME - A method of making a metal capacitor includes the following steps. A dielectric layer having a dual damascene metal interconnection and a damascene capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the damascene capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the dual damascene metal interconnection and the dielectric layer can be prevented. | 2012-05-10 |
20120115302 | METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer. | 2012-05-10 |
20120115303 | METHOD OF FABRICATING DAMASCENE STRUCTURES - Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor. | 2012-05-10 |
20120115304 | ISOLATION STRUCTURE AND FORMATION METHOD THEREOF - An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first inclined surface is different from the slope of the second inclined surface. A length of the first inclined surface is greater than 15 nanometers. | 2012-05-10 |
20120115305 | METHOD AND STRUCTURE FOR WAFER TO WAFER BONDING IN SEMICONDUCTOR PACKAGING - A method for wafer to wafer bonding in semiconductor packaging provides for roughening the bonding surfaces in one embodiment. Also provided is a method for passivating the bonding surfaces with a lower melting point material that becomes forced away from the bonding interface during bonding. Also provided is a method for forming an eutectic at the bonding interface to reduce the impact of any native oxide formation at the bonding interface. | 2012-05-10 |
20120115306 | DEFLECTOR ARRAY, CHARGED PARTICLE BEAM DRAWING APPARATUS, DEVICE MANUFACTURING METHOD, AND DEFLECTOR ARRAY MANUFACTURING METHOD - A deflector array includes a first base substrate including a plurality of apertures formed thereon, and a plurality of deflector chips including a plurality of apertures formed thereon and a plurality of electrode pairs disposed at both sides of at least a part of the plurality of apertures. The plurality of deflector chips is fixed to the first base substrate in such a manner that the plurality of apertures of the deflector chips is arranged at positions corresponding to the plurality of apertures of the first base substrate. | 2012-05-10 |
20120115307 | METHODS OF MANUFACTURING SEMICONDUCTOR CHIPS - A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate. | 2012-05-10 |
20120115308 | FABRICATION METHOD FOR DICING OF SEMICONDUCTOR WAFERS USING LASER CUTTING TECHNIQUES - A fabrication method for dicing semiconductor wafers using laser cutting techniques, which can effectively prevent the devices on semiconductor die units from the phenomenon of etching undercut caused by the sequential steps after laser cutting, comprises following steps: covering the wafer surface with a protection layer; dicing the wafer by laser and separating the die units from each other; removing the laser cutting residues on the devices on the die units by wet etching; removing the protection layer and cleaning the devices on the die units. The selection of materials for the protection layer must consider the following factors: where (1) the materials for the protection layer must have relatively good properties for adhering and covering on the wafer; (2) and the materials for the protection layer must be corrosion-resistant to the acidic or basic solution for etching residues. | 2012-05-10 |
20120115309 | Methods of Manufacturing a Vertical Type Semiconductor Device - Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure. | 2012-05-10 |
20120115310 | METHOD OF SIGE EPITAXY WITH HIGH GERMANIUM CONCENTRATION - The present invention discloses a method of SiGe epitaxy with high germanium concentration, a germanium concentration can be increased by reducing the percentage of silane and germane during introduction silane and germane. With the same flow of germanium source, the germanium concentration is significantly increased as the germane flow is reduced, therefore a defect-free SiGe epitaxial film with a germanium atomic percentage of 25˜35% can be obtained. The present invention can balance epitaxial growth rate and germanium doping concentration by using existing equipments to obtain a high germanium concentration, and the epitaxial growth rate is only reduced a little, which can keep the SiGe epitaxial layer having no defect to meet the requirements of devices and can maintain sufficient throughput. | 2012-05-10 |
20120115311 | METHOD FOR FORMING A MULTILAYER STRUCTURE - The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 10 | 2012-05-10 |
20120115312 | THIN FILMS FOR PHOTOVOLTAIC CELLS - In one aspect, a method for forming CIGSSe-based thin films includes depositing at least two layers of particles on a substrate. At least one layer includes a CIGSSe particle having a chemical composition denoted by Cu(InI-xGax)(S1-ySey)2 where 0≦x ≦1 and 0≦y≦1. The particle layers are annealed individually or in combination to form a CIGSSe thin film having a composition profile along the depth of the film In addition, one or more of the particle layers may be also deposited on a pre-existing absorber and annealed to form a film having a composition profile along the depth of the film After depositing thin film precursor layers containing CIGSSe nanoparticles (and/or any other particles) on a suitable substrate in accordance with a desired concentration profile, a subsequent treatment under an Se and/or S containing atmosphere at elevated temperature may be used to convert the precursor layers into a CIGSSe absorber film In a further aspect, a method for forming multinary metal chalcogenide semiconductor layers directly on a substrate from a solution of precursors, includes depositing a plurality of metal chalcogenide particles onto a substrate to form a precursor film A species containing a metal, chalcogen, or combination thereof is dissolved in a solution containing one or more solvents to form a liquid chalcogen medium. The precursor film is contacted with the liquid chalcogen medium at a temperature of at least 50 C to form a multinary metal chalcogenide thin film | 2012-05-10 |
20120115313 | SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND METHOD - A sealing member is lifted to cause its edge to be in contact with a contact surface of a support member. In the state where a precision ejection nozzle is isolated, a gas exhaust unit is operated to exhaust the inside of a chamber to reduce the pressure in the chamber to a predetermined level. Then, a purge gas is introduced into the chamber from a purge gas supply source through a gas introduction section to replace the atmosphere in the chamber with the purge gas, and the pressure in the chamber is returned to the atmospheric pressure. After that, the sealing member is lowered to release the isolation of the precision ejection nozzle. Then, liquid droplets of a liquid device material are ejected toward the surface of a substrate while a carriage is reciprocated in the X direction. | 2012-05-10 |
20120115314 | PLASMA PROCESSING APPARATUS AND METHOD OF PRODUCING AMORPHOUS SILICON THIN FILM USING SAME - Disclosed is a plasma processing apparatus, wherein a plasma-generating electrode has a plurality of gas exhaust holes which run through the plasma-generating electrode from the surface facing a substrate held by a substrate-holding mechanism, and reach a gas exhaust chamber; gas-feeding pipes, provided connected to a gas-introducing pipe, have gas-feeding ports for discharging source gas toward the inside of the plurality of gas exhaust holes; and the gas-feeding pipes and the gas-feeding ports are arranged in a manner such that extended lines, representing the direction of the flow of the source gas discharged from the gas-feeding ports, intersect the end surface open regions at the interface of the gas exhaust chamber to the gas exhaust holes. Also disclosed is a method of producing the amorphous silicon thin film using the plasma processing apparatus. | 2012-05-10 |
20120115315 | LOW TEMPERATURE GST PROCESS - A deposition process to form a conformal phase change material film on the surface of a substrate to produce a memory device wafer comprises providing a substrate to a chamber of a deposition system; providing an activation region; introducing one or more precursors into the chamber upstream of the substrate; optionally introducing one or more co-reactants upstream of the substrate; activating the one or more precursors; heating the substrate; and depositing the phase change material film on the substrate from the one or more precursors by chemical vapor deposition. The deposited phase change material film comprises Ge | 2012-05-10 |
20120115316 | Crystallization apparatus, crystallization method, and method of manufacturing organic light-emitting display device, which use sequential lateral solidification - A crystallization apparatus, which uses sequential lateral solidification (SLS) and crystallizes an amorphous silicon layer formed on a substrate, includes a laser generating device, a first optical system, a second optical system, and a path switching member. The laser generating device is configured to emit a laser beam. The first optical system is configured to process the laser beam emitted from the laser generating device and to irradiate the processed laser beam onto the substrate. The second optical system is parallel to the first optical system and is configured to process the laser beam emitted from the laser generating device and to irradiate the processed laser beam onto the substrate. The path switching member is configured to switch a path of the laser beam emitted from the laser generating device and to alternately distribute the laser beam to the first and second optical systems. | 2012-05-10 |
20120115317 | PLASMA DOPING METHOD AND APPARATUS THEREOF - In a plasma torch unit, a conductor rod having a spiral shape is disposed inside a quartz pipe having a surface coated with boron glass, and a brass block is disposed on the periphery thereof. While a gas is being supplied into a cylindrical chamber, a high-frequency power is supplied to the conductor rod and a plasma is generated in the cylindrical chamber, so that a base material is irradiated with the plasma. | 2012-05-10 |
20120115318 | METHOD FOR LOW TEMPERATURE ION IMPLANTATION - Techniques for low temperature ion implantation are provided to improve the throughput. During a low temperature ion implantation, an implant process may be started before the substrate temperature is decreased to be about to a prescribed implant temperature by a cooling process, and a heating process may be started to increase the substrate temperature before the implant process is finished. Moreover, one or more temperature adjust process may be performed during one or more portion of the implant process, such that the substrate temperature may be controllably higher than the prescribe implant temperature during the implant process. | 2012-05-10 |
20120115319 | CONTACT PAD - The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process. | 2012-05-10 |