19th week of 2013 patent applcation highlights part 27 |
Patent application number | Title | Published |
20130114289 | Backlight Module that Enhances Heat Dissipation of LED Light Source and Display Device - The present invention relates to a backlight module that enhances heat dissipation of LED light sources and a display device. The backlight module that enhances heat dissipation of LED light sources includes an LED light strip, a back panel, a mixed coating layer including two materials, and a thermal diode/triode. The LED light strip is arranged on the back panel. The mixed coating layer is interposed between the LED light strip and the back panel and contacts both for transfer of heat. The thermal diode/triode is connected to the mixed coating layer to control temperature of the mixed coating layer. In operation, through regulation of temperature, the thermal diode/triode makes vibration frequencies of the two materials of the mixed coating layer consistent with each other at a given temperature. The display device includes the above descried backlight module that enhances heat dissipation of LED light sources. The present invention realizes obstruction free transfer of heat from the LED light strip to the aluminum extrusion or the back panel, eliminating bottleneck of heat conduction path; reduces the temperature of the LED light strip, extending the overall lifespan of the LED light strip; and eliminates the use of thermal pad in the backlight module so as to facilitate designing narrow side frame of the backlight module. | 2013-05-09 |
20130114290 | DISPLAY MODULE - A display module includes a metal rear bezel, a backlight module, a driver circuit board and a heat dissipation film. The metal rear bezel includes a carrier surface and a back surface opposite to the carrier surface. The backlight module includes a light reflective sheet disposed on the carrier surface. The light reflective sheet includes a light reflective sheet and a heat dissipation surface opposite to the light reflective sheet. The driver circuit board is attached to the back surface of the metal rear bezel. The heat dissipation film is disposed on the heat dissipation surface. At least a portion of the heat dissipation film is overlapped with the driver circuit board. | 2013-05-09 |
20130114291 | Surface Light Guide and Luminaire - In at least one embodiment of the surface light guide, the surface light guide includes at least one scattering element for scattering light. A decoupling coefficient is caused by the scattering element. The decoupling coefficient is set in a varying fashion along a main light-guiding direction. In a direction perpendicular to the main sides of the surface light guide, the opacity value is no more than 0.10, the transmission coefficient is at least 0.75 and the quotient of the minimum light density and maximum light density seen over a continuous emitting area of at least one of the main sides is at least 0.75. | 2013-05-09 |
20130114292 | Surface Light Guide and Planar Emitter - A surface light guide has a radiation exit area extending along a main extension plane of the surface light guide and is provided for laterally coupling radiation. The surface light guide includes scattering locations for scattering the coupled radiation. The surface light guide includes a first boundary surface and a second boundary surface which delimit the light conductance of the coupled-in radiation in the vertical direction. A first layer and a second layer are formed on each other in the vertical direction between the first boundary surface and the second boundary surface. Further disclosed are a planar emitter including at least one surface light guide. | 2013-05-09 |
20130114293 | SURFACE LIGHT SOURCE DEVICE - According to one embodiment, a surface light source device includes a light guide plate, and first and second light-emitting units. The light guide plate includes a flat portion and a curved portion. The curved portion guides, to the flat portion, light introduced from the end surface and transmits light introduced from the inner circumferential surface. The flat portion includes a light diffusing portion to diffuse the light guided by the curved portion, and a light-emitting surface to output the light diffused by the light diffusing portion. The first light-emitting unit emits light toward the end surface. The second light-emitting unit emits light toward the inner circumferential surface. | 2013-05-09 |
20130114294 | FRONT LIGHT DEVICES AND METHODS OF FABRICATION THEREOF - A illumination device comprises a light guide having a first end for receiving light and configured to support propagation of light along the length of the light guide. A turning microstructure is disposed on a first side of the light guide configured to turn light incident on the first side and to direct the light out a second opposite side of the light guide, wherein the turning microstructure comprises a plurality of indentations. A cover is physically coupled to the light guide and disposed over the turning microstructure. An interlayer is between the cover and the light guide, wherein the interlayer physically couples the cover to the light guide. A plurality of open regions is between the interlayer and the plurality of indentations. Various embodiments include methods of coupling the cover to the light guide while preserving open regions between the cover and plurality of indentations. | 2013-05-09 |
20130114295 | LED LIGHTING MODULE AND LIGHTING DEVICE COMPRISED THEREOF - A lighting module and lighting device are described. Embodiments of the lighting modules comprise light emitting diodes (LEDs), a power supply, and a waveguide that disperses light from the LEDs to illuminate a lighted side of the lighting module. In one embodiment, the lighting module comprises a substrate, on which the LEDs and power supply are mounted. The substrate includes an interface that permits the lighting module to communicate with an adjacent lighting module when positioned in an array that forms an LED lighting device. | 2013-05-09 |
20130114296 | LIGHT GUIDE APPARATUS AND ELECTRONIC DEVICE USING THE SAME - A light guide apparatus includes a light guide and at least one LED arranged beside the light guide. The light guide includes a first surface and a second surface opposite to the first surface. A scatter layer is attached on the first surface adjacent to the LED and configured to scatter light beams from the at least one LED, a reflective layer is attached on the second surface away from the LED and configured to reflect light beams from the at least one LED to the first surface. The light refracting out from the first surface achieves a homogeneous illumination effect via the diffuse of the scatter layer and the reflection of the reflective layer. | 2013-05-09 |
20130114297 | BACKLIGHT UNIT, LIGHT GUIDE AND DISPLAY APPARATUS HAVING THE SAME - Disclosed are a backlight unit and light guide of a display apparatus and a display apparatus having the same, the backlight unit including: a light source unit which is disposed on at least one of edges of a display panel; and a light guide plate which is disposed at rear of the display panel so as to transmit light radiated from the light source unit to the display panel and including a lower side formed with a plurality of distributed unit patterns reflecting the radiated light and an upper side transmitting the light reflected by the unit pattern(s) engraved into the lower side and reflecting the radiated light to the upper side. | 2013-05-09 |
20130114298 | BACKLIGHT AND DISPLAY DEVICE - Embodiments of the present invention disclose a backlight and a display device, to reduce the number of LEDs in a backlight, save costs, while avoiding dark areas appearing on the screen, so as to ensure display effect. The backlight comprises a first light guide plate and at least one light-emitting diode assembly, and the light-emitting diode assembly is located on one side of the first light guide plate. The light-emitting diode assembly comprises a second light guide plate, at least one light-emitting diode and a reflective film, wherein the at least one light-emitting diode is located on at least one side of the second light guide plate, and the reflective film is located on at least one side of the second light guide plate. | 2013-05-09 |
20130114299 | DISPLAY DEVICE - Provided is a display device. The display device includes a light guide plate, a light source disposed on a side surface of the light guide plate, a light conversion member disposed between the light source and the light guide plate, and a first adhesion member closely attached to the light guide plate and the light conversion member. An air layer between the light source and the light guide plate is removed by the first and second adhesion members to improve light incident efficient into the light guide plate. | 2013-05-09 |
20130114300 | BACKLIGHT UNIT AND DISPLAY APPARATUS HAVING THE SAME - A backlight unit of a display apparatus, the backlight unit includes a light source unit disposed on at least one edge of a display panel; and a light guide plate disposed at rear of the display panel. The light guide plate includes a first pattern part including a plurality of first pattern lines formed on a lower surface of the light guide plate, and which extend perpendicularly to a transmission direction of the radiated light, and which totally reflect the radiated light to an upper surface of the light guide plate, and a second pattern part including a plurality of second pattern lines formed on the upper surface of the light guide plate, and which extend parallel with the transmission direction of the radiated light, and which guide light transmitted in the light guide plate to travel and exit along the second pattern lines. | 2013-05-09 |
20130114301 | DISPLAY DEVICE - Provided is a display device. The display device includes a light guide plate, a light source disposed on a side surface of the light guide plate, a light conversion member disposed between the light source and the light guide plate, and a plurality of light path change particles disposed between the light conversion member and the light guide plate. | 2013-05-09 |
20130114302 | METHOD AND APPARATUS FOR DETECTING ISLANDING CONDITIONS OF A DISTRIBUTED GRID - An exemplary method and apparatus for detecting islanding conditions of a distributed grid are disclosed, wherein transfer of power through a power electrical unit is controlled on the basis of a control reference. The apparatus includes a first stage and a second stage performing a respective portion of the method. The first stage injects a reactive component to the control reference, and, for at least one electrical quantity of the grid, determines a change in the quantity induced by the injected component, and determines, on the basis of the change in the electrical quantity, whether to move to the second stage of the method. The second stage, for at least one electrical quantity of the grid, determines a value of the electrical quantity, forms a positive feedback term using at the determined value adding a positive feedback term to the control reference, determines a change in an electrical quantity induced by the feedback term, and determines islanding condition on the basis of the change in the quantity induced by the feedback term. | 2013-05-09 |
20130114303 | PHOTOVOLTAIC ARRAY SYSTEMS, METHODS, AND DEVICES WITH BIDIRECTIONAL CONVERTER - Devices, systems and methods for operating, monitoring and diagnosing photovoltaic arrays used for solar energy collection. The system preferably includes capabilities for monitoring or diagnosing an array, under some circumstances, by using a bidirectional power converter not only to convert the DC output of the array to output power under some conditions, but also, for diagnostic operations, applying a back-converted DC voltage to the array. | 2013-05-09 |
20130114304 | Apparatus and Method for Power Extraction from High Impedance Sources - A system and method for extracting power from a power source having a high internal resistance are presented. A capacitor is connected to the power source. A switch is configured to selectively connect and disconnect the capacitor from a load. A processor is configured to monitor an energy flow from the power source into the capacitor and an amount of energy in the capacitor. When the energy flow from the power source into the capacitor falls below a first threshold, the processor is configured to close the switch to dissipate energy from the capacitor to the load. When the energy in the capacitor falls below a second threshold, the processor is configured to open the switch to disconnect the capacitor from the load. | 2013-05-09 |
20130114305 | POWER SOURCE CIRCUIT - In a power source circuit including a switching circuit | 2013-05-09 |
20130114306 | DYNAMIC POWER FACTOR CORRECTION AND DYNAMIC CONTROL FOR CONVERTER IN POWER SUPPLY - A welding or cutting system is provided using an interleaved buck-boost stage which dynamically controls power factor correction and operation of the interleaved buck-boost modules to optimize efficiency and operation of the welding system. | 2013-05-09 |
20130114307 | SYSTEMS AND METHODS FOR PROTECTING POWER CONVERSION SYSTEMS UNDER OPEN AND/OR SHORT CIRCUIT CONDITIONS - System and method are provided for protecting a power converter. The system includes a first comparator, and an off-time component. The first comparator is configured to receive a sensing signal and a first threshold signal and generate a first comparison signal based on at least information associated with the sensing signal and the first threshold signal, the power converter being associated with a switching frequency and further including a switch configured to affect the primary current. The off-time component is configured to receive the first comparison signal and generate an off-time signal based on at least information associated with the first comparison signal. The off-time component is further configured to, if the first comparison signal indicates the sensing signal to be larger than the first threshold signal in magnitude, generate the off-time signal to keep the switch to be turned off for at least a predetermined period of time. | 2013-05-09 |
20130114308 | Switching Regulator and Control Circuit and Control Method Thereof - The present invention discloses a switching regulator and a control circuit and a control method thereof. The control circuit of the switching regulator, which controls rectified power within a predetermined range, detects an input voltage and an input current to generate a voltage detection signal and a current detection signal respectively, and the voltage detection signal and the current detection signal are multiplied by one the other to generate a power index. The control circuit generates an error signal according to the power index and a reference signal. A low-pass-filter filters a high frequency band in the process. A control signal generation circuit of the control circuit generates a control signal according to the error signal. And a driver circuit of the control circuit generates an operation signal according to the control signal, for switching a power switch to convert the rectified power to an output voltage. | 2013-05-09 |
20130114309 | Battery Module - A battery module and an arrangement including a number of battery modules connected in series are disclosed. An energy store has a positive and a negative connection. A boost converter has a first and a second converter output. The energy store is connected at the positive connection of the energy store to a first connection and at the negative connection of the energy store to a second connection. The first converter output is connected to a first compensation connection and the second converter output is connected to a second compensation connection. The converter is designed to draw energy from the energy store and to provide the energy to the converter outputs of the converter in the form of current. | 2013-05-09 |
20130114310 | Power Supply Control Circuit and method for sensing voltage in the power supply control circuit - The present invention discloses a power supply control circuit, the power supply providing an output voltage to an output terminal from an input terminal through a transformer having a primary winding and a secondary winding, the power supply control circuit comprising: a power switch electrically connected with the primary winding; a switch control circuit controlling the power switch; and a sensing circuit supplying an output signal to the switch control circuit according to voltage signals obtained from two sides of the primary winding, wherein the sensing circuit includes a setting circuit for deciding the output voltage according to a reference signal. The present invention also relates to a voltage sensing method in the power supply control circuit. | 2013-05-09 |
20130114311 | Power Transfer Devices, Methods, and Systems with Crowbar Switch Shunting Energy-Transfer Reactance - The present application discloses methods, circuits and systems for power conversion, using a universal multiport architecture. When a transient appears on the power input (which can be, for example, polyphase AC), the input and output switches are opened, and a crowbar switch shunts the inductance which is used for energy transfer. This prevents this inductance from creating an overvoltage when it is disconnected from outside lines. | 2013-05-09 |
20130114312 | System and Method for Power Conversion for Renewable Energy Sources - An energy conversion system for use with an alternative energy source is disclosed. The alternative energy source can generate either an AC or a DC voltage. A first power converter is connected between the source and a DC bus, and a second power converter is connected between the DC bus and the grid or another load. The first power converter is configured to operate during periods of low energy generation. The energy captured will be stored in an electrical storage medium. When sufficient energy is stored, this energy is subsequently transferred to the grid or load via the second power converter. The second power converter is configured to operate intermittently during periods of low power generation, transferring energy from the DC bus when sufficient energy is stored and turning off when the stored energy drops to a point at which the second power converter can no longer be operated efficiently. | 2013-05-09 |
20130114313 | SWITCHING MODE POWER SUPPLY, APPARATUS AND METHOD OF SUPPLYING POWER BY USING THE SAME, AND IMAGE FORMING APPARATUS THEREFOR - A switching mode power supply (SMPS) usable with an image forming apparatus receives an alternating current (AC) power from an external electric power supply source and outputs a direct current (DC) power. When a supply state of an electric power to the image forming apparatus is turned off, electric charges charged in a capacitor of the SMPS are discharged. | 2013-05-09 |
20130114314 | CONVERTER SYSTEM AND POWER ELECTRONIC SYSTEM COMPRISING SUCH CONVERTER SYSTEMS - Exemplary embodiments are directed to a converter system having a phase voltage source, n partial converter systems, wherein n≧1 and, when n=1, the partial converter system is connected to the phase voltage source at a connection point and, when n>1, the partial converter systems are connected to the phase voltage source at the connection point. Furthermore, a power switch is connected in series between the phase voltage source and the connection point. An interruption element is connected in series between the phase voltage source, the power switch, and the connection point to rapidly switch off a fault current via a partial converter system. Furthermore, a power electronic system including m converter systems is specified, wherein m>1. | 2013-05-09 |
20130114315 | Power Transfer Devices, Methods, and Systems with Crowbar Switch Shunting Energy-Transfer Reactance - The present application discloses methods, circuits and systems for power conversion, using a universal multiport architecture. When a transient appears on the power input (which can be, for example, polyphase AC), the input and output switches are opened, and a crowbar switch shunts the inductance which is used for energy transfer. This prevents this inductance from creating an overvoltage when it is disconnected from outside lines. | 2013-05-09 |
20130114316 | Power Transfer Devices, Methods, and Systems with Crowbar Switch Shunting Energy-Transfer Reactance - The present application discloses methods, circuits and systems for power conversion, using a universal multiport architecture. When a transient appears on the power input (which can be, for example, polyphase AC), the input and output switches are opened, and a crowbar switch shunts the inductance which is used for energy transfer. This prevents this inductance from creating an overvoltage when it is disconnected from outside lines. | 2013-05-09 |
20130114317 | VOLTAGE CONVERTING APPARATUS AND METHOD FOR CONVERTING A VOLTAGE - A voltage converting apparatus includes a series connection of at least four switching elements each including at least one semiconductor device of turn-off type and a free-wheeling diode connected in anti-parallel therewith. The apparatus has a device configured to measure a parameter representative of the voltage across each free-wheeling diode when turned off and an arrangement configured to control the amount of charge stored in each diode at the moment the diode is turned-off by stopping to conduct depending upon the results of the measurement carried out by the device for controlling the voltage across the diode after turn-off thereof. | 2013-05-09 |
20130114318 | SOLID-STATE INDUCTIVE CONVERTER - A converter configured to transform DC into AC. Includes a first and second transistor with connected bases and emitters, and a coil or inductor having a first end that is connected to the bases, a second end that is free, and a common central zero, which is connected to the emitters and divides the inductor into two equal portions, a first portion from the end to a central zero and a second portion from the latter to the end. The circuit is supplied by a direct current applied to the collectors and envisages at least one output between said second end and the collector of one of the two transistors configured to supply a respective load and behaves substantially as a capacitor or electroluminescent cable/panel. Transistors work alternatively by following the cycles of charging and discharging of the load and obtain a supply current having a substantially perfect sinusoidal waveform. | 2013-05-09 |
20130114319 | REACTOR - A reactor having a good heat dissipation effect is provided. The reactor includes one coil formed by winding a wire, a magnetic core arranged inside and outside the coil and forming a closed magnetic circuit, and a case for housing an assembly of the coil and the magnetic core. An end surface of the coil has a race track shape, and the coil is housed in the case such that the axial direction of the coil is parallel to an outer bottom surface of the case | 2013-05-09 |
20130114320 | DEVICE FOR BALANCING THE VOLTAGE ON THE TERMINALS OF A CAPACITOR OF A SET OF CAPACITORS, AND VOLTAGE CONVERSION SYSTEM INCLUDING SUCH A BALANCING DEVICE - Device for balancing voltage on terminals of at least one capacitor of a set of N−1 capacitors connected in series between a positive terminal and a negative input terminal and connected through intermediate points, comprising at least one balancing module connected between both input terminals; each balancing module including means for determining the amount of excess or lacking charges in the intermediate points, a temporary electric energy storage element including two terminals, first current guiding means to extract electric charges from an intermediate point towards a terminal of the storage element, second current guiding means to inject electric charges from the other terminal of the storage element towards an intermediate point, and a member able to control the first means so as to extract charges from at least one intermediate point and able to control the second means so as to inject the charges to at least one intermediate point. | 2013-05-09 |
20130114321 | INVERTER TOPOLOGY CIRCUIT, INVERSION METHOD AND INVERTER - An inversion method and an inverter, in which a fifth switch tube, a sixth switch tube, a fifth diode, a sixth diode, and a first capacitor are added in the existing inverter circuit including a bridge arm, the fifth switch tube is connected in parallel to the fifth diode, and the sixth switch tube is connected in parallel to the sixth diode; wherein the positive pole of the fifth diode is connected to the negative pole of a direct current source, the negative pole of the fifth diode is connected to a connection circuit between a second inductor and an alternating current source, the positive pole of the sixth diode is connected to the negative pole of the direct current source, and the negative pole of the sixth diode is connected to a connection circuit between a first inductor and the alternating current source. | 2013-05-09 |
20130114322 | ASSOCIATIVE MEMORY - An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DT | 2013-05-09 |
20130114323 | SEMICONDUCTOR DEVICE AND DATA STORAGE APPARATUS - A semiconductor device according to an embodiment includes: a rectangular substrate having a first and a second principal surfaces ; a first semiconductor chip; one or more second semiconductor chips; and one or more third semiconductor chips. The substrate has first connection terminals connected to electrodes of the one or more second semiconductor chips, and third connection terminals electrically connected to the first connection terminals and connected to first electrodes of the first semiconductor chip, on a side of a first edge on the first principal surface. The substrate has second connection terminals connected to second electrodes of the one or more third semiconductor chips, and fourth connection terminals electrically connected to the second connection terminals and connected to electrodes of the first semiconductor chip, on a side of a second edge facing the first edge across the first semiconductor chip on the first principal surface. | 2013-05-09 |
20130114324 | Integrated Circuit Comprising a FRAM Memory and Method for Granting Read-Access to a FRAM Memory - An electronic device includes an integrated circuit with a FRAM memory and an integrated capacitor connected between a power supply for the FRAM memory and ground. The integrated capacitor has a capacitance sufficient to store the charge necessary for a complete read-and-write-back cycle of the FRAM memory. When granting read-access to the FRAM memory, the FRAM memory is supplied by the integrated capacitor. Upon receiving a request for a read-access to the FRAM memory, a charge detector detects whether the internal capacitor is sufficiently charged for a complete read-and-write-back cycle of the FRAM memory. Read-access to the FRAM memory is only granted if the internal capacitor is sufficiently charged. An alternative embodiment alternately charges and powers the FRAM from two integrated capacitors. | 2013-05-09 |
20130114325 | NON-VOLATILE RANDOM ACCESS MEMORY COUPLED TO A FIRST, SECOND AND THIRD VOLTAGE AND OPERATION METHOD THEREOF - A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage. | 2013-05-09 |
20130114326 | SEMICONDUCTOR MEMORY APPARATUS AND TEST CIRCUIT THEREFOR - Disclosed is a semiconductor memory apparatus, including: a memory cell array configured to include a plurality of memory cells; a switching unit configured to be coupled to data input and output pads and control a data transfer path of data applied to the data input and output pads in response to a test mode signal; a write driver configured to drive data transferred from the switching unit and write the data in the memory cell array at a normal mode; and a controller configured to transfer the data from the switching unit to the memory cell at a test mode. | 2013-05-09 |
20130114327 | VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE - A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block. | 2013-05-09 |
20130114328 | Low-Complexity Electronic Circuit and Methods of Forming the Same - An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit. | 2013-05-09 |
20130114329 | Multilayer Memory Array - A multilayer crossbar memory array includes a number of layers. Each layer includes a top set of parallel lines, a bottom set of parallel lines intersecting the top set of parallel lines, and memory elements disposed at intersections between the top set of parallel lines and the bottom set of parallel lines. A top set of parallel lines from one of the layers is a bottom set of parallel lines for an adjacent one of the layers. | 2013-05-09 |
20130114330 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - In a conventional DRAM, a decrease in the capacitance of a capacitor causes an error in reading data. A plurality of memory blocks MB is connected to one bit line BL_m. Each memory block MB includes a sub bit line SBL, a plurality of memory cells, and a precharge transistor. The drain of a transistor of the memory cell is connected one of the bit line BL_m and the sub bit line SBL, whereas a capacitor of the memory cell is connected to the other one of the bit line BL_m and the sub bit line SBL. The capacitance of the sub bit line SBL is sufficiently low; thus, a potential change due to electric charges of the capacitor of the memory cell can be amplified by an amplifier circuit AMP without an error and the amplified signal can be output to the bit line. | 2013-05-09 |
20130114331 | CONTROL SIGNAL GENERATION CIRCUIT AND SENSE AMPLIFIER CIRCUIT USING THE SAME - A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals. | 2013-05-09 |
20130114332 | REDUCING READ DISTURBS AND WRITE FAILS IN A DATA STORAGE CELL - A data storage cell having a data line configured to transmit a data value to and from the storage cell, a feedback loop configured to store the data value, a first access device to provide access between the data line and a first point in the feedback loop, a second access device to provide access between the data line and a second point in the feedback loop, the first access point being a less stable point in the feedback loop than the second access point such that a variation in a voltage at the first access point is more likely to disturb said data value stored in the feedback loop than a variation in voltage at the second access point. | 2013-05-09 |
20130114333 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION PROCESS THEREOF - A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element. | 2013-05-09 |
20130114334 | Magnetoresistive random access memory cell with independently operating read and write components - A new class of the memory cell is proposed. There are two separated pulse data writing and sensing current paths. The in-plane pulse current is used to flip the magnetization direction of the perpendicular-anisotropy data storage layer sandwiched between a heavy metal writing current-carrying layer and a dielectric layer. The magnetization state within data storage layer is detected by the patterned perpendicular-anisotropy tunneling magnetoresistive (TMR) stack via the output potential of the stack. Two detailed memory cells are proposed: in one proposed cell, the data storage layer is independent from but kept close to the sensing TMR stack, whose magnetization orientation affects magnetization configuration within the free layer of the TMR stack, therefor ultimately affects the output potential of the stack; in the other proposed cell, the perpendicular-anisotropy data storage layer is the free layer of the sensing TMR stack, whose magnetization state will directly affect the output potential of the stack when sensing current passes through. | 2013-05-09 |
20130114335 | MEMORY SENSING CIRCUIT - A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element. | 2013-05-09 |
20130114336 | THREE PORT MTJ STRUCTURE AND INTEGRATION - A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process. | 2013-05-09 |
20130114337 | Method Of Testing Data Retention Of A Non-volatile Memory Cell Having A Floating Gate - A method of decreasing the test time to determine data retention (e.g. leakage current) of a memory cell having a floating gate for the storage of charges thereon. The memory cell is characterized by the leakage current having a rate of leakage which is dependent upon the absolute value of the voltage of the floating gate. The memory cell is further characterized by a first erase voltage and a first programming voltage, applied during normal operation, and a first read current detected during normal operation. The method applies a voltage greater than the first erase voltage or greater than the first programming voltage, to over erase the floating gate. The memory cell including the floating gate is subject to a single high temperature bake. The memory cell is then tested for data retention of the floating gate based on the single high temperature bake. | 2013-05-09 |
20130114338 | VOLTAGE SUPPLY CONTROLLER, NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM - A nonvolatile memory device includes a voltage supply controller (VSC) detecting a level of a power supply voltage and generating a first internal voltage in response thereto. The VSC provides the first internal voltage at a level equal to an external high voltage when a power supply voltage is normally supplied, but provides the first internal voltage at a level lower than the external high voltage when a power supply voltage is abnormally supplied. | 2013-05-09 |
20130114340 | SECURE MEMORY WHICH REDUCES DEGRADATION OF DATA - A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase. | 2013-05-09 |
20130114341 | Method and Apparatus for Indicating Bad Memory Areas - Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled. | 2013-05-09 |
20130114342 | DEFECTIVE WORD LINE DETECTION - Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to determine which storage elements have a threshold voltage below a reference voltage level associated with the tracked state. By tracking which storage elements are in the tracked state, elements associated with other states may be filtered out such that an accurate assessment may be made as to which storage elements were under-programmed. From this information, a determination may be made whether the word line is defective. For example, if too many storage elements are under-programmed, this may indicate a broken word line. | 2013-05-09 |
20130114343 | SEMICONDUCTOR DEVICE WITH ONE-TIME PROGRAMMABLE MEMORY CELL INCLUDING ANTI-FUSE WITH METAL/POLYCIDE GATE - A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate. | 2013-05-09 |
20130114344 | ERRATIC PROGRAM DETECTION FOR NON-VOLATILE STORAGE - Methods and non-volatile storage systems are provided for determining erratically programmed storage elements, including under-programmed and over-programmed storage elements. Techniques do not require any additional data latches. A set of data latches may be used to store program data for a given memory element. This program data may be maintained after the programming is over for use in erratic program detection. In one embodiment, lockout status is kept in a data latch that is used to serially receive program data to be programmed into the storage element. Therefore, no extra data latches are required to program the storage elements and to maintain the program data afterwards. | 2013-05-09 |
20130114345 | NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF - According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors. | 2013-05-09 |
20130114346 | METHOD OF OPERATING A FLASH EEPROM MEMORY - The invention is a new method for operating a flash EEPROM memory device and in particular for programming and erasing the device. The memory device has a first semiconductor region within a second semiconductor region, source and drain regions in the first semiconductor region, a well terminal inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer, and a control terminal electrically isolated from the charge storing layer by a inter layer dielectric. The method comprises the steps of: applying a first voltage bias of first polarity to the well terminal; allowing a first time period to elapse; applying a second voltage bias of second polarity opposite to the first polarity to the control terminal; resetting the first voltage bias to zero; allowing a second time period to elapse; and resetting the second voltage bias to zero. | 2013-05-09 |
20130114347 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR SYSTEM - A semiconductor system includes a semiconductor memory device configured to, during a test mode, store received data in a memory cell in response to a write command, read the stored data as information data in response to a read command, and internally store the information data, in response to the read command, in synchronization with a pulse generated when a level of the information data changes. | 2013-05-09 |
20130114348 | SELF REFRESH PULSE GENERATION CIRCUIT - A self refresh pulse generation circuit includes a control signal generator configured to generate a control signal asserted for an initial period of a self refresh mode, and a self refresh pulse generator configured to generate a self refresh pulse having a period controlled in response to the control signal, in the self refresh mode. | 2013-05-09 |
20130114349 | SEMICONDUCTOR SYSTEM INCLUDING A CONTROLLER AND MEMORY - A semiconductor system includes three or more memory chips and a controller with first and second memory buffers configured to communicate with the three or more memory chips. The first and second memory buffers alternately transmit data to sequentially communicate with the three or more memory chips. | 2013-05-09 |
20130114350 | SEMICONDUCTOR MEMORY DEVICE INCLUDING INITIALIZATION SIGNAL GENERATION CIRCUIT - An initialization signal generation circuit includes: an initialization signal output unit configured to generate an initialization signal which is enabled during at least a portion of an auto refresh operation period of the initialization mode, in response to a flag signal; a refresh signal generation unit configured to generate a preliminary refresh signal and a refresh counting signal having the same period as the auto refresh signal in response to the flag signal and an auto refresh signal; and a counter unit configured to count a counting signal in response to the refresh counting signal and generate a counting initialization signal, which is delayed by at least a pulse width of the refresh counting signal, after a time point where a combination of the counting signal becomes a preset combination. | 2013-05-09 |
20130114351 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF - A semiconductor device includes a data storage unit configured to receive input data, outputs the input data with a difference in voltage level between logic levels, and output comparison data whose logic level is distinguished from the input data; a test operation unit configured to determine a logic level of test data periodically in response to a data reference voltage whose voltage level is determined in response to a level test code during a test operation period defined by a test entry command and a test exit command, and generate a test result signal by comparing a logic level of the comparison data with the logic level of the test data; and a test operation sensing signal generation unit configured to generate a test operation sensing signal that is activated in response to the test entry command and inactivated in response to the test result signal. | 2013-05-09 |
20130114352 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock. | 2013-05-09 |
20130114353 | MEMORY METHODS AND SYSTEMS WITH ADIABATIC SWITCHING - A memory system includes wordlines and pairs of complementary bitlines that provide access to memory storage elements. Capacitive and resistive loads associated with wordlines and bitlines are driven relatively slowly between voltage levels to reduce peak current, and thus power dissipation. Power dissipation is further reduced by charging complementary bitlines at substantially different rates. | 2013-05-09 |
20130114354 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A memory device comprises a nonvolatile memory device and a controller. The nonvolatile memory comprises a first memory area comprising single-bit memory cells and a second memory area comprising multi-bit memory cells. The controller is configured to receive a first unit of write data, determine a type of the first unit of write data, and based on the type, temporarily store the first unit of write data in the first memory area and subsequently migrate the temporarily stored first unit of write data to the second memory area or to directly store the first unit of write data in the second memory area, and is further configured to migrate a second unit of write data temporarily stored in the first memory area to the second memory area where the first unit of write data is directly stored in the second memory area. | 2013-05-09 |
20130114355 | METHOD FOR ADJUSTING VOLTAGE CHARACTERISTICS OF SEMICONDUCTOR MEMORY ELEMENT, METHOD FOR ADJUSTING VOLTAGE CHARACTERISTICS OF SEMICONDUCTOR MEMORY DEVICE, CHARGE PUMP AND METHOD FOR ADJUSTING VOLTAGE OF CHARGE PUMP - Voltages are applied to supply voltage application points of memory cells of an SRAM, a semiconductor substrate, a word line and bit lines so that voltage Vdd takes value V | 2013-05-09 |
20130114356 | SEMICONDUCTOR MEMORY APPARATUS, AND DIVISIONAL PROGRAM CONTROL CIRCUIT AND PROGRAM METHOD THEREFOR - A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal; a divisional program control circuit configured to generate a divisional programming enable signal according to a predetermined number of program division times, in response to the program completion signal; and a controller configured to generate the programming enable signal in response to the divisional programming enable signal. | 2013-05-09 |
20130114357 | SEMICONDUCTOR MEMORY APPARATUS, AND SUCCESSIVE PROGRAM CONTROL CIRCUIT AND PROGRAM METHOD THEREFOR - A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal in response to a programming enable signal; a successive program control circuit configured to generate a successive programming enable signal in response to received program addresses and data count signals as a buffered program command or a buffered overwrite command; and a controller configured to generate the programming enable signal in response to the successive programming enable signal. | 2013-05-09 |
20130114358 | ADDRESS DECODING METHOD AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A semiconductor memory device includes: a strobe clock generator configured to generate a strobe clock signal having a delay time controlled according to a plurality of test mode signals which are selectively enabled in response to a read signal or write signal; an internal address generator configured to latch an address in response to a first level of the strobe clock signal, and generate an internal address by decoding the address in response to a second level of the strobe clock signal; and an output enable signal generator configured to decode the internal address and generate output enable signals which are selectively enabled. | 2013-05-09 |
20130114359 | INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS AND SYSTEM WITH THE SAME - A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor memory apparatus and the controller, and configured to control input/output of signals between the controller and the semiconductor memory apparatus, wherein the input/output device operates in a normal mode which corresponds to the input/output of the signals between the controller operating at the first speed and the semiconductor memory apparatus and a test mode which corresponds to the input/output of the signals between the controller operating at the second speed and the semiconductor memory apparatus. | 2013-05-09 |
20130114360 | METHOD FOR DETECTING PERMANENT FAULTS OF AN ADDRESS DECODER OF AN ELECTRONIC MEMORY DEVICE - An embodiment of a method for detecting permanent faults of an address decoder of an electronic memory device including a memory block formed by a plurality of memory cells, including the steps of: selecting an address, which identifies a selected set of memory cells; writing at the selected address a code word generated on the basis of an information word, of the selected address, and of an error-correction code; and then detecting an error within a word stored at the selected address. The method moreover includes the steps of: selecting a set of excitation addresses; writing a test word at the selected address, and then writing an excitation word at each excitation address; and next comparing the test word with a new word stored at the selected address. | 2013-05-09 |
20130114361 | SENSE AMPLIFIER HAVING AN ISOLATED PRE-CHARGE ARCHITECTURE, A MEMORY CIRCUIT INCORPORATING SUCH A SENSE AMPLIFIER AND ASSOCIATED METHODS - Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in series. One inverter has a voltage-controlled switch controlling the electrical connection between drain nodes of the transistors. During a read operation, the pull-up transistor drain node is pre-charged high and the pull-down transistor drain node receives an input signal. The switch is tripped, thereby making the electrical connection only when the voltage at the pull-down transistor drain node is less than the switch's trip voltage. In this case, the sense node discharges to the same level as the input signal. Otherwise, the switch prevents the electrical connection and the sense node remains high. The trip voltage depends on a reference voltage, which can be variable, thereby allowing the sensitivity of the sense amplifier to be selectively adjusted. Also disclosed are associated methods. | 2013-05-09 |
20130114362 | DATA TRANSMISSION CIRCUIT - A data transmission circuit includes an enable signal generation unit configured to receive a first enable signal and generate a second enable signal having a pulse width controlled according to a swing width of data inputted through a first data line, and a sense amplification unit configured to sense and amplify the data inputted through the first data line in response to the second enable signal, and transmit the amplified data to a second data line. | 2013-05-09 |
20130114363 | MULTI-MODAL MEMORY INTERFACE - A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type of memory, and differential voltage-mode signaling from the memory to the memory controller. In contrast, in a second type of system, the memory interface is configured to provide single-ended voltage-mode signaling from the memory controller to the memory, and single-ended voltage-mode signaling from a second type of memory to the memory controller. To support these different types of systems, the memory controller couples different types of drivers to each I/O pad. The resulting capacitance is reduced by sharing components between these drivers. Moreover, in some embodiments, the memory interface is implemented using “near-ground” current-mode and voltage-mode signaling techniques. | 2013-05-09 |
20130114364 | SEMICONDUCTOR DEVICE PERFORMING REFRESH OPERATION - Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal. | 2013-05-09 |
20130114365 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - Disclosed is a semiconductor memory device, including a plurality of internal voltage generation units configured to be enabled in response to each of a plurality of decoding signals and to generate an internal voltage, a controller configured to generate a plurality of control signals in response to a power up signal and a test mode signal, and a decoder configured to generate the plurality of decoding signals corresponding to at least one decoding source signal and to simultaneously activate some or all of the plurality of decoding signals in response to the control signals. | 2013-05-09 |
20130114366 | SEMICONDUCTOR DEVICE HAVING PLURAL SELECTION LINES SELECTED BASED ON ADDRESS SIGNAL - Disclosed herein is a device that includes: a set of address terminals supplied with a set of address signals, each of the address signals being changed in logic level; memory mats to which address ranges are allocated, respectively, the address ranges being different from each other, each of the memory mats including memory cells; and decoder units each provided correspondingly to corresponding memory mat. Each of the decoder units includes a set of first input nodes and a set of second input nodes, the set of first input nodes of each of the decoder units being coupled to the set of address terminals to receive the set of address signals, the set of second input nodes of each of the decoder units being coupled to receive an associated one of sets of control signals, each of the control signals being fixed in logic level. | 2013-05-09 |
20130114367 | Apparatus For Producing Foamed Bitumen And Method For Its Maintenance - The present invention relates to an apparatus for producing foamed bitumen for a road construction machine, comprising at least one mixing device having a reaction chamber, in which hot bitumen and at least one reaction fluid can be mixed together via an inlet device comprising at least one inlet nozzle and can be discharged from the mixing device via an outlet device, with at least one compressed-air device being provided, via which the inlet device and/or the outlet device can be subjected to a compressed-air stream for testing and/or cleaning purposes. The present invention further also relates to a method for maintaining such an apparatus. | 2013-05-09 |
20130114368 | Horizontal Mixer with Center-Angled Blades - A horizontal mixer ( | 2013-05-09 |
20130114369 | MICRO MIXER - Disclosed is a micro mixer which includes a mixing plate ( | 2013-05-09 |
20130114370 | MAGNETICALLY-DRIVEN STIRRING STRUCTURE - A magnetically-driven stirring structure includes a transmission base, and a cup can be mounted to the transmission base or positioned on the transmission base. The transmission base includes a rotary mechanism, and the rotary mechanism is coupled to a first magnetic member. The rotary mechanism is coupled to an operating member in such a way that the operating member is exposed outside the transmission base. With a second magnetic member being placed in the cup, in making or brewing a drink in the cup, through actuation caused by the operating member, the rotary mechanism is made rotating and driving the first magnetic member to rotate, whereby the second magnetic member placed in the cup is caused by magnetism to rotate in the same direction so as to achieve stirring of the drink contained in the cup. | 2013-05-09 |
20130114371 | ULTRASONIC DIAGNOSTIC APPARATUS - An ultrasonic diagnostic apparatus has a storage unit for storing the elastic volume data generated on the basis of the ultrasonic image data obtained by transmitting/receiving ultrasonic waves to/from an object to be examined, an input unit for setting a region of interest in the space which is occupied by the elastic volume data, an extraction unit for extracting from the elastic volume data a voxel group having the voxel values within a set elasticity range which is set based on the elasticity value of the voxels in the region of interest, a 3-dimensional elastic image creation unit for generating a 3-dimensional elastic image basis on the elastic volume data of the voxel group which is extracted by the extraction unit or the elastic volume data excluding the extracted voxel group; and an image display unit for displaying the 3-dimensional elastic image generated by the 3-dimensional elastic image creation unit. | 2013-05-09 |
20130114372 | OSCILLATING FLARED STREAMERS - The invention relates to a seismic acquisition process where the streamers are intentionally directed to follow an oscillating sweep pattern behind a tow vessel to counteract the effect of the large gaps between the streamers while acquire a wide sweep of data through each pass over the survey area. | 2013-05-09 |
20130114373 | METHOD AND DEVICE FOR MARINE SEISMIC ACQUISITION - Method and system for improving offset/azimuth distribution. The system includes plural streamers towed by a streamer vessel; a central source towed by the streamer vessel; first and second front sources located in front of the plural streamers along a traveling direction of the streamer vessel; and first and second large offset front sources located in front of the first and second front sources along the traveling direction. The offset distance between the first and second large offset front sources, along a cross-line direction, is larger than an offset distance between the first and second front sources. | 2013-05-09 |
20130114374 | ADJUSTABLE SENSOR STREAMER STRETCH SECTION FOR NOISE CONTROL FOR GEOPHYSICAL SENSOR STREAMERS - A sensor streamer stretch section includes at least one spring. A means for coupling the spring at each end to at least one of a sensor streamer and a lead in cable is included. A cable is coupled at its ends to the means for coupling. The cable is capable of carrying at least one of electrical and optical signals. The cable is formed such that the cable undergoes substantially no axial strain when the shock cord is elongated. An adjustable damper is coupled between the means for coupling at each end of the stretch section. | 2013-05-09 |
20130114375 | Seismic Acquisition Method for Mode Separation - Method for separating different seismic energy modes in the acquisition ( | 2013-05-09 |
20130114376 | AUTOMATIC DISPERSION EXTRATION OF MULTIPLE TIME OVERLAPPED ACOUSTIC SIGNALS - Slowness dispersion characteristics of multiple possibly interfering signals in broadband acoustic waves as received by an array of two or more sensors are extracted without using a physical model. The problem of dispersion extraction is mapped to the problem of reconstructing signals having a sparse representation in an appropriately chosen over-complete dictionary of basis elements. A sparsity penalized signal reconstruction algorithm is described where the sparsity constraints are implemented by imposing a l | 2013-05-09 |
20130114377 | Systems and Methods to Discriminate Annular Heavy Fluids From Cement - A cement bond logging method for wells containing heavy mud and cement is provided. Acoustic logging tool data from a well having material in the annular space between the casing and the formation is analyzed to map relationships between waveform amplitude, acoustic impedance, and impedance derivative of the material. Map zones representing fully bonded well regions and partially bonded well regions are identified. An image is generated from the log data corresponding to the identified map zones. A cement bond logging system including a memory having cement bond logging software and a processor coupled to the memory to execute the software is also provided. | 2013-05-09 |
20130114378 | Widebeam Acoustic Transducer - An acoustic transducer for producing sonar waves features a piezoelectric structure with a radiating surface. A plurality of elements is attached to the radiating surface, and at least two of the plurality of elements have different acoustic properties. The acoustic transducer is designed for a wider beam angle for a thickness vibration mode while maintaining other desired vibration frequencies, maximum input power and low cost. | 2013-05-09 |
20130114379 | ATTENUATING MASS FOR AN ULTRASONIC SENSOR, USE OF EPOXY RESIN - Temperature stability at the temperatures prevailing in a motor and stability that is required over an entire temperature range are provided by an attenuating mass. This enables continuous use at temperatures of approximately 150° C. while providing ultrasonic attenuation at low temperatures. | 2013-05-09 |
20130114380 | ULTRASOUND BASED MOBILE RECEIVERS IN IDLE MODE - An acoustic system, which may be ultrasonic, operates in a power efficient idle mode thereby reducing the power consumption required by high frequency sampling and processing. While in idle mode, an acoustic receiver device operates with an idle sampling rate that is lower than the full sampling rate used during full operational mode, but is capable of receiving a wake-up signal from the associated acoustic transmitter. When the wake-up signal is received, the acoustic receiver switches to full operational mode by increasing the sampling rate and enables full processing. The acoustic system may be used in, e.g., an ultrasonic pointing device, location beacons, in peer-to-peer communications between devices, as well as gesture detection. | 2013-05-09 |
20130114381 | OSCILLATING WEIGHT - The oscillating weight is intended to be used in a self winding watch mechanism. It includes a basic part ( | 2013-05-09 |
20130114382 | ALARM METHOD AND DEVICE - The present invention discloses an alarm method and device, and belongs to the electronic product field. The method includes: playing a first-time alarm clock ring when an alarm clock is triggered for a first time; and playing a delay alarm clock ring when the alarm clock is triggered again after a period of delay time. The device includes: a first play module and a second play module. According to the present invention, when the alarm clock rings, even if a user is in a doze state, the user is still able to determine whether the current ring is the first-time ring or the delay ring according to the different rings of the alarm clock, and then knows whether it is time to get up, thereby ensuring that the user is able to get up at the right time, and improving the user experience. | 2013-05-09 |
20130114383 | WATCH CASE INCLUDING AN ORIENTATION MEMORY CROWN - A watch case comprising:
| 2013-05-09 |
20130114384 | MICROWAVE-ASSISTED MAGNETIC RECORDING DEVICE AND METHOD OF FORMATION THEREOF - A magnetic head, according to one embodiment, includes a magnetized high-speed rotor placed in the vicinity of a main magnetic pole, wherein the main magnetic pole generates a magnetized rotating magnetic field, wherein information is recorded by generating a high-frequency magnetic field from the magnetized high-speed rotor and switching the magnetic head between a magnetic resonance state and a magnetization state, and wherein the magnetic head has a structure such that leaking is reduced for magnetic fields applied parallel to a magnetized rotating surface of the magnetized high-speed rotor from the main magnetic pole. Additional systems and methods are also presented. | 2013-05-09 |
20130114385 | OPTICAL INFORMATION RECORDING MEDIUM AND DRIVE DEVICE - An optical information recording medium includes at least one recording layer, a protective layer that transmits a focused laser beam, and a super-resolution functional layer that changes an optical characteristic in a local region smaller than the diffraction limit determined by the optical performance of the focusing optical system and the wavelength of the laser beam during at least the period of irradiation by the focused laser beam. The maximum thickness (K) between the light incidence surface of the protective layer and the recording layer is 0.083 mm. | 2013-05-09 |
20130114386 | INFORMATION REPRODUCTION DEVICE AND METHOD OF PROVIDING CONTENT - Provided is an information reproduction device ( | 2013-05-09 |
20130114387 | MEASURING METHOD OF A MAGNETIC HEAD AND MEASURING APPARATUS THEREOF - Measuring method of a magnetic head includes (a) placing the magnetic head at normal position, defining a first direction parallel to an air bearing surface and two shielding layers of the magnetic head, and defining a second direction perpendicular to the first direction; (b) tilting the magnetic head at an angle to the second direction, applying a plurality of first magnetic fields with different intensities in the first direction, and measuring out a first output parameter curve; (c) repeating the step (b) with different angles and measuring out a plurality of first output parameter curves; (d) calculating a plurality of pinned direction tilt ratios that a pinned direction of a pinned layer of the magnetic head tilts towards the second direction according to the parameter curves; and (e) calculating a pinned direction tilt angle that the pinned direction tilts towards the second direction according to the pinned direction tilting ratios. | 2013-05-09 |
20130114388 | LENS DRIVING UNIT FOR OPTICAL PICKUP AND OPTICAL DISC DRIVE INCLUDING THE LENS DRIVING UNIT - Provided is a lens driving unit for an optical pickup and an optical disc drive employing the lens driving unit. First and second driving coils are directly wound around a coil winding unit included in the lens frame, which is different from a conventional lens frame in which a driving coil is manufactured as a separate element and is separately attached to a lens frame. | 2013-05-09 |
20130114389 | NEAR-FIELD OPTICAL HEAD AND METHOD FOR MANUFACTURING SAME - A near-field optical head which can be manufactured using a silicon process and illuminate and detect sufficient light from a very small aperture at all times in a state of stably proximate to a media. | 2013-05-09 |