19th week of 2009 patent applcation highlights part 14 |
Patent application number | Title | Published |
20090114892 | Cable Drawworks for a Drilling Rig - A cable drawworks for a drilling rig is provided having a three-phase AC electric motor controlled by a variable frequency drive control system. A primary drive transmission consisting of a chain and sprockets connects the motor to a drum shaft that passes through the hub of a cable drum such that the cable drum is rotatably mounted on the drum shaft. The drum shaft connects to a secondary drive transmission, attached to the frame via an oscillating plate assembly, that connects the drum shaft to the cable drum. Each end of the cable drum has a brake drum and a brake band wrapped around thereon. A brake actuating system is used to tighten the bands around each drum during braking conditions and includes an equalization linkage system between the brake bands resulting in equal braking forces being applied to each brake drum. | 2009-05-07 |
20090114893 | Block with Improved Central Mounting - A block with a rotating sheave mounted between a pair of side plates. Captured between the side plates may be a post about which a mounting loop may be mounted. The post is removable from the between the side plates to permit the loop to be attached or detached from the block. | 2009-05-07 |
20090114894 | Universal Sheave Wheel Adapter - An assembly is provided that includes an oilwell rig; a sheave wheel adapter connected to the rig; a sheave wheel yoke connected to the adapter; and a sheave wheel connected to the yoke. In various embodiments of the invention, this assembly is configured to permit the wheel to rotate about three mutually perpendicular planes of motion. | 2009-05-07 |
20090114895 | POST AND RAILING ASSEMBLY WITH SUPPORT BRACKET COVERS - A method for installing a post and railing assembly includes the steps of providing a post structure with a mounting bracket, mounting the post structure, lowering the end of a railing member onto the mounting bracket, providing a trim cover, wrapping the trim cover around the bracket and railing end, and locking the trim cover around the railing and bracket. A railing mounting assembly includes a U-shaped bracket having a pair of sidewalls and a bottom wall, the bottom wall comprising a pair of platform portions for supporting a railing, and a pair of recessed portions separated from one another by a channel, and a trim cover attached around the bracket, the trim cover having a slit and at least one locking member projecting through the channel of the U-shaped bracket. | 2009-05-07 |
20090114896 | MEMORY DEVICE USING ABRUPT METAL-INSULATOR TRANSITION AND METHOD OF OPERATING THE SAME - Provided are a memory device that undergoes no structural phase change, maintains a uniform thin film, and can perform a high-speed switching operation, and a method of operating the same. The memory device includes a substrate, an abrupt MIT material layer, and a plurality of electrodes. The abrupt MIT material layer is disposed on the substrate and undergoes an abrupt metal-insulator transition by an energy change between electrons. The plurality of electrodes are brought into contact with the abrupt MIT material layer and are melted by heat to form a conductive path on the abrupt MIT material layer. | 2009-05-07 |
20090114897 | PHASE CHANGE MEMORY DEVICE CAPABLE OF INCREASING SENSING MARGIN AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device capable of increasing a sensing margin and a method for manufacturing the same. The phase change memory device includes a semiconductor substrate formed with a device isolation structure which defines active regions; first conductivity type impurity regions formed in surfaces of the active regions and having the shape of a line; a second conductivity type well formed in the semiconductor substrate at a position lower than the device isolation structure; a second conductivity type ion-implantation layer formed in the semiconductor substrate at a boundary between a lower end of the device isolation structure and the semiconductor substrate; a plurality of vertical PN diodes formed on the first conductivity type impurity regions; and phase change memory cells formed on the vertical PN diodes. | 2009-05-07 |
20090114898 | Method and apparatus for reducing programmed volume of phase change memory - A phase change memory includes a volume of phase change material disposed between, and coupled to, two electrodes, with the composition of a region of at least one of the two electrodes or phase change material having been compositionally altered to reduce the programmed volume of the phase change material. | 2009-05-07 |
20090114899 | RESISTANCE MEMORY AND METHOD FOR MANUFACTURING THE SAME - A resistance memory is manufactured using semiconductor processing to comprise planar dual-tip electrodes so that the electric field in the resistance memory is concentrated to reduce the number of fuses in the dielectric material and improve the device characteristics. The resistance memory comprises: a first memory cell including a first bottom electrode and a common top electrode; and a second memory cell including a second bottom electrode and the common top electrode shared with the first memory cell; wherein the first bottom electrode, the second bottom electrode and the common top electrode are disposed on the same plane and are separated by a resistive conversion layer; wherein the common top electrode is connected to the ground through a via, while the first bottom electrode and the second bottom electrode are connected to the source of a transistor through a plug, respectively. | 2009-05-07 |
20090114900 | SEMICONDUCTOR LIGHT-EMITTING DIODE - A semiconductor light-emitting diode | 2009-05-07 |
20090114901 | Room Temperature Carbon Nanotubes Integrated on CMOS - Embodiments of the invention integrate carbon nanotubes on a CMOS substrate using localized heating. An embodiment can allow the CMOS substrate to be in a room-temperature environment during the carbon nanotube growth process. Specific embodiments utilize a maskless post-CMOS microelectromechanical systems (MEMS) process. The post-CMOS MEMS process according to an embodiment of the present invention provides a carbon nanotube growth process that is foundry CMOS compatible. The maskless process, according to an embodiment, eliminates the need for photomasks after the CMOS fabrication and can preserve whatever feature sizes are available in the foundry CMOS process. Embodiments integrate single-walled carbon nanotube devices into a CMOS platform. | 2009-05-07 |
20090114902 | TENSILE STRAINED GE FOR ELECTRONIC AND OPTOELECTRONIC APPLICATIONS - A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers. | 2009-05-07 |
20090114903 | Integrated Nanotube and CMOS Devices For System-On-Chip (SoC) Applications and Method for Forming The Same - An integrated, multilayer nanotube and complementary metal oxide semiconductor (CMOS) device is provided along with a method of forming the same. The device includes at least one CMOS device formed on at least one layer of the device, a first metal wiring layer that is electrically connected to the least one CMOS device, and at least one nanotube device formed over the first metal wiring layer in parasitic isolation from the at least one CMOS device. In one or more embodiments, the at least one CMOS device and the at least one nanotube device are located on different layers of a same semiconductor wafer chip to allow the wafer to be is used for system-on-chip (SoC) applications having RF/analog circuitry based on the least one nanotube device and digital circuitry based on the at least one CMOS device. | 2009-05-07 |
20090114904 | SEMICONDUCTOR DEVICES HAVING NANO-LINE CHANNELS - A semiconductor device includes a substrate, a gate electrode on the substrate and source and drain electrodes disposed at respective sides of the gate electrode. The device further includes a nano-line passing through the gate electrode and extending into the source and drain electrodes and having semiconductor characteristics. The nano-line may include a nano-wire and/or a nano-tube. A gate insulating layer may be interposed between the nano-line and the gate electrode. The source and drain electrodes may be disposed adjacent respective opposite sidewalls of the gate electrode, and the gate insulating layer may be further interposed between the source and drain electrodes and the gate electrode. Fabrication methods for such devices are also described. | 2009-05-07 |
20090114905 | Organic electrical or electric component with increased lifetime - In order to increase the lifetime of organic electrical or electronic components, the invention provides an organic electrical or electronic component comprising at least one organic functional layer, wherein the component contains an (e-v) quenching substance for singlet oxygen. | 2009-05-07 |
20090114906 | MATERIALS FOR N-DOPING THE ELECTRON-TRANSPORTING LAYERS IN ORGANIC ELECTRONIC COMPONENTS - New materials for the n-doping of the elctron-transporting layer in organic electronic components, their utilization, and organic electronic components | 2009-05-07 |
20090114907 | FIELD EFFECT TYPE ORGANIC TRANSISTOR AND PROCESS FOR PRODUCTION THEREOF - A field effect type organic transistor is provided which comprises a source electrode, a drain electrode, and a gate electrode, a gate insulating layer, and an organic semiconductor layer, wherein the gate insulating layer contains an optical anisotropic material having an anisotropic structure formed by light irradiation, and the organic semiconductor layer is in contact with the anisotropic structure. | 2009-05-07 |
20090114908 | ORGANIC SEMICONDUCTOR THIN FILM, ORGANIC THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING ORGANIC THIN FILM TRANSISTOR - Disclosed is an organic semiconductor thin film having excellent coating property and high carrier mobility. Also disclosed are an organic thin film transistor using such an organic semiconductor thin film, and a method for manufacturing such an organic thin film transistor. Specifically disclosed is an organic semiconductor thin film formed on a substrate subjected to a surface treatment. This organic semiconductor thin film is characterized in that a surface treating agent used in the surface treatment has a terminal structure represented by a specific general formula. | 2009-05-07 |
20090114909 | DEVICE CONTAINING POLYMER HAVING INDOLOCARBAZOLE- REPEAT UNIT AND DIVALENT LINKAGE - An electronic device comprising a polymer comprising at least one type of repeat unit comprising at least one type of an optionally substituted indolocarbazole moiety and at least one divalent linkage. | 2009-05-07 |
20090114910 | SEMICONDUCTOR DEVICE - In the present invention, a thin film transistor is formed on a plastic film substrate ( | 2009-05-07 |
20090114911 | ELECTRONIC DEVICE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the region exposed to laser light to be left and realizing a source wiring and a drain wiring having a more microscopic pattern than the pattern itself formed by discharging. One feature of the source wiring and the drain wiring is that the source wiring and the drain wiring cross an island-like semiconductor layer and overlap it. | 2009-05-07 |
20090114912 | MASK DESIGN ELEMENTS TO AID CIRCUIT EDITING AND MASK REDESIGN - An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing. | 2009-05-07 |
20090114913 | TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES - A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C | 2009-05-07 |
20090114914 | High performance sub-system design and assembly - A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry. | 2009-05-07 |
20090114915 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A separation layer containing a halogen element is formed over a glass substrate by a plasma CVD method; a semiconductor element is formed over the separation layer; and separation is then performed inside the separation layer or at its interface, so that the large-area glass substrate and the semiconductor element are detached from each other. In order to perform detachment at the interface between the glass substrate and the separation layer, the separation layer may have concentration gradient of the halogen element, and the halogen element is contained more near the interface between the separation layer and the glass substrate than in the other areas. | 2009-05-07 |
20090114916 | PHOTOELECTRIC CONVERSION DEVICE AND PHOTODETECTOR APPARATUS HAVING THE SAME - A photoelectric conversion device includes an intrinsic semiconductor layer, a first conductive type semiconductor layer disposed on a first side of the intrinsic semiconductor layer, and a second conductive type semiconductor layer disposed on a second side of the intrinsic semiconductor layer opposite the first side. The intrinsic semiconductor layer includes an amorphous semiconductor layer and a crystalline semiconductor layer including a plurality of crystals. A diameter of a crystal of the plurality of crystals is equal to or less than approximately 100 angstroms. | 2009-05-07 |
20090114917 | THIN FILM TRANSISTOR AND DISPLAY DEVICE HAVING THE THIN FILM TRANSISTOR - A thin film transistor includes a gate electrode, a gate insulating layer covering the gate electrode, a microcrystalline semiconductor layer over the gate insulating layer, an amorphous semiconductor layer over the microcrystalline semiconductor layer, source and drain regions over the amorphous semiconductor layer, source and drain electrodes in contact with and over the source and drain regions, and a part of the amorphous semiconductor layer overlapping with the source and drain regions is thicker than a part of the amorphous semiconductor layer overlapping with a channel formation region. The side face of the source and drain regions and the side face of the amorphous semiconductor form a tapered shape together with an outmost surface of the amorphous semiconductor layer. The taper angle of the tapered shape is such an angle that decrease electric field concentration around a junction portion between the source and drain regions and the amorphous semiconductor layer. | 2009-05-07 |
20090114918 | PANEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A panel structure and a manufacturing method thereof are provided. The panel structure is disposed in a display device. The panel structure includes a substrate, several first transistors and second transistors. The substrate has a display circuit and a control circuit. The first transistors are disposed at the display circuit of the substrate. Each of the first transistors has a first active layer. The second transistors are disposed at the control circuit of the substrate. Each of the second transistors has a second active layer. The materials of at least one of the first active layer and the second active layer include ZnO. | 2009-05-07 |
20090114919 | SEMICONDUCTOR RANGE-FINDING ELEMENT AND SOLID-STATE IMAGING DEVICE - A semiconductor range-finding element and a solid-state imaging device, which can provide a smaller dark current and a removal of reset noise. With n-type buried charge-generation region, buried charge-transfer regions, buried charge read-out regions buried in a surface of p-type semiconductor layer, an insulating film covering these regions, transfer gate electrodes arranged on the insulating film for transferring the signal charges to the buried charge-transfer regions, read-out gate electrodes arranged on the insulating film for transferring the signal charges to the buried charge read-out regions, after receiving a light pulse by the buried charge-generation region, in the semiconductor layer just under the buried charge-generation region, an optical signal is converted into signal charges, and a distance from a target sample is determined by a distribution ratio of the signal charges accumulated in the buried charge-transfer regions. | 2009-05-07 |
20090114920 | TFT SUBSTRATE AND LIQUID CYRSTAL DISPLAY DEVICE HAVING THE SAME - An LCD device includes a first substrate having a first base substrate, patterns disposed at different heights with respect to the first base substrate, and an insulation layer formed on the first base substrate and the patterns. The insulation layer has raised portions corresponding to the patterns. A side of the raised portions forms an inclination angle of no more than about 45° when a height of the raised portions is more than about 3000 angstroms, the side of the raised portions forms an inclination angle of no more than about 50° when a height of the raised portions is in a range of about 2000 angstroms to about 3000 angstroms, and the side of the raised portions forms an inclination angle of no more than about 90° when a height of the raised portions is more than about 2000 angstroms. Therefore, light leakage may be minimized. | 2009-05-07 |
20090114921 | THIN FILM TRANSISTOR, AND DISPLAY DEVICE HAVING THE THIN FILM TRANSISTOR - The thin film transistor includes a gate insulating film formed over a gate electrode; a microcrystalline semiconductor film including an impurity element which serves as a donor, formed over the gate insulating film; a pair of buffer layers formed over the microcrystalline semiconductor film; a pair of semiconductor films to which an impurity element imparting one conductivity type is added, formed over the pair of buffer layers; and wirings formed over the pair of semiconductor films to which an impurity element imparting one conductivity type is added. The concentration of the impurity element which serves as a donor in the microcrystalline semiconductor film is decreased from the gate insulating film side toward the buffer layers, and the buffer layers do not include the impurity element which serves as a donor at a higher concentration than the detection limit of SIMS. | 2009-05-07 |
20090114922 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, LIQUID CRYSTAL TELEVISION, AND EL TELEVISION - An object of the present invention is to provide a method for manufacturing a semiconductor device having a semiconductor element capable of reducing a cost and improving a throughput with a minute structure, and further, a method for manufacturing a liquid crystal television and an EL television. According to one feature of the invention, a method for manufacturing a semiconductor device comprises the steps of: forming a light absorption layer over a substrate, forming a first region over the light absorption layer by using a solution, generating heat by irradiating the light absorption layer with laser light, and forming a first film pattern by heating the first region with the heat. | 2009-05-07 |
20090114923 | SEMICONDUCTOR DEVICE - A semiconductor device includes a peripheral voltage withstanding structure, which includes an n | 2009-05-07 |
20090114924 | LIGHTLY DOPED SILICON CARBIDE WAFER AND USE THEREOF IN HIGH POWER DEVICES - A method for manufacturing a silicon carbide single crystal. A silicon carbide single crystal is grown. The crystal has a boron concentration less than 5×10 | 2009-05-07 |
20090114925 | PHOTON PAIR GENERATING DEVICE - A photon pair generating device capable of further increasing generation efficiency of a correlation photon pair is provided, the photon pair generating device generating the correlation photon pair by a hyper-parametric scattering. A quantum well ( | 2009-05-07 |
20090114926 | Light-emitting device - A light-emitting device includes a pixel having a transistor provided over a substrate, and a light-emitting element. The transistor includes a single-crystal semiconductor layer which forms a channel formation region, a silicon oxide layer is provided between the substrate and the single-crystal semiconductor layer, a source or a drain of the transistor is electrically connected to an electrode of the light-emitting element, and the transistor is operated in a saturation region when the light-emitting element emits light. Further, in the light-emitting device, a gray scale of the light-emitting element is displayed by changing a potential applied to the gate of the transistor. | 2009-05-07 |
20090114927 | Multi-chips with an optical interconnection unit - A multi-chip having an optical interconnection unit is provided. The multi-chip having an optical interconnection unit includes a plurality of silicon chips sequentially stacked, a plurality of optical device arrays on a side of each of the plurality of the silicon chips such that the optical device arrays correspond to each other and a wiring electrically connecting the silicon chip and the optical device array attached to a side of the silicon chip, wherein the corresponding optical device arrays forms an optical connection unit by transmitting and receiving an optical signal between the corresponding optical device arrays in different layers. Each of the optical device arrays includes at least one of a light emitting device and a light receiving device | 2009-05-07 |
20090114928 | LIGHTING STRUCTURE COMPRISING AT LEAST ONE LIGHT-EMITTING DIODE, METHOD FOR MAKING SAME AND USES THEREOF - A luminous structure based on light-emitting diodes, which includes: a first dielectric element with a substantially plane main face associated with a first electrode; a second dielectric element with a substantially plane main face associated with a second electrode that faces the first electrode and lies in a different plane; at least a first light-emitting diode including a semiconductor chip including, on first and second opposed faces, first and second electrical contacts, the first electrical contact being electrically connected to the first electrode, the second electrical contact being electrically connected to the second electrode, and at least the first element at least partly transmitting radiation within the ultraviolet or in the visible. | 2009-05-07 |
20090114929 | WHITE LIGHT EMITTING DEVICE - There is provided a white light emitting device that prevents a red phosphor from resorbing wavelength-converted light to improve white luminous efficiency. A white light emitting device according to an aspect of the invention includes a package body; at least two LED chips mounted to the package body and emitting excitation light; and a molding unit including phosphors, absorbing the excitation light and emitting wavelength-converted light, in regions of the molding unit divided according to the LED chips and molding the LED chips. According to the aspect of the invention, since the phosphor for converted red light can be prevented from resorbing light generated from other regions of the molding unit, the white light emitting device that can improve white luminous efficiency or control color rendering and color temperature by adjusting a mixing ratio of converted light for white light emission. | 2009-05-07 |
20090114930 | LIGHT-EMITTING DIODE AND LIGHT-EMITTING DIODE ARRAY LIGHT SOURCE - A light-emitting diode (LED) includes a substrate, a metallic buffer layer, a first type doped semiconductor layer, a light-emitting layer, a second type doped semiconductor layer, a first electrode, and a second electrode. The substrate has a plurality of bowl-shaped concaves or convexes on a surface thereof. The metallic buffer layer is disposed on the substrate and covers the bowl-shaped structure. The first type doped semiconductor layer is disposed on the metallic buffer layer. The light-emitting layer is disposed on a part of the first type doped semiconductor layer. The second type doped semiconductor layer is disposed on the light-emitting layer. The first electrode is disposed on the first type doped semiconductor layer not covered by the light-emitting layer. The second electrode is disposed on the second type doped semiconductor layer. | 2009-05-07 |
20090114931 | Light emitting module and method of forming the same - A method for forming a pixel of an LED light source is provided. The method includes following steps: forming a first layer on a substrate; forming a second layer and a first light-emitting active layer on the first layer; exposing a portion of an upper surface of the first layer; forming a third layer on the substrate; forming a fourth layer and a second light-emitting active layer on the third layer; exposing a portion of an upper surface of the third layer; and forming a first electrode on the exposed upper surface of the first layer, a second electrode on a portion of an upper surface of the second layer, a third electrode on the exposed upper surface of the third layer, and a fourth electrode a portion of an upper surface of the fourth layer. The first light-emitting active layer and the second light-emitting active layer emit different colors of light. | 2009-05-07 |
20090114932 | Light Source and Method of Controlling Light Spectrum of an LED Light Engine - A light emitting diode (LED) light engine includes a substrate for supporting the LED light engine. Conductive traces are formed over the substrate using a thick film screen printing, physical vapor deposition, chemical vapor deposition, electrolytic plating, printed circuit board fabricating, or electroless plating process. The conductive traces include mounting pads. LEDs are mounted to each of the mounting pads for electrical interconnection. The LEDs include red LEDs, green LEDs and blue LEDs. Each of the blue LEDs is at least partially covered with a yellow phosphor coating compound. The concentration of the yellow phosphor coating compound is controlled to allow the emission of blue and yellow spectrum light energy from each blue LED. Emissions of light energy from the red LEDs, green LEDs and blue LEDs are combined to achieve a target correlated color temperature and a target color rendering index for the LED light engine. | 2009-05-07 |
20090114933 | GaN BASED SEMICONDUCTOR LIGHT EMITTING DEVICE AND LAMP - A method for producing a gallium nitride based compound semiconductor light emitting device which is excellent in terms of the light emitting properties and the light emission efficiency and a lamp is provided. In such a method for producing a gallium nitride based compound semiconductor light emitting device, which is a method for producing a GaN based semiconductor light emitting device having at least a buffer layer, an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a translucent substrate, on which an uneven pattern composed of a convex shape and a concave shape is formed, the buffer layer is formed by a sputtering method conducted in an apparatus having a pivoted magnetron magnetic circuit and the buffer layer contains AlN, ZnO, Mg, or Hf. | 2009-05-07 |
20090114934 | Led light emitter with heat sink holder and method for manufacturing the same - An LED light emitter with heat sink holder and a method for manufacturing it are both disclosed. The LED light emitter with heat sink holder includes a heat sink holder and at least an LED chip. The heat sink holder is made of high thermal conductivity coefficient, and includes a reflecting mirror having a central portion and a reflecting portion surrounding the central portion. A normal of a top surface of the reflecting portion forms an acute angle relative to a normal of a top surface of the central portion. The LED chip is unitarily connected with a top surface of the central portion, and an electrode unit connecting with and Ohmic contacting the light emitting film for supplying power for the light emitting film. The LED light emitter with heat sink holder improves heat dissipation and working duration. | 2009-05-07 |
20090114935 | Light emitting diode and process for fabricating the same - A light emitting diode (LED) is provided. The LED at least includes a substrate, a saw-toothed multilayer, a first type semiconductor layer, an active emitting layer and a second type semiconductor layer. In the LED, the saw-tooth multilayer is formed opposite the active emitting layer below the first type semiconductor layer by an auto-cloning photonic crystal process. Due to the presence of the saw-tooth multilayer on the substrate of the LED, the scattered light form a back of the active emitting layer can be reused by reflecting and recycling through the saw-tooth multilayer. Thus, all light is focused to radiate forward so as to improve the light extraction efficiency of the LED. Moreover, the saw-tooth multilayer does not peel off or be cracked after any high temperature process because the saw-tooth multilayer has the performance of releasing thermal stress and reducing elastic deformation between it and the substrate. | 2009-05-07 |
20090114936 | LIGHT EMITTING DEVICE - To provide a light emitting device that makes it possible to form a surface light emitting apparatus of less unevenness in luminance. | 2009-05-07 |
20090114937 | RESIN-SEALED LIGHT EMITTING DEVICE AND ITS MANUFACTURING METHOD - An LED package is formed by separating a sealed body containing a substrate having a plurality of regions into individual bodies. The LED package includes an LED chip mounted on a recessed part in an upper surface of a substrate, a sealing resin to cover an entire surface of the region, a setting pattern provided on a bottom surface of the recessed part to set the LED chip, a wiring pad provided on the bottom surface of the recessed part, a wiring pattern provided on a slanted surface of the recessed part and serving as a light reflection part also, a wire to connect an electrode of the LED chip to the wiring pad, an external terminal provided on a lower surface of the substrate, a connection part to connect the wiring pattern connected to the wiring pad to the external terminal, and a heat radiating pattern provided on a lower surface to radiate a heat generated in the LED chip outside the LED package. The setting pattern is connected to the heat radiating pattern through the connection part. | 2009-05-07 |
20090114938 | Light emitting diode with sealant having filling particles - An exemplary light emitting diode (LED) includes an LED chip and a transparent sealant covering the LED chip. The sealant contains transparent filling particles and phosphor particles, wherein the filling particles are adjacent each other. Intervals are defined between the filling particles, and the phosphor particles are located in the intervals. | 2009-05-07 |
20090114939 | ILLUMINATION SYSTEM COMPRISING A RADIATION SOURCE AND A LUMINESCENT MATERIAL - An illumination system, comprising a radiation source and a luminescent material comprising at least one phosphor capable of absorbing a part of the light emitted by the radiation source and emitting light having a wavelength different from that of the absorbed light; wherein said at least one phosphor is a yellow to red-emitting europium(II)-activated ortho-phosphosilicate of general formula EA | 2009-05-07 |
20090114940 | Light-Emitting Device - The invention provides a light-emitting device, comprising a light-emitting element and a surface plasmon coupling element connected to the light-emitting element. In an embodiment of the invention, the surface plasmon coupling element comprises a dielectric layer connected to the light-emitting element and a metal layer on the dielectric layer. In another embodiment of the invention, the light-emitting device is a light-emitting diode, comprising an active layer between an n-type semiconductor layer and a p-type semiconductor layer, and a surface plasmon coupling element adjacent to the n-type semiconductor layer. In a further embodiment of the invention, a current spreading layer on a second type semiconductor layer of the light-emitting device includes a plurality of strip-shaped structures, and the surface plasmon coupling element is disposed on the current spreading layer and filled into the gap between the strip-shaped structures of the current spreading layer. | 2009-05-07 |
20090114941 | Semiconductor device and method of fabricating the same and method of forming nitride based semiconductor layer - A GaN layer is grown on a sapphire substrate, an SiO | 2009-05-07 |
20090114942 | APPARATUS FOR MANUFACTURING GROUP-III NITRIDE SEMICONDUCTOR LAYER, METHOD OF MANUFACTURING GROUP-III NITRIDE SEMICONDUCTOR LAYER, GROUP-III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING GROUP-III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - The present invention provides an apparatus for manufacturing a group-III nitride semiconductor layer having high crystallinity. An embodiment of the present invention provides an apparatus for manufacturing a group-III nitride semiconductor layer on a substrate | 2009-05-07 |
20090114943 | Nitride semiconductor free-standing substrateand device using the same - A nitride semiconductor free-standing substrate includes a surface inclined in a range of 0.03° to 1.0° from a C-plane, and an off-orientation that an angle defined between a C-axis and a tangent at each point on a whole surface of the substrate becomes maximum is displaced in a range of 0.5° to 16° from a particular M-axis orientation of six-fold symmetry M-axis orientations. The substrate does not include a region of −0.5°<φ<+0.5° on the surface, where φ represents a displacement angle of the off-orientation on a surface of the substrate from the particular M-axis orientation. | 2009-05-07 |
20090114944 | Method for Fine Processing of Substrate, Method for Fabrication of Substrate, and Light Emitting Device - The present invention provides a method for fine processing of a substrate, a method for fabrication of a substrate, and a light emitting device. In the method for fine processing of a substrate, after removing a single particle layer from the substrate having the single particle layer, a hole having an inner diameter smaller than a diameter of a particle and centering on a position on the substrate where each particle constructing the single particle layer has been placed is formed by etching. The method for fabrication of a substrateincludesthefollowingsteps (I) to (V) inthisorder:
| 2009-05-07 |
20090114945 | SPINTRONICS COMPONENTS WITHOUT NON-MAGNETIC INTERPLAYERS - A spintronics element comprises two ferromagnetic layers without a non-magnetic interlayer between them. The two ferromagnetic layers may be independently switched by various means such as but not limited to applying one or more external magnetic fields, and/or employing current induced switching, and/or applying optical spin-pumping. | 2009-05-07 |
20090114946 | SEMICONDUCTOR DEVICE HAVING A CONTROL CIRCUIT AND METHOD OF ITS MANUFACTURE - A semiconductor has an IGBT active section and a control circuit section for detecting an IGBT abnormal state. A collector region is formed on the back surface side (i.e., on the IGBT collector side) in a selective manner, namely right under the IGBT active section. | 2009-05-07 |
20090114947 | Semiconductor device and inverter circiut having the same - A semiconductor device includes a semiconductor substrate, an insulated gate transistor formed to the semiconductor substrate, a diode formed to the semiconductor substrate, and a control transistor formed to the semiconductor substrate. A first current terminal of the insulated gate transistor is coupled to a cathode of the diode at a high potential side. A second current terminal of the insulated gate transistor is coupled to an anode of the diode at a low potential side. The control transistor is configured to turn off the insulated gate transistor by reducing a potential of a gate terminal of the insulated gate transistor when the diode conducts an electric current. | 2009-05-07 |
20090114948 | SEMICONDUCTOR DEVICE - To provide a semiconductor device that has a sufficiently low on-resistance and excellent low-capacitance and high-speed characteristics as compared with conventional GaN-based diodes. The semiconductor device includes: a substrate ( | 2009-05-07 |
20090114949 | HIGH-MOBILITY TRENCH MOSFETS - High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility. | 2009-05-07 |
20090114950 | Semiconductor Device and Method of Manufacturing such a Device - The invention relates to a semiconductor device ( | 2009-05-07 |
20090114951 | MEMORY DEVICE - A memory device can be implemented including word lines connected to an array of memory transistors. Each memory transistor is also connected to bit lines and a select transistor. The select transistors each have their sources connected to a conductive source line, by a shunt and the gate of each select transistor is connected to a select line. | 2009-05-07 |
20090114952 | Interconnect Components of a Semiconductor Device - Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off. | 2009-05-07 |
20090114953 | Method For Achieving Uniform Etch Depth Using Ion Implantation And A Timed Etch - A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable. | 2009-05-07 |
20090114954 | Method of Forming a Device by Removing a Conductive Layer of a Wafer - A method of forming a MEMS device provides a wafer having a base with a conductive portion. The wafer also has an intermediate conductive layer. After it provides the wafer, the method adds a diaphragm layer to the wafer. The method removes at least a portion of the intermediate conductive layer to form a cavity between the diaphragm layer and the base. At least a portion of the diaphragm layer is movable relative to the base. After it forms the cavity, the method seals the cavity. | 2009-05-07 |
20090114955 | Method for Fabricating a Fin-Shaped Semiconductor Structure and a Fin-Shaped Semiconductor Structure - A fin-shaped structure is formed from a semiconductor material. The fin-shaped structure is processed to generate a tensile strain within the semiconductor material along a longitudinal direction of the fin. | 2009-05-07 |
20090114956 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a gate insulating film formed over the semiconductor substrate, a gate electrode formed on the gate insulating film, a first semiconductor layer which is embedded into a portion on both sides of the gate electrode in the semiconductor substrate, and which includes Si and a 4B group element other than Si, and a second semiconductor layer which is embedded into the portion on both sides of the gate electrode in the semiconductor substrate, so as to be superposed on the first semiconductor layer, and which includes Si and a 4B group element other than Si, wherein the gate electrode is more separated from an end of the first semiconductor layer than from an end of the second semiconductor layer. | 2009-05-07 |
20090114957 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method thereof that maximizes DC and AC parameter properties of a MOS transistor having a buried channel. The device includes a semiconductor substrate having a device separation film, a gate pattern formed over the semiconductor substrate, a well region formed in the semiconductor substrate, the well region including a first doped region formed at a first predetermined depth, a second doped region formed at a second predetermined depth and a third doped region formed at a third predetermined depth, trenches formed at a source/drain region around the gate pattern, and a source/drain formed in the trenches. In accordance with embodiments, the first predetermined depth is lower than the second and third predetermined depths and the third predetermined depth is greater than the second predetermined depth. | 2009-05-07 |
20090114958 | Wiring Board and Method for manufacturing the Same - A wiring board with an electronic device comprising a plurality of trenches arranged in parallel on a substrate, a common trench communicating the plurality of trenches with each other at one of their ends on the substrate, a metal layer formed at the bottom of the plurality of trenches, and an electrode layer connected with the metal layer and formed on a bottom of the common trench, wherein the electrode layer on the bottom of the common trench constitutes a source electrode or a drain electrode of a field effect transistor, whereby the wiring board and an electronic circuit having a good fine wire pattern and a good narrow gap between the patterns using a coating material can be formed, and a reduction for a cost of an organic thin film electronic device and the electronic circuit can be attained since they can be realized through a development of a printing technique. | 2009-05-07 |
20090114959 | Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors - A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or carbonated silicon is provided over the substrate of the pixel cell to reduce the dark current leakage. | 2009-05-07 |
20090114960 | Image Sensor and a Method for Manufacturing the Same - An image sensor and method for manufacturing the same are provided. According to an embodiment, the image sensor includes a photodiode on a semiconductor substrate according to unit pixels; an insulating layer arranged on the semiconductor substrate; and an inter metal dielectric (IMD) including metal wirings arranged on the insulating layer. A trench is provided through the IMD in a region corresponding to the photodiode for each unit pixel; and a color filter is arranged filling the trench. The color filter can function as a wave guide to improve the photosensitivity of the image sensor. | 2009-05-07 |
20090114961 | Image Sensor - Provided is an image sensor. According to embodiments, the subject image sensor can include a photodiode for converting incident light into electrical signals, a reset transistor for resetting a voltage value of a unit pixel, a drive transistor for providing an output voltage, a select transistor for selecting the unit pixel, a storage capacitor for storing electrons leaking from the photodiode, and a switching transistor for controlling the flow of charge to and from the storage capacitor. The switching transistor can be disposed connected to a node between the photodiode and the reset transistor, and the storage capacitor can be disposed at a side of the switching transistor. | 2009-05-07 |
20090114962 | Image Sensor and Method for Manufacturing Thereof - Disclosed are an image sensor and a method for manufacturing the same. The image sensor can include a first pixel including a first photodiode and a first gate; a second pixel adjacent the first pixel and including a second photodiode and a second gate; and a barrier layer between the first photodiode and the second photodiode. The barrier layer can be formed by implanting ions into a semiconductor substrate at a region between adjacent photodiodes. A shallow trench isolation (STI) can be omitted in the regions between adjacent photodiodes by using the ion-implanted barrier layer to isolate the photodiodes from each other. | 2009-05-07 |
20090114963 | Image Sensor and Method for Manufacturing the Same - An image sensor and a method for manufacturing the same are provided. The image sensor can include a lower interconnection for connecting transistor circuitry provided on a substrate to a photodiode element provided above the transistor circuitry, a lower electrode on the lower interconnection, and the photodiode element including an intrinsic layer and a second conductive type conduction layer. A dielectric can be disposed on the substrate exposing a top surface of the lower interconnection, and. the lower electrode can be disposed on the lower interconnection within the dielectric. The intrinsic layer can be disposed on the lower electrode, and the second conductive type conduction layer can be disposed on the intrinsic layer. | 2009-05-07 |
20090114964 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor includes a first substrate having a lower wiring line and electric circuitry formed therein, a bonding layer formed over the first substrate, a second substrate bonded to the first substrate via the bonding layer, a vertical-type photodiode formed in the second substrate, and a contact plug formed in the photodiode and the bonding layer and electrically connected to the lower wiring line. | 2009-05-07 |
20090114965 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor and a method of manufacturing the same that includes providing a semiconductor substrate having a photodiode, forming a color filter over the photodiode, forming a micro lens over the color filter and then forming at least one metal layer vertically extending through the microlens at an outer edge thereof. | 2009-05-07 |
20090114966 | DRAM DEVICE HAVING A GATE DIELECTRIC LAYER WITH MULTIPLE THICKNESSES - A transistor device employed in a support circuit of a DRAM includes a semiconductor substrate having thereon a gate trench, a recessed gate embedded in the gate trench, a source doping region disposed at one side of the recessed gate, a drain doping region disposed at the other side of the recessed gate, and a gate dielectric layer between the recessed gate and the semiconductor substrate. The gate dielectric layer has at least two thicknesses that render the high-voltage transistor device asymmetric. The thicker gate dielectric layer is between the recessed gate and the drain doping region, while the thinner gate dielectric layer is between the recessed gate and the source doping region. | 2009-05-07 |
20090114967 | TRANSISTORS HAVING A CHANNEL REGION BETWEEN CHANNEL-PORTION HOLES AND METHODS OF FORMING THE SAME - According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved. | 2009-05-07 |
20090114968 | RECESSED-GATE TRANSISTOR DEVICE HAVING A DIELECTRIC LAYER WITH MULTI THICKNESSES AND METHOD OF MAKING THE SAME - A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness. | 2009-05-07 |
20090114969 | Silicon carbide semiconductor device and related manufacturing method - An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p | 2009-05-07 |
20090114970 | EMBEDDED DRAM WITH INCREASED CAPACITANCE AND METHOD OF MANUFACTURING SAME - An embedded DRAM memory device comprising one or more cylinder type cell capacitors. Contact pillars ( | 2009-05-07 |
20090114971 | CMOS EPROM AND EEPROM DEVICES AND PROGRAMMABLE CMOS INVERTERS - A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices. | 2009-05-07 |
20090114972 | Integrated Circuit Embedded With Non-Volatile One-Time-Programmable And Multiple-Time Programmable Memory - A programmable non-volatile device uses a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 2009-05-07 |
20090114973 | METHOD FOR FORMING SELF-ALIGNED CONTACTS AND LOCAL INTERCONNECTS SIMULTANEOUSLY - The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts and the local interconnects to be widened, which makes the patterning of self-aligned contacts and local interconnects easier. The widened minimal distance requirement also allows further memory cell shrinkage. The improved structures of self-aligned contacts and local interconnects also have excellent isolation characteristic. | 2009-05-07 |
20090114974 | Semiconductor device including a plurality of memory cells and method of manufacturing semiconductor device - A semiconductor device includes a semiconductor substrate, a plurality of memory cells, a plurality of bit lines, and a plurality of source lines. The memory cells are located in the semiconductor substrate. Each of the memory cells includes a trench provided in the semiconductor substrate, an oxide layer disposed on a sidewall of the trench, a tunnel oxide layer disposed at a bottom portion of the trench, a floating gate disposed in the trench so as to be surrounded by the oxide layer and the tunnel oxide layer, and an erasing electrode disposed on an opposing side of the tunnel oxide layer from the floating gate. The bit lines and the source lines are alternately arranged on the memory cells in parallel with each other. | 2009-05-07 |
20090114975 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device, which includes a substrate and a sensing memory device. The substrate includes a metal-oxide-semiconductor transistor having a gate. The sensing memory device is disposed on the gate of the metal-oxide-semiconductor transistor and includes followings. The second conductive layer is covering the first conductive layer. The charge trapping layer is disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer has a sensing region therein when charges stored in the charge trapping layer, and the sensing region is adjacent to the charge trapping layer. The first dielectric layer and the second dielectric layer are respectively disposed between the charge trapping layer and the first conductive layer and between the charge trapping layer and the second conductive layer, wherein a third dielectric layer is disposed between the gate and the sensing memory device. | 2009-05-07 |
20090114976 | Programming and Erasing Method for Charge-Trapping Memory Devices - A method for programming and erasing charge-trapping memory device is provided. The method includes applying a first negative voltage to a gate causing a dynamic balance state (RESET\ERASE state). Next, a positive voltage is applied to the gate to program the device. Then, a second negative voltage is applied to the gate to restore the device to the RESET\ERASE state. | 2009-05-07 |
20090114977 | NONVOLATILE MEMORY DEVICE HAVING CHARGE TRAPPING LAYER AND METHOD FOR FABRICATING THE SAME - Disclosed herein is a nonvolatile memory device having a charge trapping layer and a method of making the same. The nonvolatile memory device includes a substrate, a tunneling layer disposed on the substrate, a charge trapping layer disposed on the tunneling layer, a first blocking layer disposed on the charge trapping layer, a second blocking layer disposed on the first blocking layer, and a control gate electrode disposed on the second blocking layer. A first band gap between the first blocking layer and the charge trapping layer is larger than a second band gap between the second blocking layer and the charge trapping layer. | 2009-05-07 |
20090114978 | VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME - A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions. | 2009-05-07 |
20090114979 | FinFET Device with Gate Electrode and Spacers - A semiconductor device includes a source region, a drain region, and a fin that connects the source region to the drain region. A gate electrode having a substantially planar surface overlies the fin and is positioned between the drain region and the source region. A first set of spacers is positioned between a first sidewall of the gate electrode and the source region and between a second sidewall of the gate electrode and the drain region. A second set of spacers is positioned on at least a portion of a top surface of the source region and the drain region and alongside at least a portion of the first set of spacers. At least a portion of sidewalls of the second set of spacers contacts a portion of the first or second sidewall of the gate electrode. | 2009-05-07 |
20090114980 | SEMICONDUCTOR DEVICE HAVING VERTICAL AND HORIZONTAL TYPE GATES AND METHOD FOR FABRICATING THE SAME - A semiconductor device having both vertical and horizontal type gates and a method for fabricating the same for obtaining high integration of the semiconductor device and integration with other devices while also maximizing the breakdown voltage and operational speed and preventing damage to the semiconductor device. | 2009-05-07 |
20090114981 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed. | 2009-05-07 |
20090114982 | Semiconductor device and manufacturing method thereof - A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape. | 2009-05-07 |
20090114983 | Power Transistor Capable of Decreasing Capacitance between Gate and Drain - A power transistor capable of decreasing capacitance between a gate and a drain includes a backside mental layer, a substrate formed on the backside mental layer, a semiconductor layer formed on the substrate, and a frontside mental layer formed on the semiconductor layer. The semiconductor layer comprises a first trench structure comprising a gate oxide layer, a second trench structure comprising a p-well junction formed around a second trench, a p-body region formed outside the first trench structure and the second trench structure, a first n+ source region formed on the p-body region and beside a sidewall of the first trench structure, a second n+ source region formed on the p-body region and between another sidewall of the first trench structure and the second trench structure, and a dielectric layer formed on the first trench structure, the first n+ source region, and the second n+ source region. | 2009-05-07 |
20090114984 | POWER DEVICE AND A METHOD FOR PRODUCING A POWER DEVICE - A power device with improved reliability and a method for producing the same is disclosed. One embodiment provides an active area having an electrical power dissipation characteristic, a metallization layer portion configured with respect to the active area so that the dissipation characteristic of the active area results in heating the metallization layer portion, the metallization layer portion being formed as a connected region. The metallization layer portion has at least one hole, fully extending through the metal layer and having a dielectric. The at least one hole is arranged so that each location of the metal layer portion is connected electrically to each other location via the metallization material of the metal layer portion. | 2009-05-07 |
20090114985 | Semiconductor apparatus and method for manufacturing the same - A semiconductor apparatus is disclosed. The semiconductor apparatus includes a semiconductor substrate that has a first surface and a second surface opposite to each other. The semiconductor apparatus further includes multiple double-sided electrode elements each having a pair of electrodes located respectively on the first and second surfaces of the semiconductor substrate. A current flows between the first and second electrode. Each double-sided electrode element has a PN column region located in the semiconductor substrate. The semiconductor apparatus further includes an insulation trench that surrounds each of multiple double-sided electrode elements, and that insulates and separates the multiple double-sided electrode elements from each other. | 2009-05-07 |
20090114986 | FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT - A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials. | 2009-05-07 |
20090114987 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a semiconductor layer with an impurity of a first conductivity type diffused therein, and a local insulating layer, source layer, and a drain layer formed therein. The drain layer has an impurity of a second conductivity type opposite to the first conductivity type. A gate electrode is formed over the semiconductor layer extending from over the local insulating layer to the source layer. A low-concentration diffusion layer is formed in the semiconductor layer below the drain layer. First and second gate insulating films are formed between the gate electrode and the semiconductor layer, and respectively extending from an end, on the source layer side, of the gate electrode to the local insulating layer without reaching the local insulating layer, and extending from an end on another side of the local insulting layer to the source layer. | 2009-05-07 |
20090114988 | Semiconductor Integrated Circuit Device And Method For Manufacturing Same - A semiconductor integrated circuit device ( | 2009-05-07 |
20090114989 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a semiconductor memory device including a semiconductor substrate; a buried insulation film provided on the semiconductor substrate; a semiconductor layer provided on the buried insulation film; a source layer and a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer, and being in an electrically floating state, the body region accumulating or discharging charges to store data; a gate dielectric film provided on the body region; a gate electrode provided on the gate dielectric film; and a plate electrode facing a side surface of the body region via an insulation film, in an element isolation region. | 2009-05-07 |
20090114990 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device, particularly, a method for manufacturing a high voltage semiconductor device is disclosed. The method includes forming a high voltage gate oxide film on a semiconductor substrate having a high voltage device region and a low voltage device region, forming a gate electrode on the semiconductor substrate having the high voltage gate oxide film, forming a fluorinated silicate glass (FSG) film and a liner film sequentially on an entire surface of the semiconductor substrate including the gate electrode, and forming an interlayer insulating film on the liner film. Thus, it is possible to prevent an increase in leakage current of the high voltage semiconductor device such as a MOS transistor. | 2009-05-07 |
20090114991 | SEMICONDUCTOR DEVICES HAVING A CONTACT STRUCTURE AND METHODS OF FABRICATING THE SAME - A semiconductor device includes an isolation region formed in a semiconductor substrate to define an active region. First and second impurity regions spaced apart from each other are formed in the active region. A gate trench region crosses the active region between the first and second impurity regions and extends to the isolation region. A first contact structure having a sidewall in vertical alignment with a sidewall of the gate trench region adjacent to the first impurity region is provided on the first impurity region. A second contact structure having a sidewall in vertical alignment with a sidewall of the gate trench region adjacent to the second impurity region is provided on the second impurity region. A gate electrode is provided in the gate trench region. A gate dielectric layer is interposed between the gate trench region and the gate electrode. | 2009-05-07 |