18th week of 2010 patent applcation highlights part 54 |
Patent application number | Title | Published |
20100112720 | CONTINUOUSLY REPEATABLE METHOD OF DETECTING ANTIGENS IN TEST VOLUME - A continuously repeatable method of detecting possible presence of one or several different selected target antigen(s), such as explosives and/or narcotics, in a predetermined test volume with a flow-through analysis device, such as a Piezoelectric Quartz Crystal Microbalance device (QCM), an Ellipsometer device or a Surface Plasmon Resonance biosensor device, is described. The device is equipped with one or several fluidly connected, individually operated, flow-through testing cells, each cell containing a sensing surface, each sensing surface comprising a selected modified target antigen immobilized thereon, which modified antigen has weaker affinity than the target antigen for a selected antibody specific for the selected target antigen. One testing cell is for analyzing a target antigen by the competition mode, whereas optional other testing cells are individually selected for analysis by the competition mode or the displacement mode. | 2010-05-06 |
20100112721 | BLOOD BIOMARKERS FOR BONE FRACTURE AND CARTILAGE INJURY - Blood biomarkers are described for use in methods and compositions to determine whether an individual has sustained a bone fracture or a cartilage injury. | 2010-05-06 |
20100112722 | Immunoassays and Characterization of Biomolecular Interactions Using Self-Assembled Monolayers - The present disclosure relates to methods of characterizing protein-protein interaction or conducting immunoassays in a biological sample using self-assembled monolayers (SAMs) and matrix-assisted laser desorption/ionization time of flight mass spectrometry (SAMDI). The biological sample may be obtained from a living subject, such as a human or animal clinical sample containing multiple unknown proteins and/or antigens. Label-free methods of identifying protein-protein interactions, antigen-antibody binding and/or diagnosing a medical condition based on analysis of a biological sample using SAMDI are also provided, as well as biochips comprising surface bound proteins and/or antibodies and methods of making these biochips. The methods and biochips are useful, for example, for identifying protein-protein binding interactions and/or conducting immunoassays in samples such as humoral fluids or other clinical samples, cell lysates, tissue lysates, tumor lysates, and samples obtained, isolated or derived from animals or plants. | 2010-05-06 |
20100112723 | MICROFLUIDIC APPARATUS AND METHODS FOR PERFORMING BLOOD TYPING AND CROSSMATCHING - Microfluidic cartridges for agglutination reactions are provided. The cartridges include a microfluidic reaction channel with at least two intake channels, one for an antigen-containing fluid and the other for an antibody-containing fluid, conjoined to a reaction channel modified by incorporation of a downstream flow control channel. At low Reynolds Number, the two input streams layer one on top of the other in the reaction channel and form a flowing, unmixed horizontally-stratified laminar fluid diffusion (HLFD) interface for an extended duration of reaction. Surprisingly, the design, surface properties, and flow regime of microfluidic circuits of the present invention potentiate detection of antibody mediated agglutination at the stratified interface. Antigen:antibody reactions involving agglutination potentiated by these devices are useful in blood typing, in crossmatching for blood transfusion, and in immunodiagnostic agglutination assays, for example. | 2010-05-06 |
20100112724 | METHOD OF DETERMINATION OF PROTEIN LIGAND BINDING AND OF THE MOST PROBABLE LIGAND POSE IN PROTEIN BINDING SITE - The present invention proposes a method of structural design, search and selection of potential medicinal compounds—ligands, comprising prognostication of the value of the protein ligand binding in terms of the score calculated with the help of the scoring function developed for scoring, and prognostication of the most probable ligand pose in the protein binding site in terms of the score calculated with the help of the scoring function developed for docking (the docking function). It is proposed to use two absolutely different scoring functions for docking and scoring. A special procedure is proposed for the development of docking function. Use of two absolutely different functions in the process of docking and scoring principally distinguishes the proposed method of predicting the binding affinity of ligand-protein interaction from all the known methods and makes it possible to substantially improve the quality of said prediction. | 2010-05-06 |
20100112725 | METHOD TO INCREASE SPECIFICITY AND/OR ACCURACY OF LATERAL FLOW IMMUNOASSAYS - The present invention includes methods and devices for preventing interfering substances from affecting the accuracy of a lateral flow immunoassay. In preferred embodiments, a test strip includes a capturing zone that includes at least one mobile capturing reagent that separates at least one interfering substance from the analyte. The capturing zone is preferably located upstream of the sample application zone. In some embodiments, the reagent/conjugate zone is also located upstream of the sample application zone. The capturing zone may be located upstream, downstream, or overlapping with the reagent/conjugate zone in these embodiments. In other preferred embodiments, one or more mobile capturing reagents are included in the elution medium/running buffer. In yet other embodiments, the capturing reagent is incorporated into a sample collection device of a sample collection system, preferably separate from the chromatographic test strip. A lysis zone is also included in some preferred embodiments. | 2010-05-06 |
20100112726 | RAPID IMMUNOCHROMATOGRAPHIC DETECTION BY AMPLIFICATION OF THE COLLOIDAL GOLD SIGNAL - The present invention relates to a rapid immunochromatographic test device suitable to detect an antibody and/or antigen in a sample, uses of said device for detecting diseases in a sample, a method for the production of said device as well as a kit comprising the device. | 2010-05-06 |
20100112727 | SINGLE MOLECULE ASSAYS - The present invention provides single molecule analyses of species of use in analytical, diagnostic or prognostic assays. In exemplary embodiments, the assays utilize samples prepared by novel methods, affording assays of unexpected sensitivity and robustness. The method is described in a non-limiting manner by reference to cytokine assays. | 2010-05-06 |
20100112728 | METHODS FOR STRIPPING MATERIAL FOR WAFER RECLAMATION - Removal compositions and processes for removing at least one material layer from a rejected microelectronic device structure having same thereon. The removal composition includes hydrofluoric acid. The composition achieves substantial removal of the material(s) to be removed while not damaging the layers to be retained, for reclaiming, reworking, recycling and/or reuse of said structure. | 2010-05-06 |
20100112729 | CONTACT PATTERNING METHOD WITH TRANSITION ETCH FEEDBACK - A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole. | 2010-05-06 |
20100112730 | OPTICAL INSPECTION METHODS - Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present. | 2010-05-06 |
20100112731 | ELECTRIC DEVICE HAVING NANOWIRES, MANUFACTURING METHOD THEREOF, AND ELECTRIC DEVICE ASSEMBLY - An electric device having a plurality of nanowires, in which at least one of the nanowires is cut or changed in its electric characteristics so as to have a desired characteristic value of the electric device. | 2010-05-06 |
20100112732 | NOVEL PROCESS FOR CONTROLLING SHALLOW TRENCH ISOLATION STEP HEIGHT - A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time. | 2010-05-06 |
20100112733 | MEASURING DEVICE, EXPOSURE APPARATUS, AND DEVICE MANUFACTURING METHOD - A measuring device configured to measure a wave aberration of an optical system to be measured includes a reflection optical element for reflecting light, having passed through a mask and the optical system to be measured, into the optical system to be measured, and a detector for detecting an interference fringe of light having passed through pinholes and openings. The mask has at least three pinhole-opening pairs, each including one pinhole and one opening having a larger diameter than the pinhole that are arranged point-symmetrically, the three pinhole-opening pairs having the common center of symmetry. The light to be measured formed in two of the three pairs is made to interfere with the reference light formed in the remaining pair, or, the light to be measured formed in one of the three pairs is made to interfere with the reference light formed in the other two pairs. | 2010-05-06 |
20100112734 | APPARATUS AND METHOD FOR MANUFACTURING LED DEVICE - A method for manufacturing an LED device, includes: mounting an LED chip, which emits a first light, on a bottom surface of a recess formed in an upper surface of a package, pouring a resin liquid containing phosphor particles, which emits a second light upon incidence of the first light, into the recess, fixing the package to a package fixing plate of an apparatus of the LED device, precipitating the phosphor particles in the resin liquid with a centrifugal force applying to the package in a direction from the upper surface to the lower surface of the package by rotating a rotary member with a rotary driving unit, and curing the resin liquid. | 2010-05-06 |
20100112735 | CHIP COATED LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - A chip coated LED package and a manufacturing method thereof. The chip coated LED package includes a light emitting chip composed of a chip die-attached on a submount and a resin layer uniformly covering an outer surface of the chip die. The chip coated LED package also includes an electrode part electrically connected by metal wires with at least one bump ball exposed through an upper surface of the resin layer. The chip coated LED package further includes a package body having the electrode part and the light emitting chip mounted thereon. The invention improves light efficiency by preventing difference in color temperature according to irradiation angles, increases a yield, miniaturizes the package, and accommodates mass production. | 2010-05-06 |
20100112736 | FULL COLOR DISPLAY - A full color display comprising a red, a green, and a blue light emitting diode, each light emitting diode including a light emitting region having at least one layer of single crystal rare earth material, the rare earth material in each of the light emitting diodes having at least one radiative transition, and the rare earth material producing a radiation wavelength of approximately 640 nm in the red light emitting diode, 540 nm in the green light emitting diode, and 460 nm in the blue light emitting diode. Generally, the color of each LED is determined by selecting a rare earth with a radiative transition producing a radiation wavelength at the selected color. In cases where the rare earth has more than one radiative transition, tuned mirrors can be used to select the desired color. | 2010-05-06 |
20100112737 | METHOD FOR FORMING PIXEL STRUCTURE OF TRANSFLECTIVE LIQUID CRYSTAL DISPLAY DEVICE - A forming method of the present invention includes forming a first patterned conductive layer, which includes a transparent conductive layer and a metal layer stacked together on a substrate, where the first patterned conductive layer functions as gate lines, gate electrodes, common lines and predetermined transparent pixel electrode structures; and forming a second patterned conductive layer on the substrate. The second patterned conductive layer includes data lines and reflective pixel electrodes, and be directly connected to doping regions, such as source regions/drain regions. According to the forming method of the present invention, pixel structures of a transflective liquid crystal display device can be formed through five mask processes. Therefore, the manufacturing process of the transflective liquid crystal display device is effectively simplified, so the product yield is improved and the cost can be reduced. | 2010-05-06 |
20100112738 | FFS MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A liquid crystal display device and method of fabricating the device where the device can control a viewing angle in all directions without forming a white pixel. The liquid crystal display device includes a display control region that is controlled such that liquid crystal molecules are inclined and a viewing-angle control region that is controlled such that liquid crystal molecules are aligned in a horizontal or vertical direction, where a control voltage is supplied through a viewing angle control line independent of a common line for the display control region. | 2010-05-06 |
20100112739 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A liquid crystal display device includes a first substrate and a second substrate facing each other, column spacers at designated areas of the second substrate, protrusions having a first height on the first substrate corresponding to portions of the column spacers, compensation patterns having a second height on the first substrate corresponding to the edges of the column spacers, the second height being lower than the first height, and a liquid crystal layer filling a gap between the first and second substrates. | 2010-05-06 |
20100112740 | SUBSTRATE FOR LIQUID CRYSTAL DISPLAY - A method of manufacturing a substrate for a liquid crystal display. The method includes forming a plurality of first line-shaped fine grooves parallel to each other in a lengthwise direction and a plurality of second line-shaped fine grooves parallel to each other in a width direction on the substrate, forming an inorganic insulating film on the substrate including the first and second line-shaped fine grooves, forming a plurality of gate lines within the first line-shaped fine grooves, forming a plurality of data lines that contacts an upper surface of the inorganic insulating film within the second line-shaped fine grooves, and forming a passivation layer on the substrate including the data lines. | 2010-05-06 |
20100112741 | INTEGRATED PHOTONIC SEMICONDUCTOR DEVICES AND METHODS FOR MAKING INTEGRATED PHOTONIC SEMICONDUCTOR DEVICES - A photonic semiconductor device and method are provided that ensure that the surface of the device upon completion of the SAG process is planar, or at least substantially planar, such that performance of the subsequent processes is facilitated, thereby enabling higher manufacturing yield to be achieved. A photonic semiconductor device and method are also provided that ensure that the isolation region of the device will have high resistance and low capacitance, without requiring the placement of a thick dielectric material beneath each of the contact pads. Eliminating the need to place thick dielectric materials underneath the contact pads eliminates the risk that the contact pads will peel away from the assembly. | 2010-05-06 |
20100112742 | Nitride semiconductor device and method for making same - A method of forming a nitride semiconductor device is disclosed. An n-type GaN layer is formed on a substrate. A self assembled nitride semiconductor quantum dot layer is formed on the n-type GaN layer by growing In | 2010-05-06 |
20100112743 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING VIBRATOR WHICH IS PROVIDED WITH SIDE INSULATING FILM AND INSULATING SEPARATION REGION FORMED BY THERMAL OXIDATION - A method of manufacturing a semiconductor device includes partially etching the upper surface of the semiconductor substrate to form side grooves and expose side surfaces of the vibrators, partially etching the upper surface of the semiconductor substrate to form separation grooves where insulating separation regions between the vibrators and the semiconductor substrate are to be formed, thermally oxidizing surfaces of the separation grooves to form the insulating separation region composed of oxidized films filled in the separation grooves, thermally oxidizing the side surfaces of the vibrators to form side insulating film, and performing release etching of the semiconductor substrate using the side insulating film as a mask to expose bottom surfaces of the vibrators and form the vibrators arranged in the recess formed in the semiconductor substrate. | 2010-05-06 |
20100112744 | Silicon Production with a Fluidized Bed Reactor Utilizing Tetrachlorosilane to Reduce Wall Deposition - Silicon deposits are suppressed at the wall of a fluidized bed reactor by a process in which an etching gas is fed near the wall of the reactor. The etching gas includes tetrachlorosilane. A Siemens reactor may be integrated into the process such that the vent gas from the Siemens reactor is used to form a feed gas and/or etching gas fed to the fluidized bed reactor. | 2010-05-06 |
20100112745 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - Provided is an image sensor. The image sensor can include a first substrate comprising a pixel portion in which a readout circuitry is provided and a peripheral portion in which a peripheral circuitry is provided. An interlayer dielectric including lines can be formed on the first substrate to connect with the readout circuitry and the peripheral circuitry. A crystalline semiconductor layer can be provided on a portion of the interlayer dielectric corresponding to the pixel portion through a bonding process. The crystalline semiconductor layer can include a first photodiode and second photodiode. The first and second photodiodes can be defined by device isolation trenches in the crystalline semiconductor layer. A device isolation layer can be formed on the crystalline semiconductor layer comprising the device isolation trenches. An upper electrode layer passes through the device isolation layer to connect with a portion of the first photodiode. An expose portion can be formed in the upper electrode layer to selectively expose an upper region of the first photodiode. A passivation layer can be formed on the first substrate on which the expose portion is provided. | 2010-05-06 |
20100112746 | PHOTOELECTRIC SENSOR HOUSING ASSEMBLING METHOD AND PHOTOELECTRIC SENSOR - A housing assembly method for bonding through causing a first member and a second member, which form a tightly sealed housing that contains a sensing element, to be mutually abutting. A first resin material through which a laser beam passes is used as the first member and a second resin material that absorbs the laser beam is used as the member of the second piece. With the bonding surfaces of these members abutting each other, a laser beam having a diameter that is smaller than the width of the bonding surfaces is directed towards the bonding surfaces from the member of the first piece side to weld the bonding surfaces together while leaving non-welded portions between the abutting bonding surfaces. | 2010-05-06 |
20100112747 | METHOD OF MAKING A SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes the following elements. A photoelectric conversion section is arranged in a semiconductor layer having a first surface through which light enters the photoelectric conversion section. A signal circuit section is arranged in a second surface of the semiconductor layer opposite to the first surface. The signal circuit section processes signal charge obtained by photoelectric conversion by the photoelectric conversion section. A reflective layer is arranged on the second surface of the semiconductor layer opposite to the first surface. The reflective layer reflects light transmitted through the photoelectric conversion section back thereto. The reflective layer is composed of a single tungsten layer or a laminate containing a tungsten layer. | 2010-05-06 |
20100112748 | METHODS FOR FORMING NANOSTRUCTURES AND PHOTOVOLTAIC CELLS IMPLEMENTING SAME - A method for forming a nanostructure according to one embodiment includes creating a hole in an insulating layer positioned over an electrically conductive layer; and forming a nanocable in the hole such that the nanocable extends through the hole in the insulating layer and protrudes therefrom, the nanocable being in communication with the electrically conductive layer. Additional systems and methods are also presented. | 2010-05-06 |
20100112749 | POLYSILAZANE, METHOD OF SYNTHESIZING POLYSILAZANE, COMPOSITION FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE COMPOSITION - Disclosed are polysilazane, a method of synthesizing the polysilazane, a composition for manufacturing a semiconductor device, and a method of manufacturing a semiconductor device using the composition. The polysilazane is synthesized through a reaction, under a catalyst, between dichlorosilane, trichlorosilane, and ammonia added in a reaction solvent as a reactant. In this instance, a polystyrene conversion weight average molecular weight of the polysilazane is about 2,000 to 30,000. | 2010-05-06 |
20100112750 | Post-Processing Treatment of Conductive Polymers to Enhance Electrical Conductivity - A method for enhancing electrical conductivity of a film which includes at least one conductive polymer. The method includes providing the film comprising the at least one conductive polymer and at least one polymer acid, agitating the film in at least one reagent; and, placing the film on a heated surface. The at least one reagent includes a reagent acid that is stronger than the polymer acid. The conductivity of the treated film is significantly greater than the conductivity of the untreated film. | 2010-05-06 |
20100112751 | ORGANIC DIODES AND MATERIALS - Diodes having p-type and n-type regions in contact, having at least one of either the p-type region or n-type region including a conjugated organic material doped with an immobile dopant, conjugated organic materials for incorporation into such diodes, and methods of manufacturing such diodes and materials are provided. | 2010-05-06 |
20100112752 | Method of manufacturing a variable resistance structure and method of manufacturing a phase-change memory device using the same - In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer. | 2010-05-06 |
20100112753 | SEMICONDUCTOR MEMORY DEVICE - A method includes forming a switching device which includes a vertical channel spaced apart from a semiconductor substrate, and forming a storage device which is positioned on opposed sides of the switching device. The storage device includes a cylindrically shaped storage node, a plate electrode coupled to the storage node, and a dielectric film which is formed between the storage node and plate electrode, the storage nodes being electrically connected to the switching device. | 2010-05-06 |
20100112754 | METHODS FOR SECURING SEMICONDUCTOR DEVICES USING ELONGATED FASTENERS - Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion extending continuously through an aperture in two or more such elements. Computer systems include such semiconductor device assemblies. Fasteners for securing together such elements include an elongated portion, a first end piece, and a second end piece. Methods of securing together a plurality of semiconductor devices include inserting an elongated portion of a fastener through an aperture in a first semiconductor device and an aperture in at least one additional semiconductor device. Circuit boards include a plurality of apertures disposed in an array corresponding to an array of apertures in a semiconductor device assembly. Each aperture is sized and configured to receive a fastener for maintaining an assembled relationship between the semiconductor device assembly and the circuit board. | 2010-05-06 |
20100112755 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR CHIPS STACKED AND MOUNTED THEREON AND MANUFACTURING METHOD THEREOF - Chips are stacked and mounted on a circuit board having external connection electrodes and mounted thereon by wire bonding. At least one of the chips stacked on the chip includes overhung portions each of which has a start point inside bonding pads, is made thinner in a direction towards the outer periphery to an end point reaching the side wall and forms a space used to accommodate ball bonding portions between the overhung portion and the main surface of the chip arranged in the lower stage on a backside corresponding in position to the bonding pads, and insulating members formed to cover the overhung portions and prevent bonding wires of the chip arranged in the lower stage from being brought into contact with the upper-stage chip. | 2010-05-06 |
20100112756 | INTEGRATED CIRCUIT PACKAGE FORMATION - Integrated circuit packages are formed from a panel where the panel is separated by laser cutting the panel. In some embodiments, the panel is attached to the carrier for the formation of interconnect layers on the panel. Afterwards, the panel is cut with a laser while on the carrier to separate the integrated circuit packages. A tape or other type of structure may be attached to the top of the packages after the laser cutting. The integrated circuit packages are removed from the carrier by releasing the adhesive and removing the integrated circuit packages with the tape. The packages are then removed from the tape. | 2010-05-06 |
20100112757 | ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate. | 2010-05-06 |
20100112758 | CONNECTING MICROSIZED DEVICES USING ABLATIVE FILMS - A method of providing connectivity to a microsized device, the method includes the steps of providing an ablative base material having at least a top surface; providing a die having a first and second surface and having bonding pads at least upon the first surface; placing the die with the at least first surface of the die contacting the at least first surface of the ablative base material; and ablating a channel in the ablative material proximate to the die. | 2010-05-06 |
20100112759 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE EMBEDDED SUBSTRATE - A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a third insulating layer on a surface of each of the semiconductor device and the second insulating layer; a sixth step of mounting a wiring substrate on a surface of each of the semiconductor device and the second insulating layer; a seventh step of forming a via-hole in the second insulating layer and the third insulating layer; and an eighth step of forming a second wiring pattern on a surface of each of the first insulating layer and the second insulating layer. | 2010-05-06 |
20100112760 | SEMICONDUCTOR MODULE INCLUDING CIRCUIT COMPONENT AND DIELECTRIC FILM, MANUFACTURING METHOD THEREOF, AND APPLICATION THEREOF - Multiple semiconductor device components and passive device components fixed to a substrate are embedded within an electroconductive-film/insulating-resin-film structure, and are thermally bonded to an insulating resin film. | 2010-05-06 |
20100112761 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - A semiconductor device is disclosed wherein first wiring lines in a first row extend respectively from first connecting portions toward one side of a semiconductor chip, while second wiring lines extend respectively from second connecting portions toward the side opposite to the one side of the semiconductor chip. The reduction in size of the semiconductor device can be attained. | 2010-05-06 |
20100112762 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES - Methods of fabricating a semiconductor structure with a non- epitaxial thin film disposed on a surface of a substrate of the semiconductor structure are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings. | 2010-05-06 |
20100112763 | Semiconductor device including gate stack formed on inclined surface and method of fabricating the same - A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface. A gate stack structure is formed on the inclined surface and includes a gate electrode. A first impurity region formed on one of the first and second upper surfaces contacts the gate stack structure. A second impurity region formed on the second upper surface contacts the gate stack structure. A channel between the first and second impurity regions is formed along the inclined surface in a crystalline direction. | 2010-05-06 |
20100112764 | Use of Poly Resistor Implant to Dope Poly Gates - A process of fabricating an IC is disclosed in which a polysilicon resistor and a gate region of an MOS transistor are implanted concurrently. The concurrent implantation may be used to reduce steps in the fabrication sequence of the IC. The concurrent implantation may also be used to provide another species of transistor in the IC with enhanced performance. Narrow PMOS transistor gates may be implanted concurrently with p-type polysilicon resistors to increase on-state drive current. PMOS transistor gates over thick gate dielectrics may be implanted concurrently with p-type polysilicon resistors to reduce gate depletion. NMOS transistor gates may be implanted concurrently with n-type polysilicon resistors to reduce gate depletion, and may be implanted concurrently with p-type polysilicon resistors to provide high threshold NMOS transistors in the IC. | 2010-05-06 |
20100112765 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed. | 2010-05-06 |
20100112766 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions. | 2010-05-06 |
20100112767 | Method of Manufacturing a Trench Transistor Having a Heavy Body Region - A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body. | 2010-05-06 |
20100112768 | METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR DEVICES - A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate. | 2010-05-06 |
20100112769 | VERTICAL-TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel. | 2010-05-06 |
20100112770 | Semiconductor device and method of manufacturing semiconductor device - The invention provides a method of manufacturing a semiconductor device including a non-volatile memory with high yield, and a semiconductor device manufactured by the method. A method of manufacturing a semiconductor device includes a process of forming a second side wall such that the width of the second side wall, which is formed on the side of a portion of a second gate electrode that does not face dummy gates on a drain forming region side, in a gate length direction is larger than that of the second side wall, which is formed on the side of the second gate electrode on a source forming region side, in the gate length direction, in a non-volatile memory forming region. | 2010-05-06 |
20100112771 | Method of fabricating Schottky barrier transistor - Provided is a method of fabricating a Schottky barrier transistor. The method includes (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate; | 2010-05-06 |
20100112772 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers. | 2010-05-06 |
20100112773 | PIXEL STRUCTURE AND METHOD FOR FORMING THE SAME - A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on a part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on a part of the passivation layer and is electrically connected to the transistor through the second opening. The first storage capacitor is formed by the third conductive layer, the passivation layer, and the second conductive layer. | 2010-05-06 |
20100112774 | Variable Resistance Memory Device and Methods of Forming the Same - A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern. | 2010-05-06 |
20100112775 | PLATING METHOD, SEMICONDUCTOR DEVICE FABRICATION METHOD AND CIRCUIT BOARD FABRICATION METHOD - The plating method comprises the step of forming a resin layer | 2010-05-06 |
20100112776 | APPARATUS FOR FORMING CONDUCTOR, METHOD FOR FORMING CONDUCTOR, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A conductor forming apparatus includes a reaction container having housed therein a processing target on a surface of which a recess in which a conductor is to be provided is formed, and a process for providing the conductor in the recess being carried out inside the container after a supercritical fluid dissolved with a metal compound is supplied into the container, a supply device which supplies the fluid from an outside to the inside of the container, and a discharge device which discharges the fluid that is not submitted for the process from the inside to the outside of the container, wherein while an amount of the fluid in the container is adjusted by continuously supplying the fluid into the container by the supply device and continuously discharging the fluid that is not submitted for the process to the outside of the container by the discharge device. | 2010-05-06 |
20100112777 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes forming a bottom electrode having a top surface and a side surface on a semiconductor substrate, performing a tilted ion implantation process to supply ions to the top surface of the bottom electrode and to a portion of the side surface of the bottom electrode, and forming a dielectric layer on the bottom electrode. The formation of the dielectric layer is delayed at the ion-supplied top surface of the bottom electrode and the ion-supplied portion of the side surface of the bottom electrode. | 2010-05-06 |
20100112778 | NANOSCALE FLOATING GATE AND METHODS OF FORMATION - A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer. | 2010-05-06 |
20100112779 | METHOD AND APPARATUS FOR INDICATING DIRECTIONALITY IN INTEGRATED CIRCUIT MANUFACTURING - An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit. | 2010-05-06 |
20100112780 | Microwave-Induced Ion Cleaving and Patternless Transfer of Semiconductor Films - A method of ion cleaving using microwave radiation is described. The method includes using microwave radiation to induce exfoliation of a semiconductor layer from a donor substrate. The donor substrate may be implanted, bonded to a carrier substrate, and heated via the microwave radiation. The implanted portion of the donor substrate may include increased damage and/or dipoles (relative to non-implanted portions of the donor substrate), which more readily absorb microwave radiation. Consequently, by using microwave radiation, an exfoliation time may be reduced to 12 seconds or less. In addition, a presented method also includes the use of focused ion beam implantation to achieve a pattern-less transfer of a semiconductor layer onto a carrier substrate. | 2010-05-06 |
20100112781 | METHOD FOR MANUFACTURING SOI WAFER - The present invention provides a method for manufacturing an SOI wafer, including: a step of preparing a base wafer consisting of a p | 2010-05-06 |
20100112782 | METHOD FOR REDUCING THE THICKNESS OF SUBSTRATES - The current invention presents a method for thinning wafers. The method uses a two-step process, whereby first the carrier wafer ( | 2010-05-06 |
20100112783 | ADHESIVE FILM FOR SEMICONDUCTOR, COMPOSITE SHEET, AND METHOD FOR PRODUCING SEMICONDUCTOR CHIP USING THEM - There is provided an adhesive film for a semiconductor, which can be attached to a semiconductor wafer at low temperature and which allows semiconductor chips to be obtained at high yield from the semiconductor wafer while sufficiently inhibiting generation of chip cracks and burrs. The adhesive film for a semiconductor comprises a polyimide resin that can be obtained by reaction between a tetracarboxylic dianhydride containing 4,4′-oxydiphthalic dianhydride represented by chemical formula (I) below and a diamine containing a siloxanediamine represented by the following general formula (II) below, and that can be attached to a semiconductor wafer at 100° C. or below. | 2010-05-06 |
20100112784 | LARGE AREA SEMICONDUCTOR ON GLASS INSULATOR - Methods and apparatus provide for contacting respective first surfaces of a plurality of donor semiconductor wafers with a glass substrate; bonding the first surfaces of the plurality of donor semiconductor wafers to the glass substrate using electrolysis; separating the plurality of donor semiconductor wafers from the glass substrate leaving respective exfoliation layers bonded to the glass substrate; and depositing a further semiconductor layer on exposed surfaces of the exfoliation layers to augment a thickness of the exfoliation layers. | 2010-05-06 |
20100112785 | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation - Methods and apparatus provide for forming a semiconductor-on-insulator (SOI) structure, including subjecting a implantation surface of a donor semiconductor wafer to an ion implantation step to create a weakened slice in cross-section defining an exfoliation layer of the donor semiconductor wafer; and subjecting the donor semiconductor wafer to a spatial variation step, either before, during or after the ion implantation step, such that at least one parameter of the weakened slice varies spatially across the weakened slice in at least one of X- and Y-axial directions. | 2010-05-06 |
20100112786 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor substrate has a plurality of semiconductor chip forming areas and scribe areas including substrate cutting positions arranged between the plurality of semiconductor chip forming areas. An insulating layer having first opening portions, which expose all or a part of the scribe areas respectively, is formed on the semiconductor substrate. A solder resist layer having second opening portions, which expose all or a part of the scribe areas respectively, is formed on the insulating layer. Portions of the semiconductor substrate corresponding to the substrate cutting positions are cut. | 2010-05-06 |
20100112787 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes preparing a substrate having a front surface where a circuit pattern is formed and a back surface opposite to the front surface, reading information of the circuit pattern formed at the front surface of the substrate over the back surface through the substrate by an image pickup member, forming a cutting part at the back surface of the substrate, grinding the back surface to form a portion of the cutting part as a dicing line, attaching an expanding tape to the back surface where the dicing line is formed, and expanding the expanding tape to separate the substrate into a plurality of chips along the dicing line. | 2010-05-06 |
20100112788 | METHOD TO REDUCE SURFACE DAMAGE AND DEFECTS - A method of implantation that minimizes surface damage to a workpiece is disclosed. In one embodiment, following a doping implant, a second implant is performed which causes the silicon at the surface of the workpiece to become amorphous. This reduces surface damage and interstitials, which has several benefits. First, inactive dopant clusters may become activated due to the replenishment of silicon. Secondly, the amorphous nature of the silicon makes it bond more easily in subsequent process steps, such as silicidation. | 2010-05-06 |
20100112789 | Method for Producing Semiconductor Chips using Thin Film Technology - For semiconductor chips using thin film technology, an active layer sequence is applied to a growth substrate, on which a reflective electrically conductive contact material layer is then formed. The active layer sequence is patterned to form active layer stacks, and reflective electrically conductive contact material layer is patterned to be located on each active layer stack. Then, a flexible, electrically conductive foil is applied to the contact material layers as an auxiliary carrier layer, and the growth substrate is removed. | 2010-05-06 |
20100112790 | METHOD OF MANUFACTURING SEMICONDUCTOR THIN FILM AND SEMICONDUCTOR DEVICE - On a translucent substrate, an insulating film having a refractive index n and an amorphous silicon film are deposited successively. By irradiating the amorphous silicon film with a laser beam having a beam shape of a band shape extending along a length direction with a wavelength λ, a plurality of times from a side of amorphous silicon film facing the insulating film, while an irradiation position of the laser beam is shifted each of the plurality of times in a width direction of the band shape by a distance smaller than a width dimension of the band shape, a polycrystalline silicon film is formed from the amorphous silicon film. Forming the polycrystalline silicon film forms crystal grain boundaries which extend in the width direction and are disposed at a mean spacing measured along the length direction and ranging from (λ/n)×0.95 to (λ/n)×1.05 inclusive, and crystal grain boundaries which, in a region between crystal grain boundaries adjacent to each other and extending in the width direction, extend in the length direction and are disposed at a mean spacing measured along the width direction and ranging from (λ/n)×0.95 to (λ/n)×1.05 inclusive. | 2010-05-06 |
20100112791 | METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE - A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer. | 2010-05-06 |
20100112792 | THICK EPITAXIAL SILICON BY GRAIN REORIENTATION ANNEALING AND APPLICATIONS THEREOF - The invention provides a high temperature (about 1150° C. or greater) annealing process for converting thick polycrystalline Si layers on the order of 1 μm to 40 μm on a single crystal seed layer into thick single crystal Si layers having the orientation of the seed layer, thus allowing production of thick Si films having the quality of single crystal silicon at high rates and low cost of processing. Methods of integrating such high temperature processing into solar cell fabrication are described, with particular attention to process flows in which the seed layer is disposed on a porous silicon release layer. Another aspect pertains to the use of similar high temperature anneals for poly-Si grain growth and grain boundary passivation. A further aspect relates to structures in which these thick single crystal Si films and passivated poly-Si films are incorporated. | 2010-05-06 |
20100112793 | CONFORMAL DOPING IN P3I CHAMBER - Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting ions into a substrate includes providing a substrate into a processing chamber, the substrate comprising substrate surface having one or more features formed therein and each feature having one or more horizontal surfaces and one or more vertical surfaces, generating a plasma from a gas mixture including a reacting gas adapted to produce ions, depositing a material layer on the substrate surface and on at least one horizontal surface of the substrate feature, implanting ions from the plasma into the substrate by an isotropic process into at least one horizontal surface and into at least one vertical surface, and etching the material layer on the substrate surface and the at least one horizontal surface by an anisotropic process. | 2010-05-06 |
20100112794 | DOPING PROFILE MODIFICATION IN P3I PROCESS - Methods for implanting material into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting material into a substrate includes providing a substrate into a processing chamber, the substrate comprising a substrate surface having a material layer formed thereon, generating a first plasma of a non-dopant processing gas, exposing the material layer to the plasma of the non-dopant processing gas, generating a second plasma of a dopant processing gas including a reacting gas adapted to produce dopant ions, and implanting dopant ions from the plasma into the material layer. The method may further include a cleaning or etch process. | 2010-05-06 |
20100112795 | METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS FOR SEMICONDUCTOR DEVICES - A first method for producing a doped region in a semiconductor substrate includes performing a first implant step in which a carborane cluster molecule is implanted into a semiconductor substrate to form a doped region. A second method for producing a semiconductor device having a shallow junction region includes providing a first gas and a second gas in a container. The first gas includes a first dopant and the second gas includes a second dopant. The second method also includes implanting the first and second dopants into a semiconductor substrate using an ion. The ion source is not turned off between the steps of implanting the first dopant and implanting the second dopant. | 2010-05-06 |
20100112796 | PATTERNING METHOD - Disclosed is a patterning method including: forming, on a thin film, a sacrificial film made of a material different from that of the thin film and made of SiBN; processing the sacrificial film into a pattern having a preset interval by using a photolithography technique; forming, on sidewalls of the processed sacrificial film, sidewall spacers made of a material different from those of the sacrificial film and the thin film; removing the processed sacrificial film; and processing the thin film by using the sidewall spacers as a mask. | 2010-05-06 |
20100112797 | METHOD FOR FORMING A MEMORY ARRAY - The invention is directed to a method for forming a memory array. The method comprises steps of providing a substrate having a charge trapping structure formed thereon. A patterned material layer is formed over the substrate and the patterned material layer having a plurality of trenches expose a portion of the charge trapping structure. Furthermore, a plurality of conductive spacers are formed on the sidewalls of the trenches of the patterned material layer respectively and a portion of the charge trapping structure at the bottom of the trenches is exposed by the conductive spacers. An insulating layer is formed over the substrate to fill up the trenches of the patterned material layer. Moreover, a planarization process is performed to remove a portion of the insulating layer until a top surface of the patterned material layer and a top surface of each of the conductive spacers are exposed. | 2010-05-06 |
20100112798 | METHOD FOR GAP FILLING IN A GATE LAST PROCESS - A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures. | 2010-05-06 |
20100112799 | Method of Manufacturing Flash Memory Device - A method of manufacturing a flash memory device according to an embodiment includes forming a second oxide layer pattern having a mask pattern buried therein on a first nitride layer pattern and a first oxide layer stack on a semiconductor substrate; forming first polysilicon patterns at sidewalls of the buried mask pattern; removing portions of the first oxide layer, the first nitride layer pattern, and the second oxide layer pattern to form a third oxide layer pattern, a second nitride layer pattern, and a fourth oxide layer pattern at lower portions of the first polysilicon patterns and the mask pattern; forming a fifth oxide layer pattern surrounding each of the first polysilicon patterns; forming second polysilicon patterns on sidewalls of the fifth oxide layer pattern; and removing the mask pattern and parts of the third oxide layer pattern and the second nitride layer pattern between the first polysilicon patterns. | 2010-05-06 |
20100112800 | CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS - Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates. | 2010-05-06 |
20100112801 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device is disclosed which comprises forming a gate structure on a major surface of a semiconductor substrate with a gate insulating film interposed therebetween, forming a first insulating film to cover top and side surfaces of the gate structure and the major surface of the semiconductor substrate, reforming portions of the first insulating film which cover the top surface of the gate structure and the major surface of the semiconductor substrate by an anisotropic plasma process using a gas not containing fluorine, and removing the reformed portions of the first insulating film. | 2010-05-06 |
20100112802 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE EMBEDDED SUBSTRATE - A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of preparing a support body, and arranging the semiconductor device on one surface of the support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a first wiring pattern on a surface of each of the first insulating layer and the second insulating layer; a sixth step of forming a via-hole from which the first wiring pattern is exposed on the second insulating layer; and a seventh step of forming a second wiring pattern electrically connected on a surface of the second insulating layer. | 2010-05-06 |
20100112803 | Methods of Forming Integrated Circuit Devices Using Contact Hole Spacers to Improve Contact Isolation - Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material. This sequential etching of the first material at a faster rate than the second material may yield a contact hole having a recessed sidewall. | 2010-05-06 |
20100112804 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE EMBEDDED SUBSTRATE - A manufacturing method for a semiconductor device embedded substrate, includes: a first step including: a step of forming a connection terminal on an electrode pad formed on a semiconductor integrated circuit, a step of forming a first insulating layer on the semiconductor integrated circuit, a step of providing a plate-like body on the first insulating layer, a step of exposing a part of the connection terminal, and a step of removing the plate-like body to manufacture a semiconductor device; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; and a fifth step of forming a first wiring pattern electrically connected to the exposed portion on a surface of each of the first insulating layer and the second insulating layer. | 2010-05-06 |
20100112805 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer. | 2010-05-06 |
20100112806 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR MANUFACTURING APPARATUS AND STORAGE MEDIUM - A seed layer is formed on a surface of an insulating film and along a recess of the insulating film, and after a copper wiring is buried in the recess, a barrier film is formed, and an excessive metal is removed from the wiring. On a surface of a copper lower layer conductive path exposed at the bottom of the recess, a natural oxide of the copper is reduced or removed. On a substrate from which the natural oxide is reduced or removed, the seed layer, composed of a self-forming barrier metal having oxidative tendency higher than that of copper or an alloy of such metal and copper, is formed. The substrate is heated after burying copper in the recess. Thus, a barrier layer is formed by oxidizing the self-forming barrier metal. An excessive portion of the self-forming barrier metal is deposited on a surface of the buried copper. | 2010-05-06 |
20100112807 | METHOD OF FORMING METAL WIRING OF SEMICONDUCTOR DEVICE - A method of forming a metal wiring of a semiconductor device, and devices thereof. A method of forming a metal wiring, and devices thereof, may maximize semiconductor yield by substantially removing oxide on and/or over a trench and/or by substantially removing a by-product that may remain on and/or over a surface of a wafer. A method of forming a metal wiring of a semiconductor may include forming a dielectric layer on and/or over a metal wiring. A method of forming a metal wiring of a semiconductor may include forming a contact hole, which may expose a partial surface of metal wiring, on and/or over a dielectric layer. A method of forming a metal wiring of a semiconductor may include performing an oxide removing process on and/or over an inner side of a contact hole, and/or performing a by-product removing process on and/or over an inner side wall of a trench. | 2010-05-06 |
20100112808 | Methods Of Forming A Plurality Of Transistor Gates, And Methods Of Forming A Plurality Of Transistor Gates Having At Least Two Different Work Functions - A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width being narrower than the second width. A material is deposited over the substrate including over the first and second gates. Within an etch chamber, the material is etched from over both the first and second gates to expose conductive material of the first gate and to reduce thickness of the material received over the second gate yet leave the second gate covered by the material. In situ within the etch chamber after the etching, the substrate is subjected to a plasma comprising a metal at a substrate temperature of at least 300° C. to diffuse said metal into the first gate to modify work function of the first gate as compared to work function of the second gate. | 2010-05-06 |
20100112809 | Multilevel imprint lithography - A mold with a protruding pattern is provided that is pressed into a thin polymer film via an imprinting process. Controlled connections between nanowires and microwires and other lithographically-made elements of electronic circuitry are provided. An imprint stamp is configured to form arrays of approximately parallel nanowires which have (1) micro dimensions in the X direction, (2) nano dimensions and nano spacing in the Y direction, and three or more distinct heights in the Z direction. The stamp thus formed can be used to connect specific individual nanowires to specific microscopic regions of microscopic wires or pads. The protruding pattern in the mold creates recesses in the thin polymer film, so the polymer layer acquires the reverse of the pattern on the mold. After the mold is removed, the film is processed such that the polymer pattern can be transferred on a metal/semiconductor pattern on the substrate. | 2010-05-06 |
20100112810 | Resistive random access memory and method for manufacturing the same - A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell. | 2010-05-06 |
20100112811 | METHOD FOR PATTERNING A METAL GATE - The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer. | 2010-05-06 |
20100112812 | Photomask quality estimation system and method for use in manufacturing of semiconductor device, and method for manufacturing the semiconductor device - A photomask quality estimation system comprises a measuring unit, a latitude computation unit and an estimation unit. The measuring unit measures the mask characteristic of each of a plurality of chip patterns formed on a mask substrate. The latitude computation unit computes the exposure latitude of each chip pattern based on the mask characteristic. The estimation unit estimates the quality of each chip pattern based on the exposure latitude. | 2010-05-06 |
20100112813 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device, including: forming a metallic layer and an interlayer insulation film on a semiconductor substrate sequentially; etching on the interlayer insulation film using fluorine-based etching gas to form an opening portion of a predetermined pattern, reaching the metallic layer; and supplying chlorine-based silane gas and discharging, thus forming a Si film at least on an internal surface of the opening portion without exposure to the atmosphere after the etching. | 2010-05-06 |
20100112814 | PRE-CERTIFIED PROCESS CHAMBER AND METHOD - The present invention relates generally to the field of semiconductor device manufacturing and more specifically to the manufacture and certification of semiconductor processing equipment. Systems and methods are described that establish a baseline contamination levels at each stage of the manufacture, assembly, testing, and installation of a process chamber. | 2010-05-06 |
20100112815 | FLUID STORAGE AND DISPENSING SYSTEMS AND PROCESSES - Fluid storage and dispensing systems and processes involving various devices, structures and arrangements, as well as techniques and methods, for fluid storage and dispensing, including, without limitation, pre-connect verification couplings that are usefully employed in application to fluid storage and dispensing packages, to ensure proper coupling and avoid fluid contamination issues, empty detect systems that are usefully employed for fluid storage and dispensing packages incorporating liners that are pressure-compressed in the fluid dispensing operation, ergonomically enhanced structures for facilitating removal of a dispense connector from a capped vessel, cap integrity assurance systems for preventing misuse of vessel caps, and keycoding systems for ensuring coupling of proper dispense assemblies and vessels. Fluid storage and dispensing systems are described, which achieve zero or near-zero headspace character, and prevent or ameliorate solubilization effects in liquid dispensing from liners in overpack vessels. | 2010-05-06 |
20100112816 | METHOD OF REDUCING NON-UNIFORMITIES DURING CHEMICAL MECHANICAL POLISHING OF MICROSTRUCTURE DEVICES BY USING CMP PADS IN A GLAZED MODE - In sophisticated CMP recipes, the material removal may be accomplished on the basis of a chemically reactive slurry material and a reduced down force, wherein the surface topography of a finally obtained material layer may be enhanced by using, at least in a final phase, a glazed state of the polishing pad. | 2010-05-06 |
20100112817 | METHOD FOR FORMlNG PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a pattern of a semiconductor device using a spacer patterning process comprises coating a developable antireflection film over a substrate including a spacer pattern, coating a photoresist film over the antireflection film, and patterning the antireflection film and the photoresist film by an exposing and developing process to form an etching mask pattern. The etching mask pattern has an excellent profile. When a lower underlying layer is etched using the etching mask pattern, a sufficient etching margin can be secured, thereby obtaining a reliable semiconductor device. | 2010-05-06 |
20100112818 | METHOD FOR FORMING HIGH DENSITY PATTERNS - Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching. | 2010-05-06 |
20100112819 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A plasma processing method for performing a plasma process on a substrate to be processed by making a plasma act thereon includes the following sequential steps of making a plasma weaker than one used in the plasma process act on the substrate, applying a DC voltage to an electrostatic chuck for attracting and holding the substrate while the weak plasma acts on the substrate, extinguishing the weak plasma, and performing the plasma process. Further, a plasma processing apparatus includes a plasma processing mechanism for performing a plasma process on a substrate to be processed, and a controller for controlling the plasma processing mechanism to thereby perform the plasma processing method. | 2010-05-06 |