18th week of 2011 patent applcation highlights part 24 |
Patent application number | Title | Published |
20110101977 | MAGNETIC RESONANCE IMAGING APPARATUS AND MAGNETIC RESONANCE IMAGING METHOD - According to one embodiment, an MRI apparatus includes a probe unit and a control/imaging unit. The probe unit includes an probe, an converter, an compressor and a transmitter. The control/imaging unit includes a receiver, an expander and an reconstructor. The probe detects an RF echo signal generated in a subject by a magnetic resonance phenomenon. The converter digitizes the detected signal. The compressor compresses the digitized signal in accordance with a predetermined compression parameter to obtain a compressed signal. The transmitter generates a transmission signal to wirelessly transmit the compressed echo signal and sends the transmission signal to a radio channel. The receiver receives the transmission signal and extracts the compressed signal from the received signal. The expander expands the extracted compressed signal in accordance with the parameter to obtain the RF echo signal. The reconstructor generates a video signal regarding the subject on the basis of the obtained signal. | 2011-05-05 |
20110101978 | MOTION INFORMATION CAPTURE AND AUTOMATIC MOTION CORRECTION FOR IMAGING SYSTEMS - Systems, methods and articles of manufacture are disclosed for compensating for motion of a subject during an MRI scan of the subject. k-space data may be received from the MRI scan of the subject. Motion information may be received for the subject. Based on the received motion information, a translational motion of the subject may be determined between a first point in time and a second point in time. A search space for motion correction may be reduced using the determined change and an error margin of the capturing technique. A motion-compensated, graphical image of the subject may be generated using the reduced search space. | 2011-05-05 |
20110101979 | AMPLIFIED RADIATION DAMPING FOR MR IMAGING AND SPECTROSCOPY - An imaging system including an imaging apparatus having a plurality of coils, wherein an imaging target is at least partially disposed proximate the coils with at least one excitation source providing pulse sequences. A switch switchably connects the pulse sequences from the excitation source to the coils and switchably connecting to spatially encoded images from the coils during data acquisition. There is an amplified radiation damping feedback section providing amplified radiation damping feedback to the imaging target, wherein the amplified radiation damping feedback provides recovery of longitudinal magnetization subsequent to the data acquisition, and a receiver section for processing the spatially encoded images. | 2011-05-05 |
20110101980 | MAGNETIC RESONANCE IMAGING APPARATUS - According to one embodiment, a magnetic resonance imaging apparatus includes; an imaging area setting unit configured to set an imaging area for a patient according to an imaging condition; an excitation angle determination unit configured to collect magnetic resonance signals from the imaging area by a pre-scan and to determine, on the basis of the collected magnetic resonance signal, an optimal excitation angle of a radio-frequency magnetic field for use in an imaging scan; and an imaging unit configured to acquire imaging data by carrying out the imaging scan of the set imaging area for the patient applying the radio-frequency magnetic field with the determined optimal excitation angle. | 2011-05-05 |
20110101981 | NMR MAS ROTOR ASSEMBLY WITH POROUS CERAMIC BEARINGS - Each NMR rotor bearing in an NMR magic angle spinning assembly is constructed of a porous ceramic material and has no inlet channels or nozzles. Instead, pressurized gas is forced through pores in the bearing ceramic material from an annular groove at the bearing periphery to the central aperture. Since the pores are small and very numerous, the gas pressure is effectively balanced around the periphery of the central aperture. In addition, if contaminants block one or more pores during operation, the pores are so numerous that the balanced pressure can still be maintained in the central aperture, thereby preventing an imbalance that could destroy the rotor. | 2011-05-05 |
20110101982 | CRYOGENIC SYSTEM AND METHOD FOR SUPERCONDUCTING MAGNETS - A cryogenic system for a superconducting magnet comprises a closed-loop cooling path. The closed-loop cooling path comprises a magnet cooling tube thermally coupled to the superconducting magnet. The magnet cooling tube comprises a cryogen flow passage. The closed-loop cooling tube further comprises a re-condenser is fluidly coupled to the magnet cooling tube through tube sections and a liquid cryogen container fluidly coupled between the magnet cooling tube and the re-condenser. At least one gas tank is fluidly coupled to the magnet cooling tube through a connection tube. | 2011-05-05 |
20110101983 | Logging Tool - The invention relates to a logging tool ( | 2011-05-05 |
20110101984 | DISTINGUISHING FALSE SIGNALS IN CABLE LOCATING - Discriminating between a cable locating signal and a false cable locating signal is described. A reference signal, which contains a locating signal frequency impressed on it, is transmitted in a way which provides for detection of a phase shift between the locating signal and the false locating signal. Based on the phase shift, a receiver is used to distinguish the locating signal from the false locating signal. | 2011-05-05 |
20110101985 | TRACKING THE POSITIONAL RELATIONSHIP BETWEEN A BORING TOOL AND ONE OR MORE BURIED LINES USING A COMPOSITE MAGNETIC SIGNAL - A boring tool is moved through the ground in a region which includes at least one electrically conductive in-ground line and which is subject to static magnetic fields including the magnetic field of the earth. Tracking a positional relationship between the boring tool and the line, as well as a directional heading of the boring tool within the region are provided by: (i) generating a time varying magnetic field from the line; (ii) at the boring tool, detecting a composite magnetic signal which includes one component affected by the static magnetic fields and another component affected by the time varying magnetic field such that the static magnetic field component varies as a function of the directional heading and the time varying component varies as a function of the positional relationship; and (iii) processing the composite magnetic signal to separate the static magnetic field component and the time varying magnetic field component from the composite magnetic signal for use in determining the directional heading and the positional relationship. In one feature, the static magnetic field component is used to determine the directional heading of the boring tool and the time varying magnetic field component is used to determine the positional relationship. | 2011-05-05 |
20110101986 | DEVICE AND METHOD OF TESTING AN INTERNAL RESISTANCE OF A BATTERY PACK - An internal resistance testing device includes an excitation source and a battery pack, an adjustable resistance R, a sampling unit, and a control unit. The excitation source and the battery pack form a loop circuit. The adjustable resistance R may be located at the loop circuit formed by the excitation source and the battery pack. The sampling unit samples the voltage between two sides of the battery pack, the voltage between two sides of the adjustable resistance R, and the value of the adjustable resistance R. The control unit calculates internal resistance of the battery pack according to the signal value collected by the sampling unit. The internal resistances of different voltage-ranges the battery pack are determined by adjusting the value of the adjustable resistance R to cause the actual excitation voltage to be equal to the range voltage of the sampling unit. The voltage between two sides of the adjustable resistance R is made equal to the range voltage of the sampling unit by adjusting the value of the adjustable resistance R, which effectively improves measurement accuracy of the internal resistance. | 2011-05-05 |
20110101987 | ABNORMALITY DETERMINATION SYSTEM FOR SECONDARY BATTERY - An abnormality determination system may include a secondary battery that includes a battery case including a positive terminal and a negative terminal, a switch unit that connects electrically the positive terminal to the battery case based on a first control signal, the switch unit breaking electrically a connection between the positive terminal and the battery case based on a second control signal, a voltage measurement unit that measures a voltage of the battery case, and a determination unit that determines an abnormality of the secondary battery based on the voltage. | 2011-05-05 |
20110101988 | IONISATION VACUUM GAUGES AND GAUGE HEADS - A gauge head ( | 2011-05-05 |
20110101989 | Systems and methods for testing the standoff capability of an overhead power transmission line - An overhead power transmission line system includes detector circuitry to detect a flashover event on a power line conductor in response to test over voltage excitations applied to the power line conductor applied. Processing circuitry establishes an operational voltage level for the power line conductor taking into account the lowest applied test over voltage excitation that causes a flashover event. | 2011-05-05 |
20110101990 | Compensating for Aging in Integrated Circuits - An age compensation method and apparatus for an integrated circuit (IC). An IC may be configured to operate at an initial operating voltage at the beginning of its operational life. Various circuits may be used to detect aging of the IC, and indications of aging may be stored to determine the aging of the IC. The information indicative of the determined aging of the IC may be compared to an aging threshold. If the information indicates that the aging is greater than or equal to the determined aging threshold, the operating voltage of the IC may be increased. This process may be repeated over the life of the IC, increasing the operating voltage as the IC ages. Raising the operating voltage in response to aging may compensate for various age related degradation mechanisms that can occur over the operational life of the IC. | 2011-05-05 |
20110101991 | Techniques Employing Light-Emitting Circuits - A light-emitting circuit includes a light-emitting transistor and a voltage supply in communication with the light-emitting transistor to bias the light-emitting transistor in a reasonably bright state. A reasonably bright state is a state in which light emission approaches the greatest for a given drain-source current in the light-emitting transistor. In one aspect, the light-emitting circuit is in communication with a device under test and configured so that the light-emitting transistor emits photons in a manner indicative of an operation of the device under test. The light-emitting circuit may be disposed in a first semiconductor layer, and the device under test may be disposed in a second semiconductor layer. Further, the first semiconductor layer may be included in a first die, and the second semiconductor layer may be included in a second die. | 2011-05-05 |
20110101992 | METHOD AND DEVICE FOR MONITORING A PIEZO ACTUATOR - The invention describes a device and a method for monitoring a piezoelectric actuator. It is checked whether a discharge time assumes an inadmissible value, whether the voltage at the piezoelectric actuator assumes an inadmissible value and whether a fault signal is present. A short circuit of a battery switch is detected if the three conditions are met. | 2011-05-05 |
20110101993 | SYSTEM FOR TESTING ELECTRONIC DEVICES - A system for testing an electronic device comprises a first output, a second output, and a third output connected to a positive input, an identification input, and a negative input of the electronic device, respectively. The system further comprises a switch comprising at least two dynamic contacts, each of which is connected to a resistor for the use of identification. | 2011-05-05 |
20110101994 | Calibration Apparatus And Method For Capacitive Sensing Devices - A calibration apparatus and method for a capacitive sensing device, in which a calibration capacitor device connects to the capacitive sensing device which is connected to an integration circuit that generates a voltage output and a latch output, a transforming circuit transforms a sensitivity calibration parameter into a pair of corresponding analog signal outputs, and an offset calibration parameter into a corresponding analog signal output, at least two first switches between the pair of corresponding analog signal outputs and a fixed potential according to system clock's levels, and at least a third switch switches between the corresponding analog signal output and another fixed potential according to the system clock's levels. The apparatus determines the switch between the pair of signal outputs according to the latch output. | 2011-05-05 |
20110101995 | METHOD OF AND SYSTEM FOR STABILIZATION OF SENSORS - A blood glucose sensing system includes a sensor and a sensor electronics device. The sensor includes a plurality of electrodes. The sensor electronics device includes stabilization circuitry. The stabilization circuitry causes a first voltage to be applied to one of the electrodes for a first timeframe and causes a second voltage to be applied to one of the electrodes for a second timeframe. The stabilization circuitry repeats the application of the first voltage and the second voltage to continue the anodic-cathodic cycle. The sensor electronics device may include a power supply, a regulator, and a voltage application device, where the voltage application device receives a regulated voltage from the regulator, applies a first voltage to an electrode for the first timeframe, and applies a second voltage to an electrode for the second timeframe. | 2011-05-05 |
20110101996 | METHOD AND SYSTEM FOR PERFORMANCE ENHANCEMENT OF RESONANT SENSORS - The present invention related to methods and systems for simultaneously sensing two or more environmental parameters of a sample. Included is an inductor-capacitor-resistor (LCR) resonator sensor and a pick up coil in operative association with the LCR resonator sensor wherein viscoelastic changes in the sensing film cause displacement of the antenna relative to the pick up coil. | 2011-05-05 |
20110101997 | Flush-Mounted Capacitive Sensor Mount - In some embodiments, a method of monitoring particulates may include one or more of the following steps: (a) receiving the particulates in a particulate flow channel mounted within a chute or conduit, (b) collecting a particulate sample in a body section of the flow channel, (c) sensing moisture content of the particulate with a flush mounted capacitive sensor, (d) allowing the particulate to empty out of the flow channel through an opening in a discharge section of the flow channel, (e) concentrating the particulate sample at a sensor surface, and (f) shielding the sensor from stray electromagnetic fields. | 2011-05-05 |
20110101998 | Operating parameter monitoring circuit and method - A monitoring circuit | 2011-05-05 |
20110101999 | METHOD, CAPACITANCE METER, COMPUTER PROGRAM AND COMPUTER PROGRAM PRODUCT FOR IMPROVED CAPACITANCE MEASUREMENT - A method for measuring a capacitance using a capacitance meter. The capacitance meter includes an AC power source with a controllable frequency which is fed to a capacitor to measure its capacitance. A first measurement of the capacitance is performed by the capacitance meter using a first frequency. When the first measurement of the capacitance indicates the capacitance is below a threshold capacitance a lower capacitance measurement is performed in the capacitance meter, using a second measurement of the capacitance using a second frequency. When the first measurement of the capacitance indicates the capacitance is above a threshold capacitance, a higher capacitance measurement is performed in the capacitance meter, using a second measurement of the capacitance using a third frequency, the third frequency being lower than the second frequency. | 2011-05-05 |
20110102000 | CAPACITIVE MEASURING PROBE AND METHOD FOR PRODUCING A CAPACITIVE MEASURING PROBE - The capacitive measuring probe has the following: two electrodes, a plastic casing which encapsulates the two electrodes, the plastic casing having at least one section made of a conductive plastic, which is electrically connected to one of the two electrodes. | 2011-05-05 |
20110102001 | AC LOSS MEASUREMENT DEVICE OF HIGH-TEMPERATURE SUPERCONDUCTOR - A measuring device for measuring the alternating current (AC) loss of a high-temperature superconductor is disclosed. In accordance with an embodiment of the present invention, the device includes a pulse power supply unit, which outputs pulse power in a cycle, a lead wire, which is formed on both sides of the pulse power supply unit and applies the pulse power to a superconductor, a degaussing coil unit, which is connected to one side of the superconductor and cancels an inductive voltage, a shunt unit, which is serially connected between one side of the degaussing coil unit and one side of the pulse power supply unit, and a measurement unit, which is connected to both ends of the shunt unit and measures an electric current flowing through the superconductor. | 2011-05-05 |
20110102002 | ELECTRODE AND SENSOR HAVING CARBON NANOSTRUCTURES - An active electrode structure is disclosed that includes fullerenes produced by a carbo-thermal carbide conversion of a conductive carbide without a metal catalyst. Also disclosed is an electrode that includes a fullerene covalently bonded to a conductive carbide, the fullerene being an aligned or non-aligned array. The carbide substrate having a surface coating of covalently bonded fullerenes is characterized in that the peak separation of a cyclic voltammogram for the conductive carbide having a surface layer of the fullerene is less than about 150 mV at a scan rate of 5 mV/s in a 4 mM ferricyanide, 1M KCl solution. The fullerene may include about 50% or less non-crystalline carbon and about 5% or less of a transition metal that interferes with the ability of the active electrode structure to transfer electrons or detect an analyte. | 2011-05-05 |
20110102003 | Method For Measuring Conductivity Of Ink - Methods and devices for measuring conductivity of ink in a printing system are disclosed. An embodiment of the method is used with a printing system comprising a developer roller, wherein the ink is formed on the developer roller using electrostatic forces. The method comprises printing on a substrate using the ink; measuring a first current that charges the developer roller during the printing; and determining the conductivity of the ink, wherein the conductivity is proportional to the square of the first current. | 2011-05-05 |
20110102004 | METHOD FOR TESTING A LABORATORY DEVICE AND CORRESPONDINGLY EQUIPPED LABORATORY DEVICE - The invention relates to devices for liquid level detection (LLD). It relates to a laboratory device having an electronic circuit for detecting a liquid level in a liquid container, a feeler, which can be advanced, and which is connected to an input side of the electronic circuit, and having a movement device, which allows the feeler to be advanced in the direction of the liquid in the liquid container. Upon the immersion of the feeler in the liquid, a capacitance change is caused in the electronic circuit, which triggers a signal in the circuit. The laboratory device comprises a reference circuit, which is connected to the input side of the circuit, and which specifies an effective capacitance on the input side of the circuit. A sequence controller is used, which causes the triggering of a test by the application of a control signal to the reference circuit, the control signal causing an increase of the effective capacitance through a switching procedure. The processing of the corresponding capacitance change is monitored by the sequence controller, for example. | 2011-05-05 |
20110102005 | On-Chip Accelerated Failure Indicator - An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. | 2011-05-05 |
20110102006 | CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR APPARATUS - A circuit for testing a semiconductor apparatus includes a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV. | 2011-05-05 |
20110102007 | Calibrated wideband high frequency passive impedance probe - A calibrated passive impedance probe has a wide bandwidth operating range for impedance and performance measurements of RF and microwave components, devices, and circuits in 50Ω and 75Ω environments. The probe is calibrated at the probe tip, thus allowing accurate impedance and performance measurements of in-circuit functions and on-board components. The calibrated probe can be used to eliminate RF connectors and provide input and output connections to a circuit board for prototype design and quick performance verification thus realizing cost savings on RF connectors. The probe includes a semi-rigid coaxial cable assembly filled with dielectric material, a silver plated center conductor, and silver plated ground outer conductor having an SMA male connector on one end and exposed center conductor at the opposite end and having uniform characteristic impedance of 50Ω or 75Ω along the cable length; a hexagonal shaped body made of anodized aluminum having raised texture on the surface for sure handling; a probe tip of gold plated aluminum with two spring loaded ground pins; a four-finger threaded cable catch for locking semi-rigid coaxial cable assembly inside the tip and for ground continuity from cable to spring loaded pins; an interface RF connector-adapter including SMA female-SMA female, BNC-SMA female, or Type N-SMA female; a locking nut to hold and lock cable assembly and connector-adapter inside the probe body; and 50Ω and 75Ω precision loads for probe calibration. | 2011-05-05 |
20110102008 | Socket For Testing Semiconductor Chip - A socket for testing a semiconductor chip includes a base cover, a conductive sheet, upper plungers, a housing, lower plungers and a support plate. The base cover has a coupling opening in the central portion thereof, and the conductive sheet is fitted into the coupling opening of the base cover and includes conductive parts and an insulation part. The upper plungers are seated onto upper ends of the conductive parts and come into contact with corresponding terminals of the semiconductor chip. The housing has insert holes at positions corresponding to the upper plungers and fastens the upper plungers to the corresponding conductive parts. The lower plungers are provided under lower ends of the conductive parts and come into contact with corresponding terminals of a PCB to electrically connect the conductive parts to the PCB. The support plate has holes at positions corresponding to the lower plungers and fastens the lower plungers to the lower ends of the corresponding conductive parts such that lower ends of the lower plungers protrude outside through the holes of the support plate. | 2011-05-05 |
20110102009 | TEST SOCKET ELECTRICAL CONNECTOR, AND METHOD FOR MANUFACTURING THE TEST SOCKET - A test socket, an electrical connector, and a method for manufacturing the test socket. In detail, the test socket for electrically connecting terminals of a semiconductor device to pads of a test apparatus includes: a housing having through-holes vertically extending to correspond in position to the terminals of the semiconductor device; contact pins disposed to correspond in position to the through-holes of the housing and contacting the terminals of the semiconductor device; and elastic members connected to the contact pins in the through-holes of the housing to contract and expand, wherein the elastic members are adhered to the contact pins by using an adhesive material. | 2011-05-05 |
20110102010 | METHOD AND APPARATUS FOR RECONFIGURABLE AT-SPEED TEST CLOCK GENERATOR - A reconfigurable number of at-speed pulses and reconfigurable dead cycles between pulses is utilized to enhance test coverage of an Integrated Circuit. A reconfigurable number of programmable at-speed phase-locked loop clock pulses without a dead cycle is emitted through an integrated circuit. Further, a plurality of programmable at-speed phase-locked loop clock pulses is emitted through the Integrated Circuit such that a reconfigurable number of dead cycles is between the plurality of programmable at-speed phase locked loop clock pulses. In addition, data associated with the reconfigurable number of programmable at-speed phase-locked loop clock pulses is capture. Finally, data associated with the reconfigurable number of dead cycles is captured. | 2011-05-05 |
20110102011 | METHOD AND DEVICE FOR TESTING TSVS IN A 3D CHIP STACK - A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry. | 2011-05-05 |
20110102012 | PARAMETER ESTIMATION SYSTEM AND METHOD FOR AN INDUCTION MOTOR - A method of estimating stator resistance of an induction motor is provided. The method includes applying voltage pulses through two phase paths of the motor for a plurality of electrical cycles to inject current in the motor, wherein the voltage pulses are applied until rotor flux of the motor is substantially stabilized and measuring stator voltage and stator current in response to the applied voltage pulses for each of the plurality of electrical cycles. The method also includes calculating the stator resistance based upon the measured stator voltages and the stator currents. | 2011-05-05 |
20110102013 | PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit ( | 2011-05-05 |
20110102014 | THREE DIMENSIONAL INTEGRATED CIRCUITS - A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers. | 2011-05-05 |
20110102015 | ELECTRONIC CIRCUIT DEVICE - In the electronic circuit device with stacked plural components of the same function, this invention enables to select an arbitrary component among plural components by a control element, without setting pre-determined identification information in each component. By installing a sequential logic circuit in each component, and changing a state of the sequential logic circuit by control data transmitted from the component stacked in a preceding stage or the control element, the state of the controlled component is set to a state that accepts a selection made by the control element. | 2011-05-05 |
20110102016 | Four-Terminal Reconfigurable Devices - Reconfigurable devices and methods for the fabrication thereof are provided. In one aspect, a reconfigurable device is provided. The reconfigurable device comprises a substrate; a first dielectric layer on the substrate; a conductive layer recessed into at least a portion of a side of the first dielectric layer opposite the substrate; at least one second dielectric layer over the side of the first dielectric layer opposite the substrate, so as to cover the conductive layer; a heater within the second dielectric layer; at least one programmable via extending through the second dielectric layer, extending through and surrounded by the heater and in contact with the conductive layer, the programmable via comprising at least one phase change material; a capping layer over the programmable via; a first conductive via and a second conductive via, each extending through the second dielectric layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive layer. | 2011-05-05 |
20110102017 | CONFIGURABLE TIME BORROWING FLIP-FLOPS - Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch. | 2011-05-05 |
20110102018 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5x10 | 2011-05-05 |
20110102019 | SEMICONDUCTOR DEVICE FORMED ON A SOI SUBSTRATE - Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate. | 2011-05-05 |
20110102020 | BALANCED PHASE DETECTOR - Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection. | 2011-05-05 |
20110102021 | Differential Hysteresis Comparator Circuits and Methods - A comparator circuit for providing hysteresis comprises first and second differentially coupled transistors. The first of the differentially coupled transistors provides drain current to first and second load transistors. The second of the differentially coupled transistors provides drain current to third and fourth load transistors. In one example embodiment, the drain of the first of the differentially coupled transistors also drives the gate of the first and third load transistors, while the drain of the second of the differentially coupled transistors drives the gate of the second and fourth transistors. | 2011-05-05 |
20110102022 | Input unit of portable terminal, portable terminal using the same, and operation method thereof - A portable terminal includes: a key row including a reference resistor, switches separately connected to the reference resistor, and a plurality of resistors connected to the switches, respectively; a reference voltage unit connected to the reference resistor and providing a reference voltage; and a first comparator and a second comparator dividing the reference voltage from the reference voltage unit by the reference resistor and at least one resistor connected to an activated switch, and receiving an analog key input signal corresponding to the divided reference voltage. | 2011-05-05 |
20110102023 | CURRENT-TO-VOLTAGE CONVERTERS WITH DYNAMIC FEEDBACK - An apparatus for modifying an output signal indicative of a downhole parameter that may include a carrier conveyable in a wellbore; a negative error compensator; and an output signal device. The negative error compensator may be configured to modify the output of the device to increase or decrease a characteristic of the output signal from the output signal device. Also, a method for modifying an output signal indicative of a downhole parameter that may include modifying a characteristic of an output signal produced by a output signal device in a wellbore using a negative error compensator. | 2011-05-05 |
20110102024 | DATA OUTPUT CIRCUIT - The data output circuit includes a pull-up signal generator, a pull-down signal generator and a driver. The pull-up signal generator is configured to generate a pull-up signal that is driven to a first level state when a pre-pull-up signal is activated and driven to a second level state after a first delay period. The pull-down signal generator is configured to generate a pull-down signal that is driven to a third level state when a pre-pull-down signal is activated and driven to a fourth level state after a second delay period. The driver is configured to drive output data in response to receiving either the pull-up signal and the pull-down signal. | 2011-05-05 |
20110102025 | DATA OUTPUT CIRCUIT - The data output circuit includes a first decoder, a second decoder, a first selective output circuit, a second selective output circuit, and an output driver. The first decoder is configured to generate a pull-up selection signal by decoding a pull-up code. The second decoder is configured to generate a pull-down selection signal by decoding a pull-down code. The first selective output circuit is configured to select and output a voltage level of a pull-up level signal in response to the pull-up selection signal. The second selective output circuit is configured to select and output a voltage level of a pull-down level signal in response to the pull-down selection signal. The output driver is configured to drive output data in response to receiving a pre-pull-up signal and a pre-pull-down signal. | 2011-05-05 |
20110102026 | ANTENNA DRIVING DEVICE - The antenna driving device of the present invention is composed of a trapezoidal-wave signal generating circuit for generating a trapezoidal-wave signal from a reculangular-wave signal having a predetermined frequency; and a trapezoidal-wave signal amplifying circuit for amplifying the trapezoidal-wave signal and feeding the amplified signal to an antenna load. | 2011-05-05 |
20110102027 | SEMICONDUCTOR INTEGRATED DEVICE AND CONTROL METHOD THEREOF - Provided is a semiconductor integrated device that selects one or more of a plurality of functional blocks and resets the selected functional block, and a control method of the semiconductor integrated device. The semiconductor integrated circuit includes a functional block that is reset when a clock signal and a reset signal are supplied, a reset signal output unit that outputs the reset signal for resetting the functional block, a clock mask circuit that stops the clock signal to be supplied to the functional block, and a clock mask control circuit that controls the clock mask circuit. | 2011-05-05 |
20110102028 | MULTIPHASE CLOCK GENERATION CIRCUIT - The multiphase clock generation circuit includes a variable slew rate circuit and a phase interpolation circuit. In the variable slew rate circuit, the slew rate varies according to a first control signal. Two reference clocks having a phase difference of 90° from each other are supplied to the phase interpolation circuit via the variable slew rate circuit. The phase interpolation circuit interpolates the two reference clocks having a phase difference of 90° from each other according to a second control signal to thereby generate an output clock having an intermediate phase. | 2011-05-05 |
20110102029 | DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS - Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of delay stages, each of which consists of a single inverting delay device. The inputs and outputs of a selected stage are applied to a phase inverter that inverts one of the signals and applies it to a first input of a phase mixer with the same delay that the other signal is applied to a second input of the phase inverter. The delay of the signals from the selected delay element are delayed from each other by a coarse delay interval, and the phase mixer interpolates within the coarse delay interval by fine delay intervals. A phase detector compares the timing of a signal generated by the phase interpolator to the timing of a reference clock signal applied to the delay line to determine the selected delay stage and a phase interpolation value. | 2011-05-05 |
20110102030 | SYSTEM AND METHOD FOR DYNAMICALLY SWITCHING BETWEEN LOW AND HIGH FREQUENCY REFERENCE CLOCK TO PLL AND MINIMIZING PLL OUTPUT FREQUENCY CHANGES - A circuit is provided for use with a clock signal having a plurality of clock pulses, each clock pulse having a rising edge and a falling edge. The circuit is operable to receive a reference signal and to output an output signal. The circuit includes an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion is arranged to receive the reference signal and is operable to output a divided reference signal. The feedback divider portion is arranged to receive the output signal and is operable to output a divided feedback signal. The phase detector portion is operable to output a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion is operable to output a tuning signal based on the phase detector signal. The voltage controlled oscillator portion is operable to output the output signal based on the tuning signal. The phase detector portion is further operable to change the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal, and further based on the control signal and a rising edge of a clock pulse. | 2011-05-05 |
20110102031 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes a control voltage generating block configured to generate a control voltage corresponding to a phase difference between a reference clock signal and an internal clock signal, a control voltage restoring block configured to store the control voltage as a restoring voltage when entering into a low power mode and to supply the restoring voltage to a control voltage node when exiting from the low power mode, and an internal clock signal generating block configured to generate the internal clock signal corresponding to a voltage level of the control voltage. | 2011-05-05 |
20110102032 | LOOP FILTER - A loop filter having a first node on which to receive an input signal to the loop filter, a second node on which to provide an output signal of the loop filter, and a cascade arrangement of at least a first circuit that generates a zero, a second circuit that generates a first pole, and a third circuit that generates a second pole to form a passive loop filter of at least 3rd order. The cascade arrangement includes a first signal path coupling the first node to the second node. such that the first circuit is coupled to the first node through the second circuit and the third circuit. Further, the loop filter includes at least one transistor circuit, and a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit. | 2011-05-05 |
20110102033 | LOW POWER CLOCKING SCHEME FOR A PIPELINED ADC - Delay locked loops or DLLs are oftentimes employed in pipelined analog-to-digital converters (ADCs). Conventional DLLs, though, can consume an excessive amount of power. Here, a DLL is provided with a modified charge pump that allows for reduced power consumption. | 2011-05-05 |
20110102034 | CHARGE PUMP FOR PLL/DLL - A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. | 2011-05-05 |
20110102035 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DELAY LOCKED LOOP CIRCUIT - A semiconductor integrated circuit is provided. The semiconductor integrated circuit includes: a delay locked loop (DLL) output block configured to delay an input clock signal by a predetermined time in response to a plurality of delay control signals and provide a DLL clock signal; a locking control block configured to compare a phase of a reference clock signal and a phase of a feedback clock signal, and synchronize the phase of the reference clock signal and the phase of the feedback clock signal in response to the plurality of delay control signals; and a locking detection block configured to detect whether the phase of the reference clock signal and the phase of the feedback clock signal are synchronized and the DLL clock signal is locked, wherein, when the DLL clock signal is locked, the locking control block provides the reference clock signal, which is obtained by dividing the input clock signal by n (where n is a natural number equal to or greater than 2), as an internal DLL clock signal. | 2011-05-05 |
20110102036 | PHASE SPLITTER USING DIGITAL DELAY LOCKED LOOPS - A phase splitter uses digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL. | 2011-05-05 |
20110102037 | CIRCUIT FOR RESETTING SYSTEM AND DELAY CIRCUIT - A reset circuit and a delay circuit are provided. The delay circuit includes a first resistor module, a second resistor module, a switch module and a capacitor module. First terminals of the first and the second resistor modules are coupled respectively to a first voltage and a second voltage. The switch module have a control terminal served as a input terminal of the delay circuit, a first terminal served as a output terminal of the delay circuit, a second terminal coupled to a second terminal of the first resistor module, and a third terminal coupled to a second terminal of the second resistor module. In the delay circuit, the first terminal selectively connected to the second terminal or the third terminal in accordance with the control terminal. The capacitor module couples between the first terminal of the switch module and the second voltage. | 2011-05-05 |
20110102038 | DUTY RATIO CONTROL APPARATUS AND DUTY RATIO CONTROL METHOD - There are provided a duty ratio control apparatus for altering a duty ratio of a clock signal to output an altered clock signal, including a first variable delay section that outputs a first delayed clock signal generated by delaying the clock signal by a predetermined first delay time, and a phase comparing section that compares, in terms of phase, an edge of the clock signal and an edge of the first delayed clock signal and generates the altered clock signal having a pulse width determined by a phase difference obtained by the comparison, and a duty ratio control method. | 2011-05-05 |
20110102039 | APPARATUS AND METHOD FOR CORRECTING DUTY CYCLE OF CLOCK SIGNAL - A clock correction circuit includes a delay locked loop (DLL) configured to delay an external clock signal and to generate an internal clock signal, a first duty cycle correction (DCC) unit configured to correct a duty cycle of the external clock signal in response to a first duty cycle code, a second DCC unit configured to correct a duty cycle of the internal clock signal in response to a second duty cycle code, and a duty cycle code generation unit configured to select an output of from outputs of the first and second DCC Units and to generate the first and second duty cycle codes by detecting a duty cycle ratio of the selected output. | 2011-05-05 |
20110102040 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage. | 2011-05-05 |
20110102041 | METHOD AND DEVICE FOR GENERATING PWM SIGNALS - A PWM signal for driving power transistors of a half-bridge of a converter is generated with the aid of a digital circuit, in which an internal reference value is compared to the counter content of a counting ramp. In this context, a logic state of the PWM signal depends upon whether the internal reference value is greater than the counter content of the counting ramp. After each comparison between the internal reference value and the counter content, an n-bit long data word dependent on the result of this comparison is output serially as PWM signal, n being greater than or equal to 2. The resolution of the PWM signal is thereby improved by the factor n in comparison to conventional systems, without markedly increasing the circuit expenditure. | 2011-05-05 |
20110102042 | APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES - A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor. | 2011-05-05 |
20110102043 | REDUCING POWER-SUPPLY-INDUCED JITTER IN A CLOCK-DISTRIBUTION CIRCUIT - A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary. | 2011-05-05 |
20110102044 | Clocking Architecture in Stacked and Bonded Dice - A method and apparatus for distributing clock signals throughout an integrated circuit is provided. An embodiment comprises a distribution die which contains either the clock signal distribution network by itself, or the clock signal distribution network in tandem with a clock signal generator. The distribution die is electrically connected through an interface technology, such as microbumps, to route the clock signals to the functional circuits on a separate functional die. Alternatively, the distribution die could be electrically connected to more than one die at a time, using vias through the distribution die to route the clock signals to the different die. This separate distribution die reduces the coupling between lines and also helps to prevent signal skew as the signal moves through the distribution network. | 2011-05-05 |
20110102045 | INTERFACING BETWEEN DIFFERING VOLTAGE LEVEL REQUIREMENTS IN AN INTEGRATED CIRCUIT SYSTEM - A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero. | 2011-05-05 |
20110102046 | Interfacing between differing voltage level requirements in an integrated circuit system - A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation. | 2011-05-05 |
20110102047 | Radio Frequency (RF) Power Detector Suitable for Use in Automatic Gain Control (AGC) - In one form, a power detector includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node. In another form, a power detector compares an output of a power detector core to multiple threshold voltages in corresponding comparators. | 2011-05-05 |
20110102048 | BIAS VOLTAGE GENERATION TO PROTECT INPUT/OUTPUT (IO) CIRCUITS DURING A FAILSAFE OPERATION AND A TOLERANT OPERATION - A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation. | 2011-05-05 |
20110102049 | CIRCUIT FOR GENERATING A REFERENCE VOLTAGE WITH COMPENSATION OF THE OFFSET VOLTAGE - An embodiment of a circuit includes first and second branches, an amplifier, a compensation circuit, and a bias unit. The first and second branches are respectively operable to generate first and second currents. The amplifier has a first amplifier input node coupled to the first branch, a second amplifier input node coupled to the second branch, an amplifier output node coupled to the first and second branches, and a first compensation node. The compensation unit is operable to provide a first offset-compensation signal to the first compensation node. And the first bias unit is operable to provide first and second bias signals to the first and second input nodes, respectively, such that the amplifier is operable to cause the first current to approximately equal the second current. | 2011-05-05 |
20110102050 | Attenuator - An attenuator includes a T-type two terminal pair network including first and second terminals, first, second and third circuits, wherein the first terminal receives an input signal to be attenuated, wherein the first circuit is connected between the first and second terminals, wherein the second circuit is connected between the first circuit and the second terminal and is connected to the first circuit via a node, wherein the third circuit is connected to the node, and a capacitor connected to the node, wherein the capacitance value of the capacitor is variable. | 2011-05-05 |
20110102051 | HARMONIC REJECTION MIXER - A harmonic rejection mixer includes a differential in-phase signal path and a differential quadrature signal path, a shared differential transconductor for generating a shared transconductor output signal from a mixer input signal, a first selective mixing circuit disposed in the differential quadrature signal path and coupled to the shared differential transconductor, and a second selective mixing circuit disposed in the differential in-phase signal path and coupled to the shared differential transconductor, the first selective mixing circuit is controlled by a first selective control signal and the second selective mixing circuit is controlled by a second selective control signal to selectively supply the shared transconductor output signal to the differential quadrature signal path and the differential in-phase signal path, respectively. | 2011-05-05 |
20110102052 | Hybrid Switch Circuit - A hybrid switch circuit includes a hybrid switch that couples an input conductor connected to an AC power supply to an output conductor connected to a load. The hybrid switch includes a power semiconductor in parallel with an electromagnetic relay. A control circuit turns on the hybrid switch by turning on the power semiconductor at a zero-voltage crossing of the AC voltage to provide a conductive path and then closing the relay to provide a conductive bypass path that bypasses the power semiconductor. The control circuit turns off the hybrid switch by opening the relay and subsequently turning off the power semiconductor at a zero crossing of the load current. The control circuit operates in response to at least one switch control signal that indicates whether an operating fault condition exists. | 2011-05-05 |
20110102053 | METHOD AND SOC FOR IMPLEMENTING TIME DIVISION MULTIPLEX OF PIN - A method for using pins in different mode during different time is provided. The method is able to make at least one pin of a SOC be used in a first interface mode or a second interface mode during different time; wherein the SOC comprises a first interface circuit, a first pin, a second interface circuit, and a second pin; the first interface circuit comprises a first bidirectional PAD unit, a first signal interface unit of the first interface mode and a interface unit of the second interface mode; the second interface circuit comprises a second bidirectional PAD unit, a second signal interface unit of the first interface mode. The method comprises: selecting the output of the first signal interface unit or the output of the interface unit of the second interface mode to be connected with the first pin through the first bidirectional PAD unit during different time. | 2011-05-05 |
20110102054 | POWER SEMICONDUCTOR MODULE AND METHOD FOR OPERATING A POWER SEMICONDUCTOR MODULE - A power semiconductor module includes a normally on, controllable first power semiconductor switch including at least one first power semiconductor chip, and a normally off, controllable second power semiconductor switch including at least one second power semiconductor chip. The load paths of the first power semiconductor switch and of the second power semiconductor switch are connected in series. The control terminals of all first power semiconductor chips are permanently electrically conductively connected to a conductor track to which no load terminal of any of the first power semiconductor chips is permanently electrically conductively connected, and to which no load terminal and no control terminal of any of the second power semiconductor chips are permanently electrically conductively connected. | 2011-05-05 |
20110102055 | LOW-SIDE DRIVER HIGH-VOLTAGE TRANSIENT PROTECTION CIRCUIT - A low-side driver circuit includes a low-side driver integrated circuit and a controllable switch. The low-side driver integrated circuit is responsive to an on-off command input signal to selectively operate in an ON mode and an OFF mode. The controllable switch is responsive to the on-off command signal to selectively operate in a CLOSED mode and an OPEN mode. The low-side driver integrated circuit and the controllable switch are configured to simultaneously operate in the ON mode and the CLOSED mode, respectively, and in the OFF mode and the OPEN mode, respectively. During a voltage transient the potential will be realized across the controllable switch, thus protecting the lower voltage rated low-side integrated circuit. | 2011-05-05 |
20110102056 | METHOD FOR SWITCHING WITHOUT ANY INTERRUPTION BETWEEN WINDING TAPS ON A TAP-CHANGING TRANSFORMER - The invention relates to a method for switching without any interruption between two winding taps (tap n, tap n+1) of a tap-changing transformer, wherein each of the two winding taps is connected to the common load output line via in each case one mechanical switch (Ds) and a series circuit, arranged in series thereto, comprising two IGBTs (Ip, In) which are switched in opposite directions. | 2011-05-05 |
20110102057 | TEMPERATURE AND PROCESS DRIVEN REFERENCE - A reference voltage generation circuit for generating a reference voltage that can adaptively depend on temperature and process includes: a comparator, having a process, temperature and voltage (PVT) insensitive reference as a first input, and a feedback of the output as a second input, for generating a voltage reference output; a first resistor, coupled to the output of the operational amplifier; a second and a third variable resistor coupled in parallel, and coupled between the first resistor and ground; and a transistor, coupled between the third variable resistor and ground. | 2011-05-05 |
20110102058 | CIRCUIT FOR GENERATING A REFERENCE VOLTAGE - An embodiment of a bandgap voltage reference circuit for generating a bandgap voltage reference. Said embodiment comprises a current generator controlled by a first driving voltage for generating a first current depending on the driving voltage, and a first reference circuit element coupled to the controlled current generator for receiving the first current and generating a first reference voltage in response to the first current. The circuit further comprises a second reference circuit element for receiving a second current corresponding to the first current; said second reference circuit element is adapted to generate a second reference voltage in response to the second current. Said circuit further comprises a third reference circuit element for receiving a third current corresponding to the first current and generating the bandgap reference voltage in response to the third current, and an operational amplifier. The operational amplifier has a first input terminal coupled to the first circuit element for receiving a first reference voltage input based on the first reference voltage, a second input terminal coupled to the second reference circuit element for receive a second input voltage based on the second reference voltage and an output terminal coupled to the controlled current generator to provide the first driving voltage to the current generator according to the difference between the first input voltage and the second input voltage. The circuit also comprises a control circuit comprising first capacitive means and second capacitive means. The first capacitive means have a first terminal coupled to the first reference circuit element to receive the first reference voltage and a second terminal coupled to the first input terminal to provide the first input voltage. The second capacitive means comprise a first terminal coupled to the second reference circuit element for receiving the second reference voltage and a second terminal coupled to the second input terminal to provide the second input voltage. The control circuit also comprises biasing means to selectively provide a common-mode voltage to the second terminals of the first and second capacitive means. | 2011-05-05 |
20110102059 | Location-Related Adjustment of the Operatng Temperature Distribution or Power Distribution of a Semiconductor Power Component, and Component for Carrying Out Said Method - Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network ( | 2011-05-05 |
20110102060 | RESISTIVE SHEET, PRESSURE-SENSITIVE SWITCH, AND INPUT DEVICE - A resistive sheet includes a flexible cover sheet, a wiring part provided on the bottom face of the cover sheet, and ring, circular-arc, or spiral resistive layer connected to the wiring part. This resistive layer has uneven bottom face. The resistive sheet also includes a spacer layer whose bottom face is disposed at a position lower than the resistive layer. The wiring part is sandwiched between the bottom face of the cover sheet and the spacer layer. | 2011-05-05 |
20110102061 | Touch panel sensing circuit - A touch panel sensing circuit senses a voltage variation of a coupling capacitor formed between a first directional signal line and a second directional signal line separated from the first directional signal line by a dielectric when an object approaches. The sensing circuit eliminates the parasitic capacitance effect on the signal lines and rapidly accumulates charges for an amplifier in sensing to thereby increase the operational speed of the sensing circuit. | 2011-05-05 |
20110102062 | MULTI-SUPPLY VOLTAGE COMPATIBLE I/O RING - Systems and methods for achieving multiple supply voltage compatibility of an input/output (I/O) ring of an integrated circuit (IC) chip. The IC chip includes a core surrounded by the I/O ring which includes a voltage detector circuit. An I/O supply voltage of the IC chip is sensed by the voltage detector circuit to generate a control signal. The control signal is used to configure the I/O ring to operate at the I/O supply voltage of the I/O ring, thus enabling the IC to operate at multiple supply voltage levels. | 2011-05-05 |
20110102063 | CURRENT-CONTROLLED RESISTOR - A current-controlled resistor comprises a first input terminal configured to receive an input signal and a second input terminal configured to receive a current control signal. The resistor comprises a first stage configured to receive the current control signal; the first stage includes first and second PN diodes having first terminals of a first type and second terminals of a second type. The first terminals of the first and second PN diodes are coupled each other and a second terminal of the first PN diode is coupled to the first input terminal. The resistor comprises a second stage configured to receive the current control signal; the second stage includes a third PN diode having first and second terminals of the first and second types, the second terminal of the third PN diode being coupled to the second terminal of the second PN diode. | 2011-05-05 |
20110102064 | Electronic Age Detection Circuit - An aging detection circuit is disclosed. An aging detection circuit may include at least an inverter and a half-latch. During a power-up sequence, if an input voltage of the first inverter changes sufficiently to cause the output of the inverter to change states, the output of the half-latch may be set to a state indicating aging of the circuit. This indication may be used in determining whether or not a supply voltage should be changed to compensate for the aging. A first transistor of the inverter may be arranged such that it remains active subsequent to power-up of the circuit. When active, the first transistor may be subject to degradation mechanisms associated with aging and which change its threshold voltage. The threshold voltage may change such that on a successive power-ups of the circuit, the first transistor is at least momentarily deactivated, leading to the setting of the state indicating aging by the half-latch circuit. | 2011-05-05 |
20110102065 | SEMICONDUCTOR APPARATUS AND CHIP SELECTION METHOD THEREOF - A semiconductor apparatus having a plurality of stacked chips includes: a plurality of latch units, each of which is disposed in a corresponding one of the plurality of chips and is configured to latch a clock signal and a frequency-divided signal at mutually different points of time to generate an chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is disposed in the corresponding one of the plurality of chips and is configured to compare the chip identification signal of the corresponding one of the plurality of chips with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips, wherein the chip selection signal is configured to enable the corresponding one of the plurality of chips when the chip identification signal matches the chip selection identification signal. | 2011-05-05 |
20110102066 | SEMICONDUCTOR APPARATUS AND CHIP SELECTION METHOD THEREOF - A semiconductor apparatus having a plurality of stacked chips includes: a through silicon via (TSV) configured to couple the plurality of chips together and configured to be coupled in series to a plurality of voltage drop units; a plurality of signal conversion units, each of which is configured to convert a voltage outputted from the voltage drop unit of the corresponding one of the plurality of chips to a digital code signal and provide the digital code signal as chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is configured to compare the chip identification signal with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips. | 2011-05-05 |
20110102067 | Fuse devices and methods of operating the same - A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor. | 2011-05-05 |
20110102068 | GRAPHENE DEVICE AND METHOD OF USING GRAPHENE DEVICE - An embodiment of a graphene device includes a layered structure, first and second electrodes, and a dopant island. The layered structure includes a conductive layer, an insulating layer, and a graphene layer. The electrodes are coupled to the graphene layer. The dopant island is coupled to an exposed surface of the graphene layer between the electrodes. An embodiment of a method of using a graphene device includes providing the graphene device. A voltage is applied to the conductive layer of the graphene device. Another embodiment of a method of using a graphene device includes providing the graphene device without the dopant island. A dopant island is placed on an exposed surface of the graphene layer between the electrodes. A voltage is applied to the conductive layer of the graphene device. A response of the dopant island to the voltage is observed. | 2011-05-05 |
20110102069 | CHARGE PUMP CIRCUIT AND DRIVING METHOD THEREOF - A charge pump circuit includes an input end, a first reservoir capacitor, a second reservoir capacitor, two output ends, a charge pump unit and a charge module. The input end receives an input voltage, and the two output ends output a positive pumping voltage and a negative pumping voltage, respectively. The charge pump unit is utilized for charging the first reservoir capacitor and the second reservoir capacitor respectively by referring to a plurality of operational phases, wherein the charge pump unit does not charge at least one designated reservoir capacitor of the first reservoir capacitor and the second reservoir capacitor during at least one designated operational phase of the plurality of operational phases. When the charge pump unit operates in the at least one designated operational phase, the charge module is utilized for charging the at least one designated reservoir capacitor. | 2011-05-05 |
20110102070 | VOLTAGE PUMPING CIRCUIT - In a first pair of stacked PMOS devices comprising a first PMOS device and a second PMOS device, the first pumping circuit is coupled between a gate of the first PMOS device and a P pre-driver signal. In a second pair of stacked NMOS devices comprising a first NMOS device and a second NMOS device, the second pumping circuit is coupled between a gate of the first NMOS device and an N pre-driver signal. The pumping circuits recognizing the transition from the pre-driver signals provide a voltage to the gate of the first PMOS device and of the first NMOS device so that the first PMOS and NMOS devices are turned on better. As a result, their voltage Vds peaks are suppressed to a safe level; the devices avoid hot-carrier degradations; and their lifetimes are prolonged. | 2011-05-05 |
20110102071 | CURVATURE-COMPENSATED BAND-GAP VOLTAGE REFERENCE CIRCUIT - A band-gap reference voltage is developed by a phase-clocked band-gap circuit including a single PN junction through which first and second constant currents are alternately directed. A current proportional to absolute temperature is selectively added to one of the first and second constant currents to curvature-compensate the developed band-gap reference voltage. The band-gap circuit is calibrated at any desired temperature by interrupting the curvature compensation current and trimming the one constant current to bring the un-compensated band-gap reference voltage into correspondence with a nominal band-gap voltage functionally related to the calibration temperature and circuit component values. | 2011-05-05 |
20110102072 | Power management of an integrated circuit - An integrated circuit | 2011-05-05 |
20110102073 | Semiconductor device, system with semiconductor device, and calibration method - Variations of the impedance of each output driver of a semiconductor device can be reduced, and high-speed calibration is achieved. A calibration circuit including a replica circuit having the same configuration as each pull-up circuit or pull-down circuit included in an output driver of a semiconductor device is provided within a chip. During a first calibration operation, the replica circuit is provided with voltage conditions that allow the maximum current to flow through the output driver so that an impedance of the replica circuit is equal to a value of an external resistor. During a second calibration operation, table parameters obtained in the first calibration operation are used to adjust the impedance of the output driver without use of the replica circuit. | 2011-05-05 |
20110102074 | PROGRAMMABLE RF ARRAY - The present disclosure relates to radio frequency integrated circuits. More particularly, systems, devices and methods related to field programmable, software implemented, radio frequency integrated circuits are disclosed. In accordance with an exemplary embodiment, a field programmable, software implemented, radio frequency integrated circuit may comprise a high frequency IF embodiment. An input signal may be up converted to a high frequency, such as 60 GHz. Next, the amplitude and/or phase may be adjusted as desired. Subsequently, the signal may be down converted. | 2011-05-05 |
20110102075 | POWER DISTRIBUTION SYSTEM FOR INTEGRATED CIRCUITS - A power distribution system for integrated circuits includes methods to damp resonance between a bypass capacitor network and a power/ground cavity of the printed circuit board that (a) does not require excessive quantities of bypass/damping components or (b) does not require high plane cavity capacitance or in the alternative can insure a Q of less than 1.4 at the transition from the bypass network to the plane cavity impedance cross-over. | 2011-05-05 |
20110102076 | Semiconductor integrated circuit - A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line. | 2011-05-05 |